Semiconductor device

Abstract

The present art relates to a semiconductor device in which noise can be more suitably reduced. A semiconductor device according to the present art comprises: a first insulating film that defines a channel region between a source region and a drain region; a gate region that is formed on the channel region; a first semiconductor region that is separated from an adjacent semiconductor device; and a contact that penetrates the first insulating film, connects the gate region and the first semiconductor region, and is connected to external wiring. The present art can be applied to, e.g., a differential input transistor of a light detection element.

Description

Semiconductor device

[0001] The present technology relates to a semiconductor device, and particularly relates to a semiconductor device configured to more suitably reduce noise.

[0002] Conventionally, in comparators included in CMOS image sensors, countermeasures against RTS noise have been required. As a countermeasure against RTS noise, there is a method of increasing the element area of a transistor configuring the comparator. However, in recent years, demand for pixel miniaturization and increased pixel count has grown, and it has been desired to suppress the generation of RTS noise by means other than increasing the element area of the transistor.

[0003] Therefore, in order to suppress the generation of noise, for example, a transistor in which a gate region and a back gate region are electrically connected via a metal contact and a multilayer wiring has been proposed (see, for example, Patent Document 1).

[0004] Japanese Patent Application Laid-Open No. 2021-34493

[0005] In the technology described in Patent Document 1, since a well tap region configuring a back gate terminal needs to be formed for each transistor, the size of the transistor increases. In addition, in the technology described in Patent Document 1, parasitic capacitance is generated, for example, between a source region and a back gate terminal.

[0006] The present technology has been made in view of such circumstances, and is intended to enable more suitable noise reduction.

[0007] A semiconductor device according to one aspect of the present technology is a semiconductor device comprising: a first insulating film that defines a channel region between a source region and a drain region; a gate region formed on the channel region; a first semiconductor region separated from an adjacent semiconductor device; and a contact that penetrates the first insulating film, connects the gate region to the first semiconductor region, and is connected to an external wiring.

[0008] In a semiconductor device according to one aspect of this technology, a first insulating film is formed that defines a channel region between a source region and a drain region, a gate region is formed on the channel region, a first semiconductor region is separated from adjacent semiconductor devices, and a contact is formed that penetrates the first insulating film, connects the gate region and the first semiconductor region, and is connected to an external wiring.

[0009] This figure shows an example configuration of one embodiment of a photodetector to which this technology is applied. This figure shows an example of a pixel circuit configuration. This figure shows an example of a comparator circuit configuration. This figure shows an example of vertical streak noise appearing in an captured image. This is a cross-sectional view showing the configuration of a semiconductor device as a comparative example. This figure compares the flicker noise spectrum when the MOSFET is a standard structure and when the MOSFET is an FG=GB structure. This figure compares the RTS noise distribution and transconductance when the MOSFET is a standard structure and when the MOSFET is an FG=GB structure. This figure compares the element area and parasitic capacitance of the semiconductor device when the MOSFET is a standard structure and when the MOSFET is an FG=GB structure. This figure shows an example configuration of a semiconductor device as a transistor according to one embodiment of this technology. This is a side cross-sectional view showing an example configuration of a semiconductor device. This figure shows an example of a comparator circuit configuration to which this technology is applied. This is a side cross-sectional view showing a first modified example of the semiconductor device configuration. This is a side cross-sectional view showing a second modified example of the semiconductor device configuration. This figure explains an example of a contact via configuration. This figure explains a modified example of the contact via configuration. This is a side cross-sectional view showing a third modified example of the semiconductor device configuration. This is a side cross-sectional view showing a fourth modified example of the semiconductor device configuration. This is a side cross-sectional view showing a fifth modified example of the semiconductor device configuration. This is a side cross-sectional view showing a sixth modified example of the configuration of a semiconductor device. This is a side cross-sectional view showing a seventh modified example of the configuration of a semiconductor device. This is a side cross-sectional view showing an eighth modified example of the configuration of a semiconductor device. This is a side cross-sectional view showing a ninth modified example of the configuration of a semiconductor device. This is an enlarged cross-sectional view of the vicinity of the gate region of the semiconductor device. This is a first diagram illustrating a method for connecting contact vias and external wiring. This is a second diagram illustrating a method for connecting contact vias and external wiring. This is a diagram showing an example of the configuration of a semiconductor layer. This is a block diagram showing an example of the configuration of an imaging device as an electronic device to which the technology of this disclosure is applied. This is a diagram showing an example of use using a solid-state imaging device. This is a diagram showing an example of the schematic configuration of an endoscopic surgical system. This is a block diagram showing an example of the functional configuration of a camera head and a CCU. This is a block diagram showing an example of the schematic configuration of a vehicle control system. This is an explanatory diagram showing an example of the installation position of an external information detection unit and an imaging unit.

[0010] The following describes the forms in which this technology can be implemented. In the drawings referenced in the following description, identical or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from reality. Therefore, specific thicknesses and dimensions should be determined by referring to the following description. Furthermore, it goes without saying that there may be parts where the relationships and ratios of dimensions differ between drawings.

[0011] In this specification, the "+" and "-" prefixes attached to "n" and "p" indicate semiconductor regions with relatively higher or lower impurity concentrations, respectively, compared to semiconductor regions without these prefixes. However, even if two semiconductor regions are labeled with the same "n," this does not mean that their impurity concentrations are exactly the same.

[0012] Furthermore, the definitions of directions such as up and down in the following explanation are merely for explanatory convenience and do not limit the technical concept of this technology. For example, it is obvious that if an object is rotated 90 degrees and observed, up and down will be converted to left and right, and if it is rotated 180 degrees and observed, up and down will be inverted and read.

[0013] <Example of Photodetector Configuration> Figure 1 shows an example of the configuration of one embodiment of a photodetector to which this technology is applied.

[0014] The photodetector element 1 in Figure 1 is constructed on a semiconductor substrate 2 made of, for example, silicon (Si) as a semiconductor, and has a pixel array section 3 and a peripheral circuit section around it. The peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a reference signal generation circuit 6, a horizontal drive circuit 7, a timing control circuit 8, and the like.

[0015] The pixel array section 3 is composed of multiple pixels 41 arranged in an array and receives light focused by an optical system (not shown). The multiple pixels 41 sequentially output pixel signals corresponding to the amount of light they received, at timings selected by the vertical drive circuit 4, to the column signal processing circuit 5 via the vertical signal wiring 22.

[0016] Pixel 41 has a photoelectric conversion unit that generates and stores an electric charge corresponding to the amount of light received, and a plurality of pixel transistors (so-called MOS transistors). As an example of the circuit configuration of pixel 41, for example, the configuration described later with reference to Figure 2 can be adopted.

[0017] The vertical drive circuit 4 sequentially supplies drive signals to each pixel 41 via the horizontal signal wiring 21 for driving (transferring, selecting, resetting, etc.) each pixel 41 in each row of the multiple pixels 41 arranged in the pixel array section 3.

[0018] The column signal processing circuit 5 performs CDS (Correlated Double Sampling) processing on the pixel signals output from a plurality of pixels 41 arranged in the pixel array section 3 via vertical signal wiring 22, thereby performing AD (Analog to Digital) conversion on each column of pixels 41 in parallel and removing reset noise. As shown in Figure 1, the column signal processing circuit 5 is configured to have a number of AD converters 42 corresponding to the number of columns of the plurality of pixels 41 arranged in the pixel array section 3, and each AD converter 42 is configured to have a comparator 61, a counter 62, and a latch 63.

[0019] In the AD converter 42, the RAMP signal supplied from the reference signal generation circuit 6 and the pixel signal supplied from the pixel 31 via the vertical signal wiring 22 are input to the comparator 61. The comparator 61 compares the magnitude relationship between the RAMP signal and the pixel signal and outputs an OUT signal to the counter 62 indicating the timing when their magnitude relationship is reversed. The counter 62 starts counting from the timing when the RAMP signal begins to change at a predetermined slope, and obtains the count value up to the timing when the magnitude relationship between the RAMP signal and the pixel signal is reversed as the result of AD conversion of the pixel signal, and supplies it to the latch 63. The latch 63 holds the AD-converted pixel signal supplied from the counter 62 and sequentially outputs the held pixel signal to the data output signal wiring 23 at timings selected by the horizontal drive circuit 7.

[0020] The reference signal generation circuit 6 generates a RAMP signal (reference signal) that is referenced when the AD converter 42 performs AD conversion of the pixel signal, and supplies it to the comparator 61 of the AD converter 42.

[0021] The horizontal drive circuit 7 supplies a drive signal to the latch 63 of the column signal processing circuit 5, which causes the sequentially A / D converted pixel signals of each row of multiple pixels 41 arranged in the pixel array section 3 to be output to the data output signal wiring 23.

[0022] The timing control circuit 8 controls the timing of each block's operation by generating and supplying clock signals according to the drive cycle of each block of the photodetector 1. For example, the timing control circuit 8 can control the slope of the RAMP signal generated in the reference signal generation circuit 6, or the on / off state of the switch (Figure 3) provided in the comparator 61.

[0023] The photodetector element 1 configured as described above has a structure called a column AD method, in which column signal processing circuits 5 that perform CDS processing and AD conversion processing are arranged for each pixel row. Furthermore, the photodetector element 1 is a back-illuminated photodetector element in which light is incident from the back side opposite to the front side of the semiconductor substrate 2 on which the pixel transistors are formed.

[0024] The photodetector 1 generates a pixel signal corresponding to the amount of light received by each pixel 41 of the pixel array 3 and outputs it to the outside. The photodetector 1 can be used, for example, as a light-receiving device in a solid-state imaging device that detects the distribution of incident light amounts of visible light or infrared light and captures it as an image, or as a light-receiving device in a distance measuring system that receives light (reflected light) reflected from an object when infrared light is irradiated as active light, and measures the distance to the subject using a direct ToF or indirect ToF method.

[0025] Figure 2 shows an example of the circuit configuration of pixel 41.

[0026] Each pixel 41 is composed of a photodiode PD, a transfer transistor TG, a floating diffusion transistor FD, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. The transfer transistor TG, reset transistor RST, amplification transistor AMP, and selection transistor SEL are, for example, n-type MOS transistors (MOSFETs: Metal Oxide Semiconductor Field Effect Transistors). In addition, a constant current source IS is connected to a vertical signal wiring 22 shared by each pixel row in order to extract the signal from the pixel 41 as a voltage fluctuation.

[0027] A photodiode PD is a photoelectric conversion unit that converts incident light into photoelectric energy and generates an electric charge (signal charge) corresponding to the amount of incident light received. In a photodiode PD, the cathode is connected to the source of a transfer transistor TG, and the anode is connected to a reference potential wiring (e.g., ground).

[0028] The transfer transistor TG controls the transfer of charge generated by the photodiode PD. When the transfer transistor TG is turned on, it transfers the charge generated by the photodiode PD to the floating diffusion FD. In the transfer transistor TG, the drain is connected to the floating diffusion FD and the gate is connected to the horizontal signal wiring 21.

[0029] The floating diffusion transistor (FD) is a charge storage unit that temporarily stores the charge transferred from the photodiode (PD), and also a charge-voltage conversion unit that generates a voltage corresponding to the amount of charge. The floating diffusion transistor (FD) is connected to the gate of the amplification transistor (AMP) and the source of the reset transistor (RST).

[0030] When a reset signal is supplied to the gate of the reset transistor RST via the horizontal signal wiring 21 and it turns on, it resets the potential of the floating diffusion FD to the potential of the power wiring VDD. The reset transistor RST is connected between the power wiring VDD and the floating diffusion FD.

[0031] The amplification transistor AMP generates a signal with a voltage corresponding to the level of charge accumulated in the floating diffusion FD as a pixel signal. The amplification transistor AMP is connected in series with the selection transistor SEL and connected to the vertical signal wiring 22 via the selection transistor SEL. The amplification transistor AMP, together with the constant current source IS, constitutes a source follower. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to that potential to the column signal processing circuit 5 via the vertical signal wiring 22. In the amplification transistor AMP, the drain is connected to the power supply wiring VDD, and the source is connected to the drain of the selection transistor SEL.

[0032] The selection transistor SEL controls the output timing of the pixel signal. In the selection transistor SEL, the source is connected to the vertical signal wiring 52 and the gate is connected to the pixel drive wiring. When the selection signal is supplied to the gate of the selection transistor SEL via the horizontal signal wiring 21 and it turns on, it outputs the pixel signal from the amplification transistor AMP to the vertical signal wiring 22.

[0033] The circuit configuration described above is just one example of a pixel 41 circuit configuration, and other configurations may be adopted. For example, in the circuit configuration shown in Figure 2, a floating diffusion FD, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL are provided in a one-to-one relationship with the photodiode PD and transfer transistor TG provided in each pixel 41 as a readout circuit. However, one set of readout circuits may be provided for the photoelectric conversion section of multiple pixels 41. For example, a photodiode PD and transfer transistor TG may be provided for each pixel 41, and a configuration in which readout circuits are provided in units of multiple pixels such as 2 pixels, 4 pixels, or 8 pixels may be adopted.

[0034] Figure 3 shows an example of the circuit configuration of the comparator 61.

[0035] As shown in Figure 3, the comparator 61 is configured with a differential amplifier circuit that includes differential input transistors T21 and T22 constituting a differential pair, and active load transistors T11 and T12 constituting a current mirror circuit. The differential input transistors T21 and T22 are composed of MOSFETs (for example, n-type MOSFETs (hereinafter also referred to as NMOS)). The active load transistors T11 and T12 are composed of MOSFETs (for example, p-type MOSFETs (hereinafter also referred to as PMOS)).

[0036] Two differential input terminals of the comparator 61 are connected in series to sampling capacitors C1 and C2, respectively. One end of sampling capacitor C1 is connected to the signal wiring for inputting the RAMP signal output from the reference signal generation circuit 6 to the comparator 61, and the other end is connected to the gate terminal of the differential input transistor T21.

[0037] The drain of the differential input transistor T21 is connected to the power supply wiring VDD via the active load transistor T11. The drain of the differential input transistor T21 is also connected to the gate of the differential input transistor T21 via an auto-zero switch S1. The source of the differential input transistor T21 is connected to a reference potential wiring (e.g., ground) via a constant current source.

[0038] One end of the sampling capacitor C2 is connected to the vertical signal wiring 22 for inputting the pixel signal Vsig output from the pixel 41 to the comparator 61, and the other end is connected to the gate of the differential input transistor T22.

[0039] The drain of the differential input transistor T22 is connected to the power supply wiring VDD via the active load transistor T12. The drain of the differential input transistor T22 is also connected to the gate of the differential input transistor T22 via the auto-zero switch S2. The source of the differential input transistor T22 is connected to the reference potential wiring via a constant current source.

[0040] The comparator 61 configured as described above compares the magnitude relationship between the RAMP signal input to the gate of the differential input transistor T22 and the pixel signal input to the gate of the differential input transistor T21. The comparator 61 outputs a signal Vn indicating the timing at which the magnitude relationship of these signals is inverted from the connection point between the active load transistor T12 and the differential input transistor T22. The signal Vn is amplified by a PMOS and output to the counter 62 as an Out signal Vout.

[0041] Incidentally, in the peripheral circuit section of the photodetector element 1, the differential input transistors T21 and T22 tend to become noise sources. Due to RTS (Random Telegraph Signal) noise generated in the differential input transistors T21 and T22, as shown in FIG. 4, vertical streak noise may appear in a captured image captured by the photodetector element 1.

[0042] It is known that RTS noise is inversely proportional to the element area of a differential input transistor (MOSFET). Therefore, as a countermeasure against RTS noise, increasing the element area of the differential input transistor has been considered. However, in recent years, demand for pixel miniaturization and increased pixel count has grown, and it is desired to suppress the generation of RTS noise by means other than increasing the element area of the differential input transistor.

[0043] In response to such a demand, as shown in FIG. 5, a semiconductor device 100A having a structure (FG=BG structure) in which a gate region (FG) 121 and a p-type well 103 constituting a back gate region (BG) are electrically connected (shared) via metal contacts and multilayer wiring has been proposed.

[0044] As shown in FIG. 5, an n-type well 102 and a p-type well 103 are formed on a p-type semiconductor substrate 101. An STI (Shallow Trench Isolation) 104 that defines an active region of the semiconductor device 100A is formed in a part of an upper portion of the p-type well 103.

[0045] In the example of FIG. 5, the STI 104 forms an n +An active region in which a source region 122 and a drain region 123 of type p are formed, and a p is formed at the top of the p-type well 103. + An active region is defined in which a p-type well tap region 124 is formed. The well tap region 124 is a region for connecting the p-type well 103 and the metal contact. A gate region 121 is formed on the p-type well 103 of the active region in which a source region 122 and a drain region 123 are formed.

[0046] Directly beneath the STI 104, an n-type well 105 is formed to electrically isolate the p-type well 103 between adjacent semiconductor devices 100A.

[0047] Figure 6 compares the flicker noise spectra for a MOSFET with a standard structure (where the gate region and back gate region are not shared) and a MOSFET with an FG=GB structure.

[0048] As shown in Figure 6, by using an FG=GB structure for the MOSFET, the gate-referred noise (Svg) can be reduced by approximately half compared to the case where the MOSFET has a standard structure.

[0049] Figure 7 compares the distribution of RTS noise and transconductance when the MOSFET is in a standard structure and when the MOSFET is in an FG=GB structure.

[0050] As shown in Figure 7A, by using an FG=GB structure for the MOSFET, the generation of RTS noise can be suppressed compared to when the MOSFET has a standard structure.

[0051] Furthermore, as shown in Figure 7B, by making the MOSFET an FG=GB structure, the transconductance of the MOSFET can be increased by approximately 16% compared to when the MOSFET has a standard structure.

[0052] Figure 8 compares the device area and parasitic capacitance of a semiconductor device when the MOSFET is in a standard structure and when the MOSFET is in an FG=GB structure.

[0053] When a MOSFET has a standard structure, as shown in the upper part of Figure 8, the p-type wells 103 that constitute the back gate region and the well-tapped regions 124 that constitute the back gate terminals are shared among multiple semiconductor devices 100A-1, 100A-2, ... On the other hand, when a MOSFET has an FG=GB structure, as shown in the lower part of Figure 8, it is necessary to separate the p-type wells 103 for each semiconductor device and form the well-tapped regions 124 for each semiconductor device.

[0054] Therefore, when the MOSFET has an FG=GB structure, the area of ​​the column signal processing circuit 5 where the semiconductor devices 100A-1, 100A-2, ... are provided becomes larger compared to when the MOSFET has a standard structure. Also, when the MOSFET has an FG=GB structure, parasitic capacitance occurs between the source region 122 and the back gate region, and between the source region 122 and the back gate terminal, compared to when the MOSFET has a standard structure.

[0055] In addition, parasitic capacitance occurs between the gate region 121 and the source region 122, whether the MOSFET has a standard structure or a FG=GB structure.

[0056] This technology was developed in view of the above circumstances, and by forming a first insulating film that defines a channel region between a source region and a drain region in a semiconductor device, a gate region formed on the channel region, a first semiconductor region separated from adjacent semiconductor devices, and a contact that penetrates the first insulating film to connect the gate region and the first semiconductor region and is connected to external wiring, it is possible to reduce noise without increasing the element area of ​​the semiconductor device or increasing parasitic capacitance.

[0057] <Example of Transistor Configuration> Figure 9 shows an example of the configuration of a semiconductor device 100 as a transistor according to one embodiment of this technology. Hereinafter, the surface on which the gate region 121, source region 122, and drain region 123 are formed will also be called the front surface of the semiconductor device 100, and the surface opposite to the front surface will also be called the back surface. Viewing the semiconductor device 100 from a direction perpendicular to the front or back surface (substrate thickness direction) will also be called a plan view, and viewing the semiconductor device 100 from a direction parallel to the front or back surface will also be called a cross-sectional view. Figure 9 shows a plan view of the semiconductor device 100 as seen from the front surface side.

[0058] As shown in Figure 9, the semiconductor device 100 includes a p-type well 103, part of which constitutes a channel region, an STI 104 that defines the channel region of the semiconductor device 100, a gate region 121, a source region 122, and a drain region 123.

[0059] In the semiconductor device 100, for example, the portion of the p-type well 103 surrounded by the STI 104 and formed between the source region 122 and the drain region constitutes the channel region, and the remaining portion of the p-type well 103 constitutes the back gate region. The channel region is the region in which the channel between the source and drain of the semiconductor device 100 is formed.

[0060] The gate region 121 is formed so as to overlap, in a plan view, with the p-type well 103 (channel region) between the source region 122 and the drain region 123 and a portion of the STI 104.

[0061] In the portion of the gate region 121 that overlaps with a part of the STI 104, a contact via 151 is formed that penetrates at least the STI 104. A metal contact 161 is formed on the contact via 151. In addition, a metal contact 162 is formed on the source region 122, and a metal contact 163 is formed on the drain region 123.

[0062] Figure 10 is a side cross-sectional view showing an example of the configuration of the semiconductor device 100. Figure 10A shows an example of the A-A' section in Figure 9, in other words, a side cross-section in the gate length direction (the direction connecting the source region 122 and the drain region 123). Figure 10B shows an example of the B-B' section in Figure 9, in other words, a side cross-section in the gate width direction (the direction perpendicular to the gate length direction).

[0063] As shown in Figure 10, the semiconductor device 100 comprises a semiconductor substrate 101 which is a p-type silicon substrate, an n-type semiconductor region 102 which is an n-type well formed on the semiconductor substrate 101, and a p-type semiconductor region 103 which is a p-type well formed on the n-type well 102. An STI 104 is formed in a part of the upper part of the p-type well 103.

[0064] The STI 104 is constructed by embedding an insulating material, such as silicon oxide (SiO2) or a silicon-based oxide or nitride, in a trench formed to a predetermined depth from the front surface of the p-type well 103. As described above, the STI 104 is an insulating film (first insulating film) that defines the channel region.

[0065] As shown in Figure 10A, the upper part of the p-type well 103 is n + The source region 122 and drain region 123 of the type are formed spaced apart from each other. A gate region 121 is formed on the p-type well 103 (channel region) between the source region 122 and the drain region 123, with a gate insulating film 181 in between. The gate region 121 is formed of polysilicon or a metallic material with a high impurity concentration.

[0066] Directly beneath the STI 104, an n-type well 105 is formed to electrically isolate the lower part of the p-type well 103 that constitutes the back gate region between adjacent semiconductor devices 100. As shown in Figure 10A, the width of the n-type well 105 in the gate length direction is approximately the same as the width of the STI 104 in the gate length direction. On the other hand, as shown in Figure 10B, the width of the n-type well 105 in the gate width direction is smaller than the width of the STI 104 in the gate width direction. That is, in the side cross-section in the gate width direction, a part of the lower part of the p-type well 103 and the n-type well 105 are formed side by side directly beneath the STI 104.

[0067] In example B of Figure 10, the contact via 151 penetrates the gate region 121 and the STI 104, and is formed to a depth where the bottom surface of the contact via 151 reaches the interior (lower part) of the p-type well 103. In the semiconductor device 100, the contact via 151 electrically connects the gate region 121 and the p-type well 103. Such a contact is also called a shared contact.

[0068] An impurity region 152 is formed in the portion of the p-type well 103 that contacts the contact via 151, for connecting the p-type well 103 and the contact via 151. The impurity region 152 has a higher impurity concentration than the p-type well 103. + It is composed of at least one of a semiconductor region and a silicide layer.

[0069] As described above, by simply forming a contact via 151 that penetrates the gate region 121 and the STI 104 and reaches a depth where its bottom surface reaches the inside of the p-type well 103, the gate region 121 and the p-type well 103 can be made common, i.e., an FG=GB structure can be realized. Since the semiconductor device 100 does not need to have a separate back gate terminal, it is possible to realize an FG=GB structure and reduce noise without increasing the element area. Furthermore, since the gate region 121 and the p-type well 103 are connected to the metal contact 161 via a common contact via 151, it is possible to realize an FG=GB structure and reduce noise without increasing parasitic capacitance.

[0070] Furthermore, the semiconductor device 100 described with reference to Figures 9 and 10 can be applied, for example, to the differential input transistor of the comparator 61 (Figure 1) of the column signal processing circuit 5.

[0071] Figure 11 shows an example of the circuit configuration of a comparator 61 to which this technology is applied. In Figure 11, components identical to those in Figure 3 are denoted by the same reference numerals. Repetitive explanations are omitted as appropriate.

[0072] The comparator 61 in Figure 11 differs from the comparator 61 in Figure 3 in that it is equipped with differential input transistors T51 and T52 instead of differential input transistors T21 and T22.

[0073] The differential input transistors T51 and T52 are composed of MOSFETs (e.g., NMOS) whose gates and back gates are electrically connected by contact vias 151 (Figure 9 or Figure 10). The gate of differential input transistor T51 is connected to a signal line that transmits the RAMP signal, for example, via contact vias 151 and metal contact 161. The gate of differential input transistor T52 is connected to a signal line that transmits the pixel signal Vsig, for example, via contact vias 151 and metal contact 161.

[0074] Since the generation of RTS noise is suppressed in the differential input transistors T51 and T52, vertical streak noise is less likely to appear in the image captured by the photodetector 1. Note that the differential input transistors T51 and T52 are examples of the use of the semiconductor device 100 in this technology, and the semiconductor device 100 may also be used as other transistors constituting the comparator 61, or as transistors mounted in devices other than the comparator 61.

[0075] Figure 12 is a side cross-sectional view showing a first modified example of the configuration of the semiconductor device 100, regarding the depth of the bottom surface of the contact via.

[0076] As shown in Figure 12, the contact via 151 may extend from the front side of the semiconductor device 100, through the gate region 121 and the STI 104, and be formed up to the (lower) interface between the STI 104 and the p-type well 103.

[0077] Figure 13, an example in which a contact via is formed between the gate region and the p-type well, is a side cross-sectional view showing a second modified configuration of the semiconductor device 100.

[0078] As shown in Figure 13, the contact via 151 may extend from the interface between the gate region 121 and the gate insulating film 181, through the gate insulating film 181 and the STI 104, and be formed to a depth where the bottom surface of the contact via 151 reaches the interior of the p-type well 103.

[0079] In this case as well, the gate region 121 and the p-type well 103 are electrically connected by the contact via 151. The metal contact 161 is formed on the gate region 121. In other words, the p-type well 103 and the contact via 151 are connected to the metal contact 161 via the gate region 121.

[0080] Regarding the configuration of the contact vias, Figure 14 is a diagram illustrating an example of the configuration of a contact via 151.

[0081] As shown in Figure 14, the contact via 151 is composed of a metal film 201, such as tungsten (W), cobalt (Co), or ruthenium (Ru), and a barrier metal 202, such as titanium nitride (TiN), formed to cover the bottom and sides of the metal film 201. In the example in Figure 14, the barrier metal 202 and the impurity region 152 are in contact.

[0082] Alternatively, the barrier metal 202 may not be formed, and the metal film 201 and the impurity region 152 may be in contact. Alternatively, the impurity region 152 may not be formed, and the p-type well 103 and the contact via 151 may be directly connected.

[0083] Figure 15 illustrates a modified configuration of the contact via 151.

[0084] The contact via 151 may be composed of multiple layers, including the metal film 201 and the barrier metal 202, as well as other films.

[0085] In example A of Figure 15, an interlayer 203 is formed between the barrier metal 202 and the STI 104 (p-type well 103). The interlayer 203 is formed from titanium oxide (TiO3) or lanthanum oxide (La2O3), and can reduce the Schottky barrier between the metal and the semiconductor. In example A of Figure 15, the impurity region 152 is not formed, and the p-type well 103 and the contact via 151 are directly connected.

[0086] In example B of Figure 15, an interlayer 204 is formed between the metal film 201 and the barrier metal 202. The interlayer 204 is formed of tungsten containing boron (B), which allows for a larger particle size of the tungsten forming the metal film 201, thereby reducing the resistance of the contact via 151 itself. In example B of Figure 15, the barrier metal 202 and the impurity region 152 are in contact.

[0087] Figure 16, an example where the contact vias are formed from the same material as the gate region, is a side cross-sectional view showing a third modified configuration of the semiconductor device 100.

[0088] As shown in Figure 16, the gate region 121 and the contact via 151 may be formed integrally. In the example in Figure 16, the gate region 121 and the contact via 151 are formed of polysilicon. In this case, the impurity region 152 is, for example, p + It is composed of semiconductor regions of a certain type.

[0089] Figure 17 is a side cross-sectional view showing a fourth modified configuration of the semiconductor device 100.

[0090] In the example in Figure 17, as in the example in Figure 16, the gate region 121 and the contact via 151 are formed integrally. In the example in Figure 17, the gate region 121 and the contact via 151 are composed of multiple layers, including a metal film 211 as a filler and a metal film 212 called a work function metal.

[0091] The metal film 211 is formed from tungsten or the like, and the metal film 212 is formed from titanium nitride, titanium-aluminum alloy (TiAl), tantalum nitride (TaN), TiOC, or the like. A high dielectric constant insulating film (not shown) is formed between the metal film 212 and the gate insulating film 181. Such a gate is called a High-k metal gate.

[0092] Regarding the conductivity type of the channel region (back gate region), the semiconductor device 100 may be composed of either NMOS or PMOS. In other words, the conductivity type of the semiconductor region constituting the channel region (back gate region) can be either p-type or n-type. Furthermore, the conductivity type of the semiconductor substrate stacked on the semiconductor region constituting the channel region (back gate region) can also be either p-type or n-type.

[0093] Figure 18 is a side cross-sectional view showing a fifth modified configuration of the semiconductor device 100. Figure 18 shows an example configuration where the semiconductor device 100 is composed of NMOS.

[0094] In the example shown in Figure 18A, the semiconductor device 100 includes a semiconductor substrate 101 which is a p-type silicon substrate, an n-type well 102 which is an n-type semiconductor region formed on the semiconductor substrate 101, and a p-type well 103 which is a p-type semiconductor region formed on the n-type well 102. As described above, the upper part of the p-type well 103 constitutes a channel region, and the lower part constitutes a back gate region. An STI 104 is formed in a part of the upper part of the p-type well 103, and an n-type well 105 is formed between the STI 104 and the n-type well 102 to electrically isolate the lower part of the p-type well 103 between adjacent semiconductor devices 100.

[0095] In the example shown in Figure 18B, the semiconductor device 100 comprises a semiconductor substrate 251 which is an n-type silicon substrate and a p-type well 103 which is a p-type semiconductor region formed on the semiconductor substrate 251. An STI 104 is formed in a part of the upper part of the p-type well 103, and an n-type well 105 is formed between the STI 104 and the semiconductor substrate 251 to electrically isolate the lower part of the p-type well 103 between adjacent semiconductor devices 100.

[0096] In the example shown in Figure 18C, the semiconductor device 100 comprises a semiconductor substrate 251 which is an n-type silicon substrate, a well 252 which is a semiconductor region formed on the upper part of the semiconductor substrate 251, and a p-type well 103 which is a p-type semiconductor region formed on the well 252. The well 252 is either a p-type semiconductor region or an n-type semiconductor region with an impurity concentration higher or lower than that of the semiconductor substrate 251. An STI 104 is formed in a part of the upper part of the p-type well 103, and an n-type well 105 is formed between the STI 104 and the semiconductor substrate 251 and well 252 to electrically isolate the lower part of the p-type well 103 between adjacent semiconductor devices 100.

[0097] If the p-type wells 103 are electrically isolated between the semiconductor devices 100, multiple semiconductor regions may be formed between the p-type wells 103 and the semiconductor substrate.

[0098] Figure 19 is a side cross-sectional view showing a sixth modified configuration of the semiconductor device 100. Figure 19 shows an example configuration where the semiconductor device 100 is composed of PMOS.

[0099] In the example shown in Figure 19A, the semiconductor device 100 comprises a semiconductor substrate 101 which is a p-type silicon substrate, and an n-type well 271 which is an n-type semiconductor region formed on the semiconductor substrate 101. The upper part of the n-type well 271 constitutes a channel region, and the lower part constitutes a back gate region. An STI 104 is formed in a part of the upper part of the n-type well 271, and a p-type well 272 is formed between the STI 104 and the semiconductor substrate 101 to electrically isolate the lower part of the n-type well 271 between adjacent semiconductor devices 100. The p-type well 272 is a p-type semiconductor region.

[0100] In the example shown in Figure 19B, the semiconductor device 100 comprises a semiconductor substrate 101 which is a p-type silicon substrate, a well 273 which is a semiconductor region formed on the upper part of the semiconductor substrate 101, and an n-type well 271 which is an n-type semiconductor region formed on the well 273. The well 273 is either an n-type semiconductor region or a p-type semiconductor region with an impurity concentration higher or lower than that of the semiconductor substrate 101. An STI 104 is formed in a part of the upper part of the n-type well 271, and a p-type well 272 is formed between the STI 104 and the semiconductor substrate 101 and well 273 to electrically isolate the n-type well 271 between adjacent semiconductor devices 100.

[0101] In the example shown in Figure 19C, the semiconductor device 100 includes a semiconductor substrate 251 which is an n-type silicon substrate, a p-type well 274 which is a p-type semiconductor region formed on the semiconductor substrate 251, and an n-type well 271 which is an n-type semiconductor region formed on the p-type well 274. An STI 104 is formed in a part of the upper part of the n-type well 271, and a p-type well 272 is formed between the STI 104 and the p-type well 274 to electrically isolate the lower part of the n-type well 271 between adjacent semiconductor devices 100.

[0102] If the n-type wells 271 are electrically isolated between the semiconductor devices 100, multiple semiconductor regions may be formed between the n-type wells 271 and the semiconductor substrate.

[0103] As explained with reference to Figures 18 and 19, the first semiconductor region constituting the back gate region (the lower part of the p-type well 103 and the lower part of the n-type well 271) is separated from the adjacent semiconductor device 100 by semiconductor regions with the opposite conductivity type to the first semiconductor region (the n-type well 105 and the p-type well 272).

[0104] Figure 20, an example showing complete separation of semiconductor devices 100 with an insulating film, is a side cross-sectional view illustrating a seventh modified configuration of the semiconductor device 100.

[0105] In the example shown in Figure 20A, a Full Trench Isolation (FTI) 311 is formed directly beneath the STI 104, which is an insulating film (second insulating film) for electrically separating the lower part of the p-type well 103 from the semiconductor substrate 101 stacked on the p-type well 103 between adjacent semiconductor devices 100. The FTI 311 is constructed by embedding an insulating material, such as silicon oxide or a silicon-based oxide or nitride, in a trench that penetrates from the bottom surface of the STI 104 to the back surface of the semiconductor substrate 101.

[0106] The element isolation film 312, composed of continuous STI 104 and FTI 311, completely separates adjacent semiconductor devices 100. The width of the FTI 311 in the gate width direction is smaller than the width of the STI 104 in the gate width direction. That is, in the side cross-section in the gate width direction, the lower part of the p-type well 103 and the FTI 311 are formed side by side directly below the STI 104.

[0107] In example A of Figure 20, the contact via 151 penetrates the gate region 121 and the STI 104, and is formed to a depth where the bottom surface of the contact via 151 reaches the interior of the p-type well 103.

[0108] As shown in Figure 20B, the contact via 151 may be formed such that one half of the bottom (tip) of the contact via 151 is embedded in the FTI 311, and the other half is in contact with the p-type well 103 (impurity region 152).

[0109] Furthermore, if the element isolation film 312 completely separates adjacent semiconductor devices 100, it is optional whether or not to form an n-type well 102 between the semiconductor substrate 101 and the p-type well 103.

[0110] Figure 21 is a side cross-sectional view showing an eighth modified example of the configuration of the semiconductor device 100, in which an insulating layer (BOX layer) is formed between the back gate region and the semiconductor substrate.

[0111] As shown in Figure 21A, an insulating layer (third insulating film) 331 may be formed between the semiconductor substrate 101 and the p-type well 103. In other words, the semiconductor substrate 101 and the p-type well 103 are stacked with the insulating layer 331 in between.

[0112] In the example shown in Figure 21A, a DTI (Deep Trench Isolation) 341, which is an insulating film (second insulating film) for electrically isolating the lower part of the p-type well 103 between adjacent semiconductor devices 100, is formed between the STI 104 and the insulating layer 331. The DTI 341 is constructed by embedding an insulating material such as silicon oxide or nitride in a trench formed from the bottom surface of the STI 104 to the interface between the p-type well 103 and the insulating layer 331.

[0113] The element isolation film 342, composed of continuous STI 104 and DTI 341, separates the p-type wells 103 between adjacent semiconductor devices 100. The width of the DTI 341 in the gate width direction is smaller than the width of the STI 104 in the gate width direction. That is, in the side cross-section in the gate width direction, the lower part of the p-type well 103 and the DTI 341 are formed side by side directly below the STI 104.

[0114] In example A of Figure 21, the contact via 151 penetrates the gate region 121 and the STI 104, and is formed to a depth where the bottom surface of the contact via 151 reaches the interior of the p-type well 103.

[0115] When an insulating layer 331 is formed between the semiconductor substrate 101 and the p-type well 103, the FTI 311 may be formed directly beneath the STI 104, as shown in Figure 21B.

[0116] In the example shown in Figure 21B, the contact via 151 is formed such that one half of the bottom of the contact via 151 is embedded in the FTI 311, and the other half is in contact with the p-type well 103.

[0117] Figure 22, an example showing that the gate region and the semiconductor substrate are electrically connected by contact vias, is a side cross-sectional view illustrating a ninth modified configuration of the semiconductor device 100.

[0118] Instead of electrically connecting the gate region 121 and the back gate region (the lower part of the p-type well 103 or the lower part of the n-type well 271) via the contact via 151, the gate region 121 may be electrically connected to the semiconductor substrate located on the back side of the semiconductor device 100 via the contact via 151, as shown in Figure 22.

[0119] The semiconductor device 100 shown in Figure 22A comprises a semiconductor substrate 101 which is a p-type silicon substrate (semiconductor region), an insulating layer 331 formed on the semiconductor substrate 101, and a p-type well 103 which is a p-type semiconductor region formed on the insulating layer 331. On the side surface of the p-type well 103, an STI 104 is formed to electrically isolate the p-type well 103 constituting a channel region between adjacent semiconductor devices 100 (for defining the channel region).

[0120] The STI 104 is constructed by embedding insulating material in a trench formed from the front surface of the p-type well 103 to the interface between the p-type well 103 and the insulating layer 331.

[0121] Directly beneath the STI 104, an FTI 345 is formed to electrically isolate the semiconductor substrate 101 from adjacent semiconductor devices 100. The FTI 345 is constructed by embedding an insulating material, such as silicon oxide or nitride, in a trench that penetrates from the bottom surface of the STI 104 through the back surface of the semiconductor substrate 101.

[0122] The element isolation film 346, composed of continuous STI 104 and FTI 345, completely separates adjacent semiconductor devices 100. The width of the FTI 345 in the gate width direction is smaller than the width of the STI 104 in the gate width direction. That is, in the side cross-section in the gate width direction, a part of the insulating layer 331 and the FTI 345 are formed side by side directly beneath the STI 104.

[0123] In example A of Figure 22, the contact via 151 is formed from the front side of the semiconductor substrate 101, penetrating the gate region 121, the STI 104, and the insulating layer 331, and extending to the interface between the insulating layer 331 and the semiconductor substrate 101. The contact via 151 electrically connects the gate region 121 and the semiconductor substrate 101.

[0124] An impurity region 351 is formed in the portion of the semiconductor substrate 101 that contacts the contact via 151, for connecting the semiconductor substrate 101 and the contact via 151. The impurity region 351 has a higher impurity concentration than the semiconductor substrate 101. + It is composed of at least one of a semiconductor region and a silicide layer.

[0125] As shown in Figure 22B, the gate region 121 and the semiconductor substrate 251, which is an n-type silicon substrate, may be electrically connected by contact vias 151.

[0126] In this case, an impurity region 352 is formed in the portion of the semiconductor substrate 251 that contacts the contact via 151, for connecting the semiconductor substrate 251 and the contact via 151. The impurity region 352 has a higher impurity concentration than the semiconductor substrate 251. + It is composed of at least one of a semiconductor region and a silicide layer.

[0127] As described above, the gate region 121 and the semiconductor substrate (first semiconductor region) which is laminated with an insulating layer 311 in between the semiconductor region constituting the channel region (for example, the p-type well 103) may be electrically connected by the contact via 151.

[0128] - Example Figure 23 shows an enlarged cross-sectional view of the vicinity of the gate region 121 of the semiconductor device 100, illustrating the fin structure of the channel region.

[0129] As shown in Figure 23, three fins 103A-1 to 103A-3 extending along the gate length direction may be formed on the upper part of the p-type well 103 that constitutes the back gate region. Each of the fins 103A-1 to 103A-3 is formed in a convex shape such that a part of the p-type well 103 protrudes toward the gate region 121. The fins 103A-1 to 103A-3 constitute a channel region. The number of fins formed on the upper part of the p-type well 103 can be any number.

[0130] The gate region 121 is formed within the insulating film 371 so as to straddle each of the fins 103A-1 to 104-3. The insulating film 371 is an insulating film that constitutes a wiring layer formed on the front surface of the semiconductor device 100, and a portion of it functions as an insulating film (first insulating film) that defines the channel region of the semiconductor device 100. A gate insulating film 181 is formed between the gate region 121 and the fins 103A-1 to 103A-3.

[0131] By employing such a fin structure, the semiconductor device 100 can have characteristics such as faster switching time and higher current density.

[0132] If the channel region (p-type well 103) has a fin structure, the contact via 151 is formed from the interface between the side edge of the gate region 121 and the gate insulating film 181, penetrating the gate insulating film 181 and the insulating film 371, to a depth where the bottom surface of the contact via 151 reaches the interior of the p-type well 103. The contact via 151 electrically connects the gate region 121 and the p-type well 103. The p-type well 103 and the contact via 151 are connected to a metal contact formed on the gate region 121 via the gate region 121.

[0133] An impurity region 152 is formed in the portion of the p-type well 103 that contacts the contact via 151, for connecting the p-type well 103 and the contact via 151. Similar to the example described with reference to Figure 10, the p-type well 103 is formed, for example, on an n-type well 102 formed on a semiconductor substrate 101. Between the insulating film 371 and the n-type well 102, an n-type well 105 is formed to electrically isolate the p-type well 103 between adjacent semiconductor devices 100.

[0134] The contact via 151 may be formed so as to be in contact with the gate region 121 on its side. In this case, the contact via 151 is formed, for example, from a position shallower than the gate region 121 to a depth where its bottom surface reaches the interior of the p-type well 103. A metal contact 161, for example, is formed on the contact via 151.

[0135] The method for connecting contact vias and wiring will be explained by referring to Figures 24 and 25, and will describe how to connect contact via 151 to external wiring.

[0136] In the example shown in Figure 24A, the contact via 151 is connected via a metal contact 161 to a metal wiring 421 (external wiring) in a wiring layer 402 formed on the front surface of a semiconductor layer 401 on which multiple semiconductor devices 100 are formed.

[0137] In example B of Figure 24, the contact via 151 is directly connected to the metal wiring 421 in the wiring layer 402.

[0138] In the example shown in Figure 25A, the contact via 151 is formed from the back side of the semiconductor device 100, penetrating the semiconductor substrate 101, the p-type well 103, the STI 104, the gate insulating film 181, and the gate region 121, all the way to the metal wiring 421 in the wiring layer 402. The contact via 151 is directly connected to the metal wiring 421.

[0139] In the example shown in Figure 25B, the contact via 151 is formed from the back side of the semiconductor device 100, penetrating the semiconductor substrate 101, the p-type well 103, the STI 104, and the gate insulating film 181, up to the interface between the gate insulating film 181 and the gate region 121. The contact via 151 is directly connected to the metal wiring 441 in the wiring layer 403 formed on the back side of the semiconductor layer 401.

[0140] • Semiconductor layer configuration diagram 26 is a diagram showing an example of the configuration of semiconductor layer 401.

[0141] As shown in Figure 26, in the semiconductor layer 401, semiconductor device 100-1, which is composed of PMOS, and semiconductor device 100-2, which is composed of NMOS, may be arranged adjacent to each other. In the example of Figure 25, semiconductor device 100-1 and semiconductor device 100-2 share one gate region 121.

[0142] The contact via 151 of the semiconductor device 100-1 electrically connects the gate region 121 and the n-type well 271. In the semiconductor device 100-1, an impurity region 501 is formed in the portion of the n-type well 271 that is in contact with the contact via 151, for connecting the n-type well 271 and the contact via 151.

[0143] Furthermore, the contact via 151 of the semiconductor device 100-2 electrically connects the gate region 121 and the p-type well 103.

[0144] In this way, multiple semiconductor regions with different conductivity types may be electrically connected to a single gate region 121 by multiple contact vias 151.

[0145] <Examples of application to electronic devices> The above-described photodetector 1 can be applied to various electronic devices, such as imaging devices like digital still cameras and digital video cameras, mobile phones equipped with imaging functions, or other devices equipped with imaging functions.

[0146] Figure 27 is a block diagram showing an example configuration of an imaging device as an electronic device to which the present disclosure applies.

[0147] The imaging device 1001 shown in Figure 27 comprises an optical system 1002, a shutter device 1003, a solid-state imaging device 1004, a drive circuit 1005, a signal processing circuit 1006, a monitor 1007, and a memory 1008, and is capable of capturing still images and moving images.

[0148] The optical system 1002 is composed of one or more lenses and guides light from the subject (incident light) to the solid-state imaging device 1004, where it forms an image on the light-receiving surface of the solid-state imaging device 1004.

[0149] The shutter device 1003 is positioned between the optical system 1002 and the solid-state imaging device 1004, and controls the light irradiation period and light shielding period for the solid-state imaging device 1004 according to the control of the drive circuit 1005.

[0150] The solid-state imaging device 1004 is composed of the photodetector element 1 shown in Figure 1. The solid-state imaging device 1004 accumulates signal charge for a certain period of time in response to light that is imaged onto the light-receiving surface via the optical system 1002 and shutter device 1003. The signal charge accumulated in the solid-state imaging device 1004 is transferred according to the drive signal (timing signal) supplied from the drive circuit 1005.

[0151] The drive circuit 1005 drives the solid-state imager 1004 and the shutter device 1003 by outputting drive signals that control the transfer operation of the solid-state imager 1004 and the shutter operation of the shutter device 1003.

[0152] The signal processing circuit 1006 performs various signal processing operations on the signal charge output from the solid-state imaging device 1004. The image (image data) obtained by the signal processing circuit 1006 is supplied to the monitor 1007 for display or supplied to the memory 1008 for storage (recording).

[0153] Even in the imaging device 1001 configured in this way, by applying the photodetector element 1 shown in Figure 1 as the solid-state imaging device 1004, it becomes possible to capture images with less noise.

[0154] <Example of use of solid-state imaging device> Figure 28 shows an example of use using the photodetector element 1 described above.

[0155] The above-described photodetector 1 can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows.

[0156] - Devices that capture images for viewing purposes, such as digital cameras and portable devices with camera functions. - Devices used for traffic purposes, such as in-vehicle sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. - Devices used in home appliances such as TVs, refrigerators, and air conditioners that capture user gestures and allow device operation according to those gestures. - Devices used for medical and healthcare purposes, such as endoscopes and devices that perform angiography using infrared light reception. - Devices used for security purposes, such as surveillance cameras for crime prevention and cameras for person recognition. - Devices used for beauty purposes, such as skin measuring devices that capture images of skin and microscopes that capture images of the scalp. - Devices used for sports purposes, such as action cameras and wearable cameras for sports use. - Devices used for agriculture, such as cameras that monitor the condition of fields and crops.

[0157] <Examples of application to endoscopic surgical systems> The technology disclosed herein (this technology) can be applied to various products. For example, the technology disclosed herein may be applied to endoscopic surgical systems.

[0158] Figure 29 is a diagram showing an example of a schematic configuration of an endoscopic surgical system to which the technology described herein (the technology) may be applied.

[0159] Figure 29 illustrates a surgeon (physician) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgical system 11000. As shown in the figure, the endoscopic surgical system 11000 consists of an endoscope 11100, other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy treatment device 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 equipped with various devices for endoscopic surgery.

[0160] The endoscope 11100 consists of a barrel 11101, the tip of which is inserted into the body cavity of the patient 11132 for a predetermined length, and a camera head 11102 connected to the base end of the barrel 11101. In the illustrated example, the endoscope 11100 is shown as a so-called rigid endoscope having a rigid barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible endoscope having a flexible barrel.

[0161] An opening into which an objective lens is fitted is provided at the tip of the microscope tube 11101. A light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the tip of the microscope tube by a light guide extending inside the microscope tube 11101, and is irradiated through the objective lens towards the object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a straight-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0162] The camera head 11102 contains an optical system and an image sensor. Reflected light from the object being observed (observation light) is focused onto the image sensor by the optical system. The image sensor converts the observation light into electrical signals, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0163] The CCU 11201 is composed of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and other components, and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various image processing operations on that image signal, such as development processing (demosaic processing), to display an image based on that image signal.

[0164] The display device 11202 displays an image based on an image signal that has been processed by the CCU 11201, under control from the CCU 11201.

[0165] The light source device 11203 is composed of a light source such as an LED (light-emitting diode) and supplies illumination light to the endoscope 11100 when photographing the surgical area, etc.

[0166] The input device 11204 is an input interface for the endoscopic surgical system 11000. The user can input various types of information and instructions to the endoscopic surgical system 11000 via the input device 11204. For example, the user can input instructions to change the imaging conditions (type of light, magnification, focal length, etc.) of the endoscope 11100.

[0167] The treatment instrument control device 11205 controls the drive of the energy treatment instrument 11112 for purposes such as tissue cauterization, incision, or blood vessel sealing. The insufflation device 11206 injects gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity for the purpose of securing a field of view by the endoscope 11100 and securing the operator's workspace. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, images, or graphs.

[0168] The light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical area can be configured as a white light source consisting of, for example, an LED, a laser light source, or a combination thereof. When the white light source is configured as a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to capture images corresponding to each of the RGB colors in time-division by irradiating the observation target with laser light from each of the RGB laser light sources in time-division and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter on the image sensor.

[0169] Furthermore, the light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the drive of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity, images can be acquired in time-division order, and these images can be combined to generate high dynamic range images without so-called black crushing and white clipping.

[0170] Furthermore, the light source device 11203 may be configured to supply light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption in body tissue and irradiating with narrow-band light compared to the irradiation light used during normal observation (i.e., white light), so-called narrow-band imaging is performed to image predetermined tissues such as blood vessels on the surface of mucosa with high contrast. Alternatively, in special light observation, fluorescence observation may be performed to obtain an image from fluorescence generated by irradiation with excitation light. In fluorescence observation, excitation light is irradiated onto body tissue and fluorescence from the body tissue is observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) is injected into body tissue and excitation light corresponding to the fluorescence wavelength of the reagent is irradiated onto the body tissue to obtain a fluorescence image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0171] Figure 30 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in Figure 29.

[0172] The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0173] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and then incident on the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses, including a zoom lens and a focus lens.

[0174] The imaging unit 11402 may consist of one image sensor (a so-called single-chip type) or multiple image sensors (a so-called multi-chip type). If the imaging unit 11402 is configured as a multi-chip type, for example, each image sensor may generate image signals corresponding to RGB, and these may be combined to obtain a color image. Alternatively, the imaging unit 11402 may be configured to have a pair of image sensors for acquiring image signals for the right eye and left eye, respectively, corresponding to 3D (dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical area. In addition, if the imaging unit 11402 is configured as a multi-chip type, multiple lens units 11401 may be provided corresponding to each image sensor.

[0175] Furthermore, the imaging unit 11402 does not necessarily have to be located on the camera head 11102. For example, the imaging unit 11402 may be located inside the lens barrel 11101, directly behind the objective lens.

[0176] The drive unit 11403 is composed of actuators and, under control from the camera head control unit 11405, moves the zoom lens and focus lens of the lens unit 11401 along the optical axis by a predetermined distance. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted as appropriate.

[0177] The communication unit 11404 is composed of communication devices for sending and receiving various types of information with the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0178] Furthermore, the communication unit 11404 receives a control signal from the CCU 11201 to control the drive of the camera head 11102 and supplies it to the camera head control unit 11405. The control signal includes information about imaging conditions, such as information to specify the frame rate of the captured image, information to specify the exposure value at the time of imaging, and / or information to specify the magnification and focus of the captured image.

[0179] The imaging conditions such as frame rate, exposure value, magnification, and focus may be specified by the user as appropriate, or they may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with so-called AE (Auto Exposure), AF (Auto Focus), and AWB (Auto White Balance) functions.

[0180] The camera head control unit 11405 controls the drive of the camera head 11102 based on the control signal received from the CCU 11201 via the communication unit 11404.

[0181] The communication unit 11411 is comprised of a communication device for sending and receiving various types of information with the camera head 11102. The communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400.

[0182] Furthermore, the communication unit 11411 transmits control signals to the camera head 11102 to control the driving of the camera head 11102. Image signals and control signals can be transmitted by telecommunications, optical communications, etc.

[0183] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102.

[0184] The control unit 11413 performs various controls related to imaging the surgical area, etc., by the endoscope 11100, and the display of the images obtained from imaging the surgical area, etc. For example, the control unit 11413 generates a control signal to control the driving of the camera head 11102.

[0185] Furthermore, the control unit 11413 displays the captured image showing the surgical area, etc., on the display device 11202 based on the image signal processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical instruments such as forceps, specific biological sites, bleeding, mist when using the energy treatment device 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When the control unit 11413 displays the captured image on the display device 11202, it may use the recognition results to superimpose various surgical support information onto the image of the surgical area. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can proceed with the surgery reliably.

[0186] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable thereof.

[0187] In the illustrated example, communication was performed via a wired connection using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.

[0188] The above describes an example of an endoscopic surgical system to which the technology of this disclosure may be applied. The technology of this disclosure can be applied to, for example, the endoscope 11100, the camera head 11102 (imaging unit 11402), the CCU 11201 (image processing unit 11412), etc., among the configurations described above. Specifically, for example, the photodetector element 1 according to the above embodiment can be applied to the imaging unit 10402. By applying the technology of this disclosure to the imaging unit 10402, surgical images with less noise can be obtained.

[0189] While an endoscopic surgical system has been described here as an example, the technology described herein may also be applied to other systems, such as microsurgical systems.

[0190] <Examples of application to mobile devices> The technology disclosed herein (this technology) can be applied to various products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0191] Figure 31 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0192] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 31, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0193] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0194] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0195] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0196] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0197] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0198] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0199] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0200] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12030 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0201] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 31, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0202] Figure 32 shows an example of the installation position of the imaging unit 12031.

[0203] In Figure 32, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0204] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0205] Figure 32 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0206] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0207] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0208] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0209] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0210] The above describes an example of a vehicle control system to which the technology of this disclosure may be applied. The technology of this disclosure can be applied to, for example, the imaging unit 12031 of the configuration described above. Specifically, for example, the photodetector element 1 according to the above-described embodiment can be applied to the imaging unit 12031. By applying the technology of this disclosure to the imaging unit 12031, it is possible to provide an image with less noise. Furthermore, by using the obtained image, it becomes possible to reduce driver fatigue and improve the safety of the driver and the vehicle.

[0211] Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also occur.

[0212] <Examples of configuration combinations> This technology can also be configured as follows:

[0213] (1) A semiconductor device comprising: a first insulating film defining a channel region between a source region and a drain region; a gate region formed on the channel region; a first semiconductor region separated from an adjacent semiconductor device; and a contact that penetrates the first insulating film, connecting the gate region and the first semiconductor region, and connected to an external wiring. (2) The semiconductor device according to (1), wherein an impurity region is formed in the portion of the first semiconductor region that is in contact with the contact. (3) The semiconductor device according to (2), wherein the impurity region is composed of at least one of a silicide layer and a semiconductor region having a higher impurity concentration than the first semiconductor region. (4) The semiconductor device according to (1) to (3), wherein the contact is composed of at least a metal film. (5) The semiconductor device according to any one of (4), wherein the contact is composed of a plurality of layers including the metal film and a barrier metal. (6) The semiconductor device according to (5), wherein the contact is composed of a plurality of layers including the metal film, the barrier metal, and an interlayer. (7) The semiconductor device according to any one of (1) to (5), wherein the contact is connected to the external wiring via the gate region. (8) The semiconductor device according to any one of (1) to (7), wherein the first semiconductor region is a semiconductor region in which part constitutes the channel region. (9) The semiconductor device according to (8), wherein the first semiconductor region is separated from an adjacent semiconductor device by a semiconductor region having a conductivity type opposite to that of the first semiconductor region. (10) The semiconductor device according to (8), wherein the first semiconductor region is separated from an adjacent semiconductor device by a second insulating film continuous with the first insulating film. (11) The semiconductor device according to (10), wherein the contact is formed such that one half of the bottom is embedded in the second insulating film and the other half is in contact with the first semiconductor region. (12) The semiconductor device according to any one of (10) or (11), wherein the first semiconductor region is laminated on a semiconductor substrate with a third insulating film in between. (13) The semiconductor device according to any one of (8) to (12), wherein the first semiconductor region has a convex shape that protrudes toward the gate region.(14) The semiconductor device according to any one of (1) to (13), wherein the contact is formed to a depth that penetrates the first insulating film and reaches the interior of the first semiconductor region. (15) The semiconductor device according to any one of (1) to (14), wherein the contact penetrates the first insulating film from the surface opposite to the surface on which the gate region is formed and connects the gate region and the first semiconductor region. (16) The semiconductor device according to any one of (1) to (15), wherein the contact is connected to the external wiring that transmits a reference signal or a pixel signal.

[0214] 1 Photodetector, 2 Semiconductor substrate, 3 Pixel array section, 4 Vertical drive circuit, 5 Column signal processing circuit, 6 Reference signal generation circuit, 7 Horizontal drive circuit, 8 Timing control circuit, 21 Horizontal signal wiring, 22 Vertical signal wiring, 23 Data output signal wiring, 31 Pixel, 41 Pixel, 42 AD converter, 52 Vertical signal wiring, 61 Comparator, 62 Counter, 63 Latch, 100 Semiconductor device, 101 Semiconductor substrate, 102 n-type well, 103 p-type well, 103A-1 to 103A-3 Fins, 105 n-type well, 121 Gate region, 122 Source region, 123 Drain region, 151 Contact via, 152 Impurity region, 161 to 163 Metal contacts, 181 Gate insulating film, 201 Metal film, 202 Barrier metal, 203, 204 Interlayer, 211, 212 Metal film, 251 Semiconductor substrate, 252 Well, 271 n-type well, 272 p-type well, 273 Well, 274 p-type well, 311 Insulating layer, 312 Element isolation film, 331 Insulating layer, 342 Element isolation film, 346 Element isolation film, 351 Impurity region, 352 Impurity region, 371 Insulating film, 401 Semiconductor layer, 402, 403 Wiring layer, 421, 441 Metal wiring, 501 Impurity region, 1001 Imaging device

Claims

1. A semiconductor device comprising: a first insulating film defining a channel region between a source region and a drain region; a gate region formed on the channel region; a first semiconductor region separated from an adjacent semiconductor device; and a contact that penetrates the first insulating film, connects the gate region and the first semiconductor region, and is connected to an external wiring.

2. The semiconductor device according to claim 1, wherein an impurity region is formed in the portion of the first semiconductor region that is in contact with the contact.

3. The semiconductor device according to claim 2, wherein the impurity region is comprised of at least one of a silicide layer and a semiconductor region having a higher impurity concentration than the first semiconductor region.

4. The semiconductor device according to claim 1, wherein the contact is composed of at least a metal film.

5. The semiconductor device according to claim 4, wherein the contact is composed of a plurality of layers including the metal film and a barrier metal.

6. The semiconductor device according to claim 5, wherein the contact is composed of a plurality of layers including the metal film, the barrier metal, and the interlayer.

7. The semiconductor device according to claim 1, wherein the contact is connected to the external wiring via the gate region.

8. The semiconductor device according to claim 1, wherein a portion of the first semiconductor region is a semiconductor region that constitutes the channel region.

9. The semiconductor device according to claim 8, wherein the first semiconductor region is separated from an adjacent semiconductor device by a semiconductor region having a conductivity type opposite to that of the first semiconductor region.

10. The semiconductor device according to claim 8, wherein the first semiconductor region is separated from an adjacent semiconductor device by a second insulating film continuous with the first insulating film.

11. The semiconductor device according to claim 10, wherein one half of the bottom of the contact is embedded in the second insulating film and the other half is in contact with the first semiconductor region.

12. The semiconductor device according to claim 10, wherein the first semiconductor region is laminated on a semiconductor substrate with a third insulating film in between.

13. The semiconductor device according to claim 8, wherein the first semiconductor region has a convex shape that protrudes toward the gate region.

14. The semiconductor device according to claim 1, wherein the contact is formed to a depth that penetrates the first insulating film and reaches the interior of the first semiconductor region.

15. The semiconductor device according to claim 1, wherein the contact connects the gate region and the first semiconductor region by penetrating the first insulating film from the surface opposite to the surface where the gate region is formed.

16. The semiconductor device according to claim 1, wherein the contact is connected to the external wiring that transmits a reference signal or a pixel signal.

Images