Photodetection device and electronic apparatus

Abstract

The present disclosure relates to a photodetection device and an electronic apparatus configured so that reliability can be improved. The photodetection device according to the present disclosure comprises: a semiconductor substrate in which pixels are formed; a processed section formed by executing trench processing in the semiconductor substrate; and a pinning layer provided along the processed section. Between the pinning layer and an N-type semiconductor region forming the semiconductor substrate, the photodetection device has a P-type semiconductor region formed by a P-type impurity. The present disclosure can be applied to, for example, a CMOS image sensor.

Description

Photodetection device and electronic device

[0001] The present disclosure relates to a photodetection device and an electronic device, and particularly relates to a photodetection device and an electronic device configured to improve reliability.

[0002] Patent Document 1 discloses a technology that can provide an image sensor in which the occurrence of noise is suppressed by appropriately arranging a vertical light shielding portion and a horizontal light shielding portion with respect to a photoelectric conversion portion and a charge holding portion arranged in a semiconductor substrate.

[0003] International Publication No. 2024 / 127854

[0004] In the image sensor disclosed in Patent Document 1, there is a risk that reliability may be reduced due to processing variations.

[0005] The present disclosure has been made in view of such circumstances, and is intended to improve reliability.

[0006] The photodetection device of the present disclosure includes: a semiconductor substrate on which pixels are formed; a processed portion formed by trench processing in the semiconductor substrate; and a pinning layer provided along the processed portion, wherein the photodetection device has a P-type semiconductor region formed of P-type impurities between the pinning layer and an N-type semiconductor region forming the semiconductor substrate.

[0007] The electronic device of the present disclosure is an electronic device including a photodetection device, the photodetection device including: a semiconductor substrate on which pixels are formed; a processed portion formed by trench processing in the semiconductor substrate; and a pinning layer provided along the processed portion, wherein the photodetection device has a P-type semiconductor region formed of P-type impurities between the pinning layer and an N-type semiconductor region forming the semiconductor substrate.

[0008] In the present disclosure, in a photodetection device including a semiconductor substrate on which pixels are formed, a processed portion formed by trench processing in the semiconductor substrate, and a pinning layer provided along the processed portion, the photodetection device having a P-type semiconductor region formed of P-type impurities between the pinning layer and an N-type semiconductor region forming the semiconductor substrate, the P-type semiconductor region formed of P-type impurities is provided between the pinning layer and the N-type semiconductor region forming the semiconductor substrate.

[0009] This figure shows an example of the configuration of an image sensor to which the technology relating to this disclosure is applied. This figure shows an example of the circuit configuration of a pixel. This is a side cross-sectional view showing the cross-sectional structure of the image sensor. This is a side cross-sectional view showing an example of the configuration of a light-shielding portion. This is a plan cross-sectional view showing an example of the configuration of a light-shielding portion. This is a plan cross-sectional view showing an example of the configuration of a 2x2 pixel light-shielding portion. This figure illustrates the variation range of the horizontal light-shielding portion. This figure illustrates the flow of the light-shielding portion formation process. This figure illustrates the flow of the light-shielding portion formation process. This figure illustrates the thickness of the P-type semiconductor region. This is a side cross-sectional view showing another example of the configuration of the light-shielding portion. This figure illustrates the thickness of the P-type semiconductor region. This is a side cross-sectional view showing yet another example of the configuration of the light-shielding portion. This figure illustrates the thickness of the P-type semiconductor region. This figure shows an example of a PN junction between a part of the pinning layer and an N-type semiconductor region. This figure shows an example of a PN junction between a part of the pinning layer and an N-type semiconductor region. This figure illustrates the horizontal end face of the horizontal light-shielding portion. This is a side cross-sectional view showing a modified example of the horizontal light-shielding portion. This is a plan cross-sectional view showing a modified example of the horizontal light-shielding portion. This is a side plan cross-sectional view showing a modified example of the horizontal light-shielding portion. This is a plan cross-sectional view showing a modified example of a 2x2 pixel horizontal light-shielding section. This is a diagram illustrating the thickness of the P-type semiconductor region. This is a side cross-sectional view showing an example of the configuration of a pixel-dividing light-shielding section. This is a plan cross-sectional view showing an example of the configuration of a pixel-dividing light-shielding section. This is a plan cross-sectional view showing an example of the configuration of a 2x2 pixel pixel-dividing light-shielding section. This is a diagram showing an example of the configuration of an electronic device to which the technology according to this disclosure is applied.

[0010] The following describes the forms for implementing this disclosure (hereinafter referred to as embodiments). The explanation will be given in the following order.

[0011] 1. Conventional technology and its problems 2. Image sensor of this embodiment 3. Structure and formation process of the light-shielding portion 4. Thickness of the P-type semiconductor region 5. Modified examples 6. Consideration of the thickness of the P-type semiconductor region 7. Structure of the pixel-dividing light-shielding portion 8. Others 9. Example of electronic device configuration

[0012] <1. Conventional Technology and its Problems> Patent Document 1 discloses a technology that enables the provision of an image sensor in which noise generation is suppressed by appropriately arranging a vertical light-shielding section and a horizontal light-shielding section with respect to a photoelectric conversion section and a charge-holding section arranged in a semiconductor substrate.

[0013] In the image sensor disclosed in Patent Document 1, there was a risk that its reliability would decrease due to variations in manufacturing.

[0014] In conventional technology, a horizontal light-shielding portion is formed by wet etching starting from a vertical light-shielding portion formed by dry etching. However, variations in the dry etching and wet etching processes can cause variations in the horizontal length, vertical thickness, and vertical formation position of the horizontal light-shielding portion. In this case, the influence of the potential due to the pinning layer formed along the horizontal light-shielding portion can fluctuate, potentially resulting in a failure of charge transfer if the desired potential shape cannot be obtained.

[0015] In contrast, the technology disclosed herein reduces the influence of variations in processed areas formed by trenching, such as horizontal light-shielding areas, by forming a P-type semiconductor region that covers the processed area, thereby reducing the influence of the potential due to the pinning layer and ultimately improving the reliability of the image sensor.

[0016] <2. Image Sensor of this Embodiment> The image sensor of this embodiment is a global shutter type back-illuminated image sensor such as a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The image sensor of this embodiment receives light from the subject pixel by pixel, converts it into photoelectricity, and generates a pixel signal, which is an electrical signal.

[0017] A global shutter system is a method in which the exposure of all pixels is started and stopped simultaneously. Here, "all pixels" refers to all pixels that form a valid image, excluding dummy pixels and other pixels that do not contribute to image formation. Furthermore, simultaneous exposure is not necessarily required, as long as the image distortion and exposure time differences are small enough not to be problematic. For example, the operation of simultaneously exposing multiple rows (tens of rows, etc.) in units, while shifting them by multiple rows in the row direction, is also included in the global shutter system. Simultaneous exposure of only a portion of the pixel area is also included in the global shutter system.

[0018] A back-illuminated image sensor is an image sensor in which a photoelectric conversion unit, such as a photodiode, which receives light from a subject and converts it into an electrical signal, is arranged for each pixel between the light-receiving surface into which light from the subject enters and the wiring layer on which wiring such as transistors that drive each pixel is provided. The technology disclosed herein can also be applied to image sensors of imaging methods other than CMOS image sensors.

[0019] (Example of image sensor configuration) Figure 1 shows an example of an image sensor configuration to which the technology described herein is applied.

[0020] The image sensor 1 in this embodiment is formed on a semiconductor substrate, and is therefore technically a solid-state image sensor, but hereafter it will simply be referred to as an image sensor.

[0021] The image sensor 1 comprises a pixel array unit 11, a vertical drive unit 12, a ramp wave module 13, a column signal processing unit 14, a clock module 15, a data storage unit 16, a horizontal drive unit 17, a system control unit 18, and a signal processing unit 19.

[0022] The pixel array section 11 has a plurality of pixels 21, each containing a photoelectric conversion element that generates and stores an electric charge corresponding to the amount of light incident from the subject. The plurality of pixels 21 are arranged in both the horizontal (row) and vertical (column) directions, as shown in Figure 1.

[0023] Furthermore, the pixel array section 11 has pixel drive lines 22 and vertical signal lines 23. The pixel drive lines 22 are wired along the row direction for each pixel row, which consists of pixels 21 arranged in a single column in the row direction. The vertical signal lines 23 are wired along the column direction for each pixel column, which consists of pixels 21 arranged in a single column in the column direction.

[0024] The vertical drive unit 12 consists of a shift register, an address decoder, and the like. The vertical drive unit 12 drives all of the multiple pixels 21 in the pixel array unit 11 simultaneously, or drives them row by row, by supplying control signals to each of the multiple pixels 21 via the multiple pixel drive lines 22.

[0025] The ramp wave module 13 generates a ramp wave signal used for A / D (Analog / Digital) conversion of the pixel signal and supplies it to the column signal processing unit 14.

[0026] The column signal processing unit 14 consists of a shift register, an address decoder, and other components, and performs noise reduction processing, correlated double sampling processing, A / D conversion processing, etc., to generate a pixel signal. The column signal processing unit 14 supplies the generated pixel signal to the signal processing unit 19.

[0027] The clock module 15 supplies clock signals for operation to each part of the image sensor 1.

[0028] The horizontal drive unit 17 sequentially selects the unit circuits corresponding to the pixel rows of the column signal processing unit 14. Through the selective scanning by the horizontal drive unit 17, the pixel signals processed for each unit circuit in the column signal processing unit 14 are sequentially output to the signal processing unit 19.

[0029] The system control unit 18 consists of a timing generator that generates various timing signals. Based on the timing signals generated by the timing generator, the system control unit 18 controls the drive of the vertical drive unit 12, ramp wave module 13, column signal processing unit 14, clock module 15, and horizontal drive unit 17.

[0030] The signal processing unit 19, if necessary, temporarily stores data in the data storage unit 16, performs signal processing such as calculations on the pixel signals supplied from the column signal processing unit 14, and outputs an image signal consisting of each pixel signal.

[0031] The image sensor 1 is composed of one or more semiconductor substrates. For example, it is possible to form the vertical drive unit 12, ramp wave module 13, column signal processing unit 14, clock module 15, data storage unit 16, horizontal drive unit 17, system control unit 18, and signal processing unit 19 on a separate semiconductor substrate, and then electrically connect this separate semiconductor substrate to the semiconductor substrate on which the pixel array unit 11 is formed by a Cu-Cu junction or the like to constitute the image sensor 1. It is also possible to form some of the elements constituting the pixel array unit 11 on a separate semiconductor substrate.

[0032] (Example of pixel circuit configuration) Figure 2 shows an example of the circuit configuration of pixel 21.

[0033] The pixel 21 includes a photodiode (PD) 51, a transfer transistor 52, a floating diffusion (FD) 53, a reset transistor 54, an amplification transistor 55, and a selection transistor 56.

[0034] A MOS transistor can be used for each of the pixel transistors: the transfer transistor 52, the reset transistor 54, the amplification transistor 55, and the selection transistor 56.

[0035] The pixel 21 is wired with the aforementioned pixel drive line 22 and vertical signal line 23. The pixel drive line 22 consists of the control line TRG (Transfer Gate), the control line RST (Reset), and the control line SEL (Select). These control lines are connected to the gate of the MOS transistor and transmit the control signals described in Figure 1. When a voltage exceeding the gate-source threshold voltage of the MOS transistor is input to these control lines, the corresponding MOS transistor becomes conductive.

[0036] The control line TRG transmits a signal that controls on / off of the transfer transistor 52. The control line RST transmits a signal that controls resetting of the FD 53. The control line SEL transmits a signal that selects the pixel 21.

[0037] Furthermore, a power supply line Vdd is wired to the pixel 21. The power supply line Vdd supplies a positive polarity power supply.

[0038] The anode of the PD 51 is grounded, and the cathode is connected to the source of the transfer transistor 52. The gate of the transfer transistor 52 is connected to the control line TRG, and the drain is connected to one end of the FD 53, the gate of the amplification transistor 55, and the source of the reset transistor 54. The other end of the FD 53 is grounded.

[0039] The drain of the reset transistor 54 is connected to the power supply line Vdd, and the gate is connected to the control line RST. The drain of the amplification transistor 55 is connected to the power supply line Vdd, and the source is connected to the drain of the selection transistor 56. The gate of the selection transistor 56 is connected to the control line SEL, and the source is connected to the vertical signal line 23.

[0040] The PD 51 generates electric charge corresponding to the amount of light incident from a subject through photoelectric conversion.

[0041] The transfer transistor 52 transfers the electric charge generated in the PD 51 to the FD 53. The transfer transistor 52 transfers electric charge by bringing the PD 51 and the FD 53 into conduction.

[0042] The FD 53 accumulates the electric charge generated in the PD 51. The FD 53 is formed, for example, in a diffusion layer of a semiconductor substrate such as a Si substrate.

[0043] The reset transistor 54 resets the electric charge accumulated in the FD 53. The reset transistor 54 performs resetting by bringing the power supply line Vdd and the FD 53 into conduction, thereby applying a power supply voltage to the FD 53.

[0044] The amplification transistor 55 detects a signal corresponding to the electric charge held in the FD 53 as a pixel signal.

[0045] The selection transistor 56 outputs the pixel signal detected by the amplification transistor 55. The selection transistor 56 outputs the pixel signal by conducting between the amplification transistor 55 and the vertical signal line 23.

[0046] Note that the pixel 21 may include a charge holding unit that accumulates charges generated in the PD 51, separately from the FD 53.

[0047] With the configuration described above, resetting of the FD 53 and transfer of charges from the PD 51 to the FD 53 are performed simultaneously for all pixels. That is, the imaging element 1 can perform imaging in a global shutter system.

[0048] (Cross-sectional Structure of Imaging Element) FIG. 3 is a side cross-sectional view showing the cross-sectional structure of the imaging element 1.

[0049] The imaging element 1 shown in FIG. 3 includes a semiconductor substrate 100 on which pixels 21 are formed, and a wiring layer 101 on which various types of wirings are formed, and a color filter 102 and a light-receiving lens 103 are provided for each pixel 21. In FIG. 3, the surface of the semiconductor substrate 100 on which the wiring layer 101 is arranged is defined as a front surface, and the surface on which the light-receiving lens 103 is arranged is defined as a back surface. The front surface is the surface opposite to the light incident surface of the semiconductor substrate 100, and the back surface is the light incident surface (light-receiving surface) of the semiconductor substrate 100.

[0050] In the semiconductor substrate 100 shown in FIG. 3, the symbols "P" and "N" represent a P-type semiconductor region and an N-type semiconductor region, respectively. Further, the "+" at the end of each of the symbols "P+" and "N+" indicates that the impurity concentration of the corresponding P-type semiconductor region or N-type semiconductor region is high.

[0051] Although a detailed explanation will be omitted, the semiconductor substrate 100 has the aforementioned photodiode and charge holding portion formed on it. In addition, a light-shielding portion 110 is formed on the semiconductor substrate 100 as a processed portion formed by trenching. The light-shielding portion 110 has the function of absorbing or reflecting light. The light-shielding portion 110 includes a vertical light-shielding portion 110V that extends in a wall-like manner in a direction perpendicular to the front and back surfaces of the semiconductor substrate 100 (hereinafter also referred to as the vertical direction), and a horizontal light-shielding portion 110H that extends in a plate-like manner in a direction parallel to the front and back surfaces of the semiconductor substrate 100 (hereinafter also referred to as the horizontal direction).

[0052] <3. Structure and Formation Process of the Light-Blocking Section> The structure and formation process of the light-blocking section will be explained in detail below.

[0053] (Configuration of light-shielding portion) The configuration of the light-shielding portion for each pixel will be explained with reference to Figures 4 to 6. Figure 4 is a side cross-sectional view showing an example of the configuration of the light-shielding portion of a single pixel, and Figure 5 is a plan cross-sectional view showing an example of the configuration of the light-shielding portion of a single pixel. Figure 6 is a plan cross-sectional view showing an example of the configuration of the light-shielding portion of a 2x2 pixel.

[0054] Figures 4 and 5 show the side and planar cross-sectional structures of the semiconductor substrate 100P on which the pixels 21 are formed, for each pixel 21. Figure 4 shows the A'-B' cross-section of Figure 5, and Figure 5 shows the A-B cross-section of Figure 4.

[0055] The vertical light-shielding portion 110V is positioned along the boundary portions of the multiple pixels 21 arranged in a grid pattern in a plan view. Here, a plan view refers to viewing from a direction perpendicular to the front surface of the semiconductor substrate 100 (the Z direction). The vertical light-shielding portion 110V functions as an inter-pixel separator that separates pixels from each other.

[0056] The horizontal light-shielding portion 110H is arranged to extend in a plate-like shape from a part of the vertical light-shielding portion 110V in a horizontal direction (X, Y direction) parallel to the front and back surfaces of the semiconductor substrate. As shown in Figure 6, the horizontal light-shielding portion 110H is formed to have a hexagonal shape in 2x2 pixel units when viewed from above.

[0057] The vertical light-shielding section 110V and the horizontal light-shielding section 110H are made of a material containing at least one of the following: a single metal, a metal alloy, a metal nitride, and a metal silicide, all of which have light-shielding properties. Specifically, examples of materials that make up the vertical light-shielding section 110V and the horizontal light-shielding section 110H include W (tungsten), Ti (titanium), Ta (tantalum), Ni (nickel), Mo (molybdenum), Cr (chromium), Ir (iridium), platinum-iridium, TiN (titanium nitride), Al (aluminum), Cu (copper), Co (cobalt), and tungsten-silicon compounds. However, the materials that make up the vertical light-shielding section 110V and the horizontal light-shielding section 110H are not limited to these. For example, it is also possible to use light-shielding substances other than metals, such as carbon, oxide films, and electromic materials.

[0058] Although not shown in the diagram, the areas surrounding the vertical light-shielding portion 110V and the horizontal light-shielding portion 110H are covered with an insulating film made of an insulating material such as SiO2.

[0059] The semiconductor substrate 110P has an N-type semiconductor region 121 and a P-type semiconductor region 122 formed by P-type impurities. In addition, a pinning layer 123 is formed (provided) along the vertical light-shielding portion 110V and the horizontal light-shielding portion 110H in the region surrounding the vertical light-shielding portion 110V and the horizontal light-shielding portion 110H of the semiconductor substrate 110P. The pinning layer 123 is formed as a P+-type semiconductor region and has the effect of fixing the surface states of the vertical light-shielding portion 110V and the horizontal light-shielding portion 110H and suppressing dark current. Furthermore, the pinning layer 123 has the effect of improving the saturation charge amount (Qs) of the image sensor 1.

[0060] The P-type semiconductor region 122, which has a lower impurity concentration than the pinning layer 123, is formed between the pinning layer 123, which is formed along the horizontal light-shielding portion 110H, and the N-type semiconductor region 121 that forms the semiconductor substrate 110P. In other words, the P-type semiconductor region 122 is formed to cover the pinning layer 123, which is formed along the horizontal light-shielding portion 110H. The maximum impurity concentration of the pinning layer 123 is 1 cm³. 3 10 17 ~10 18While it is considered to be of the order of magnitude, the maximum impurity concentration in the P-type semiconductor region 122 is 1 cm³. 3 10 16 It is considered an order.

[0061] The horizontal light-shielding portion 110H is formed by wet etching starting from the vertical light-shielding portion 110V, which is formed by dry etching.

[0062] However, variations in the dry etching and wet etching processes may result in variations in the horizontal light-shielding portion 110H.

[0063] Specifically, due to variations in the manufacturing process, variations may occur in the vertical (Z-direction) formation position of the horizontal light-shielding portion 110H, as shown in Figure 7A, and variations may occur in the vertical (Z-direction) thickness of the horizontal light-shielding portion 110H, as shown in Figure 7B. In addition, variations may occur in the horizontal (X, Y-direction) length of the horizontal light-shielding portion 110H, as shown in Figure 7C.

[0064] In this case, in a conventional structure in which the P-type semiconductor region 122 is not provided, the influence of the potential due to the pinning layer 123 formed along the horizontal light-shielding portion 110H fluctuates, making it difficult to obtain the desired potential shape, and raising concerns that charge transfer may fail.

[0065] In contrast, by providing a P-type semiconductor region 122 between the pinning layer 123 formed along the horizontal light-shielding portion 110H and the N-type semiconductor region 121, the position of the PN junction is determined by the N-type semiconductor region 121 and the P-type semiconductor region 122, as shown by the thick dotted line in Figure 4. This reduces the influence of variations in the horizontal light-shielding portion 110H on the pinning layer 123's potential, enabling a robust design for charge transfer. Furthermore, since the effects of variations in processing do not need to be considered, it becomes possible to increase the junction capacitance generated at the PN junction portion between the P-type semiconductor region 122 covering the pinning layer 123 and the N-type semiconductor region 121, thereby increasing the saturation signal amount. As a result, the reliability of the image sensor 1 can be improved.

[0066] (Formation Process of Light-Blocking Sections) The formation process of the vertical light-blocking section 110V and the horizontal light-blocking section 110H will be described with reference to Figures 8 and 9. The upper part of Figures 8 and 9 shows the side cross-sectional structure of the semiconductor substrate 100P, and the lower part of Figures 8 and 9 shows the planar cross-sectional structure of the semiconductor substrate 100P.

[0067] In step P1, a semiconductor substrate is prepared in which an N-type semiconductor region 121 is formed.

[0068] In step P2, a P-type semiconductor region 122 is formed by ion implantation of P-type impurities into the area where the horizontal light-shielding portion 110H is formed in the N-type semiconductor region 121. Here, the ion implantation of P-type impurities may be carried out in multiple steps.

[0069] In step P3, a vertical light-shielding portion 110V, which serves as an inter-pixel separation portion, is formed by dry etching in the Z direction. At this time, in the P-type semiconductor region 122, the vertical light-shielding portion 110V is formed up to the location where the horizontal light-shielding portion 110H is formed.

[0070] In step P4, a horizontal light-shielding portion 110H is formed by wet etching in the X and Y directions.

[0071] In step P5, the vertical light-shielding portion 110V is formed in the portion where it has not yet been formed by dry etching in the Z direction.

[0072] In step P6, a pinning layer 123 is formed on the wall surface of the vertical light-shielding section 110V by the diffusion of P-type impurities with a higher impurity concentration than the P-type semiconductor region 122.

[0073] As described above, a vertical light-shielding portion 110V, a horizontal light-shielding portion 110H, and a P-type semiconductor region 122 covering the horizontal light-shielding portion 110H can be formed. Furthermore, according to the formation process described with reference to Figures 8 and 9, not limited to the horizontal light-shielding portion 110H, a P-type semiconductor region exhibiting similar effects to the P-type semiconductor region 122 can be formed by ion implanting P-type impurities to cover any processed portion of any shape formed by trenching.

[0074] <4. Thickness of the P-type semiconductor region> In the image sensor 1 of this embodiment, the thickness (vertical thickness, horizontal thickness) of the P-type semiconductor region 122 covering the horizontal light-shielding portion 110H is set to a thickness obtained by adding a predetermined margin to the variation range of the horizontal light-shielding portion 110H.

[0075] The variation range of the horizontal light-shielding portion 110H is defined as the variation range of the horizontal length of the horizontal light-shielding portion 110H, the variation range of the vertical thickness of the horizontal light-shielding portion 110H, and the variation range of the vertical formation position of the horizontal light-shielding portion 110H, as explained with reference to Figure 7.

[0076] Figure 10 illustrates the thickness of the P-type semiconductor region 122.

[0077] As shown in Figure 10, the vertical thickness (width) of the P-type semiconductor region 122 covering the horizontal light-shielding portion 110H is denoted as a, and the horizontal thickness (width) is denoted as b. The depth of the horizontal light-shielding portion 110H from the interface (front surface) of the semiconductor substrate 100 on the wiring layer 101 side is denoted as c, and the horizontal length (X, Y direction) of the horizontal light-shielding portion 110H is denoted as d. Furthermore, the vertical width of the pinning layer 123 covering the horizontal light-shielding portion 110H is denoted as e, and the horizontal width is denoted as f.

[0078] In this case, the vertical thickness a and horizontal thickness b of the P-type semiconductor region 122 should satisfy the following equation.

[0079] [Math. 1] a>(x*c)+e+100nm b>(y*d)+f+100nm

[0080] Here, x represents the variation coefficient of the formation position of the horizontal light-shielding portion 110H in the vertical direction (Z direction), and y represents the variation coefficient of the length of the horizontal light-shielding portion 110H in the horizontal direction (X, Y direction).

[0081] In this way, by making the thickness of the P-type semiconductor region 122 greater than the thickness obtained by adding the width of the pinning layer 123 and a predetermined margin (100 nm) to the variation range of the horizontal light-shielding portion 110H, the influence of the pinning layer 123 on the potential is reduced, and the P-type semiconductor region 122 can be designed robustly against variations in the horizontal light-shielding portion 110H.

[0082] In the above, the pinning layer 123 is formed by P-type impurities diffused around the vertical light-shielding portion 110V and the horizontal light-shielding portion 110H, but it is not limited to this.

[0083] Figure 11 is a side cross-sectional view showing another example of the configuration of the light-shielding portion 110 (vertical light-shielding portion 110V, horizontal light-shielding portion 110H) for a single pixel.

[0084] In the example shown in Figure 11, the pinning layer is formed by a fixed charge film 123a deposited around the vertical light-shielding portion 110V and the horizontal light-shielding portion 110H.

[0085] Figure 12 illustrates the thickness of the P-type semiconductor region 122 in the example shown in Figure 11.

[0086] As shown in Figure 12, the vertical thickness (width) of the P-type semiconductor region 122 covering the horizontal light-shielding portion 110H is denoted as a, and the horizontal thickness (width) is denoted as b. Furthermore, the depth of the horizontal light-shielding portion 110H from the interface (front surface) of the semiconductor substrate 100 on the wiring layer 101 side is denoted as c, and the horizontal length (X, Y direction) of the horizontal light-shielding portion 110H is denoted as d.

[0087] In this case, the vertical thickness a and horizontal thickness b of the P-type semiconductor region 122 should satisfy the following equation.

[0088] [Math 2] a>(x*c)+100nm b>(y*d)+100nm

[0089] Here, x represents the variation coefficient of the formation position of the horizontal light-shielding portion 110H in the vertical direction (Z direction), and y represents the variation coefficient of the length of the horizontal light-shielding portion 110H in the horizontal direction (X, Y direction).

[0090] In this way, by making the thickness of the P-type semiconductor region 122 greater than the variation range of the horizontal light-shielding portion 110H plus a predetermined margin (100 nm), the influence of the pinning layer (fixed charge film 123a) on the potential is reduced, and the P-type semiconductor region 122 can be designed robustly against variations in the horizontal light-shielding portion 110H.

[0091] Figure 13 is a side cross-sectional view showing yet another configuration example of the light-shielding portion 110 (vertical light-shielding portion 110V, horizontal light-shielding portion 110H) of a single pixel.

[0092] In the example shown in Figure 13, the pinning layer is formed by applying a negative bias to the polysilicon electrodes 210 embedded in the vertical light-shielding portion 110V and the horizontal light-shielding portion 110H.

[0093] Figure 14 illustrates the thickness of the P-type semiconductor region 122 in the example shown in Figure 13.

[0094] As shown in Figure 14, the vertical thickness (width) of the P-type semiconductor region 122 covering the horizontal light-shielding portion 110H is denoted as a, and the horizontal thickness (width) is denoted as b. Furthermore, the depth of the horizontal light-shielding portion 110H from the interface (front surface) of the semiconductor substrate 100 on the wiring layer 101 side is denoted as c, and the horizontal length (X, Y direction) of the horizontal light-shielding portion 110H is denoted as d.

[0095] In this case, the vertical thickness a and horizontal thickness b of the P-type semiconductor region 122 should satisfy the following equation.

[0096] [Math 3] a>(x*c)+100nm b>(y*d)+100nm

[0097] Here, x represents the variation coefficient of the formation position of the horizontal light-shielding portion 110H in the vertical direction (Z direction), and y represents the variation coefficient of the length of the horizontal light-shielding portion 110H in the horizontal direction (X, Y direction).

[0098] In this way, by making the thickness of the P-type semiconductor region 122 greater than the variation range of the horizontal light-shielding portion 110H plus a predetermined margin (100 nm), the influence of the pinning layer (polysilicon electrode 210) on the potential is reduced, and the P-type semiconductor region 122 can be designed robustly against variations in the horizontal light-shielding portion 110H.

[0099] <5. Modified Examples> Below, modified examples of the cross-sectional structure of the image sensor 1 of this embodiment will be described.

[0100] (PN junction between a part of the pinning layer and the N-type semiconductor region) The image sensor 1 of this embodiment can have a PN junction formed between a part of the pinning layer 123 around the horizontal light-shielding portion 110H and the N-type semiconductor region 121.

[0101] Here, as shown in Figures 15 and 16, we define a cross-section C1 in the XY plane and a cross-section C2 in the YZ plane that pass through the horizontal light-shielding portion 110H.

[0102] In the example shown in Figure 15, a PN junction is formed in cross-section C2 by the N-type semiconductor region 121 and the P-type semiconductor region 122, while in cross-section C1, a PN junction is formed by the pinning layer 123 around the horizontal light-shielding portion 110H and the N-type semiconductor region 121. Specifically, in the example shown in Figure 15, the PN junction between a part of the pinning layer 123 and the N-type semiconductor region 121 is formed at the horizontal end of the horizontal light-shielding portion 110H, and the P-type semiconductor region 122 is formed to cover the front and back sides of the horizontal light-shielding portion 110H.

[0103] This structure allows for a reduction in the number of ion implantations during the formation of the P-type semiconductor region 122, thereby reducing crystal defects, minimizing the effects of the well proximity effect, and reducing the number of process steps. This structure is particularly effective when it is desired to reduce the influence of potential on vertical variations in the horizontal light-shielding portion 110H.

[0104] In the example shown in Figure 16, a PN junction is formed in cross-section C1 by the N-type semiconductor region 121 and the P-type semiconductor region 122, while in cross-section C2, a PN junction is formed by the pinning layer 123 around the horizontal light-shielding portion 110H and the N-type semiconductor region 121. Specifically, in the example shown in Figure 16, the PN junction between a part of the pinning layer 123 and the N-type semiconductor region 121 is formed in a part of the front side and a part of the back side of the horizontal light-shielding portion 110H, and the P-type semiconductor region 122 is formed to cover the portion including the horizontal end of the horizontal light-shielding portion 110H.

[0105] This structure allows for a reduction in the amount of impurities during the formation of the P-type semiconductor region 122, thereby reducing crystal defects. This structure is particularly effective when it is desired to reduce the influence of potential on horizontal variations in the horizontal light-shielding portion 110H.

[0106] (Horizontal end face of the horizontal light-shielding portion) Ideally, the horizontal end face of the horizontal light-shielding portion 110H is formed perpendicular (parallel to the Z direction) to the front and back surfaces of the semiconductor substrate 100.

[0107] However, due to variations in processing, the horizontal end face of the horizontal light-shielding portion 110H may be inclined toward the back side (upper side in the figure), as shown in Figure 17A, or toward the front side (lower side in the figure), as shown in Figure 17B. Furthermore, depending on the processing conditions, the horizontal end face of the horizontal light-shielding portion 110H may be intentionally inclined toward the back side or the front side. In such cases, with the conventional structure, the area of ​​the PN bond differs between the front and back sides of the horizontal light-shielding portion 110H, and the pinning layer 123 formed along the horizontal light-shielding portion 110H may affect the potential.

[0108] In contrast, by providing a P-type semiconductor region 122 between the pinning layer 123 formed along the horizontal light-shielding portion 110H and the N-type semiconductor region 121, the position of the PN junction is determined by the N-type semiconductor region 121 and the P-type semiconductor region 122, regardless of the shape of the horizontal end face of the horizontal light-shielding portion 110H. This reduces the influence of variations in the horizontal light-shielding portion 110H on the pinning layer 123 to the potential, enabling a robust design against variations in the horizontal light-shielding portion 110H.

[0109] (Image sensor having a multi-stage light-shielding structure) The image sensor 1 of this embodiment can have a multi-stage light-shielding structure, similar to the image sensor disclosed in Patent Document 1. That is, in the image sensor 1 of this embodiment, the horizontal light-shielding portion 110H can be arranged in multiple stages in the vertical direction on the semiconductor substrate 100.

[0110] Referring to Figures 18 to 22, the configuration of the light-shielding portion 110 for each pixel in the image sensor 1 having a multi-stage light-shielding structure will be described. Figure 18 is a side cross-sectional view showing an example of the configuration of a single-pixel light-shielding portion 110, and Figure 19 is a plan cross-sectional view showing an example of the configuration of a single-pixel light-shielding portion 110. Figure 20 is a side cross-sectional view showing an example of the configuration of a 2x2 pixel light-shielding portion 110, and Figures 21 and 22 are plan cross-sectional views showing examples of the configuration of a 2x2 pixel light-shielding portion 110.

[0111] Figure 19A shows the A1-B1 cross-section of Figure 18, and Figure 19B shows the A2-B2 cross-section of Figure 18. Furthermore, Figure 21 shows the A3-B3 cross-section of Figure 20, and Figure 22 shows the A4-B4 cross-section of Figure 20.

[0112] As shown in Figures 18 to 22, the horizontal light-shielding sections 110H are arranged in two stages in the vertical direction (Z direction) on the semiconductor substrate 100. Here, from the viewpoint of suppressing noise generation, one of the horizontal light-shielding sections 110H should be arranged so as to cover at least a portion of the area where the other horizontal light-shielding section 110H is not located, when viewed from the vertical direction.

[0113] In other words, the horizontal light-shielding portion 110H shown in the A1-B1 cross-section of Figure 18 (Figure 19, Part A) is positioned to cover at least a portion of the area where the horizontal light-shielding portion 110H shown in the A2-B2 cross-section of Figure 18 (Figure 19, Part B) is not located, when viewed from the vertical direction.

[0114] Furthermore, the horizontal light-shielding portion 110H (Figure 21), shown in the A3-B3 cross-section of Figure 20, is positioned to cover at least a portion of the area where the horizontal light-shielding portion 110H (Figure 22), shown in the A4-B4 cross-section of Figure 20, is not located, when viewed from the vertical direction.

[0115] In an image sensor 1 having such a multi-stage light-shielding structure, variations in processing may cause the pinning layer 123 formed along the horizontal light-shielding portion 110H to affect the potential in terms of the sum of squares. In contrast, by providing a P-type semiconductor region 122 between the pinning layer 123 formed along the horizontal light-shielding portion 110H and the N-type semiconductor region 121, the influence of variations in the horizontal light-shielding portion 110H on the potential of the pinning layer 123 is reduced, enabling a robust design against variations in the horizontal light-shielding portion 110H.

[0116] <6. Examination of the thickness of the P-type semiconductor region> In the variation of the processing of the horizontal light-shielding portion 110H, the variation in length in the horizontal direction (X, Y direction) is often less than the variation in thickness in the vertical direction (Z direction) and the variation in formation position in the vertical direction.

[0117] Therefore, as shown in Figure 23, the horizontal thickness b of the P-type semiconductor region 122 covering the horizontal light-shielding portion 110H may be made smaller than the vertical thickness a. In this case, the N-type semiconductor region 121, which becomes the charge transfer region, can be expanded, which is advantageous from the viewpoint of charge transfer.

[0118] <7. Configuration of Pixel-Separating Light-Shielding Section> In the above, a structure was described in which the light-shielding section 110, which is a processed section formed by trenching on the semiconductor substrate 100, is composed of a vertical light-shielding section 110V and a horizontal light-shielding section 110H. However, the processed section (light-shielding section) in the image sensor 1 of this embodiment may also include a pixel-separating light-shielding section that divides the N-type semiconductor region 121 in a vertical direction perpendicular to the front and back surfaces of the semiconductor substrate 100.

[0119] Referring to Figures 24 to 26, the configuration of the pixel-divided light-shielding section for each pixel will be explained. Figure 24 is a side cross-sectional view showing an example of the configuration of the pixel-divided light-shielding section for a single pixel, and Figure 25 is a plan cross-sectional view showing an example of the configuration of the pixel-divided light-shielding section for a single pixel. Figure 26 is a plan cross-sectional view showing an example of the configuration of the 2x2 pixel-divided light-shielding section.

[0120] Figures 24 and 25 show the side and planar cross-sectional structures of the semiconductor substrate 100P', where each pixel 21 is formed. Figure 24 shows the C'-D' cross-section of Figure 25, and Figure 25 shows the C-D cross-section of Figure 24.

[0121] The vertical light-shielding portion 110V is positioned along the boundary portions of a plurality of pixels 21 arranged in a grid pattern in a plan view.

[0122] The pixel-dividing light-shielding portion 310 is arranged in the semiconductor substrate 100P' for each pixel to divide the N-type semiconductor region 121 in the vertical direction (Z direction). As shown in Figures 25 and 26, the pixel-dividing light-shielding portion 310 is formed to divide the light-receiving surface of each pixel (semiconductor substrate 100P') in a plan view. However, as shown in Figure 24, unlike the vertical light-shielding portion 110V, the pixel-dividing light-shielding portion 310 is formed so as not to penetrate from the back side to the front side of the semiconductor substrate 100P'.

[0123] The semiconductor substrate 110P' has an N-type semiconductor region 121 and a P-type semiconductor region 122 formed by P-type impurities. In addition, in the semiconductor substrate 110P', a pinning layer 123 is formed in the region surrounding the vertical light-shielding portion 110V and the pixel-dividing light-shielding portion 310, along the vertical light-shielding portion 110V and the pixel-dividing light-shielding portion 310.

[0124] The P-type semiconductor region 122, which has a lower impurity concentration than the pinning layer 123, is formed between the pinning layer 123, which is formed along the pixel division light-shielding portion 310, and the N-type semiconductor region 121 that forms the semiconductor substrate 110P.

[0125] Here, the pixel division light-shielding portion 310 is formed, for example, by dry etching.

[0126] However, variations in the dry etching process can cause variations in the pixel division light-shielding portion 310.

[0127] Specifically, variations in the manufacturing process can cause variations in the horizontal (X-direction) formation position of the pixel-dividing light-shielding portion 310, as well as variations in the horizontal (X-direction) thickness of the pixel-dividing light-shielding portion 310. Furthermore, variations can also occur in the vertical (Z-direction) length of the pixel-dividing light-shielding portion 310.

[0128] In this case, the influence of the potential due to the pinning layer 123 formed along the pixel division light-shielding portion 310 fluctuates, making it difficult to obtain the desired potential shape and raising concerns that charge transfer may break down.

[0129] In contrast, by providing a P-type semiconductor region 122 between the pinning layer 123 formed along the pixel division light-shielding portion 310 and the N-type semiconductor region 121, the position of the PN junction is determined by the N-type semiconductor region 121 and the P-type semiconductor region 122, as shown by the thick dotted line in Figure 24. This reduces the influence of variations in the pixel division light-shielding portion 310 on the potential of the pinning layer 123, enabling a robust design for charge transfer. Furthermore, since the effects of variations in processing do not need to be considered, it is possible to increase the junction capacitance generated at the PN junction portion between the P-type semiconductor region 122 covering the pinning layer 123 and the N-type semiconductor region 121, thereby increasing the saturation signal amount. As a result, the reliability of the image sensor 1 can be improved.

[0130] <8. Others> The embodiments described above can be combined as appropriate.

[0131] Furthermore, the technology relating to this disclosure can be applied to all types of optical detection devices, including not only solid-state imaging devices such as the CMOS image sensor described above, but also distance measuring sensors, also known as ToF (Time of Flight) sensors. A distance measuring sensor emits light toward an object, detects the reflected light that returns after the light is reflected from the surface of the object, and calculates the distance to the object based on the flight time from when the light is emitted until the reflected light is received. The pixel structure of the pixel 21 described above can be adopted as the pixel structure of this distance measuring sensor.

[0132] Furthermore, the technology relating to this disclosure is not limited to image sensors having a pixel array portion in which pixels are arranged in two dimensions, but can also be applied to line sensors in which pixels are arranged in one dimension (specifically, arranged in one row or several rows).

[0133] <9. Examples of Electronic Device Configurations> The image sensor 1 described above can be applied to various electronic devices, such as imaging systems like digital still cameras and digital video cameras, mobile phones equipped with imaging functions, or other devices equipped with imaging functions.

[0134] Figure 27 is a block diagram showing an example configuration of an imaging device, which is an electronic device to which the present disclosure is applied.

[0135] As shown in Figure 27, the imaging device 501 includes an optical system 502, a solid-state image sensor 503, and a DSP (Digital Signal Processor) 504. The DSP 504, display device 505, operating system 506, memory 508, recording device 509, and power supply system 510 are connected via a bus 507, and the device is capable of capturing both still and moving images.

[0136] The optical system 502 is composed of one or more lenses and guides the image light (incident light) from the subject to the solid-state image sensor 503, forming an image on the light-receiving surface (sensor part) of the solid-state image sensor 503.

[0137] As the solid-state image sensor 503, an image sensor 1 having pixels 21 as in any of the above-described configuration examples is used. Electrons are accumulated in the solid-state image sensor 503 for a certain period of time in accordance with the image formed on the light-receiving surface via the optical system 502. Then, a signal corresponding to the electrons accumulated in the solid-state image sensor 503 is supplied to the DSP 504.

[0138] The DSP 504 performs various signal processing on the signal from the solid-state image sensor 503 to acquire an image, and temporarily stores the image data in the memory 508. The image data stored in the memory 508 is recorded in the recording device 509 or supplied to the display device 505 to display the image. The operation system 506 receives various operations from the user and supplies operation signals to each block of the imaging device 501, and the power supply system 510 supplies the power necessary to drive each block of the imaging device 501.

[0139] In the imaging device 501 configured in this way, by applying the image sensor 1 described above as the solid-state image sensor 503, the influence of the potential due to the pinning layer can be reduced, thereby improving image quality.

[0140] The effects described herein are merely illustrative and not limited to those described herein; other effects may also occur.

[0141] Furthermore, embodiments applying the technology described herein are not limited to those described above, and various modifications are possible without departing from the gist of the technology described herein.

[0142] Furthermore, the present disclosure can take the following configurations: (1) A photodetector comprising a semiconductor substrate on which pixels are formed, a processed portion formed in the semiconductor substrate by trenching, and a pinning layer provided along the processed portion, wherein a P-type semiconductor region formed by P-type impurities is located between the pinning layer and the N-type semiconductor region forming the semiconductor substrate. (2) The photodetector according to (1), wherein the processed portion includes a horizontal light-shielding portion that extends in a plate-like manner in a horizontal direction parallel to the front and back surfaces of the semiconductor substrate. (3) The photodetector according to (2), wherein the thickness of the P-type semiconductor region covering the horizontal light-shielding portion is greater than the thickness of the horizontal light-shielding portion plus a predetermined margin. (4) The photodetector according to (3), wherein the variation range is the horizontal length of the horizontal light-shielding portion, the vertical thickness perpendicular to the horizontal direction, and the variation range of the formation position in the vertical direction. (5) The photodetector according to (4), wherein the pinning layer is formed by P-type impurities diffused around the horizontal light-shielding portion. (6) The photodetector according to (5), wherein the impurity concentration of the pinning layer is higher than the impurity concentration of the P-type semiconductor region. (7) The photodetector according to (6), wherein the thickness of the P-type semiconductor region covering the horizontal light-shielding portion is greater than the thickness of the pinning layer plus the width of the pinning layer. (8) The photodetector according to (4), wherein the pinning layer is formed by a fixed charge film deposited around the horizontal light-shielding portion. (9) The photodetector according to (4), wherein the pinning layer is formed by applying a negative bias to a polysilicon electrode embedded in the horizontal light-shielding portion. (10) The photodetector according to any one of (4) to (9), wherein the pinning layer has a PN junction formed between a part of the pinning layer and the N-type semiconductor region. (11) The photodetector according to (10), wherein the PN junction is formed at the horizontal end of the horizontal light-shielding portion, and the P-type semiconductor region is formed to cover the front and back sides of the horizontal light-shielding portion.(12) The PN junction is formed on a part of the front side and a part of the back side of the horizontal light-shielding portion, and the P-type semiconductor region is formed to cover the portion of the horizontal light-shielding portion including the horizontal end, as described in (10). (13) The horizontal end face of the horizontal light-shielding portion is inclined toward the front side or the back side, as described in any of (4) to (12). (14) The horizontal light-shielding portion is arranged in multiple stages in the vertical direction on the semiconductor substrate, as described in any of (4) to (13). (15) One of the horizontal light-shielding portions is arranged to cover at least a portion of the area where the other horizontal light-shielding portion is not arranged, as viewed from the vertical direction, as described in (14). (16) The horizontal thickness of the P-type semiconductor region covering the horizontal light-shielding portion is smaller than the vertical thickness, as described in any of (4) to (15). (17) The photodetector according to (1), wherein the processed portion includes a pixel-dividing light-shielding portion that divides the N-type semiconductor region in a direction perpendicular to the front and back surfaces of the semiconductor substrate. (18) An electronic device comprising a semiconductor substrate on which pixels are formed, a processed portion formed in the semiconductor substrate by trenching, and a pinning layer provided along the processed portion, wherein a P-type semiconductor region formed by P-type impurities is located between the pinning layer and the N-type semiconductor region forming the semiconductor substrate.

[0143] 1 Image sensor, 11 Pixel array, 21 Pixel, 100 Semiconductor substrate, 101 Wiring layer, 102 Color filter, 103 Light-receiving lens, 110 Light-shielding section, 110V Vertical light-shielding section, 110H Horizontal light-shielding section, 121 N-type semiconductor region 121, 122 P-type semiconductor region, 123 Pinning layer, 501 Imaging device, 503 Solid-state image sensor

Claims

A semiconductor substrate on which pixels are formed, A processed portion formed by trenching in the aforementioned semiconductor substrate, A pinning layer provided along the aforementioned processed portion and Equipped with, Between the pinning layer and the N-type semiconductor region forming the semiconductor substrate, there is a P-type semiconductor region formed by P-type impurities. Light detection device. 　 The processed portion includes a horizontal light-shielding portion that extends in a plate-like shape in a horizontal direction parallel to the front and back surfaces of the semiconductor substrate. The light detection device according to claim 1. 　 The thickness of the P-type semiconductor region covering the horizontal light-shielding portion is greater than the thickness obtained by adding a predetermined margin to the variation range of the horizontal light-shielding portion. The light detection device according to claim 2. 　 The aforementioned variation range is defined as the variation range of the horizontal length of the horizontal light-shielding portion, the thickness in the vertical direction perpendicular to the horizontal direction, and the formation position in the vertical direction. The light detection device according to claim 3. 　 The pinning layer is formed by P-type impurities diffused around the horizontal light-shielding portion. The light detection device according to claim 4. 　 The impurity concentration of the pinning layer is higher than the impurity concentration of the P-type semiconductor region. The light detection device according to claim 5. 　 The thickness of the P-type semiconductor region covering the horizontal light-shielding portion is greater than the thickness obtained by adding the width of the pinning layer. The light detection device according to claim 6. 　 The pinning layer is formed by a fixed charge film deposited around the horizontal light-shielding portion. The light detection device according to claim 4. 　 The pinning layer is formed by applying a negative bias to the polysilicon electrode embedded in the horizontal light-shielding portion. The light detection device according to claim 4. 　 The pinning layer has a PN junction formed between a portion of the pinning layer and the N-type semiconductor region. The light detection device according to claim 4. 　 The PN joint is formed at the horizontal end of the horizontal light-shielding portion. The P-type semiconductor region is formed to cover the front and back sides of the horizontal light-shielding portion. The light detection device according to claim 10. 　 The PN joint is formed in a part of the front side and a part of the back side of the horizontal light-shielding portion. The P-type semiconductor region is formed to cover the portion of the horizontal light-shielding portion that includes the horizontal end. The light detection device according to claim 10. 　 The horizontal end face of the horizontal light-shielding portion is inclined toward the front side or the back side. The light detection device according to claim 4. 　 The horizontal light-shielding portion is arranged in multiple stages in the vertical direction on the semiconductor substrate. The light detection device according to claim 4. 　 One of the horizontal light-shielding portions is positioned such that, when viewed from the vertical direction, it covers at least a portion of the area where the other horizontal light-shielding portion is not located. The light detection device according to claim 14. 　 The horizontal thickness of the P-type semiconductor region covering the horizontal light-shielding portion is smaller than the vertical thickness. The light detection device according to claim 4. 　 The processing portion includes a pixel division light-shielding portion that divides the N-type semiconductor region in a vertical direction perpendicular to the front and back surfaces of the semiconductor substrate. The light detection device according to claim 1. 　 A semiconductor substrate on which pixels are formed, A processed portion formed by trenching in the aforementioned semiconductor substrate, A pinning layer provided along the aforementioned processed portion and Equipped with, Between the pinning layer and the N-type semiconductor region forming the semiconductor substrate, there is a P-type semiconductor region formed by P-type impurities. Light detection device Electronic devices including those mentioned.

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