Inductor element

Abstract

This inductor element comprises: a first insulator layer having a first surface; a second insulator layer laminated on the first insulator layer and having a second surface on the opposite side from the first surface; a linear first inductor conductor formed on the first surface and having a lower surface in contact with the first surface; and a linear second inductor conductor formed on the second surface and having a lower surface in contact with the second surface. When viewed in the lamination direction, the first inductor conductor and the second inductor conductor have portions that extend in parallel, and the parallel extending portion of the first inductor conductor and the parallel extending portion of the second inductor conductor are disposed at positions that do not overlap each other. In the lamination direction, the upper surface of the parallel extending portion of the first inductor conductor is located at the same position as the lower surface of the second inductor conductor.

Description

Inductor element

[0001] The present invention relates to an inductor element formed using a plurality of layers of conductor patterns.

[0002] Patent Documents 1 and 2 describe a configuration in which an inductor conductor is formed on a semiconductor substrate. In the configurations described in Patent Documents 1 and 2, a lower-layer wiring pattern and an upper-layer wiring pattern are provided at positions adjacent to each other in the lamination direction.

[0003] The upper-layer wiring pattern and the lower-layer wiring pattern are configured so as not to overlap each other when viewed in plan. In other words, in a cross section orthogonal to the direction in which each wiring extends, they are configured in a staggered wiring arrangement.

[0004] Japanese Patent Application Laid-Open No. 61-265857 International Publication No. 2022 / 215665

[0005] However, although the above configuration can suppress parasitic capacitance between the upper-layer wiring pattern and the lower-layer wiring pattern, the element becomes high in profile.

[0006] Accordingly, an object of the present invention is to provide an inductor element that can suppress parasitic capacitance and achieve a low profile.

[0007] An inductor element according to an embodiment of the present invention includes: a first insulator layer having a first surface; a second insulator layer laminated on the first insulator layer and having a second surface on an opposite side from the first surface; a linear first inductor conductor formed on the first surface, with a lower surface thereof in contact with the first surface; and a linear second inductor conductor formed on the second surface, with a lower surface thereof in contact with the second surface.

[0008] When viewed in the lamination direction, the first inductor conductor and the second inductor conductor have a parallel running portion. The parallel running portion of the first inductor conductor and the parallel running portion of the second inductor conductor are arranged at positions that do not overlap each other. In the lamination direction, an upper surface of the parallel running portion of the first inductor conductor is at the same position as a lower surface of the second inductor conductor.

[0009] An inductor element according to one embodiment of this invention comprises a first insulating layer having a first surface, a second insulating layer laminated to the first insulating layer and having a second surface on the side opposite to the first surface, a linear first inductor conductor formed on the first surface with its lower surface in contact with the first surface, and a linear second inductor conductor formed on the second surface with its lower surface in contact with the second surface.

[0010] Viewed in the stacking direction, the first inductor conductor and the second inductor conductor have parallel sections, and the parallel sections of the first inductor conductor and the second inductor conductor are positioned so as not to overlap. In the stacking direction, the upper surface of the parallel section of the first inductor conductor is located on the upper surface side of the second inductor conductor than the lower surface of the second inductor conductor.

[0011] An inductor element according to one embodiment of this invention comprises a first insulating layer having a first surface, a second insulating layer laminated to the first insulating layer and having a second surface on the side opposite to the first surface, a linear first inductor conductor formed on the first surface with its lower surface in contact with the first surface, and a linear second inductor conductor formed on the second surface with its lower surface in contact with the second surface.

[0012] Viewed in the stacking direction, the first inductor conductor and the second inductor conductor have parallel sections, and the parallel sections of the first inductor conductor and the second inductor conductor are positioned so as not to overlap. In the stacking direction, the distance between the upper surface of the parallel section of the first inductor conductor and the lower surface of the second inductor conductor is less than the thickness of the second insulator layer.

[0013] In these configurations, the area between the first and second inductor conductors is reduced, thereby suppressing parasitic capacitance. Furthermore, the distance between the top surface of the first inductor conductor and the bottom surface of the second inductor conductor becomes smaller than the thickness of the second insulator layer, resulting in a lower profile.

[0014] According to this invention, an inductor element with suppressed parasitic capacitance can be constructed in a low-profile design.

[0015] Figure 1 is a side cross-sectional view showing an example of the configuration of an inductor element according to the first embodiment. Figure 2 is an enlarged side cross-sectional view of the inductor element according to the first embodiment. Figure 3 is an exploded perspective view showing an example of the shape of the inductor conductor of the inductor element according to the first embodiment. Figure 4 is an enlarged side cross-sectional view of the inductor element according to the second embodiment. Figure 5 is an enlarged side cross-sectional view of the inductor element according to the third embodiment. Figure 6 is an enlarged side cross-sectional view of the inductor element according to the fourth embodiment. Figure 7 is an enlarged side cross-sectional view of the inductor element according to the fifth embodiment.

[0016] [First Embodiment] An inductor element according to the first embodiment of the present invention will be described with reference to the figures. Figure 1 is a side cross-sectional view showing an example of the configuration of the inductor element according to the first embodiment. Figure 2 is an enlarged side cross-sectional view of the inductor element according to the first embodiment. Figure 3 is an exploded perspective view showing an example of the shape of the inductor conductor of the inductor element according to the first embodiment. Note that Figure 3 is shown with fewer turns than the configurations in Figures 1 and 2. Also, Figure 3 is just one example, and the configuration of the present invention can be applied to other inductor shapes as well.

[0017] The inductor element of this invention is particularly effective for applications in circuits that handle high-frequency signals. However, the following configuration can also be applied to circuits that do not handle high-frequency signals.

[0018] As shown in Figures 1 and 2, the inductor element 10 comprises a base substrate 20, an insulating layer 31, an insulating layer 32, an insulating layer 33, an inductor conductor 41, and an inductor conductor 42. The insulating layer 31 corresponds to the "first insulating layer," and the insulating layer 32 corresponds to the "second insulating layer." The inductor conductor 41 corresponds to the "first inductor conductor," and the inductor conductor 42 corresponds to the "second inductor conductor."

[0019] The base substrate 20 is constructed using a semiconductor substrate, such as a Si substrate. However, the base substrate 20 can also be constructed using a ceramic substrate, a glass substrate, a glass epoxy substrate, or other semiconductor substrates.

[0020] The insulating layer 31 is placed on the surface of the base substrate 20. The insulating layer 31 is made of, for example, polyimide, epoxy resin, PBO, SiO ２ It is constructed using materials such as SiN. Note that the inductor element 10 does not necessarily have an insulating layer 31.

[0021] The upper surface FU31 of the insulating layer 31 (the surface opposite to the surface connected to the base substrate 20) is a substantially flat surface.

[0022] The inductor conductor 41 is placed on the upper surface FU 31 of the insulator layer 31. The inductor conductor 41 is wound and linear, for example, as shown in Figure 3. The inductor conductor 41 is made of a highly conductive material, for example, the material of the inductor conductor 41 is metal.

[0023] The inductor conductor 41 has a lower surface F41D and an upper surface F41U, and its cross-section, when cut by a plane perpendicular to its direction of extension, is rectangular. The lower surface F41D of the inductor conductor 41 is in contact with the upper surface FU31 of the insulator layer 31.

[0024] The inductor conductor 41 has a width W41 and a thickness D41. The width W41 is the length in a direction parallel to the upper surface F41U and the lower surface F41D and perpendicular to the direction of extension, and the thickness D41 is the length in a direction perpendicular to the upper surface F41U and the lower surface F41D.

[0025] The insulating layer 32 is placed on the surface of the insulating layer 31 and covers the upper surface F41U and side surfaces of the inductor conductor 41. The insulating layer 32 is made of, for example, polyimide, epoxy resin, PBO, etc.

[0026] The insulating layer 32 has an upper surface FU 32 on the side opposite to the surface in contact with the upper surface F41U of the insulating layer 31 and the inductor conductor 41. The insulating layer 32 has a thickness D32. The thickness of the insulating layer 32 in the portion that does not overlap with the inductor conductor 41 is thinner than the sum of the thickness D41 of the inductor conductor 41 and the thickness D32 of the insulating layer 32.

[0027] Therefore, the upper surface FU32 of the portion of the insulating layer 32 that is in contact with the upper surface F41U of the inductor conductor 41 is further away from the upper surface F41U of the inductor conductor 41 in the stacking direction than the upper surface FU32 of the portion of the insulating layer 32 that is in contact with the insulating layer 31.

[0028] In other words, the upper surface F32U of the insulating layer 32 has a shape in which the portion that overlaps the inductor conductor 41 when viewed from above protrudes more than the portion that does not overlap the inductor conductor 41 when viewed from above. Conversely, the upper surface F32U of the insulating layer 32 has a shape in which the portion that does not overlap the inductor conductor 41 when viewed from above is recessed more than the portion that overlaps the inductor conductor 41 when viewed from above.

[0029] In other words, the upper surface F32U of the insulating layer 32 has a shape in which the portion between adjacent, parallel inductor conductors 41 is recessed compared to the portion that overlaps the inductor conductor 41.

[0030] The inductor conductor 42 is placed on the upper surface FU 32 of the insulator layer 32. The inductor conductor 42 is wound and linear, for example, as shown in Figure 3. The inductor conductor 42 is made of a highly conductive material, for example, the material of the inductor conductor 42 is metal. The inductor conductor 42 is connected to the inductor conductor 41 through a via conductor VIA, for example, as shown in Figure 3.

[0031] The inductor conductor 42 has a lower surface F42D and an upper surface F42U, and its cross-section, when cut by a plane perpendicular to its direction of extension, is rectangular. The lower surface F42D of the inductor conductor 42 is in contact with the upper surface FU32 of the insulator layer 32.

[0032] The inductor conductor 42 has a width W42 and a thickness D42. The width W42 is the length in a direction parallel to the upper surface F42U and the lower surface F42D and perpendicular to the direction of extension, and the thickness D42 is the length in a direction perpendicular to the upper surface F42U and the lower surface F42D.

[0033] The width W42 of inductor conductor 42 and the width W41 of inductor conductor 41 may be the same or different. Similarly, the thickness D42 of inductor conductor 42 and the thickness D41 of inductor conductor 41 may be the same or different. If the widths and thicknesses of inductor conductors 41 and 42 are the same, the inductor element 10 becomes easier to manufacture. On the other hand, in some cases, the widths and thicknesses of inductor conductors 41 and 42 may be different from each other in terms of the characteristics to be obtained.

[0034] Viewed in the stacking direction, the inductor conductor 42 runs parallel to the inductor conductor 41. The inductor conductor 42 is positioned in the recessed portion of the upper surface FU 32 of the insulator layer 32. That is, the lower surface F 42D of the inductor conductor 42 is in contact with the bottom surface of the recessed portion of the upper surface FU 32 of the insulator layer 32.

[0035] With this configuration, when viewed in the stacking direction, the parallel portions of the inductor conductor 41 and the parallel portions of the inductor conductor 42 are positioned so as not to overlap.

[0036] In this way, by ensuring that the inductor conductor 41 and the inductor conductor 42 do not overlap when viewed in the stacking direction, the inductor element 10 can reduce the parasitic capacitance between the inductor conductor 41 and the inductor conductor 42.

[0037] Furthermore, multiple inductor conductors 41 are arranged on the upper surface FU 31 of the insulator layer 31, and due to the winding shape described above, there are portions where multiple inductor conductors 41 run parallel to each other. In this case, adjacent inductor conductors 41 are arranged with a gap G 41 between them.

[0038] The spacing G41 is greater than the width W41 of the inductor conductor 41. That is, the spacing G41 satisfies the relationship G41 ≥ W41 + 2 × D32 × tanθ, where the width W41 of the inductor conductor 41 and the thickness D32 of the insulating layer 32 are used, and the inclination of the convex portion of the insulating layer 32 is θ.

[0039] With this configuration, the upper surface FU32 of the portion that forms the bottom of the recess in the insulating layer 32 can be positioned in the same location as the upper surface FU31 of the inductor conductor 41 in the stacking direction.

[0040] A lower surface F42D of the inductor conductor 42 is in contact with an upper surface FU32 of the insulator layer 32. Accordingly, in a portion where the inductor conductor 41 and the inductor conductor 42 run in parallel, the lower surface F42D of the inductor conductor 42 and the upper surface F41U of the inductor conductor 41 can be at the same position in the lamination direction.

[0041] As a result, the inductor element 10 can have a lower profile than a configuration in which the inductor conductor 41 and the inductor conductor 42 overlap when viewed in the lamination direction.

[0042] Furthermore, since the inductor conductor 41 and the inductor conductor 42 do not face each other across surfaces, the parasitic capacitance between the inductor conductor 41 and the inductor conductor 42 can be further suppressed.

[0043] As described above, the inductor element 10 can simultaneously achieve reduced parasitic capacitance and a lower profile.

[0044] Furthermore, in the inductor element 10, a thickness D32 of the insulator layer 32 is smaller than a thickness D41 of the inductor conductor 41 and a thickness D42 of the inductor conductor 42. Accordingly, the inductor element 10 can suppress resistance loss of the inductor conductor 41 and the inductor conductor 42 while achieving further reduction in profile. Additionally, the inductor conductor 41 and the inductor conductor 42 can achieve a high Q factor by suppressing resistance loss.

[0045] [Second Embodiment] An inductor element according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 4 is an enlarged side cross-sectional view of the inductor element according to the second embodiment.

[0046] As shown in FIG. 4, an inductor element 10A according to the second embodiment differs from the inductor element 10 according to the first embodiment in the position of the inductor conductor 42 in the lamination direction. Other configurations of the inductor element 10A are the same as those of the inductor element 10, and descriptions of similar portions are omitted.

[0047] In the inductor element 10A, in the lamination direction, the upper surface F41U of the parallel-running portion of the inductor conductor 41 is positioned closer to the upper surface F42U side of the inductor conductor 42 than the lower surface F42D of the inductor conductor 42 is.

[0048] In other words, in the stacking direction, the lower surface F42D of the inductor conductor 42 is located closer to the upper surface FU31 of the insulator layer 31 than the upper surface F41U of the inductor conductor 41.

[0049] Furthermore, to put it another way, the lower surface F42D of the inductor conductor 42 extends below the plane that includes the upper surface F41U of the inductor conductor 41.

[0050] This configuration can be realized, for example, by appropriately setting the thickness D41 of the inductor conductor 41, the thickness D32 of the insulating layer 32, the spacing G41 between adjacent inductor conductors 41, and the width W42 of the inductor conductor 42. For example, if the thickness D41 of the inductor conductor 41, the spacing G41 between adjacent inductor conductors 41, and the width W42 of the inductor conductor 42 are the same as in the first embodiment, the thickness D32 of the insulating layer 32 should be made thinner.

[0051] With this configuration, the inductor element 10A can be made even lower in profile while suppressing parasitic capacitance.

[0052] [Third Embodiment] An inductor element according to a third embodiment of the present invention will be described with reference to the figures. Figure 5 is an enlarged side cross-sectional view of the inductor element according to the third embodiment.

[0053] As shown in Figure 5, the inductor element 10B according to the third embodiment differs from the inductor element 10 according to the first embodiment in the position of the inductor conductor 42 in the stacking direction. The other configurations of the inductor element 10B are the same as those of the inductor element 10, and a description of the similar parts will be omitted.

[0054] In the inductor element 10B, in the stacking direction, the lower surface F42D of the parallel-running portion of the inductor conductor 42 is located on the upper surface F42U side of the parallel-running portion of the inductor conductor 42, rather than on the upper surface F41U of the parallel-running portion of the inductor conductor 41.

[0055] In this case, the distance GH between the upper surface F41U of the parallel portion of the inductor conductor 41 in the stacking direction and the lower surface F42D of the inductor conductor 42 is smaller than the thickness D32 of the insulating layer 32.

[0056] With this configuration, the distance between the inductor conductor 41 and the inductor conductor 42 is further increased, and the parasitic capacitance between the inductor conductor 41 and the inductor conductor 42 can be further suppressed.

[0057] Furthermore, because the distance GH is smaller than the thickness D32 of the insulating layer 32, the height of the insulating layer 32 can be reduced compared to the case where the insulating layer 32 does not have a recess.

[0058] [Fourth Embodiment] An inductor element according to the fourth embodiment of the present invention will be described with reference to the figures. Figure 6 is an enlarged side cross-sectional view of the inductor element according to the fourth embodiment.

[0059] As shown in Figure 6, the inductor element 10C according to the fourth embodiment differs from the inductor element 10A according to the second embodiment in that it includes an inductor conductor 41C and an inductor conductor 42C. The other configurations of the inductor element 10C are the same as those of the inductor element 10A, and a description of the similar parts will be omitted.

[0060] The inductor conductor 41C has a trapezoidal cross-section. In the inductor conductor 41C, the width of the upper surface F41U is smaller than the width of the lower surface F41D.

[0061] The inductor conductor 42C has a trapezoidal cross-section. In the inductor conductor 42C, the width of the upper surface F42U is smaller than the width of the lower surface F42D.

[0062] With this configuration, the inductor element 10C, like the inductor element 10A, can suppress parasitic capacitance and achieve a low profile. In the normal manufacturing process, the width of the upper surface of each inductor conductor in the inductor element 10C is smaller than the width of the lower surface, as described above. However, the width of the upper surface of each inductor conductor may be made larger than the width of the lower surface by process control.

[0063] Furthermore, in the inductor element 10C, the sides are not parallel at the opposing portions of the inductor conductor 41C and the inductor conductor 42C. Therefore, the inductor element 10C can suppress parasitic capacitance.

[0064] [Fifth Embodiment] An inductor element according to the fifth embodiment of the present invention will be described with reference to the figures. Figure 7 is an enlarged side cross-sectional view of the inductor element according to the fifth embodiment.

[0065] As shown in Figure 7, the inductor element 10D according to the fifth embodiment differs from the inductor element 10 according to the first embodiment in that it includes an inductor conductor 41D and an inductor conductor 42D. The other configurations of the inductor element 10D are the same as those of the inductor element 10, and a description of the similar parts will be omitted.

[0066] The inductor conductor 41D has a rounded edge. The inductor conductor 42D also has a rounded edge.

[0067] With this configuration, the inductor element 10D, like the inductor element 10, can suppress parasitic capacitance and achieve a low profile.

[0068] Furthermore, in the inductor element 10D, the distance between the inductor conductors 41D and 42D is longer than in a shape with corners. Therefore, the parasitic capacitance of the inductor element 10D can be further suppressed.

[0069] In each of the embodiments described above, the dielectric constant of the insulating layer 31 and the dielectric constant of the insulating layer 32 are the same, but they may be different. For example, the dielectric constant of the insulating layer 31 can be made lower than that of the insulating layer 32. This further suppresses the parasitic capacitance between the inductor conductor 41 and the inductor conductor 42.

[0070] Furthermore, the viscosity of the insulating layer 31 before curing and the viscosity of the insulating layer 32 before curing may be made different. In this case, the viscosity of the insulating layer 32 before curing is made lower than the viscosity of the insulating layer 31 before curing. This makes it easier for the insulating layer 32 to penetrate between adjacent inductor conductors 41 and allows it to be made thinner. Therefore, the inductor element can be made even lower in height.

[0071] Furthermore, the configurations of each of the above embodiments can be combined as appropriate, and effects can be achieved depending on the combination.

[0072] 10, 10A, 10B, 10C, 10D: Inductor element 20: Base substrate 31, 32, 33: Insulating layer 41, 41C, 41D, 42, 42C, 42D: Inductor conductor D32, D41, D42: Thickness FU31, FU32, F41U, F42U: Top surface F41D, F42D: Bottom surface G41: Spacing GH: Distance VIA: Via conductor W41, W42: Width

Claims

1. An inductor element comprising: a first insulating layer having a first surface; a second insulating layer laminated to the first insulating layer and having a second surface on the opposite side of the first surface; a linear first inductor conductor formed on the first surface with its lower surface in contact with the first surface; and a linear second inductor conductor formed on the second surface with its lower surface in contact with the second surface, wherein, viewed in the lamination direction, the first inductor conductor and the second inductor conductor have parallel portions, the parallel portions of the first inductor conductor and the parallel portions of the second inductor conductor are arranged in positions that do not overlap, and in the lamination direction, the upper surface of the parallel portion of the first inductor conductor is in the same position as the lower surface of the second inductor conductor.

2. An inductor element comprising: a first insulating layer having a first surface; a second insulating layer laminated to the first insulating layer and having a second surface on the opposite side of the first surface; a linear first inductor conductor formed on the first surface with its lower surface in contact with the first surface; and a linear second inductor conductor formed on the second surface with its lower surface in contact with the second surface, wherein, in the direction of lamination, the first inductor conductor and the second inductor conductor have parallel portions, the parallel portions of the first inductor conductor and the parallel portions of the second inductor conductor are arranged in positions that do not overlap, and in the direction of lamination, the upper surface of the parallel portion of the first inductor conductor is located on the upper surface side of the second inductor conductor than the lower surface of the second inductor conductor.

3. An inductor element comprising: a first insulating layer having a first surface; a second insulating layer laminated to the first insulating layer and having a second surface on the opposite side of the first surface; a linear first inductor conductor formed on the first surface with its lower surface in contact with the first surface; and a linear second inductor conductor formed on the second surface with its lower surface in contact with the second surface, wherein, in the direction of lamination, the first inductor conductor and the second inductor conductor have parallel portions, the parallel portions of the first inductor conductor and the parallel portions of the second inductor conductor are positioned so as not to overlap, and in the direction of lamination, the distance between the upper surface of the parallel portion of the first inductor conductor and the lower surface of the parallel portion of the second inductor conductor is less than the thickness of the second insulating layer.

4. The inductor element according to any one of claims 1 to 3, wherein the thickness of the first inductor conductor and the thickness of the second inductor conductor are greater than the thickness of the second insulator layer.

5. The inductor element according to any one of claims 1 to 4, wherein the first insulating layer is disposed on a semiconductor substrate.

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