Method for forming via-fill interlayer conductor, and circuit board

Abstract

The purpose of the present invention is to provide a high-quality via-fill interlayer conductor that has high electrical stability and that is capable of filling a through-hole having a high aspect ratio with a conductive metal at high speed. To achieve the foregoing, provided is a method for forming a via-fill interlayer conductor, which is obtained by burying a through hole that has a high aspect ratio and that is provided in an insulating base material. As a first step of this method, a first conductive metal layer is formed on a surface on one side of the insulating base material provided with the through hole, the first conductive metal layer serving as an electrode layer covering at least the outer peripheral part of the through hole and the through hole itself. As a second step, the current density is increased in a stepwise manner when depositing conductive metal by electrolytic plating from the inner surface of the first conductive metal layer toward the other-face side of the insulating base material, and at the same time, a via-fill interlayer conductor is obtained by using a PR electrolytic plating method or the like in which a reverse current is intermittently made to flow a plurality of times during energization.

Description

Method for forming via-fill interlayer conductors and circuit board

[0001] This application relates to a method for forming via-fill interlayer conductors used for interlayer conductivity in multilayer substrates and the like. Specifically, it relates to a method for forming via-fill interlayer conductors in through-holes of an insulating substrate using an embedded plating method.

[0002] In recent years, multilayer substrates have been used in electronic circuit boards to improve mounting density. To electrically connect these multiple stacked insulating substrates, via holes (through-holes) are provided in each substrate, penetrating from top to bottom. Techniques such as conformal plating have been used to deposit a conductive metal, such as copper, on the surface of these through-holes. However, because conformal plating deposits a conductive metal on the surface of the through-holes, voids remain in the through-holes. If voids remain in the through-holes, during thermal processes such as solder reflow to connect electronic components to the circuit board, the air in the voids after conformal plating expands, leading to defects such as cracks in the plating film due to blowholes or damage to the circuit board, resulting in a decrease in product quality. Therefore, techniques have been adopted to fill the voids in the through-holes after conformal plating with resin or other materials to eliminate these voids.

[0003] However, as the mounting density of electronic circuit boards increases, electronic components become smaller, and the wiring width and spacing of electronic circuit boards become finer, the via hole diameter relative to the via hole length also decreases, resulting in a higher aspect ratio. This makes it difficult to fill high aspect ratio via holes (through holes) with resin without any gaps.

[0004] To address these problems, Patent Documents 1 and 2 disclose a method for forming through-holes by depositing and layering conductive metal to fill the through-holes using an electroplating method in which an electrode provided on one side of the through-hole is used as a power supply layer. However, when depositing and layering conductive metal in high-aspect-ratio through-holes using the general electroplating method disclosed in Patent Documents 1 and 2, it was necessary to perform electroplating at a low current for a long time in order to deposit and layer the conductive metal while suppressing the generation of voids (gaps remaining that could not be filled by the deposited conductive metal).

[0005] Therefore, with the aim of improving productivity, the applicants have proposed a plating method for through holes provided in an insulating substrate, as disclosed in Patent Document 3, which involves filling the through holes with metal to fill the cavities of the through holes, wherein the aspect ratio of the through holes is such that the thickness of the insulating substrate is 10 or more when the diameter of the through holes is 1, and the method includes: step 1 of forming a first conductive metal layer on the surface of one side A of the insulating substrate that covers at least the periphery of the through holes and the through holes themselves; and step 2 of using an electrolytic plating method to deposit a second conductive metal layer in the direction of a side B of the insulating substrate, different from side A, using the first conductive metal layer as a current-carrying layer, thereby filling the through holes, wherein the electrolytic plating method in step 2 is characterized by using a method in which the electrolytic plating solution used in the electrolytic plating method is stirred by a powerful jet so that it circulates within the through holes, and the current density is started at a low current density and gradually increased as the deposition of the second conductive metal layer progresses.

[0006] Japanese Patent Application No. 2017-126865, Japanese Patent Application No. 2006-210369, Japanese Patent Application No. 2024-155302

[0007] However, the invention disclosed in Patent Document 3 makes it possible to form via-fill interlayer conductors at high speed by filling high aspect ratio through-holes with conductive metal, and the occurrence of voids inside the via-fill interlayer conductors is reduced compared to conventional methods, but there was a tendency for variations in the electrical resistance of the via-fill interlayer conductors. In other words, even if the occurrence of voids is reduced, it is thought that a certain amount of deposition defects still occur.

[0008] Therefore, the market has desired the provision of high-quality via-fill interlayer conductors that can be filled with conductive metal at high speed and with a high aspect ratio, and that also offer high electrical stability.

[0009] Therefore, in order to solve the above-mentioned problems, we have diligently researched and arrived at the following method for forming via-fill interlayer conductors and circuit boards.

[0010] A. Method for Forming Via-Fill Interlayer Conductors The method for forming a via-fill interlayer conductor according to the present application is a method for forming a via-fill interlayer conductor obtained by filling a through-hole having a high aspect ratio provided in an insulating substrate with metal to fill the cavity portion of the through-hole, characterized in that a via-fill interlayer conductor is obtained by filling a through-hole with metal to fill the cavity portion of the through-hole through the following steps 1 and 2.

[0011] Step 1: A first conductive metal layer is formed on one side surface of the insulating substrate having the through-hole, covering at least the outer periphery of the through-hole and the through-hole itself to form an electrode layer. Step 2: Using the first conductive metal layer as an electrode layer, a via-fill interlayer conductor is obtained by depositing conductive metal into the through-hole from the inner surface of the first conductive metal layer toward the other side of the insulating substrate using an electrolytic plating method. The current density used for depositing the deposit is started at a low current density, and as the deposition progresses, the current density is gradually increased. The deposit plating is performed using a PR electrolytic method in which a reverse current is intermittently passed multiple times while the deposition current is being applied to obtain a via-fill interlayer conductor.

[0012] In the method for forming via-fill interlayer conductors according to this application, the current density used for current deposition of the embedded plating is 0.5 A / dm ２ ~110 A / dm ２ Therefore, it is preferable to gradually increase the current density within this range as the deposition progresses.

[0013] In the method for forming via-fill interlayer conductors according to the present application, the pretreatment for the embedded plating is 1 A / dm for 30 to 100 seconds. ２ ~5A / dm ２ It is preferable to perform reverse electrolysis.

[0014] In the via-fill interlayer conductor formation method relating to this application, the PR electrolysis method involves applying 2 A / dm² for 0.5 to 1.5 seconds every 100 to 150 seconds during the deposition current of the embedded plating. ２ ~5A / dm ２ It is preferable that the reverse electrolysis is applied in a pulsed manner.

[0015] In the method for forming via-fill interlayer conductors according to the present application, the high aspect ratio is preferably such that the thickness of the insulating substrate is 10 or more when the through-hole diameter is 1.

[0016] In the method for forming via-fill interlayer conductors according to the present application, the electrolytic plating solution used in step 2 is an electrolytic copper plating solution containing copper sulfate pentahydrate and sulfuric acid, and preferably contains dithiobis(1-propanesulfonic acid) disodium as an additive, with the content of dithiobis(1-propanesulfonic acid) disodium being 50 ppm or more.

[0017] In the method for forming via-fill interlayer conductors according to the present application, step 1 preferably involves forming a first conductive metal layer that serves as an electrode layer by covering at least the outer periphery of the through-hole and the opening of the through-hole on one side surface of the insulating substrate having the through-hole.

[0018] In the method for forming via-fill interlayer conductors according to the present application, step 1 also preferably involves laminating a metal foil onto one side of the insulating substrate having the through-holes to form the first conductive metal layer as an electrode layer.

[0019] In the method for forming via-fill interlayer conductors according to the present application, it is preferable to include a step of degassing the air in the through-hole between step 1 and step 2.

[0020] The method for forming a via-fill interlayer conductor according to the present application, further comprising an etching step as a subsequent step to step 2, to remove unnecessary portions of the via-fill interlayer conductor protruding to the other side, as described in claim 1.

[0021] B. Circuit board The circuit board relating to this application is obtained using the method for forming via-fill interlayer conductors relating to this application, and is equipped with high-quality via-fill interlayer conductors with few deposition defects.

[0022] By using the via-fill interlayer conductor formation method described in this application, high-quality via-fill interlayer conductors with few deposition defects can be formed at high speed. Therefore, circuit boards obtained using the via-fill interlayer conductor formation method described in this application have via-fill interlayer conductors with stable electrical conductivity, thus improving the quality of the wiring board and contributing to the improvement of the quality stability of electrical and electronic products.

[0023] This is an enlarged schematic diagram of the cross-sectional state of the through-hole portion provided in the insulating substrate at each step of the process. This is a schematic diagram showing the current flow pattern of the embedded plating in step 2. These are optical microscope images of the via-fill interlayer conductors obtained in the example and comparative example.

[0024] The following describes the forming method and the embodiment of the circuit board related to this application. It should be noted that the following description merely illustrates one aspect and should not be interpreted as limiting the scope of the description below.

[0025] A. Embodiment of the Method for Forming Via-Fill Interlayer Conductors The method for forming via-fill interlayer conductors according to this application is a method for forming via-fill interlayer conductors obtained by filling through-holes having a high aspect ratio provided in an insulating substrate with metal to fill the cavities of the through-holes, and is characterized by obtaining via-fill interlayer conductors by filling through-holes with metal to fill the cavities of the through-holes through the following steps 1 and 2. A schematic flow of the steps shown below is shown in Figure 1. Figure 1 is an enlarged schematic diagram showing the cross-sectional state of the through-hole portion provided in the insulating substrate at each step until embedding plating is performed in the through-holes provided in the insulating substrate to form a via-fill interlayer conductor. This is the cross-sectional state as the process progresses from No. 1 to No. 4 in Figure 1. For the sake of clarity, it should be noted that in the process from No. 1 to No. 4 in Figure 1, it is also possible to include other illustrated steps and processes without hindering the basic technical concept.

[0026] The "insulating base material 10" referred to in the present application may be used as long as it has electrical insulating properties, and is, for example, a resin base material such as a glass-epoxy base material or a phenol resin base material, or a base material such as glass or ceramic. It is also possible to use, as the insulating base material 10, a base material that is electrically insulated by, for example, resin-coating the surface of a conductive base material such as aluminum provided with an insulating surface by a method such as alumite treatment and the surface of a through-hole provided in the conductive base material. There are no particular limitations on the thickness of this insulating base material 10.

[0027] The state of No. 1 in FIG. 1 shows a state in which through-holes 11 are provided in the insulating base material 10. Any method can be used for forming the through-holes 11 as long as the desired through-holes 11 can be formed. For example, a perforation method such as a laser method, a drill method, or a resin etching method can be employed. Further, the through-hole 11 in FIG. 1 typically has a cylindrical shape with a circular cross-section, but may have a quadrangular prismatic shape or a polygonal prismatic shape with an angular cross-section. Further, the through-hole may have a tapered shape in the thickness direction of the insulating base material 10.

[0028] The aspect ratio of the through-hole 11 is intended for cases where the thickness of the insulating base material 10 is 10 or more when the diameter of the through-hole 11 is taken as 1. There is no problem in adopting the method for forming a via-filled interlayer conductor according to the present application even when the diameter of the through-hole is 10 μm or less, because the greater the aspect ratio, the more obvious the effect of the invention according to the present application becomes. When the diameter of the through-hole 11 is taken as 1, favorable via-filled interlayer conductors can be formed even when the thickness of the insulating base material 10 is about 250. The process will be described step by step below.

[0029] Step 1: In this step 1, a first conductive metal layer that covers at least the outer periphery of the through-hole and the opening of the through-hole to serve as an electrode layer is formed on one surface side of the insulating base material provided with the through-hole. The description will be given with reference to FIG. 1. The lower one surface side (lower surface A) 12 of the cross-section of No. 1 in FIG. 1, and the upper side of the cross-section of No. 1 is the other surface side (upper surface B) 13.

[0030] Step 1 is a step of forming a first conductive metal layer 20 that covers at least the outer peripheral portion of the through hole 11 and the through hole opening on the surface of one lower surface side (lower surface A) 12 of the insulating base material shown in FIG. 1, as shown in No. 2 of FIG. 1.

[0031] In Step 1, any method can be used for forming the first conductive metal layer 20 on the surface of one surface side (lower surface) 12 of the insulating base material 10, as long as the method can cover at least the outer peripheral portion of the through hole 11 and the through hole opening.

[0032] When only an electrochemical method is used for forming the first conductive metal layer 20, a partial conductive metal layer is formed by plating on at least only the outer peripheral portion of the through hole 11 on the one surface side (lower surface) 12 of the insulating base material 10, and then the first conductive metal layer covering the surface of the partial conductive metal layer and the opening of the through hole 11 can be formed by plating.

[0033] In addition, when an electrochemical method is used for forming the first conductive metal layer 20, titanium oxide (TiO ２ ) and a metal complex containing copper are coated on the one surface side (lower surface) 12 of the insulating base material 10, after heating at 200°C to 300°C, the coated surface is reduced using a reducing agent or the like. Thereafter, a palladium catalyst is applied to the reduced coated surface, electroless nickel plating is performed, and it is also possible to cover the entire surface of the one surface side (lower surface A) 12 of the insulating base material 10 and the through hole opening.

[0034] Furthermore, after activating the reduced coated surface, electroless copper plating is performed to temporarily form an electroless copper plating layer. Subsequently, thick plating is performed by electrolytic copper plating on the surface of the electroless copper plating layer, so that it is also possible to cover the entire surface of the one surface side (lower surface A) 12 of the insulating base material 10 and the through hole opening.

[0035] Furthermore, methods other than electrochemical methods can be used to form the first conductive metal layer 20. The simplest method is to form the first conductive metal layer 20 by laminating a metal foil, such as copper foil or nickel foil, to the surface of one lower side (bottom surface A) 12 of the insulating substrate 10 shown in Figure 1. For example, the first conductive metal layer 20 can be formed by laminating a copper foil with a film thickness of 3 μm to 35 μm to one side (bottom surface A) 12 of the insulating substrate 10.

[0036] Furthermore, as a dry method for forming the first conductive metal layer 20, it is possible to use a sputtering method on the surface of one lower side (bottom surface A) 12 of the insulating substrate 10 shown in Figure 1. For example, the first conductive metal layer 20 can be formed by activating one side (bottom surface A) 12 of the insulating substrate 10 in a vacuum using the ion banvard method and sputtering titanium or copper onto the surface. Here, when performing ion banvard, it is preferable to clean and activate the surface of the insulating substrate 10 before sputtering by degassing the chamber containing the insulating substrate 10 to 0.1 Pa or less, then slowly leaking argon gas into the chamber to a range of 20 Pa to 30 Pa, and plasmaizing the argon gas.

[0037] Step 2: In this step 2, the first conductive metal layer is used as an electrode layer, and a via-fill interlayer conductor is obtained by depositing conductive metal into the through-holes by electroplating from the inner surface of the first conductive metal layer toward the other side of the insulating substrate and performing embedding plating.

[0038] The electroplating in step 2 will now be described. This electroplating solution can be used without any particular limitations, as long as it is capable of being embedded in the through-hole 11 according to this application. For example, when copper is used as the constituent metal of the second conductive metal layer 21, an electroplating solution with the following composition can be used.

[0039] [Basic composition of copper electroplating solution] Copper sulfate pentahydrate: 200-300 g / L Sulfuric acid concentration: 50-100 g / L Cl － Concentration: 50 ppm Additives: Appropriate amount

[0040] Here, the additive in the electrolytic copper plating solution preferably uses at least polyethylene glycol with a polymerization degree of 2,000 to 20,000 (hereinafter referred to as "PEG") and at least one other type selected from disodium dithio-bis(1-propanesulfonate) (hereinafter referred to as "SPS") and Janus Green B (hereinafter referred to as "JGB").

[0041] A nonionic surfactant such as PEG is added for the purpose of eliminating variation in the deposition amount of the second conductive metal layer 21 at the position of the through-hole 11 in the insulating base material 10. The addition amount may be appropriately selected according to the thickness of the insulating base material 10 and the size of the through-hole 11. However, when PEG is used as an additive, it is preferably added at a PEG content of 10 ppm or less. This is because when the PEG content increases, the solution viscosity increases, making it difficult for the plating solution to penetrate into the through-hole 11.

[0042] In addition, sulfur-based organic compounds such as SPS generally bring beneficial effects such as smoothing the surface of the deposited plating film when plating at high current density in electrolytic plating. However, in the electrolytic copper plating solution of the present application, for 200 A / dm ２ it is preferable to use SPS as an additive even in the following low current density regions. In the case of the electrolytic copper plating solution of the present application, it is preferable to add SPS at a content of 50 ppm or more. This is because the deposited copper plating surface is smoothed and has excellent gloss. Although the upper limit of the SPS content is not particularly limited, it is preferably set to 100 ppm or less.

[0043] Dye-based additives such as JGB can obtain the effect of smoothing the surface of the deposited plating film. However, if the addition amount of JGB is excessive, the obtained plating film becomes brittle, so the addition amount is preferably 30 ppm or less.

[0044] The electroplating solution described above is preferably used for plating operations at a bath temperature of 25 ± 5°C. While higher bath temperatures promote plating deposition, higher bath temperatures tend to increase the likelihood of decomposition of additives in the electroplating solution, leading to a decrease in the stability of the plating bath. Therefore, it is preferable to select the bath temperature within the above range, taking into consideration the lifespan of the electroplating solution and productivity.

[0045] Next, the method of applying current for electroplating will be described. Conductive metal is deposited into the through-holes by electroplating from the inner surface of the first conductive metal layer 20 toward the other side of the insulating substrate, thereby performing embed plating. Before performing electroplating, it is preferable to pre-activate the inner surface 13 of the first conductive metal layer 20 by pickling it with dilute sulfuric acid or the like. Furthermore, to prevent excess plating deposition during the electroplating operation, it is preferable to cover the outer surface 12 of the first conductive metal layer 20 with a plating resist, resin film, or the like.

[0046] Then, the first conductive metal layer 20 is used as the current-carrying layer, and the embedding plating of the through-hole 11 is started. When current is applied at this time, it is preferable to start with a low current density in the initial stages of application and gradually increase the current density to a high current density as deposition progresses to perform the embedding plating. As the deposition of electrolytic plating progresses and the through-hole gradually becomes shallower and the aspect ratio decreases, gradually increasing the current density accelerates the plating deposition and allows the plating of the through-hole to be completed in a short time without increasing the deposition defects. Here, "gradually" means that the current density used for electrolytic plating is 1 A / dm ２ ~100 A / dm ２ Assuming electrolysis is performed, the following can be given as examples.

[0047] An example of performing 100 μm of embedded plating using the electroplating method is shown below. (1) As the first electrolytic step, the initial current density of the electroplating is set to 1 A / dm ２ (2) As the second electrolytic step, the current density is set to 50 A / dm ２Then, a 45 μm thick plating deposit constituting the second conductive metal layer 21 is formed inside the through hole 11 in the thickness direction of the insulating substrate. At this point, the embedded plating height is 55 μm. (3) Furthermore, the current density is set to 100 A / dm ２ In this way, a 45 μm thick plating deposition constituting the second conductive metal layer 21 is formed inside the through-hole 11 in the thickness direction of the insulating substrate. (At this point, the embedded plating height becomes 100 μm. In this way, 100 μm of embedded plating can be performed inside the through-hole 11 in the thickness direction of the insulating substrate. Other variations in gradually changing the electrolytic current are determined by considering the aspect ratio of the through-hole, the height (length) of the through-hole, etc., and an example of a 5-stage case is shown in Table 1.

[0048]

[0049] In the present application, when depositing conductive metal into through holes by electroplating and performing embedded plating, it is preferable to use a PR electrolytic method in which a reverse current is intermittently applied multiple times during the current flow of the deposition current in the process of gradually increasing the electrolytic current density as described above. This PR (Periodics Reverse) electrolytic method involves applying a reverse current of 2 A / dm for 0.5 to 1.5 seconds every 100 to 150 seconds during the current flow of the deposition of the embedded plating. ２ ~5A / dm ２ It is preferable to apply reverse electrolysis in a pulsed manner. By adding PR electrolysis, it is possible to appropriately clean the plated deposition surface and flash dissolve abnormal deposition areas during the deposition process, thereby preventing the occurrence of deposition defects such as voids with extremely high precision and reducing variations in electrical conductivity.

[0050] Therefore, in the method for forming via-fill interlayer conductors according to the present application, a pretreatment of 30 to 100 seconds at 1 A / dm is performed as a pretreatment for embedded plating. ２ ~5A / dm ２ It is preferable to first perform reverse electrolysis to smooth and flatten the inner surface 13 side (initial deposition surface) of the first conductive metal layer 20.

[0051] Figure 2(1) shows a schematic diagram of an energizing pattern with reverse electrolysis. Figure 2 is an example of an energizing pattern in which reverse electrolysis is applied in pulses when the current density is increased in stages. Figure 2(1) is an example of an energizing pattern in which reverse electrolysis is performed first as a pretreatment for embedded plating, and then reverse electrolysis is applied in pulses when the current density is increased in stages. In contrast, Figure 2(2) is an example of an energizing pattern in which the current density is simply increased in stages, and no reverse electrolysis is used at all.

[0052] In the case of the electroplating described above, there are no particular limitations on the material of the counter electrode, but it is preferable to use a counter electrode made of a material that contains the metal species to be plated. For example, when performing electroplating of copper, it is preferable to use a copper-based electrode such as copper or phosphorus-containing copper. When electroplating of copper, the amount of copper ions in the copper plating solution decreases, but the dissolution of the counter electrode supplies copper ions to the copper plating solution, thereby maintaining the balance of copper ions contained in the electroplating solution and enabling a longer lifespan of the plating solution.

[0053] Furthermore, by employing the aforementioned plating method for through-holes, it becomes possible to quickly obtain high-quality via-fill interlayer conductors by filling high-aspect-ratio through-holes in insulating substrates with conductive metal and performing high-quality embedded plating without deposition defects.

[0054] In the present application, high-speed electroplating is performed with a high current, requiring a stable supply of metal ions to the plating deposition area and the breakdown of the electron double layer. Therefore, it is thought that strong jet agitation is necessary to efficiently circulate the electroplating solution within the through-holes. However, by adopting the above-described electroplating solution and plating conditions used in this application, when a high-aspect-ratio through-hole 11 is provided in the insulating substrate 10, the electroplating solution is drawn into the through-hole 11 by capillary action. Moreover, when electroplating is performed under the above plating conditions, a significant exothermic reaction occurs at the deposition site, causing convection of the electroplating solution inside the through-hole 11 and obtaining an effect similar to agitation. This makes it possible to supply metal ions to the plating deposition surface that can withstand high-speed electrolysis without supplying a strong flow of electroplating solution into the through-hole 11. It should be noted that sufficient ion supply to the insulating resin substrate surface with the through-hole is necessary, so it is preferable to supply a sufficient amount of electroplating solution to the resin substrate surface.

[0055] In the via-fill interlayer conductor formation method according to the present application described above, it is preferable to include a step of degassing the air in the through-hole between step 1 and step 2. Since the first conductive metal layer 20 covers the through-hole 11, one side 12 of the through-hole 11 is blocked, and the air in the through-hole 11 cannot easily escape. Therefore, by performing a degassing step to degas the air in the through-hole 11, the electroplating solution used in electroplating can easily penetrate into the through-hole 11. Any method that can degas the air in the through-hole 11 can be used. For example, one method is to degas the air in the through-hole 11 by applying ultrasonic vibration to the insulating substrate 10 or the water while the insulating substrate 10 that has gone through step 1 is immersed in water. Alternatively, it is possible to employ a method in which the air in the through-hole 11 is degassed by expanding the air in the through-hole 11 by raising and lowering the water temperature while the insulating substrate 10 that has gone through step 1 is immersed in water. Another method involves immersing the insulating substrate 10 that has gone through step 1 in water and then creating a vacuum in the container of water to remove the air from inside the through-hole 11.

[0056] In the method for forming via-fill interlayer conductors according to the present application, it is preferable to include an etching step as a post-step of step 2 to remove the unnecessary portion of the via-fill interlayer conductor protruding to the other side. No. 3 in Figure 1 shows the state in which the through-hole 11 has been filled in step 2, but the second conductive metal layer 21 is protruding from the other side surface 13. If such a raised portion on the surface of the second conductive metal layer 21 is unnecessary, a via-fill interlayer conductor can be obtained by removing it by etching. No. 4 in Figure 1 shows the state in which the raised portion on the upper part of the other side surface 13 of the second conductive metal layer 21 has been removed by etching.

[0057] Any etching method can be used as long as it can remove unwanted portions of the second conductive metal layer 21. For example, if electrolytic copper plating is performed in step 2 described above, the second conductive metal layer 21 is copper, so a copper etching solution with the following composition can be used.

[0058] [Basic composition of copper etching solution] Sulfuric acid: 5 g / L H ２ O ２ : 50-150 g / L PEG (stabilizer): 5-15 g / L Bath temperature: 20-30°C

[0059] The via-fill interlayer conductor formation method described above in this application allows for the rapid filling of high aspect ratio through-holes in an insulating substrate with conductive metal, thereby filling the cavities of the through-holes with embedded plating that produces fewer deposition defects. The embodiments described so far represent one aspect of the present invention and can be modified as appropriate without departing from the spirit of the present invention. The present invention will be described in more detail below with reference to examples. The invention will be described in more detail below through the examples.

[0060] Example 1 used a glass insulating substrate 10 with a thickness of 200 μm (aspect ratio: 20) and a through hole 11 with a diameter of 10 μm. After degreasing the glass insulating substrate 10, the above-described step 1 was performed using TiO ２A metal complex containing copper was coated onto one side 12, heated at 250°C, and then the coating surface was reduced using a reducing agent. Subsequently, a palladium catalyst was applied to the reduced coating surface, and electroless nickel plating was performed to form a nickel plating layer. Next, the surface of the nickel plating layer was plated using the electrolytic copper plating solution shown below, with phosphorus-containing copper as the counter electrode, at an electrolytic current density of 150 A / dm². ２ By applying a thick layer of electrolytic copper plating, a first conductive metal layer 20 with a thickness of approximately 10 μm was formed, covering the conductive metal layer and the openings of the conductive metal layer.

[0061] [Composition of the electrolytic copper plating solution used for thick plating in Step 1] Copper sulfate pentahydrate: 250 g / L Sulfuric acid: 50 g / L Additives PEG: 0 ppm SPS: 50 ppm JGB: 30 ppm Cl － Concentration: 50ppm Bath temperature: 25℃ Stirring method: High speed stirring

[0062] When step 1 is completed, the through hole 11 is covered by the first conductive metal layer 20, sealing it and preventing air from easily escaping. Therefore, as a degassing step, a method was adopted in which the insulating substrate 10 that has gone through step 1 is immersed in water and subjected to ultrasonic vibration to degas the air inside the through hole 11.

[0063] Next, as a pretreatment for step 2 (embedded plating), a 60-second 3 A / dm ２ Reverse electrolysis was performed to smooth and flatten the inner surface 13 side (initial deposition surface) of the first conductive metal layer 20. Then, as step 2, electrolytic copper plating was performed using the electrolytic copper plating solution shown below, with copper as the counter electrode. The current flow pattern at this time was 1 A / dm ２ ~100 A / dm ２ Within the specified current density range, a five-step electrolysis process was employed. These five steps are described below in detail.

[0064] [Composition of the electrolytic copper plating solution used in step 2] Copper sulfate pentahydrate: 250 g / L Sulfuric acid: 50 g / L Additives SPS: 50 ppm JGB: 30 ppm Cl －Concentration: 50 ppm Bath temperature: 25 ± 5°C Stirring method: Oscillating and high-speed stirring (flow rate 4 L / min)

[0065] [Energy application step in step 2 of Example 1] First electrolysis step: 5 A / dm ２ Second electrolysis step: 15 A / dm ２ Third electrolysis step: 40 A / dm ２ Fourth electrolysis step: 80 A / dm ２ Fifth electrolysis step: 100 A / dm ２

[0066] Furthermore, in the process of gradually increasing the electrolytic current density as described above, the PR electrolytic method, which uses a reverse current that is intermittently passed multiple times while the deposition current is being applied, applies 3 A / dm for 1.0 second every 120 seconds during the deposition current application of the embedded plating. ２ By applying pulsed reverse electrolysis, the plated deposition surface during the deposition process was cleaned, and abnormal deposition areas were flash-dissolved to prevent the occurrence of deposition defects.

[0067] As described above, copper was filled into through-holes with a high aspect ratio provided in the insulating substrate, and the cavities of the through-holes were filled with copper plating to form the basic shape of the via-fill interlayer conductor (No. 3 in Figure 1). Then, as a post-processing step of step 2, the raised protruding portions on the surface of the second conductive metal layer 21 were removed by etching using the copper etching solution described above to obtain a high-quality via-fill interlayer conductor with few deposition defects. Comparative Example

[0068] This comparative example uses a 60-second 3 A / dm² treatment as a pretreatment for step 2 (embedded plating) of the example. ２ The reverse electrolysis and the PR electrolysis method, which involves intermittently applying multiple reverse currents while the deposition current is being supplied, were omitted to obtain a via-fill interlayer conductor. The rest of the procedure was the same as in Example 1.

[0069] [Comparison of Examples and Comparative Examples] The insulating substrate 10 equipped with via-fill interlayer conductors obtained in the examples and comparative examples were subjected to X-ray imaging and optical microscope observation as shown in Figure 3 of the cross-section. As a result, as shown in Figure 3(1), it can be confirmed that the filling plating of the through holes 11 in the examples has very few deposition defects such as voids. In contrast, in the case of the comparative examples, as can be seen from Figure 3(2), many deposition defects are observed near the center of the filling plating of the through holes 11 compared to the examples.

[0070] The method for forming via-fill interlayer conductors according to this application allows for the rapid filling of cavities in high-aspect-ratio through-holes provided in an insulating substrate, and enables the formation of via-fill interlayer conductors with excellent electrical conductivity stability due to fewer deposition defects. Therefore, it becomes possible to provide high-quality multilayer wiring boards equipped with such via-fill interlayer conductors.

[0071] 10 Insulating substrate 11 Through hole 12 One side 13 Other side 20 First conductive metal layer 21 Second conductive metal layer

Claims

1. A method for forming a via-fill interlayer conductor obtained by filling a through-hole having a high aspect ratio in an insulating substrate with metal to fill the cavity portion of the through-hole, characterized in that a via-fill interlayer conductor is obtained by filling a through-hole with metal to fill the cavity portion of the through-hole through the following steps 1 and 2. Step 1: A first conductive metal layer is formed on one side surface of the insulating substrate having the through-hole, covering at least the outer periphery of the through-hole and the through-hole itself to form an electrode layer. Step 2: Using the first conductive metal layer as an electrode layer, a via-fill interlayer conductor is obtained by depositing conductive metal into the through-holes from the inner surface of the first conductive metal layer toward the other side of the insulating substrate using an electrolytic plating method. The current density used for depositing the embedded plating is started at a low current density, and as the deposition progresses, the current density is gradually increased. The embedded plating is performed using a PR electrolytic method in which a reverse current is intermittently passed multiple times while the deposition current is being applied, thereby obtaining a via-fill interlayer conductor.

2. The current density used for current deposition of the embedded plating is 0.5 A / dm². ２ ~110 A / dm ２ The method for forming a via-fill interlayer conductor according to claim 1, wherein the current density is increased in stages within this range as the deposition progresses.

3. As a pretreatment for the embedded plating in step 2, 1 A / dm for 30 to 100 seconds. ２ ~5A / dm ２ A method for forming a via-fill interlayer conductor according to claim 1, wherein reverse electrolysis is performed.

4. The PR electrolytic method involves applying a current of 2 A / dm² for 0.5 to 1.5 seconds every 100 to 150 seconds during the deposition current application of the embedded plating. ２ ~5A / dm ２ A method for forming a via-fill interlayer conductor according to claim 1, wherein reverse electrolysis is pulsed.

5. The method for forming a via-fill interlayer conductor according to claim 1, wherein the high aspect ratio is such that the thickness of the insulating substrate is 10 or more when the through-hole diameter is 1.

6. The method for forming a via-fill interlayer conductor according to claim 1, wherein the electrolytic plating solution used in step 2 is an electrolytic copper plating solution containing copper sulfate pentahydrate and sulfuric acid, and contains dithiobis(1-propanesulfonic acid) disodium as an additive, and the content of dithiobis(1-propanesulfonic acid) disodium is 50 ppm or more.

7. The method for forming a via-fill interlayer conductor according to claim 1, wherein step 1 is the process of forming a first conductive metal layer that covers at least the outer periphery of the through-hole and the opening of the through-hole on one side surface of an insulating substrate having the through-hole, thereby forming an electrode layer.

8. The method for forming a via-fill interlayer conductor according to claim 1, wherein step 1 is performed by laminating a metal foil onto one surface of the insulating substrate having the through-hole to form the first conductive metal layer as a copper electrode.

9. The method for forming a via-fill interlayer conductor according to claim 1, further comprising a step of degassing the air in the through-hole between step 1 and step 2.

10. The method for forming a via-fill interlayer conductor according to claim 1, further comprising an etching step as a post-step of step 2, to remove unnecessary portions of the via-fill interlayer conductor protruding to the other side.

11. A circuit board characterized by ensuring interlayer conductivity using the via-fill interlayer conductor formation method described in claim 1.

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