Design support method, program, and information processing device

Abstract

This design support method causes a computer to perform a process for: acquiring a code at a register-transfer level generated in accordance with performance metrics; extracting memory information from the acquired code; and deriving, on the basis of the extracted memory information, applicable memory configuration information to be applied on a chip on which a semiconductor integrated circuit is to be implemented.

Description

Design support method, program, and information processing apparatus

[0001] The present invention relates to a design support method, a program, and an information processing apparatus. This application claims priority based on United States Application No. 63 / 779799 filed on March 28, 2025, and incorporates all contents described in said United States application by reference.

[0002] Conventionally, general-purpose semiconductors that can be mounted on various products have been mass-produced. Examples of general-purpose semiconductors include a CPU (Central Processing Unit) mounted on a personal computer. General-purpose semiconductors based on the basic concept of the conventional von Neumann architecture have been designed to have high performance in sequential processing. According to Moore's Law, it is believed that the production cost of semiconductors can be reduced by increasing the degree of integration. Therefore, conventional semiconductors have had the main goal of increasing the production volume of general-purpose semiconductors and reducing production costs. However, increasing the production volume of semiconductors requires a large amount of capital investment. For this reason, the fabless production system, in which a business operator mainly engaged in semiconductor design outsources semiconductor production to an external business operator, has become mainstream. Patent Document 1 discloses a technique related to lithography-based pattern optimization.

[0003] U.S. Patent No. 11449659 Specification

[0004] However, in the technique disclosed in Patent Document 1, no consideration is given at all to the point of deriving applied memory configuration information to be applied on a chip on which a semiconductor integrated circuit is mounted, based on memory information extracted from an acquired code.

[0005] An object of the present disclosure is to provide a design support method and the like that can derive applied memory configuration information to be applied on a chip on which a semiconductor integrated circuit is mounted, based on memory information extracted from an acquired code.

[0006] A design support method according to one aspect of this disclosure involves obtaining register transfer level code generated according to a performance indicator, extracting memory information from the obtained code, and causing a computer to perform a process to derive applicable memory configuration information to be applied on a chip on which a semiconductor integrated circuit is mounted, based on the extracted memory information.

[0007] A program according to one aspect of this disclosure obtains register transfer level code generated according to a performance indicator, extracts memory information from the obtained code, and causes a computer to perform a process to derive applicable memory configuration information to be applied on a chip on which a semiconductor integrated circuit is mounted, based on the extracted memory information.

[0008] An information processing device according to one aspect of the present disclosure is an information processing device comprising a control unit that performs processing related to the design support of a semiconductor integrated circuit, wherein the control unit acquires register transfer level code generated according to a performance indicator, extracts memory information from the acquired code, and derives applicable memory configuration information to be applied on a chip on which a semiconductor integrated circuit is mounted based on the extracted memory information.

[0009] According to one aspect of this disclosure, a design support method can be provided that derives applicable memory configuration information to be applied on a chip on which a semiconductor integrated circuit is mounted, based on memory information extracted from acquired code.

[0010] This is a schematic diagram illustrating the overview of the semiconductor design support system according to Embodiment 1. This is a block diagram showing the configuration of the information processing device. This is a functional block diagram illustrating the functional units included in the control unit of the information processing device. This is an explanatory diagram illustrating a floor plan corresponding to memory configuration. This is a flowchart illustrating the processing procedure by the control unit of the information processing device.

[0011] (Embodiment 1) Hereinafter, embodiments will be described based on the drawings. Figure 1 is a schematic diagram illustrating the overview of the semiconductor design support system S according to Embodiment 1. Figure 2 is a block diagram showing the configuration of the information processing device 1. The semiconductor design support system S is configured with an information processing device 1, which functions as a semiconductor design support server, as the main device. The information processing device 1 (semiconductor design support server) is connected to a terminal device 2 (designer PC) used by a semiconductor integrated circuit designer, for example, via a network such as the Internet or an intranet, so as to be able to communicate.

[0012] As will be explained in detail later, the terminal device 2 (designer's PC) transmits logic design data such as register transfer level (RTL), performance indicators (PPA: Power / Performance / Area), timing constraints (SDC: Synopsys Design Constraints), and memory library (LIB) for the semiconductor integrated circuit that is the target of physical design to the information processing device 1 (semiconductor design support server). Based on the logic design data acquired from the terminal device 2, the information processing device 1 outputs the code (RTL) or netlist to be used for logic synthesis when performing physical design such as the placement and routing process of the semiconductor integrated circuit. The code (RTL) or netlist is derived using an AI analysis engine (PPA evaluation model 101, design difficulty evaluation model 102, etc.) implemented in the information processing device 1, and incorporates or applies the optimal or suitable memory configuration and floor plan (partitioning) corresponding to the memory configuration for the placement and routing process.

[0013] A designer using terminal device 2 performs physical design, such as placement and routing processes, using code (RTL) or netlist output from information processing device 1, and outputs the results of applying the netlist, etc., to the physical design (application result data) to information processing device 1. This enables efficient support for physical design of semiconductor integrated circuits. When performing physical design, such as placement and routing processes, information processing device 1 can improve the accuracy of deriving or evaluating memory configuration proposals (configurations combining memory configuration and floor plan) by registering or performing additional training on all acquired, generated, and derived data, including the application result data finally acquired from terminal device 2, into the AI ​​analysis engine.

[0014] The information processing device 1 is a computer capable of various information processing and information transmission / reception, such as a server device or a personal computer. The server device includes not only a single server device but also a cloud server device or a virtual server device composed of multiple computers. The information processing device 1 includes a control unit 11, a storage unit 12, a communication unit 13, and an input / output interface 14.

[0015] The control unit 11 has one or more arithmetic processing units equipped with timing functions, such as a CPU (Central Processing Unit), an MPU (Micro-Processing Unit), and a GPU (Graphics Processing Unit), and performs various information processing, control processing, etc., by reading and executing a program P (program product) stored in the storage unit 12. Furthermore, the control unit 11 may include a semiconductor chip (AI chip) specialized for AI processing such as machine learning and deep learning.

[0016] The storage unit 12 includes volatile storage areas such as SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and flash memory, as well as non-volatile storage areas such as EEPROM or hard disk. The storage unit 12 pre-stores programs P (program products) and data referenced during processing, and also stores various data, including intermediate data, generated during processing. The programs P (program products) stored in the storage unit 12 may be programs P (program products) read from a recording medium M that the information processing device 1 can read. Alternatively, programs P (program products) may be downloaded from an external computer (not shown) connected to a communication network (not shown) and stored in the storage unit 12. As will be described in detail later, the storage unit 12 stores actual files such as a design database 121, a PPA evaluation model 101, and a design difficulty evaluation model 102.

[0017] The communication unit 13 is a communication module or communication interface for communicating with terminal devices 2, etc., via wired or wireless methods such as Ethernet (registered trademark), and is, for example, a narrow-area wireless communication module such as Wi-Fi (registered trademark) or Bluetooth (registered trademark), or a wide-area wireless communication module such as 4G or 5G. The control unit 11 communicates with terminal devices 2, such as personal computers used by designers, etc., via the communication unit 13, for example, through an external network such as the Internet or a LAN, and may also communicate with an external server (AI cloud server) on which LLM, etc., is implemented.

[0018] The input / output interface 14 includes terminals such as USB or serial cables, to which a display unit such as a monitor or an input / output device such as a keyboard is connected.

[0019] Figure 3 is a functional block diagram illustrating the functional units included in the control unit 11 of the information processing device 1. The control unit 11 of the information processing device 1 functions as the acquisition unit 111, memory configuration extraction unit 112, memory configuration generation unit 113 (memory compiler), partition generation unit 114 (partition engine), memory configuration proposal derivation unit 115, optimal memory configuration proposal derivation unit 116, improvement feasibility determination unit 117, convergence feasibility determination unit 118 (simulator), and output unit 119, etc., by executing the program P stored in the storage unit 12. The control unit 11 of the information processing device 1 functions as an AI analysis engine (learning model) including the PPA evaluation model 101 and the design difficulty evaluation model 102, etc., by reading the actual files of the PPA evaluation model 101 (performance index estimation model) and the design difficulty evaluation model 102 stored in the storage unit 12.

[0020] The AI ​​analysis engine (learning model) that functions as a PPA evaluation model 101 or a design difficulty evaluation model 102, etc., is not limited to being implemented in the information processing device 1, but may also be implemented in a cloud server (AI cloud server), for example, and consist of a large-scale language model (LLM) that has been fine-tuned with various design information (corpus) related to semiconductor integrated circuits. In this case, the information processing device 1 that functions as a semiconductor design support server may communicate with the AI ​​cloud server via an API (Application Programming Interface) and perform various processing using the large-scale language model implemented in the AI ​​cloud server.

[0021] The acquisition unit 111 acquires logic design data, including, for example, performance indicators (PPA: Power / Performance / Area) required for the semiconductor integrated circuit, register transfer level code (RTL: Register Transfer Level) generated according to the performance indicators (PPA), timing constraints (SDC: Synopsys Design Constraints), and memory library (LIB), from the terminal device 2 (designer PC) of a designer performing the logic design of a semiconductor integrated circuit. Alternatively, the acquisition unit 111 may acquire a netlist synthesized using the register transfer level code (RTL), etc., as logic design data. The acquisition unit 111 stores this acquired logic design data in the storage unit 12 and outputs it to the memory configuration extraction unit 112 and the partition generation unit 114, etc., which are responsible for subsequent processes.

[0022] The memory configuration extraction unit 112 extracts memory information (Memory Instance) from the acquired code (RTL). At this time, the memory configuration extraction unit 112 extracts the memory request amount (for example, RTL) defined in the bitword configuration contained in the code (RTL).<Memory instance> It is also acceptable to derive memory information (Mrmory Instance) as 160 [Width] × 2048 [depth].

[0023] The memory configuration generation unit 113 (memory compiler) may, for example, use a general-purpose memory compiler, and this memory compiler may derive multiple candidate memory configuration information (memory configuration proposals) by referring to a memory library (LIB) obtained together with the code (RTL). The memory library (LIB) contains multiple possible memory configuration proposals for memory information (Mrmory Instance), and each memory configuration proposal defines information regarding the number of memory divisions and the location of memory.

[0024] The memory configuration generation unit 113 derives a memory configuration proposal with divided memory if there is no memory corresponding to the bitword configuration requested in the memory information (Mrmory Instance) (because the requested size is larger than the supported bitword (B / W) configuration). Alternatively, even if the implementable memory is smaller than the maximum difference size supported by the bitword configuration, the memory configuration generation unit 113 may derive a memory configuration proposal with divided memory if dividing the memory is advantageous from a floor plan design perspective. As the size of each divided memory becomes smaller, the dead space tends to increase, the access time per memory unit becomes faster, and the degree of placement flexibility tends to increase. The memory configuration generation unit 113 may comprehensively judge the trends in each characteristic and derive multiple candidate memory configuration information (memory configuration proposals).

[0025] The partition generation unit 114 (partition engine) may, for example, use a general-purpose partition engine, and this partition engine derives multiple partition proposals (floor plan proposals) based on acquired code (RTL), performance indicators (PPA), and timing constraints (SDC), etc. Each floor plan proposal includes multiple partitions, and these partitions divide the area to form a hierarchical layout block (HLB). Each partition (HLB) will be allocated memory (multiple divided memories) as indicated in the memory configuration proposal.

[0026] The memory configuration proposal derivation unit 115 derives multiple memory configuration proposals by combining multiple candidate memory configuration information and multiple partition proposals. Given the importance of optimal memory configuration, the memory configuration and the corresponding floor plan are inseparable for evaluating performance indicators such as PPAC+t. Therefore, it is necessary to perform a search that considers variations in memory configuration (multiple candidate memory configuration information) in addition to the normal floor plan (a floor plan derived by a general-purpose partition engine), i.e., to derive the optimal result. In response to this, the memory configuration proposal derivation unit 115 derives multiple memory configuration proposals for all combinations of the derived candidate memory configuration information (memory configuration proposals) and partition proposals (floor plan proposals), so it can efficiently perform a search for all of these combinations.

[0027] The memory configuration deriving unit 115 may derive multiple memory configurations using a memory configuration model (memory layout model) that derives a memory configuration in which divided memory is placed on the floor plan when memory configuration information (memory configuration) and partition proposals (floor plan proposals) are input. The memory configuration deriving unit 115 sequentially inputs each of the derived multiple memory configurations into the PPA evaluation model 101.

[0028] The PPA evaluation model 101 receives data in which the memory configuration (proposed memory configuration), i.e., the memory configuration has been expanded into the floor plan, as input. Based on this memory configuration, it estimates the performance indicators of a semiconductor integrated circuit when a physical design is performed, and outputs the estimated performance indicators (predicted performance indicators). In other words, the PPA evaluation model 101 functions as a performance indicator estimation model. Alternatively, the PPA evaluation model 101 may individually output the estimated performance indicators (predicted performance indicators) for each partition where memory is located. The PPA evaluation model 101 may be composed of a large-scale language model (LLM) trained by self-supervised learning using design information consisting of a combination of logic design data, floor plan data, physical design process, and performance indicators of the semiconductor integrated circuit manufactured in the physical design process. In this case, the PPA evaluation model 101 may output performance indicators (predicted performance indicators) such as the degree of PPA achievement for the input memory configuration proposal by referring to and searching a design database 121, for example, a RAG (vector database).

[0029] The design database 121 stores data related to past floor plans (memory configuration such as memory partitioning, hierarchical layout, partitioning, and floor plans) and the design difficulty for said floor plan, in association with each other. The PPA evaluation model 101 may interpret the various information contained in the input memory configuration proposal by, for example, vectorizing it, and then perform a vector search using cosine similarity or the like on the design database 121 to obtain related data such as PPA evaluations of memory configurations similar to the memory configuration proposal. Alternatively, the PPA evaluation model 101 may consist of a simulator that performs simulations based on the input physical design process and design to estimate performance indicators. The PPA evaluation model 101 performs PPA evaluations (estimates performance indicators) for all memory configuration proposals derived by the memory configuration proposal derivation unit 115, and stores the evaluation results and the memory configuration proposals to be evaluated in association with each other in the storage unit 12.

[0030] The optimal memory configuration derivation unit 116 derives the memory configuration (candidate memory configuration information) with the highest degree of PPA achievement (most positive verification results) as the optimal memory configuration (applicable memory configuration information) based on the evaluation results of the PPA evaluation model 101 for all memory configurations (candidate memory configuration information) derived by the memory configuration derivation unit 115. When the PPA evaluation model 101 estimates each performance indicator consisting of processing performance (Performance), power (Power), and area (Area), it is assumed that a trade-off relationship will occur between these performance indicators. In response to this, the optimal memory configuration derivation unit 116 may derive a suitable or optimal memory configuration as the optimal memory configuration (applicable memory configuration information) by, for example, using a Pareto optimal solution for these performance indicators.

[0031] The optimal memory configuration derivation unit 116 inputs the derived optimal memory configuration (applicable memory configuration information) into the design difficulty evaluation model 102. Alternatively, the optimal memory configuration derivation unit 116 may incorporate the derived optimal memory configuration (applicable memory configuration information) into a netlist and input the netlist into the design difficulty evaluation model 102.

[0032] The design difficulty evaluation model 102 takes a memory configuration or a netlist incorporating the memory configuration as input and estimates and outputs the design difficulty if a physical design were performed based on the said memory configuration (netlist). Furthermore, if a memory configuration (netlist) is input, the design difficulty evaluation model 102 may also output the expected convergence period (expected convergence period) and the PPA metrics evaluation (overall performance indicator evaluation) for the design. In addition, if there is room for improvement (possibility of improvement), such as when the design difficulty is higher than a predetermined threshold, the design difficulty evaluation model 102 may also pick out the estimated causes of the evaluation result and output improvement proposals.

[0033] The design difficulty evaluation model 102 may be composed of a large-scale language model (LLM) trained by self-supervised learning using design information including logic design data, floor plan data, physical design process, and the design difficulty of the semiconductor integrated circuit manufactured in the physical design process. In this case, the design difficulty evaluation model 102 may output the design difficulty for the input memory configuration proposal by referring to and searching a design database 121, which is composed of, for example, a RAG (vector database). Based on the optimal memory configuration proposal output from the optimal memory configuration proposal derivation unit 116, the design difficulty evaluation model 102 outputs an evaluation result including the design difficulty for the optimal memory configuration proposal.

[0034] The improvement feasibility determination unit 117 determines whether the optimal memory configuration to be evaluated is improveable based on the evaluation results, such as design difficulty, output from the design difficulty evaluation model 102. In this case, the evaluation results output from the design difficulty evaluation model 102 may include whether or not improvement is possible, and if improvement is possible, the estimated cause of the evaluation result and the improvement plan. The improvement feasibility determination unit 117 may determine whether or not the optimal memory configuration to be evaluated is improveable based on these evaluation results, including improvement feasibility and estimated cause.

[0035] If the improvement feasibility determination unit 117 determines that improvement is possible, it may generate an iteration (repeated processing) by outputting the estimated cause and improvement plan resulting from the evaluation to the partition generation unit 114. The partition generation unit 114 takes the estimated cause and improvement plan from the improvement feasibility determination unit 117 as additional input information and executes the partition engine again to regenerate a partition plan (floor plan plan) that reflects the improvement plan, and performs the processes described above again. The improvement feasibility determination unit 117 may also output the estimated cause and improvement plan to the memory configuration generation unit 113, generating an iteration (repeated processing). The memory configuration generation unit 113 also performs the processes described above again, such as regenerating a memory configuration plan that reflects the improvement plan, similar to the partition generation unit 114.

[0036] If the improvement feasibility determination unit 117 determines that improvement is not possible, that is, that there is no further room for improvement, it outputs the optimal memory configuration proposal to the convergence feasibility determination unit 118. If the processing of the optimal memory configuration proposal is performed on a partition basis for each partition included in the partition proposal (floor plan proposal), the improvement feasibility determination unit 117 may determine whether improvement is possible for all partitions (HLBs) included in the partition proposal (floor plan proposal), and if it determines that improvement is not possible for all partitions (determined that there is no further room for improvement), it may output the optimal memory configuration proposal to the convergence feasibility determination unit 118.

[0037] The convergence feasibility determination unit 118 (simulator) checks the design convergence of the entire design, which is composed of all partitions (HLBs) included in the partition plan (floor plan), for the optimal memory configuration plan output from the improvement feasibility determination unit 117. Design convergence is determined by whether or not the design can be completed within a predetermined period of time. The convergence feasibility determination unit 118 may, for example, determine the presence or absence of design convergence by using a simulator (design convergence simulator) on a netlist incorporating the optimal memory configuration plan. Alternatively, the convergence feasibility determination unit 118 may determine the presence or absence of design convergence of the optimal memory configuration plan by inputting the optimal memory configuration plan (netlist) into a design convergence model that outputs whether or not design convergence is present when a memory configuration (netlist) is input. In this case, if the simulator or design convergence model outputs a determination (prediction) that design convergence is not present, it may also identify and output the problem locations (e.g., within a partition, top, partition boundary, etc.) that form the basis of the determination result.

[0038] If the convergence feasibility determination unit 118 determines that the design does not converge, it may generate an iteration (repeated processing) by outputting the problem locations that form the basis of the evaluation result to the partition generation unit 114. The partition generation unit 114 takes the problem locations from the convergence feasibility determination unit 118 as additional input information and executes the partition engine again to regenerate a partition plan (floor plan plan) that reflects the improvement plan, and performs the processing described above again. The convergence feasibility determination unit 118 may also output the problem locations to the memory configuration generation unit 113, generating an iteration (repeated processing). The memory configuration generation unit 113 also performs the processing described above again, such as regenerating a memory configuration plan that reflects the countermeasures for the problem locations, similar to the partition generation unit 114. If the convergence feasibility determination unit 118 determines that the design converges, it outputs the optimal memory configuration plan to the output unit 119.

[0039] The output unit 119 may generate an application code (RTL) incorporating the application memory configuration information by incorporating the optimal memory configuration proposal from the convergence feasibility determination unit 118 into the code (RTL) from the acquisition unit 111, and output the application code (RTL) to the terminal device 2 (designer PC). The output unit 119 may also store the generated application code (RTL) in the storage unit 12 and generate a netlist by logic synthesis, and in this case, it may also output the netlist to the terminal device 2 (designer PC).

[0040] In this embodiment, the PPA evaluation model 101 and the design difficulty evaluation model 102, etc., are assumed to be separate instances of LLM, etc., but this is not limited to this. The PPA evaluation model 101 and the design difficulty evaluation model 102, etc., may be implemented in a single instance of LLM, etc. Thus, the AI ​​analysis engine environment in the semiconductor design support system S may be composed of a single LLM and RAG, etc., that comprehensively include the necessary processing and data.

[0041] Figure 4 is an explanatory diagram illustrating a floor plan corresponding to a memory configuration. In the semiconductor design support system S, the memory configuration and floor plan (partition) are automatically generated (automatic partitioning) based on the input register transfer level code (RTL). The memory configuration is generated as multiple candidates based on the memory instances extracted from the code (RTL). The memory configuration generated as multiple candidates has the size and placement location of each of the multiple memories divided according to the memory instances defined. The floor plan is divided into areas by multiple partitions and is generated as multiple candidates. The floor plan generated as multiple candidates has the area and placement location of each partition that divides each area defined according to the PPA that the code (RTL) should possess.

[0042] From the input code (RTL), a plurality of memory configuration candidates and a plurality of floor plan candidates are generated. For all combinations (memory configuration candidates) of these plurality of memory configuration candidates and floor plan candidates, PPA metric evaluation or design difficulty evaluation is executed by the PPA evaluation model 101 or the design difficulty evaluation model 102. Based on the results of the PPA metric evaluation, for example, the memory configuration candidate with the highest PPA evaluation, the memory configuration candidate with the lowest design difficulty, or the most suitable or positive memory configuration candidate determined by comprehensive judgment of a plurality of evaluation indicators is selected as the optimal memory configuration candidate. The optimal memory configuration candidate selected in this way is incorporated into the register transfer level code (RTL), which is the input data for a series of processes, and is logically synthesized, whereby a netlist to which an optimal or suitable memory configuration is applied can be obtained.

[0043] FIG. 5 is a flowchart illustrating an example of a processing procedure performed by the control unit 11 of the information processing apparatus 1. The control unit 11 of the information processing apparatus 1 receives an operation by an operator from, for example, the terminal apparatus 2 (designer PC) or an operation by an operator via a keyboard or the like connected to the input / output I / F 14, and performs the following processing based on the received operation.

[0044] The control unit 11 of the information processing apparatus 1 acquires a code at the register transfer level and performance indicators (S101). The control unit 11 of the information processing apparatus 1 acquires logic design data such as a code at the register transfer level (RTL), performance indicators (PPA), and timing constraints (SDC) for a semiconductor integrated circuit that is a target of physical design from, for example, the terminal apparatus 2 (designer PC). Furthermore, the control unit 11 of the information processing apparatus 1 may also acquire a memory library (LIB) corresponding to various bit words.

[0045] The control unit 11 of the information processing device 1 extracts memory information from the acquired code (S102). The control unit 11 of the information processing device 1 may also refer to a memory library (LIB) acquired together with the code (RTL) at the register transfer level and extract memory information (Memory instance) from the code (RTL). Alternatively, the storage unit 12 of the information processing device 1 may have a memory library (LIB) containing various types of memory information (Memory instance) pre-stored in it, and the control unit 11 of the information processing device 1 may refer to the memory library (LIB) pre-stored in the storage unit 12 and extract memory information (Memory instance) from the code (RTL).

[0046] The control unit 11 of the information processing device 1 derives a plurality of candidate memory configuration information based on the extracted memory information (S103). The control unit 11 of the information processing device 1 may, for example, start a memory compiler by executing an application stored in the storage unit 12, and use the memory compiler to derive a plurality of candidate memory configuration information (memory configuration proposals) based on the extracted memory information. The control unit 11 of the information processing device 1 stores the derived plurality of candidate memory configuration information (memory configuration proposals) in the storage unit 12. Each of the candidate memory configuration information (memory configuration proposals) is defined by the amount of memory required by the bit word included in the acquired code (RTL) (for example, RTL<Memory instance> This corresponds to a 160[Width] x 2048[depth] configuration, and includes the size and arrangement of multiple divided memory modules.

[0047] The control unit 11 of the information processing apparatus 1 derives a plurality of partition plans based on the acquired code (S104). For example, the control unit 11 of the information processing apparatus 1 activates a partition engine by executing an application stored in the storage unit 12, and uses the partition engine to derive a plurality of partition plans. In this case, the partitions correspond to hierarchical layout blocks (HLBs), and a floorplan divided by a plurality of partitions may be derived as a partition plan. In other words, the control unit 11 of the information processing apparatus 1 may derive a plurality of floorplan plans based on the acquired code (RTL). In this case, each individual floorplan plan includes a plurality of partitions and is configured by being divided by these partitions.

[0048] The control unit 11 of the information processing apparatus 1 derives a plurality of memory configuration plans based on combinations of a plurality of candidate memory configuration information items and a plurality of partition plans (S105). The candidate memory configuration information includes the sizes and arrangements of a plurality of memories divided according to bit words, and the partition plan (floorplan plan) includes the number of HLBs, the shape of HLBs, and the memory arrangement (arrangement area) in each HLB for a plurality of hierarchical layout blocks (HLBs). When the control unit 11 of the information processing apparatus 1 derives memory configuration plans, the number of memory configuration plans is, for example, a value obtained by multiplying the number of candidate memory configuration information items by the number of partition plans (floorplan plans), and may be the number of combinations of all candidate memory configuration information items and partition plans (floorplan plans). Each of the plurality of derived memory configuration plans is an evaluation target for design difficulty or achievement level such as PPA.

[0049] The control unit 11 of the information processing apparatus 1 performs PPA evaluation on a plurality of memory configuration plans (S106). For example, the control unit 11 of the information processing apparatus 1 uses the PPA evaluation model 101 to perform PPA evaluation on each individual memory configuration plan, and stores the evaluation result (for example, the achievement level of PPA) in the storage unit 12 in association with the memory configuration plan that is the evaluation target.

[0050] The control unit 11 of the information processing device 1 identifies one of the multiple memory configurations as the optimal memory configuration based on the evaluation results of the PPA (S107). The control unit 11 of the information processing device 1 may also identify the memory configuration that yields the most suitable or positive evaluation result in the PPA evaluation results for each of the multiple memory configurations as the optimal memory configuration. In this case, the control unit 11 of the information processing device 1 may identify the optimal memory configuration by, for example, using a Pareto optimal solution for each performance indicator consisting of processing performance, power, and area included in the PPA evaluation results.

[0051] The control unit 11 of the information processing device 1 performs an evaluation of the design difficulty for the identified optimal memory configuration (S108). The control unit 11 of the information processing device 1 performs an evaluation of the design difficulty for the optimal memory configuration, for example, by using a design difficulty evaluation model 102, and stores the evaluation result (for example, design difficulty) in the storage unit 12, relating it with the optimal memory configuration that was evaluated. At this time, the design difficulty evaluation model 102 may output the design difficulty, convergence period prediction, and PPA metric evaluation results for the input optimal memory configuration.

[0052] The control unit 11 of the information processing device 1 determines whether the optimal memory configuration can be improved (S109). The control unit 11 of the information processing device 1 determines whether the optimal memory configuration can be improved based on the output results from the design difficulty evaluation model 102, i.e., the design difficulty, convergence period prediction, and PPA metric evaluation results, and other evaluation results. In this case, the design difficulty evaluation model 102 may also output whether improvements are possible based on these evaluation results, in addition to the design difficulty, convergence period prediction, and PPA metric evaluation results. Furthermore, if the design difficulty evaluation model 102 outputs that improvements are possible, it may, for example, search or refer to the design database 121 (RAG) to pick up the estimated causes that form the basis of the evaluation and also output improvement proposals.

[0053] The control unit 11 of the information processing device 1 may determine whether the optimal memory configuration can be improved based on whether improvements are possible as included in the output content from the design difficulty evaluation model 102. Alternatively, the storage unit 12 of the information processing device 1 may store a table (feasibility determination table) that associates the feasibility of improvements with combinations of various evaluation results such as design difficulty, convergence period prediction, and PPA metric evaluation, and the control unit 11 of the information processing device 1 may refer to the feasibility determination table based on the evaluation results from the design difficulty evaluation model 102 to determine whether the optimal memory configuration can be improved.

[0054] If improvement is possible (S109: YES), the control unit 11 of the information processing device 1 picks up the estimated cause and derives an improvement plan (S1091). The control unit 11 of the information processing device 1 may, for example, pick up the estimated cause and derive an improvement plan by obtaining the estimated cause and improvement plan from the design difficulty evaluation model 102. Alternatively, the control unit 11 of the information processing device 1 may pick up the estimated cause and derive an improvement plan by searching or referring to the design database 121 (RAG) based on the evaluation results from the design difficulty evaluation model 102. After executing this process, the control unit 11 of the information processing device 1 performs a loop process to execute the process of S104 again using the derived improvement plan.

[0055] If improvement is not possible (S109: NO), the control unit 11 of the information processing device 1 performs a design convergence check for all partitions (S110). The control unit 11 of the information processing device 1 performs a design convergence check for the overall design formed by applying the corresponding memory configuration information (memory configuration proposal) to each partition (each HLB) included in the floor plan proposal selected as the optimal memory configuration proposal.

[0056] The control unit 11 of the information processing device 1 may, for example, start a simulator by executing an application stored in the memory unit 12, and by executing the simulator, perform a design convergence check for the entire design for all partitions (HLBs) to which the optimal memory configuration proposal (memory configuration proposal) has been applied. In this case, the simulator calculates (simulates) the design convergence for the input optimal memory configuration proposal (memory configuration proposal) for all partitions and outputs whether or not the design convergence is achieved. When the simulator outputs that the design convergence is not achieved, it may also identify the location where the problem occurred (for example, within a partition, at the top, at a partition boundary, etc.) that is the basis for the simulation result, and output the location where the problem occurred.

[0057] The control unit 11 of the information processing device 1 determines whether convergence is possible (S111). Based on the output results from the simulator, the control unit 11 of the information processing device 1 determines whether design convergence is possible for the overall memory configuration obtained by applying the memory configuration proposal to all partitions included in the floor plan proposal, that is, whether or not design convergence is possible. If the design related to the placement and routing process for the entire design can be completed within a predetermined period in the output results from the simulator, it is determined that design convergence is possible; if it cannot be completed within the predetermined period, it is determined that design convergence is not possible. The control unit 11 of the information processing device 1 may also determine whether or not convergence is possible based on the presence or absence of design convergence included in the output results from the simulator.

[0058] If convergence is not possible (S111: NO), the control unit 11 of the information processing device 1 identifies the location of the problem (S1111). If convergence is not possible, the control unit 11 of the information processing device 1 identifies the location of the problem by extracting the location of the problem from the output results of the simulator. The control unit 11 of the information processing device 1 then uses the partition engine again to derive multiple partition options according to the identified location of the problem, and performs loop processing to execute the process from S104 again.

[0059] If convergence is possible (S111: YES), the control unit 11 of the information processing device 1 executes processing related to the placement and routing process (S112). If convergence is possible, that is, if the overall memory configuration obtained by applying the memory configuration proposal to all partitions included in the floor plan proposal, which is the subject of this determination, has design convergence, the control unit 11 of the information processing device 1 generates an applicable code by incorporating the derived optimal memory configuration proposal (memory configuration proposal) into the acquired register transfer level code, that is, the code (RTL), which is the input data in this process. This optimal memory configuration proposal (memory configuration proposal) corresponds to the applicable memory configuration information to be applied on the chip on which the semiconductor integrated circuit is mounted. Furthermore, the control unit 11 of the information processing device 1 may generate a netlist (gate-level HDL) used in the placement and routing process by performing logic synthesis using this applicable code.

[0060] In this embodiment, the control unit 11 of the information processing device 1 performs a determination (evaluation) of performance indicators such as PPA for each memory configuration proposal (combination of memory configuration proposal and floor plan proposal), and then performs a determination (evaluation) of design difficulty, etc., but is not limited to this. The control unit 11 of the information processing device 1 may perform a determination of design difficulty, etc., for each of the multiple memory configuration proposals, and then perform a determination of performance indicators such as PPA for memory configuration proposals whose design difficulty is less than or equal to a predetermined value. Alternatively, the control unit 11 of the information processing device 1 may perform both a determination of performance indicators such as PPA and a determination of design difficulty, etc., for each of the multiple memory configuration proposals, and identify the optimal memory configuration proposal based on these determination results. In this case, it is assumed that there will be a trade-off relationship between the results of the determination of performance indicators such as PPA (evaluation results) and the results of the determination of design difficulty, etc. (evaluation results). In this case, the control unit 11 of the information processing device 1 may, for example, use a Pareto optimal solution to identify the optimal memory configuration proposal (applicable memory configuration information).

[0061] According to this embodiment, the information processing device 1 acquires performance indicators (PPA: Performance / Power / Area) that define the functional requirements specifications of a semiconductor integrated circuit, and register transfer level codes. The performance indicators (PPA) define processing performance, power consumption, and mounting area on the silicon die in the functional requirements specifications of a semiconductor integrated circuit. The register transfer level codes are written in, for example, HDL (Hardware Description Language) or C++, and include RTL (Register Transfer Level) or SDC (Synopsys Design Constraints). These performance indicators (PPA) and codes (RTL, etc.) correspond to logic design data in the semiconductor integrated circuit design process. The information processing device 1 extracts memory information defined in or included as requirements in the input code (RTL, etc.). Based on the extracted memory information, the information processing device 1 derives multiple candidate memory configuration information (memory configuration proposals) that are candidates for the memory configuration on the chip on which the semiconductor integrated circuit is mounted. The information processing device 1 verifies the multiple candidate memory configuration information (memory configuration proposals) derived, derives the candidate memory configuration information that is most positive in the verification results as the applicable memory configuration information, and outputs the applicable memory configuration information to a terminal device 2 used by a physical designer who performs physical design of a semiconductor integrated circuit, for example. This provides the physical designer with support information for floor plan design, and improves or guarantees the efficiency, accuracy, and quality of floor plan design that takes into account the most suitable memory configuration.

[0062] According to this embodiment, the storage unit 12 of the information processing device 1 stores a design database 121 containing design data that has already been performed. The design database 121 is configured, for example, as RAG (Retrieval-Augmented Generation), and stores data related to floor plans performed in the past (memory configuration such as memory partitioning, partitioning, hierarchical layout, and floor plan) and the design difficulty for said floor plan in association with each other. The information processing device 1 may derive the design difficulty for each of the multiple candidate memory configuration information by referring to the design database 121 (RAG) for each combination of individual candidate memory configuration information (memory configuration proposal) and multiple partition proposals (floor plan proposals) derived using, for example, a known automatic partitioning tool (general-purpose partition engine). The information processing device 1 may select the candidate memory configuration information with the lowest design difficulty among these multiple combinations (combinations of memory configuration proposals and partition proposals) and derive it as the applicable memory configuration information. Alternatively, the design database 121 (RAG) stores data on past floor plans, associated with the design's PPAt (Power Performance Area and Time) or PPAC+t (Power Performance Area Cost and Time). The information processing device 1 may derive the applicable memory configuration information based on the ease of design and the degree of PPAt achievement. In this case, it is assumed that there is a trade-off relationship between the ease of design and the degree of PPAt achievement. The information processing device 1 may, for example, use a Pareto optimal solution to derive the applicable memory configuration information. By deriving (selecting) the applicable memory configuration information from multiple candidate memory configuration information (memory configuration proposals) based on the ease of design, etc., it is possible to provide the most suitable applicable memory configuration information (memory configuration proposal) from the viewpoint of the ease of design, etc.

[0063] According to this embodiment, the information processing device 1 obtains a register transfer level code (RTL [HDL]) and then processes the memory request amount (for example, RTL) defined by the bit word configuration included in the code.<Memory instance> The information processing device 1 identifies or extracts a memory size of 160 [Width] × 2048 [depth] and derives memory configuration information (multiple candidate memory configuration information) including the size and location of the memory divided into multiple parts to correspond to the memory request amount (memory information). Furthermore, the information processing device 1 derives multiple partition options from the acquired register transfer level code (RTL [HDL]) by using a known automatic partitioning tool (general-purpose partition engine). Each partition option includes multiple hierarchical layout blocks (HLBs), and each hierarchical layout block (HLB) will have memory corresponding to that hierarchical layout block. When deriving (configuring) candidate memory configuration information, the information processing device 1 may combine each of the multiple candidate memory configuration information (memory configuration options) with each of the multiple partition options. That is, the candidate memory configuration information may include multiple combinations of candidate memory configuration information (memory configuration options) and partition options (number of HLBs, HLB shape, and memory arrangement within HLBs). Each of these multiple combinations (combinations of memory configuration proposals and partition proposals) may be subject to evaluation such as design difficulty or PPAt. Thus, the candidate memory configuration information includes partition proposals related to hierarchical layout blocks (HLBs), and is composed of combinations of these partition proposals and memory configuration proposals. Therefore, the information processing device 1 can determine a suitable or optimal memory configuration and placement, etc., after considering the physical arrangement or position of the derived memory configuration proposals in the actual floor plan (partition proposal) of the hierarchical blocks.

[0064] According to this embodiment, the information processing device 1 generates an application code by incorporating the memory configuration (instance) included in the derived application memory configuration information into the acquired code (RTL [HDL]). Since the application code generated in this way is a code that can be directly synthesized logically, the information processing device 1 can efficiently generate a netlist with a hierarchical floor plan to which a suitable memory configuration proposal is applied by synthesizing the application code logically, thereby improving the efficiency of the placement and routing process using the netlist.

[0065] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this disclosure is indicated by the claims and not in the sense described above, and all modifications within the meaning and scope equivalent to the claims are intended.

[0066] With respect to the multiple claims described in the claims, they may be combined with each other regardless of the form of reference. Multiple dependent claims that depend on multiple claims may be described in the claims. Multiple dependent claims that depend on multiple dependent claims may be described. Even if multiple dependent claims that depend on multiple dependent claims are not described, this does not limit the description of multiple dependent claims that depend on multiple dependent claims.

[0067] S Semiconductor Design Support System 1 Information Processing Unit (Semiconductor Design Support Server) 11 Control Unit 111 Acquisition Unit 112 Memory Configuration Extraction Unit 113 Memory Configuration Generation Unit (Memory Compiler) 114 Partition Generation Unit (Partition Engine) 115 Memory Configuration Proposal Derivation Unit 116 Optimal Memory Configuration Proposal Derivation Unit 117 Improvement Feasibility Determination Unit 118 Convergence Feasibility Determination Unit (Simulator) 119 Output Unit 12 Storage Unit 121 Design Database (RAG) M Recording Medium P Program (Program Product) 13 Communication Unit 14 Input / Output I / F 101 PPA Evaluation Model (Performance Index Estimation Model) 102 Design Difficulty Evaluation Model 2 Terminal Device (Designer PC)

Claims

1. A design support method that causes a computer to perform the following processes: obtain register transfer level code generated according to performance indicators, extract memory information from the obtained code, and derive applicable memory configuration information to be applied on a chip on which a semiconductor integrated circuit is mounted, based on the extracted memory information.

2. The design support method according to claim 1, wherein, based on the extracted memory information, a plurality of candidate memory configurations that are candidates for memory configurations on a chip on which the semiconductor integrated circuit is mounted are derived, the derived plurality of candidate memory configurations are verified, and the applicable memory configuration is derived by selecting the candidate memory configuration from the plurality of candidate memory configurations that has the most positive verification result.

3. The design support method according to claim 2, wherein, in performing the verification of the plurality of candidate memory configuration information, a performance index or design difficulty is derived for each of the plurality of candidate memory configuration information, and based on the derived performance index or design difficulty, one of the candidate memory configuration information is derived from the plurality of candidate memory configuration information as the applicable memory configuration information.

4. The design support method according to claim 2, wherein a plurality of hierarchical blocks are derived by performing partitioning on the acquired code, and the candidate memory configuration information includes the number of hierarchical blocks, the shape of the hierarchical blocks, and the memory arrangement within the hierarchical blocks.

5. A design support method according to any one of claims 1 to 4, comprising: generating an applied code by applying the derived applied memory configuration information to the acquired code; and generating a netlist for performing the placement and routing process on the chip of the semiconductor integrated circuit by performing logic synthesis using the applied code.

6. A program that causes a computer to perform the following processes: obtain register transfer level code generated according to performance indicators, extract memory information from the obtained code, and derive applicable memory configuration information to be applied on the chip on which the semiconductor integrated circuit is mounted, based on the extracted memory information.

7. An information processing device comprising a control unit that performs processing related to the design support of a semiconductor integrated circuit, wherein the control unit acquires register transfer level code generated according to a performance indicator, extracts memory information from the acquired code, and derives applicable memory configuration information to be applied on a chip on which a semiconductor integrated circuit is mounted based on the extracted memory information.

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