Photodetection element

Abstract

The present disclosure relates to a photodetection element that makes it possible to improve the transfer capability of a transfer transistor. The photodetection element comprises a gate electrode of a transfer transistor that transfers charges obtained by photoelectric conversion by a photoelectric conversion unit to a charge storage unit, and an insulating film provided around the gate electrode. The insulating film has a first thickness on a main transfer path side for transferring the charges from the photoelectric conversion unit to the charge storage unit, and has a second thickness and a third thickness at different depths on the opposite side to the main transfer path. The first thickness is smaller than the second thickness, the second thickness is smaller than the third thickness, and the insulating film having the second thickness is provided at a position deeper from a light incident surface of a semiconductor substrate than the insulating film having the third thickness. The technology of the present disclosure can be applied to, for example, a photodetection element or the like that generates a signal corresponding to the amount of light received by each pixel and outputs the signal to the outside.

Description

Photodetecting element

[0001] The present disclosure relates to a photodetecting element, and particularly relates to a photodetecting element configured to improve the transfer capability of a transfer transistor.

[0002] A solid-state imaging device includes, for each pixel, a transfer transistor that transfers signal charges photoelectrically converted by a photoelectric conversion unit to a charge accumulation region. The gate electrode of the transfer transistor is formed, for example, by embedding a polycrystalline silicon film to serve as the gate electrode in a trench formed by selectively etching a part of an insulating film formed with an STI (Shallow Trench Isolation) structure on a semiconductor substrate (see, for example, Patent Document 1).

[0003] [Correction under Rule 91 13.05.2026]International Publication No. 2022 / 091592

[0004] Further improvement for the structure of the transfer transistor is desired for the purpose of improving transfer performance.

[0005] The present disclosure has been made in view of such circumstances, and is intended to make it possible to improve the transfer capability of a transfer transistor.

[0006] According to one aspect of the present disclosure, a photodetecting element includes: a gate electrode of a transfer transistor that transfers charges photoelectrically converted by a photoelectric conversion unit to a charge accumulation unit; and an insulating film provided around the gate electrode, wherein the insulating film has a first thickness on a main transfer path side for transferring the charges from the photoelectric conversion unit to the charge accumulation unit, and has a second thickness and a third thickness at different depths on a side opposite to the main transfer path, the first thickness is smaller than the second thickness, the second thickness is smaller than the third thickness, and the insulating film having the second thickness is provided at a position deeper from a light incident surface of the semiconductor substrate than the insulating film having the third thickness.

[0007] In one aspect of this disclosure, a gate electrode of a transfer transistor that transfers the charge photoelectrically converted in a photoelectric conversion unit to a charge storage unit, and an insulating film provided around the gate electrode, wherein the insulating film has a first thickness on the main transfer path side for transferring the charge from the photoelectric conversion unit to the charge storage unit, and a second thickness and a third thickness at different depths on the opposite side of the main transfer path, the first thickness being thinner than the second thickness, the second thickness being thinner than the third thickness, and the insulating film of the second thickness being provided at a deeper position from the light incident surface of the semiconductor substrate than the insulating film of the third thickness.

[0008] The photodetector may be a standalone device or a module incorporated into another device.

[0009] This figure shows a schematic configuration of a photodetector element to which the technology of this disclosure is applied. This figure shows an example of the basic circuit configuration of a pixel of the photodetector element. This is a plan view showing a first configuration example of a pixel. This is a cross-sectional view taken along the X-X' line in Figure 3. This is a cross-sectional view taken along the Y-Y' line in Figure 3. This figure illustrates a method for manufacturing the transfer gate electrode of a pixel according to the first configuration example. This figure illustrates a method for manufacturing the transfer gate electrode of a pixel according to the first configuration example. This figure illustrates a method for manufacturing the transfer gate electrode of a pixel according to the first configuration example. This is a plan view showing a second configuration example of a pixel. This is a cross-sectional view taken along the X1-X1' line in Figure 10. This is a cross-sectional view taken along the X2-X2' line in Figure 10. This is a cross-sectional view taken along the Y-Y' line in Figure 10. This is a plan view showing a third configuration example of a pixel. This is a cross-sectional view taken along the X-X' line in Figure 14. This is a plan view showing a fourth configuration example of a pixel. This is a cross-sectional view taken along the X-X' line in Figure 16. This is a cross-sectional view taken along the Y-Y' line in Figure 16. This is a plan view showing a fifth configuration example of a pixel. This is a plan view showing a sixth configuration example of a pixel. This is a plan view showing a modified example of the sixth pixel configuration. This is a plan view showing the seventh pixel configuration. This is a plan view showing the first modified example of the seventh configuration. This is a plan view showing the second modified example of the seventh configuration. This is a plan view showing the second modified example of the seventh configuration. This is a diagram illustrating the configuration of the element isolation insulating film of the present disclosure. This is a block diagram illustrating an example of the configuration of an electronic device to which the technology of the present disclosure is applied. This is a diagram illustrating an example of the use of an image sensor.

[0010] The following describes embodiments for implementing the technology of this disclosure (hereinafter referred to as "embodiments") with reference to the attached drawings. The description will proceed in the following order: 1. Outline configuration example of a photodetector element 2. Basic circuit configuration example of a pixel 3. First configuration example of a pixel 4. Method for manufacturing a transfer gate electrode 5. Second configuration example of a pixel 6. Third configuration example of a pixel 7. Fourth configuration example of a pixel 8. Fifth configuration example of a pixel 9. Sixth configuration example of a pixel 10. Seventh configuration example of a pixel 11. Summary 12. Configuration example of an electronic device 13. Example of using an image sensor

[0011] In this specification and the drawings, identical or similar parts are denoted by the same or similar reference numerals, thereby omitting redundant explanations as appropriate. The drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from the actual ones. Furthermore, there may be parts where the dimensional relationships and ratios differ between drawings.

[0012] Furthermore, the definitions of directions such as up and down in the following explanation are merely for explanatory convenience and do not limit the technical concept of this disclosure. For example, if an object is rotated 90° and observed, up and down will be converted to left and right and read accordingly, and if it is rotated 180° and observed, up and down will be inverted and read accordingly.

[0013] Furthermore, the + and - symbols attached to P-type and N-type in the following explanation indicate semiconductor regions with relatively higher or lower impurity concentrations compared to semiconductor regions without + and - markings. However, even if semiconductor regions are both labeled P and N, this does not mean that the impurity concentrations in each semiconductor region are exactly the same.

[0014] The technology disclosed herein can be applied to all photodetectors having a pixel array in which pixels are arranged two-dimensionally in a matrix, and which convert incident light into photoelectric signals and output a pixel signal corresponding to the amount of light. The light to be detected may be light in the visible light region including wavelengths such as R (Red), G (Green), and B (Blu), or it may be light in the invisible light region such as infrared light. Alternatively, both visible and invisible light regions may be used as the detection target. The photodetector can be used as a solid-state imaging device that generates and outputs an imaging signal corresponding to the amount of incident light, or as a light-receiving device (distance sensor) in a distance measuring system that receives light (reflected light) reflected from an object after infrared light irradiated as active light is received, and measures the distance to the subject using a direct ToF (Time of Flight) or indirect ToF (Time of Flight) method. Below, an example of applying the technology disclosed herein to a photodetector that receives light in the visible light region and generates and outputs an imaging signal corresponding to the amount of incident light will be described.

[0015] <1. Schematic Example of Photodetector Element Configuration> Figure 1 shows an example of the functional configuration of a photodetector element to which the technology of this disclosure is applied.

[0016] The photodetector element 1 in Figure 1 is constructed on a semiconductor substrate 21 made of silicon (Si) as the semiconductor material, and comprises a pixel array section 3 in which a plurality of pixels 2 are arranged in a matrix, and a peripheral circuit region. The peripheral circuit region includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

[0017] Pixel 2 consists of a photodiode and a plurality of pixel transistors. The plurality of pixel transistors consist of, for example, four transistors: a transfer transistor, a selection transistor, a reset transistor, and an amplification transistor, each of which is a MOS transistor (MOS FET).

[0018] Pixel 2 can also be a shared pixel structure. This shared pixel structure consists of multiple photodiodes, multiple transfer transistors, one or more shared floating diffusions, and one shared other pixel transistor. In other words, in a shared pixel structure, each pixel 2 has a photodiode and a transfer transistor, and the other pixel transistors are shared and used by multiple pixels 2.

[0019] The control circuit 8 receives the input clock and data that commands the operating mode, and outputs data such as internal information of the photodetector 1. Based on the vertical synchronization signal, horizontal synchronization signal, and master clock, the control circuit 8 generates clock signals and control signals that serve as the reference for the operation of the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6, etc. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6, etc.

[0020] The vertical drive circuit 4 is configured, for example, by a shift register, and selects a predetermined pixel drive wiring 10, supplies pulses to the selected pixel drive wiring 10 to drive the pixels 2, and drives the pixels 2 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 2 of the pixel array 3 row by row in the vertical direction, and supplies a signal based on the charge generated in the photoelectric conversion unit of each pixel 2 according to the amount of light received to the column signal processing circuit 5 through the vertical signal line 9.

[0021] The column signal processing circuit 5 is located for each column of pixels 2 and performs signal processing such as noise reduction on the signals output from each row of pixels 2 for each pixel column. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and AD conversion to remove pixel-specific fixed pattern noise.

[0022] The horizontal drive circuit 6 is composed of, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, causing each of the column signal processing circuits 5 to output a pixel signal to the horizontal signal line 11.

[0023] The output circuit 7 processes the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 11 and outputs them. The output circuit 7 may, for example, only perform buffering, or it may perform black level adjustment, column variation correction, various digital signal processing, etc. The input / output terminal section 13 exchanges signals with the outside.

[0024] The photodetector element 1, configured as described above, has a structure called a column AD system, in which column signal processing circuits 5 that perform CDS processing and AD conversion processing are arranged in each column. The photodetector element 1 generates a signal corresponding to the amount of light received by each pixel 2 in the pixel array 3 and outputs it to the outside.

[0025] <2. Example of Basic Circuit Configuration for Pixels> Figure 2 shows an example of the basic circuit configuration for pixel 2.

[0026] Pixel 2 includes, for example, a photodiode PD, a transfer transistor TG electrically connected to the photodiode PD, and a floating diffusion transistor FD electrically connected to the transfer transistor TG. Pixel 2 also includes a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. The transfer transistor TG, reset transistor RST, amplification transistor AMP, and selection transistor SEL are composed of, for example, N-type MOS transistors (MOS FETs).

[0027] A photodiode (PD) converts incident light into electricity, generating an electric charge (signal charge) corresponding to the amount of incident light received. In a photodiode (PD), the cathode is electrically connected to the source of a transfer transistor (TG), and the anode is electrically connected to a reference potential line (e.g., ground).

[0028] The transfer transistor TG controls the transfer of charge generated by the photodiode PD. When the transfer transistor TG is turned ON, it transfers the charge generated by the photodiode PD to the floating diffusion FD. In the transfer transistor TG, the drain is electrically connected to the floating diffusion FD, and the gate is electrically connected to the pixel drive wiring. This pixel drive wiring is part of the pixel drive wiring 10 described in Figure 1.

[0029] The floating diffusion transistor (FD) is a charge storage unit that temporarily stores the charge transferred from the photodiode (PD), and also a charge-voltage conversion unit that generates a voltage corresponding to the amount of charge. The floating diffusion transistor (FD) is electrically connected to the gate of the amplification transistor (AMP) and the source of the reset transistor (RST).

[0030] The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on by the pixel drive wiring supplied to the gate, it resets the potential of the floating diffusion FD to the potential of the power line VDD. This pixel drive wiring is part of the pixel drive wiring 10 described in Figure 1. When the potential of the floating diffusion FD is reset, the reset transistor RST is also controlled to be turned on at the same time.

[0031] The amplification transistor AMP generates a signal with a voltage corresponding to the level of charge accumulated in the floating diffusion FD as a pixel signal. The amplification transistor AMP is connected in series with the selection transistor SEL and is connected to the vertical signal line 9 via the selection transistor SEL. This amplification transistor AMP, together with the load circuit in the column signal processing circuit 5 connected to the vertical signal line 9, constitutes a source follower. When the selection transistor SEL is turned on, the amplification transistor AMP outputs the voltage of the floating diffusion FD to the column signal processing circuit 5 via the vertical signal line 9. The drain of the amplification transistor AMP is connected to the power line VDD, and the source of the amplification transistor AMP is connected to the drain of the selection transistor SEL.

[0032] The selection transistor SEL controls the output timing of the pixel signal. The source of the selection transistor SEL is connected to the vertical signal line 9, and the gate of the selection transistor SEL is connected to the pixel drive wiring. When the selection transistor SEL is turned on by the pixel drive wiring supplied to its gate, it outputs the pixel signal from the amplification transistor AMP to the vertical signal line 9. This pixel drive wiring is part of the pixel drive wiring 10 described in Figure 1.

[0033] The selection transistor SEL may be located between the power line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP. The source of the amplification transistor AMP (the output terminal of pixel 2) is electrically connected to the vertical signal line 9, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST.

[0034] In the pixel 2 configured as described above, a pixel signal corresponding to the amount of incident light is output to the column signal processing circuit 5 via the vertical signal line 9, according to the control of the vertical drive circuit 4. The circuit configuration in Figure 2 is the basic configuration of pixel 2, and various modifications are possible for the circuit configuration of pixel 2. For example, in the case of a shared pixel structure, each pixel 2 has a photodiode PD and a transfer transistor, while the reset transistor RST, amplification transistor AMP, and selection transistor SEL are shared by multiple pixels. There are also configurations in which two photodiodes PD and two transfer transistors are provided within the pixel area.

[0035] The following describes various pixel structures that can be used as pixels 2 of the photodetector element 1.

[0036] <3. First Example of Pixel Configuration> Figures 3 to 5 show the first example of pixel configuration 2. Figure 3 is a plan view of the first example of pixel configuration 2, Figure 4 is a cross-sectional view along the line X-X' in Figure 3, and Figure 5 is a cross-sectional view along the line Y-Y' in Figure 3.

[0037] Figure 3 is a plan view of the pixel 2 region as seen from the front side of the semiconductor substrate 21. The front side of the semiconductor substrate 21 is the transistor formation surface where transfer transistors TG and pixel transistors Tr are formed, and the back side opposite the front side is the light incident surface where the light to be photoelectrically converted is incident. The pixel transistor Tr represents either a reset transistor RST, an amplification transistor AMP, or a selection transistor SEL.

[0038] Pixel 2 in the first configuration example has a square pixel area. A transfer transistor TG, a pixel transistor Tr, and a floating diffusion FD are arranged symmetrically (mirror symmetrically) with respect to a center line (not shown) that divides the square pixel area into two horizontally (left-right direction) parts of the pixel array 3. One of the areas arranged symmetrically is called sub-pixel area 2A, and the other area is called sub-pixel area 2B. The two floating diffusion FDs are electrically connected and integrated, as will be described later. As shown in the cross-sectional view along line X-X' in Figure 4, the photodiode PD is also arranged symmetrically in sub-pixel area 2A and sub-pixel area 2B, respectively. Therefore, pixel 2 in the first configuration example has two photodiodes PD and two transfer transistors TG within the pixel area.

[0039] In the plan view of Figure 3, a well contact region 46 is provided in the center of the pixel region for applying a predetermined potential to the substrate region (well region) 41 of the semiconductor substrate 21. The substrate region 41 is formed of a P-type semiconductor region, which is a first conductivity type, and the well contact region 46 is formed of a P-type (P+) semiconductor region with a higher impurity concentration than the substrate region 41. A predetermined potential, such as ground (GND) which is a reference potential, is applied to the well contact region 46.

[0040] A pixel isolation portion 22 is formed on the outer periphery of the pixel region. As shown in the cross-sectional views of Figures 4 and 5, the pixel isolation portion 22 has a full trench structure that penetrates the depth direction of the semiconductor substrate 21 (Figure 4), and is constructed by embedding an insulating film such as SiO2 inside the full trench structure. The width in the planar direction of the pixel isolation portion 22 that penetrates the depth direction of the semiconductor substrate 21 may be the same throughout the depth direction, or it may be a different width on the front side of the substrate and the back side of the substrate. The pixel isolation portion 22 physically and electrically isolates the photodiode PD in the pixel region from the photodiode PD of other adjacent pixels 2. At the boundary between sub-pixel region 2A and sub-pixel region 2B, a pixel isolation protrusion portion 22SL is provided that protrudes for a predetermined length from the pixel isolation portion 22 on the outer periphery toward the central well contact region 46. The pixel separation protrusion 22SL is provided at the boundary between subpixel region 2A and subpixel region 2B, excluding the vicinity of the central well contact region 46, and separates the photodiodes PD formed in subpixel region 2A and subpixel region 2B.

[0041] Furthermore, the pixel separation portion 22 and the pixel separation protrusion portion 22SL may not be a full trench structure penetrating the depth direction of the semiconductor substrate 21, but rather a partial trench structure formed to at least a portion of the depth of the semiconductor substrate 21. For example, a partial trench structure in which an insulating film is embedded inside a trench structure dug from the back side of the semiconductor substrate 21 to a depth midway through the substrate may also be used. In addition to the insulating film, metallic materials such as tungsten, aluminum, silver, and copper may be further embedded inside the full trench structure or partial trench structure.

[0042] Each of the sub-pixel region 2A and sub-pixel region 2B is provided with a pixel transistor Tr. These two pixel transistors Tr are either a reset transistor RST, an amplification transistor AMP, or a selection transistor SEL. That is, in the pixel array section 3, two pixels, each consisting of a pixel 2 shown in Figure 3 and a pixel 2 in a mirror arrangement obtained by inverting the pixel 2 in Figure 3 symmetrically (mirror symmetrically) with respect to the pixel separation section 22 to which the floating diffusion FD is in contact, are used as a repeating unit and are repeatedly arranged in the row and column directions of the pixel array section 3. The two pixels forming the repeating unit are also a shared unit that shares the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL with the floating diffusion FD. Four pixel transistors Tr can be placed in the two pixels of the repeating unit, but the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are placed in the positions of three of these pixel transistors Tr. The position of the remaining pixel transistor Tr does not need to have a pixel transistor Tr, or an undriven dummy pixel transistor Tr may be placed to maintain the symmetry of the pixel 2.

[0043] A pixel transistor Tr has a gate electrode Tr-PG and source / drain electrodes SD1 and SD2. One of the source / drain electrodes SD1 and SD2 is the source electrode, and the other is the drain electrode. The gate electrode Tr-PG is formed of, for example, polysilicon, and the source / drain electrodes SD1 and SD2 are formed of N-type semiconductor regions, which are the second conductivity type opposite to the first conductivity type (P-type).

[0044] The floating diffusion FD is formed by an N-type semiconductor region 43 at the corner where the pixel separation portion 22 and the pixel separation protruding portion 22SL are connected. In the peripheral region of the floating diffusion FD, an N-type (N-) semiconductor region 44 having a lower impurity concentration than the floating diffusion FD is formed. A contact wiring 101 is connected to each of the floating diffusion FDs of the two pixels in the shared unit, as shown in the cross-sectional view along the line Y-Y' in FIG. 5. Then, by connecting the four contact wirings 101 connected to the four floating diffusion FDs provided in the two pixels of the shared unit within the wiring layer, the four floating diffusion FDs of the shared unit are electrically integrated and shared by the two pixels of the shared unit.

[0045] The gate electrode TGg of the transfer transistor TG is formed of, for example, polysilicon, and is provided between the pixel transistor Tr and the floating diffusion FD. An element isolation insulating film 45 formed by embedding an insulating film such as SiO 2 is provided around the gate electrode TGg of the transfer transistor TG and the source / drain electrodes SD1 and SD2 of the pixel transistor Tr. The element isolation insulating film 45 is formed with an STI (Shallow Trench Isolation) structure. Hereinafter, to facilitate distinction between the gate electrode TGg of the transfer transistor TG and the gate electrode Tr-PG of the pixel transistor Tr, it is referred to as a transfer gate electrode TGg.

[0046] A partial front surface vicinity region within a pixel region surrounded by a pixel isolation section 22 serves as a substrate region 41 of a semiconductor substrate 21. The substrate region 41 is formed of a P-type semiconductor region. As shown in the cross-sectional view taken along line X-X' of Fig. 4, an N-type semiconductor region 42 is formed in each of a left sub-pixel region 2A and a right sub-pixel region 2B, whereby two photodiodes PD are formed in the pixel region. The N-type semiconductor region 42 is a photoelectric conversion section of a pixel 2 that converts incident light into electric charges (signal charges), and accumulates the charges generated by photoelectric conversion. The semiconductor substrate 21 has a first surface FA and a second surface SA, wherein the first surface FA is a front surface of the semiconductor substrate 21, and the second surface SA is a light incident surface on which light to be subjected to photoelectric conversion is incident. A pixel transistor Tr, a transfer transistor TG, a well contact region 46 and the like are formed on the first surface FA of the semiconductor substrate 21. Although not shown in the figure, a color filter layer, an on-chip lens, and the like are formed on the second surface SA of the semiconductor substrate 21. As for the arrangement of on-chip lenses, for example, one on-chip lens is arranged for one pixel region.

[0047] On the first surface FA of the semiconductor substrate 21, an element isolation insulating film 45 having an STI structure is formed around source / drain electrodes SD1 and SD2 of the pixel transistor Tr. The element isolation insulating film 45 has a first depth DP1 from the first surface FA of the semiconductor substrate 21.

[0048] In the cross-sectional view taken along line Y-Y' of Fig. 5, the pixel transistor Tr, the transfer transistor TG, and a floating diffusion FD (N-type semiconductor region 43) are arranged side by side within the pixel region. In other words, a transfer gate electrode TGg is arranged between the pixel transistor Tr and the floating diffusion FD.

[0049] A gate electrode Tr-PG of the pixel transistor Tr has a planar gate electrode structure formed on the first surface FA of the semiconductor substrate 21. On the other hand, the transfer gate electrode TGg has a vertical gate electrode structure including a planar gate electrode TGgp formed on the first surface FA of the semiconductor substrate 21 and a buried gate electrode TGgv buried in the semiconductor substrate 21.

[0050] An element isolation insulating film 45 is provided around the transfer gate electrode TGg. The element isolation insulating film 45 also serves as the gate insulating film of the transfer transistor TG. Among the element isolation insulating films 45 around the transfer gate electrode TGg, a first thickness DS1 of the element isolation insulating film 45 facing a main transfer path PS for transferring charges accumulated in an N-type semiconductor region 42 to the floating diffusion FD is formed thinner than a second thickness DS2 of the element isolation insulating film 45 on the side opposite to the main transfer path PS (DS1<DS2). Note that the main transfer path PS refers to the main path through which the largest amount of charge flows among the charge transfer paths by the transfer transistor TG, but this does not exclude other paths. Charges are also transferred to the floating diffusion FD through paths other than the main transfer path PS. Regarding the film thickness of the element isolation insulating film 45, in the present specification, the film thickness in a direction parallel to the planar direction of the semiconductor substrate 21 is referred to as the "thickness" of the element isolation insulating film 45, and the film thickness in a direction perpendicular to the planar direction of the semiconductor substrate 21 is referred to as the "depth" of the element isolation insulating film 45 in the following description. Therefore, the first thickness DS1 and the second thickness DS2 of the element isolation insulating film 45 are the film thicknesses of the element isolation insulating film 45 in contact with the sidewall of the buried gate electrode TGgv in a direction parallel to the planar direction of the semiconductor substrate 21.

[0051] Looking at the depth of the element isolation insulating film 45 from the first surface FA of the semiconductor substrate 21, a second depth DP2 of the element isolation insulating film 45 where the element isolation insulating film 45 has the second thickness DS2 around the transfer gate electrode TGg is deeper than a first depth DP1 (FIG. 4) of the element isolation insulating film 45 around the pixel transistor Tr. The portions of the element isolation insulating film 45 having the first thickness DS1 and the second thickness DS2 are provided at positions deeper than the first depth DP1 of the element isolation insulating film 45 provided around the pixel transistor Tr. This is because the transfer gate electrode TGg has a vertical gate electrode structure, and the buried gate electrode TGgv is formed to a position deeper than the element isolation insulating film 45 around the pixel transistor Tr formed at the first depth DP1.

[0052] When comparing the thickness of the element isolation insulating film 45 between the shallow portion and the deep portion of the buried gate electrode TGgv, the shallow portion of the buried gate electrode TGgv is formed thicker. Specifically, between the shallow portion and the deep portion on the main transfer path PS side, the first thickness DS1 of the element isolation insulating film 45 in the deep portion of the buried gate electrode TGgv is formed thinner than the fourth thickness DS4 of the element isolation insulating film 45 in the shallow portion of the buried gate electrode TGgv (DS1<DS4). In other words, the portion of the element isolation insulating film 45 having the first thickness DS1 is provided at a position deeper from the first surface FA of the semiconductor substrate 21 than the portion having the fourth thickness DS4. Between the shallow portion and the deep portion on the side opposite to the main transfer path PS side, the third thickness DS3 of the element isolation insulating film 45 in the shallow portion of the buried gate electrode TGgv is formed thicker than the second thickness DS2 of the element isolation insulating film 45 in the deep portion of the buried gate electrode TGgv (DS2<DS3). In other words, the portion of the element isolation insulating film 45 having the second thickness DS2 is provided at a position deeper from the first surface FA of the semiconductor substrate 21 than the portion having the third thickness DS3. When comparing the shallow portion of the buried gate electrode TGgv between the main transfer path PS side and the opposite side, the fourth thickness DS4 of the element isolation insulating film 45 on the main transfer path PS side is formed thinner than the third thickness DS3 of the element isolation insulating film 45 on the side opposite to the main transfer path PS (DS4<DS3).

[0053] In the pixel 2 according to the first configuration example, as described above, the depth of (the buried gate electrode TGgv of) the transfer gate electrode TGg is formed deeper than the first depth DP1 of the element isolation insulating film 45 of the STI structure around the pixel transistor Tr, and the first thickness DS1 of the element isolation insulating film 45 on the main transfer path PS side in the deep portion of the buried gate electrode TGgv is made thinner than the second thickness DS2 on the opposite side, whereby the transfer capability of the transfer transistor TG can be improved.

[0054] Furthermore, by making the fourth thickness DS4 of the element isolation insulating film 45 in the shallow part of the embedded gate electrode TGgv on the main transfer path PS side thicker than the first thickness DS1 in the deep part of the embedded gate electrode TGgv, and by increasing the distance from the embedded gate electrode TGgv to the floating diffusion FD, defect noise (such as white spots) caused by the strong electric field between the transfer gate electrode TGg and the floating diffusion FD can be prevented.

[0055] Although Figure 3 shows an example where sub-pixel region 2A and sub-pixel region 2B are arranged symmetrically in the horizontal direction of the pixel array 3, a configuration in which sub-pixel region 2A and sub-pixel region 2B are arranged symmetrically in the vertical direction of the pixel array 3, such as by rotating the pixel region in Figure 3 by 90 degrees, is also possible.

[0056] <4. Method for Manufacturing the Transfer Guard Gate> Next, a method for manufacturing the transfer guard gate TGg of pixel 2 according to the first configuration example will be described with reference to Figures 6 to 9. In Figures 6 to 9, the upper section shows a cross-sectional view of the transfer guard gate TGg formation portion, and the lower section shows a plan view of the transfer guard gate TGg formation portion. The upper cross-sectional view is a cross-sectional view taken along the line X-X' in the lower section.

[0057] First, as shown in Figure 6A, an insulating film 71, such as a silicon oxide film (SiO2), and an insulating film 72, such as a silicon nitride film (SiN), are laminated on the first surface FA, which is the front surface of the semiconductor substrate 21, and then a resist 73 is formed as a hard mask. An aperture region 74 of a predetermined size is formed in the formed resist 73 using lithography.

[0058] Next, as shown in Figure 6B, the insulating film 71 and insulating film 72 of the formed opening region 74 are removed using dry etching or the like.

[0059] Next, as shown in Figure 6C, after the resist 73 is peeled off, the substrate region 41 of the semiconductor substrate 21 is etched to a predetermined depth using the insulating film 72 as a hard mask, and a trench 75 of a predetermined depth is formed in the substrate region 41 of the semiconductor substrate 21.

[0060] Next, as shown in Figure 7A, after the resist 81 as a hard mask is formed on the insulating film 72, an opening region 82 of a predetermined size is formed on the formed resist 81 using lithography. The opening region 82 is formed so that a part of the trench 75 is filled and a part of the insulating film 71 and insulating film 72 is exposed. Then, the exposed portions of the insulating film 71 and insulating film 72 are removed using dry etching or the like.

[0061] Next, as shown in Figure 7B, after the resist 81 is peeled off, the substrate region 41 of the semiconductor substrate 21 is etched to a predetermined depth using the insulating film 72 as a hard mask, and a trench 83 is formed. In the trench 83 formed by etching, a step difference is created due to the difference between the region of the trench 75 formed in step C of Figure 6 and the opening region 82 formed in step A of Figure 7.

[0062] Next, as shown in Figure 7C, after the insulating film 72 acting as a hard mask is removed, an insulating film 84 made of the same material as insulating film 71 (for example, a silicon oxide film) is embedded in the trench 83. After embedding insulating film 84, the upper surfaces of insulating film 71 and insulating film 84 are planarized using CMP (Chemical Mechanical Polishing).

[0063] Next, as shown in Figure 8A, after the resist 91, which serves as a hard mask, is formed on the insulating film 71, an opening region 92 of a predetermined size is formed on the formed resist 91 using lithography. The opening region 92 corresponds to a part of the trench 83 in which the insulating film 84 was embedded in step C of Figure 7. Subsequently, using the resist 91 with the opening region 92 formed on it as a hard mask, the insulating film 84 in the trench 83 is removed using dry etching or the like.

[0064] Next, as shown in Figure 8B, after the resist 91 is removed, an insulating film 93, for example, made of a silicon oxide film, is formed on the side and bottom surfaces of the trench 83 corresponding to the opening region 92 by CVD or thermal oxidation.

[0065] Next, as shown in Figure 8C, polysilicon 94, which is the gate electrode material, is deposited inside the trench 83 corresponding to the opening region 92 and on the upper surface of the insulating film 71 on the semiconductor substrate 21. Subsequently, a resist 95, which functions as a hard mask, is patterned on a predetermined region on the polysilicon 94 using lithography.

[0066] Using the patterned resist 95 as a hard mask, the polysilicon 94, which is the gate electrode material, is etched, and as shown in Figure 9A, the polysilicon 94 on the upper surface of the semiconductor substrate 21 and some of the polysilicon 94 in the trench 83 are removed. Once some of the polysilicon 94 in the trench 83 is removed, a trench 96 is formed in the semiconductor substrate 21.

[0067] Finally, as shown in Figure 9B, an insulating film 97 made of the same material as the insulating film 71 is deposited inside the trench 96 formed in the semiconductor substrate 21 and on the insulating film 71 on the upper surface of the semiconductor substrate 21 using a CVD method or the like. The polysilicon 94 in Figure 9B corresponds to the transfer gate electrode TGg shown in Figure 5 in a horizontally inverted state. The insulating films 71, 84, 93, and 97 surrounding the transfer gate electrode TGg correspond to the element isolation insulating film 45 in Figure 5.

[0068] The transfer gate electrode TGg shown in Figure 5 can be manufactured as described above.

[0069] <5. Second Pixel Configuration Example> Figures 10 to 13 show a second configuration example of pixel 2. Figure 10 is a plan view of pixel 2 according to the second configuration example, Figure 11 is a cross-sectional view along the line X1-X1' in Figure 10, Figure 12 is a cross-sectional view along the line X2-X2' in Figure 10, and Figure 13 is a cross-sectional view along the line Y-Y' in Figure 10.

[0070] The second configuration example shown in Figures 10 to 13 will be explained by focusing on the differences from the first configuration example described above, and explanations of common parts will be omitted as appropriate. The same applies to the third to seventh configuration examples described later.

[0071] The pixel 2 according to the second configuration example also includes a sub-pixel region 2A and a sub-pixel region 2B arranged line-symmetrically in a square pixel region, similarly to the first configuration example. The pixel 2 according to the second configuration example differs from the first configuration example in the arrangement of the transfer gate electrode TGg. Specifically, in the first configuration example, the transfer gate electrode TGg is arranged between the pixel transistor Tr and the floating diffusion FD. In contrast, the transfer gate electrode TGg of the second configuration example is arranged at a corner of the square pixel region. Similar to the first configuration example, the transfer gate electrode TGg of the sub-pixel region 2A and the transfer gate electrode TGg of the sub-pixel region 2B are arranged line-symmetrically. Although the width of the corner of the pixel isolation portion 22 where the transfer gate electrode TGg is arranged is reduced due to the element isolation insulating film 45 around the transfer gate electrode TGg, both the element isolation insulating film 45 and the pixel isolation portion 22 are formed of an insulating material, so the electrical isolation function does not deteriorate. The pixel isolation portion 22 is formed after the element isolation insulating film 45 is formed.

[0072] The thickness of the element isolation insulating film 45 around the transfer gate electrode TGg will be described with reference to the cross-sectional view taken along line X1-X1' in FIG. 11, which is a cut surface passing through the transfer gate electrode TGg.

[0073] The main charge transfer path PS is located in the vicinity of the side wall of (the embedded gate electrode TGgv of) the transfer gate electrode TGg, which faces the floating diffusion FD (the N-type semiconductor region 43). A first thickness DS1 of the element isolation insulating film 45 facing the main transfer path PS is formed to be thinner than a second thickness DS2 of the element isolation insulating film 45 on the opposite side to the main transfer path PS (DS1<DS2). Further, regarding the depth of the element isolation insulating film 45 from the first surface FA of the semiconductor substrate 21, a second depth DP2 of the element isolation insulating film 45 around the transfer gate electrode TGg is formed to be deeper than a first depth DP1 (FIG. 12) of the element isolation insulating film 45 around the pixel transistor Tr (DP1<DP2). A contact wiring 102 to which a gate control signal is supplied is connected to the transfer gate electrode TGg.

[0074] In the shallow portion of the embedded gate electrode TGgv, a fourth thickness DS4 of the element isolation insulating film 45 on the main transfer path PS side is formed to be thinner than a third thickness DS3 of the element isolation insulating film 45 on the side opposite to the main transfer path PS (DS4<DS3).

[0075] On the main transfer path PS side, the fourth thickness DS4 of the element isolation insulating film 45 in the shallow portion of the embedded gate electrode TGgv is formed to be thicker than a first thickness DS1 of the element isolation insulating film 45 in the deep portion of the embedded gate electrode TGgv (DS1<DS4). On the side opposite to the main transfer path PS, the third thickness DS3 of the element isolation insulating film 45 in the shallow portion of the embedded gate electrode TGgv is formed to be thicker than a second thickness DS2 of the element isolation insulating film 45 in the deep portion of the embedded gate electrode TGgv (DS2<DS3).

[0076] The cross-sectional view taken along line X2-X2' in Fig. 12 is the same as the cross-sectional view taken along line X-X' of the first configuration example shown in Fig. 4.

[0077] The cross-sectional view taken along line Y-Y' in Fig. 13 is a cross-sectional view corresponding to the boundary portion between the sub-pixel region 2A and the sub-pixel region 2B. The pixel separation protruding portion 22SL is provided in a part of the boundary portion between the sub-pixel region 2A and the sub-pixel region 2B by a full trench structure.

[0078] Also in the pixel 2 according to the second configuration example described above, the depth of the transfer gate electrode TGg (the embedded gate electrode TGgv thereof) is formed deeper than a first depth DP1 of the element isolation insulating film 45 of the STI structure around the pixel transistor Tr, and the first thickness DS1 of the element isolation insulating film 45 on the main transfer path PS side in the deep portion of the embedded gate electrode TGgv is made thinner than the second thickness DS2 on the opposite side, thereby improving the transfer capability of the transfer transistor TG.

[0079] Furthermore, by making the fourth thickness DS4 of the element isolation insulating film 45 in the shallow portion of the embedded gate electrode TGgv on the main transfer path PS side thicker than the first thickness DS1 in the deep portion of the embedded gate electrode TGgv, and increasing the distance from the embedded gate electrode TGgv to the floating diffusion FD, it is possible to prevent defect noise caused by a strong electric field between the transfer gate electrode TGg and the floating diffusion FD.

[0080] <6. Third Pixel Configuration Example> Figures 14 and 15 show a third configuration example of pixel 2. Figure 14 is a plan view of pixel 2 according to the third configuration example, and Figure 15 is a cross-sectional view taken along the line X-X' in Figure 14.

[0081] The third configuration is similar to the second configuration described above in that the transfer gate electrode TGg is positioned at the corner of a square pixel region. On the other hand, the third configuration differs from the second configuration described above in the configuration of the pixel separation portion 22 to which the floating diffusion FD is in contact.

[0082] Specifically, in the third configuration example, a conductor 111 (first conductor) made of a conductive material is embedded in the region of the pixel separation section 22 that the floating diffusion FD is in contact with. The conductive material of the conductor 111 can be, for example, a metallic material such as tungsten (W), aluminum (Al), copper (Cu), or gold (Au), or a silicon material doped with N-type impurities such as PDAS (Phosphorus Doped Amorphous Silicon). As shown in the cross-sectional view along line X-X' in Figure 15, the conductor 111 is in contact with the floating diffusion FD (N-type semiconductor region 43) on its side. This structure, in which the conductor is electrically connected by contacting the floating diffusion FD on its side, is called a side contact structure. Since the conductor 111 is in contact on its side with the four floating diffusion FDs provided for each of the two pixels of the shared unit including the mirror-arranged pixel 2, the signal of the floating diffusion FD can be output by connecting a single contact wire 103 to the conductor 111.

[0083] By providing the conductor 111, the number of contact wires connected to the floating diffusion FD can be reduced, thereby reducing wiring capacitance and easing constraints on element placement. Specifically, in the second configuration example, where the conductor 111 is not provided, as shown in Figure 11, contact wires 101 are provided on the upper surface (on the first surface FA of the semiconductor substrate 21) of each N-type semiconductor region 43, so as many contact wires 101 as there are N-type semiconductor regions 43 are required. On the other hand, in the third configuration example, where the conductor 111 is provided, only one contact wire 103 needs to be provided on the upper surface of the conductor 111 (on the first surface FA of the semiconductor substrate 21), thus reducing the number of contact wires connected to the floating diffusion FD. Furthermore, since the conductor 111 is in contact with all two pixels of the shared unit's floating diffusion FD (N-type semiconductor region 43) on its side, the connection resistance can be reduced.

[0084] The relationship between the first thickness DS1 to the fourth thickness DS4 of the element isolation insulating film 45 surrounding the transfer gate electrode TGg is the same as in the second configuration example described above.

[0085] In the pixel 2 according to the third configuration example configured as described above, the transfer capability of the transfer transistor TG can be improved by forming the depth of the transfer gate electrode TGg (or its embedded gate electrode TGgv) to be deeper than the first depth DP1 of the element isolation insulating film 45 of the STI structure surrounding the pixel transistor Tr, and by making the first thickness DS1 of the element isolation insulating film 45 on the main transfer path PS side of the deep part of the embedded gate electrode TGgv thinner than the second thickness DS2 on the opposite side.

[0086] Furthermore, by making the fourth thickness DS4 of the element isolation insulating film 45 in the shallow part of the embedded gate electrode TGgv on the main transfer path PS side thicker than the first thickness DS1 in the deep part of the embedded gate electrode TGgv, and by increasing the distance from the embedded gate electrode TGgv to the floating diffusion FD, defect noise caused by the strong electric field between the transfer gate electrode TGg and the floating diffusion FD can be prevented.

[0087] <7. Fourth Configuration Example of Pixel> Figures 16 to 18 are diagrams showing a fourth configuration example of the pixel 2. Fig. 16 is a plan view of the pixel 2 according to the fourth configuration example, Fig. 17 is a cross-sectional view taken along line X-X' of Fig. 16, and Fig. 18 is a cross-sectional view taken along line Y-Y' of Fig. 16.

[0088] The fourth configuration example is an example in which the first configuration example described with reference to Figs. 3 to 5 is modified such that two transfer transistors TG are arranged for one photodiode PD. The two transfer transistors TG are referred to as transfer transistors TG1 and TG2, and the two transfer gate electrodes TGg are referred to as transfer gate electrodes TGg1 and TGg2.

[0089] In the pixel 2 according to the fourth configuration example, as shown in Fig. 16, two transfer gate electrodes TGg1 and TGg2 are arranged between the pixel transistor Tr and the floating diffusion FD. The two transfer gate electrodes TGg1 and TGg2 are arranged side by side in a direction perpendicular to a direction connecting the pixel transistor Tr and the floating diffusion FD. The main transfer path PS is provided between the two transfer gate electrodes TGg1 and TGg2. A region 121 of the element isolation insulating film 45 between the transfer gate electrode TGg2 indicated by a broken ellipse in Fig. 16 and the floating diffusion FD is close to the floating diffusion FD but does not serve as the main transfer path PS.

[0090] The thickness of the element isolation insulating film 45 around the transfer gate electrodes TGg1 and TGg2 will be described with reference to the cross-sectional view taken along line X-X' of Fig. 17, which is a cut surface passing through the two transfer gate electrodes TGg1 and TGg2.

[0091] A first thickness DS1 of the element isolation insulating film 45 facing the main transfer path PS between the two transfer gate electrodes TGg1 and TGg2 is formed thinner than a second thickness DS2 of the element isolation insulating film 45 on the opposite side to the main transfer path PS (DS1<DS2). Further, looking at the depth of the element isolation insulating film 45 from the first surface FA of the semiconductor substrate 21, a second depth DP2 of the element isolation insulating film 45 around the transfer gate electrodes TGg1 and TGg2 is formed deeper than a first depth DP1 (Fig. 4) of the element isolation insulating film 45 around the pixel transistor Tr.

[0092] In the shallow portion of the buried gate electrode TGgv, the fourth thickness DS4 of the element isolation insulating film 45 on the main transfer path PS side is formed thinner than the third thickness DS3 of the element isolation insulating film 45 on the side opposite to the main transfer path PS (DS4<DS3).

[0093] The fourth thickness DS4 of the element isolation insulating film 45 in the shallow portion of the buried gate electrode TGgv is formed thicker than the first thickness DS1 of the element isolation insulating film 45 in the deep portion of the buried gate electrode TGgv (DS1<DS4). The third thickness DS3 of the element isolation insulating film 45 in the shallow portion of the buried gate electrode TGgv is formed thicker than the second thickness DS2 of the element isolation insulating film 45 in the deep portion of the buried gate electrode TGgv (DS2<DS3).

[0094] The cross-sectional view taken along line Y-Y' in Fig. 18 is a cross-sectional view in the direction connecting the transfer gate electrode TGg2 and the floating diffusion FD. As shown in Fig. 18, the element isolation insulating film 45 in the region 121 between the transfer gate electrode TGg2 and the floating diffusion FD is formed thicker than the element isolation insulating film 45 facing the main transfer path PS, and does not serve as the main transfer path PS.

[0095] Also in the pixel 2 according to the fourth configuration example configured as described above, the depth of the transfer gate electrodes TGg1 and TGg2 (of the buried gate electrode TGgv thereof) is formed deeper than the first depth DP1 of the element isolation insulating film 45 of the STI structure around the pixel transistor Tr, and the first thickness DS1 of the element isolation insulating film 45 on the main transfer path PS side in the deep portion of the buried gate electrode TGgv is made thinner than the second thickness DS2 on the opposite side, whereby the transfer capability of the transfer transistor TG can be improved.

[0096] <8. Fifth Configuration Example of Pixel> Fig. 19 is a plan view showing a fifth configuration example of the pixel 2.

[0097] The fifth configuration example shows an example in which the planar shape of the transfer gate electrode TGg, which was square in the second configuration example described with reference to FIGS. 10 to 13, is changed to a triangular shape. A main transfer path PS (not shown) for charges to the floating diffusion FD is a region facing the side wall that forms the hypotenuse among the three sides of the triangular transfer gate electrode TGg. The triangular transfer gate electrode TGg can secure a large surface area facing the main transfer path PS despite its small volume.

[0098] In the shallow portion of the buried gate electrode TGgv in FIG. 19, a fourth thickness DS4 of the element isolation insulating film 45 on the main transfer path PS side facing the hypotenuse side wall is formed thinner than a third thickness DS3 of the element isolation insulating film 45 on the side opposite to the main transfer path PS (DS4<DS3). Although not illustrated in the figure, a first thickness DS1 of the element isolation insulating film 45 facing the main transfer path PS in the deep portion of the buried gate electrode TGgv is formed thinner than a second thickness DS2 of the element isolation insulating film 45 on the side opposite to the main transfer path PS (DS1<DS2). Further, the fourth thickness DS4 of the element isolation insulating film 45 in the shallow portion of the buried gate electrode TGgv is formed thicker than the first thickness DS1 of the element isolation insulating film 45 in the deep portion of the buried gate electrode TGgv (DS1<DS4). The third thickness DS3 of the element isolation insulating film 45 in the shallow portion of the buried gate electrode TGgv on the side opposite to the main transfer path PS is formed thicker than the second thickness DS2 of the element isolation insulating film 45 in the deep portion of the buried gate electrode TGgv (DS2<DS3).

[0099] A second depth DP2 from the first surface FA of the semiconductor substrate 21 of the element isolation insulating film 45 around the transfer gate electrode TGg is formed deeper than a first depth DP1 of the element isolation insulating film 45 around the pixel transistor Tr.

[0100] <9. Sixth Configuration Example of Pixel> FIG. 20 is a plan view showing a sixth configuration example of the pixel 2.

[0101] The sixth configuration example shows a change in the planar shape of the transfer gate electrode TGg, which was square in the second configuration example described in Figures 10 to 13, to a rectangular shape. The main charge transfer path PS (not shown) to the floating diffusion FD is the region facing the side wall of the side between the floating diffusion FD and the transfer gate electrode TGg, out of the four sides of the rectangular transfer gate electrode TGg.

[0102] Figure 21 shows a modified example of pixel 2 according to the sixth configuration example, and differs from the basic configuration of the sixth configuration example shown in Figure 20 in the arrangement of the floating diffusion FD (N-type semiconductor region 43). In the basic configuration shown in Figure 20, the floating diffusion FD was arranged in contact with the pixel separation portion 22 at the outer periphery of the pixel region, but in the modified example of Figure 21, it is arranged on the tip side of the pixel separation protrusion 22SL, which is close to the well contact region 46. In this way, the floating diffusion FD can be provided at any position in contact with the pixel separation protrusion 22SL.

[0103] The cross-sectional view along the line X-X' in the plan view of Figure 20 is the same as the cross-sectional view along the line X1-X1' shown in Figure 11 in the second configuration example. Therefore, the relationship between the first thickness DS1 to the fourth thickness DS4 of the element isolation insulating film 45 around the transfer gate electrode TGg is the same as in the second configuration example described above. The modified example in Figure 21 is also the same as in the second configuration example described above.

[0104] Accordingly, in the shallow portion of the embedded gate electrode TGgv shown in FIG. 20 and FIG. 21, the fourth thickness DS4 of the element isolation insulating film 45 on the main transfer path PS side is formed thinner than the third thickness DS3 of the element isolation insulating film 45 on the opposite side to the main transfer path PS (DS4<DS3). In the deep portion of the embedded gate electrode TGgv, the first thickness DS1 of the element isolation insulating film 45 facing the main transfer path PS is formed thinner than the second thickness DS2 of the element isolation insulating film 45 on the opposite side to the main transfer path PS (DS1<DS2). Further, the fourth thickness DS4 of the element isolation insulating film 45 in the shallow portion of the embedded gate electrode TGgv is formed thicker than the first thickness DS1 of the element isolation insulating film 45 in the deep portion of the embedded gate electrode TGgv (DS1<DS4). The third thickness DS3 of the element isolation insulating film 45 in the shallow portion of the embedded gate electrode TGgv is formed thicker than the second thickness DS2 of the element isolation insulating film 45 in the deep portion of the embedded gate electrode TGgv (DS2<DS3).

[0105] Further, the second depth DP2 from the first surface FA of the semiconductor substrate 21 of the element isolation insulating film 45 around the transfer gate electrode TGg is formed deeper than the first depth DP1 of the element isolation insulating film 45 around the pixel transistor Tr.

[0106] In the pixel 2 according to the fifth configuration example and the sixth configuration example described above, the transfer capability of the transfer transistor TG can also be improved. Further, defect noise caused by a strong electric field between the transfer gate electrode TGg and the floating diffusion FD can be prevented.

[0107] <10. Seventh Configuration Example of Pixel> FIG. 22 is a plan view showing a seventh configuration example of the pixel 2.

[0108] The pixels 2 according to the first to sixth configuration examples described above have a configuration in which two photodiodes PD are arranged in a square pixel region.

[0109] In contrast, the seventh configuration example shown in FIG. 22 is an example in which one photodiode PD is arranged in a square pixel region. Further, the seventh configuration example, similar to the fourth configuration example shown in FIG. 16 to FIG. 18, has a twin gate electrode structure in which one pixel includes two transfer gate electrodes TGg1 and TGg2.

[0110] In the seventh configuration example, the 2x2 4-pixel region shown in Figure 22 becomes a repeating unit that is repeatedly arranged in the row and column directions of the pixel array section 3. Each of the four pixels 2 constituting the repeating unit has a transfer transistor TG, a floating diffusion FD, and a pixel transistor Tr arranged within the pixel such that they are symmetrical (mirror symmetrical) in the horizontal and vertical directions. The floating diffusion FD of each pixel 2 is positioned close to the center of the 2x2 4-pixel region. The well contact region 46 is located at the opposite corner in the column direction of the same side of the pixel separation section 22 that the floating diffusion FD contacts.

[0111] Figure 23 is a plan view showing a first modified example of the seventh configuration.

[0112] The first modified example shown in Figure 23 differs from the basic configuration in Figure 22 in that the number of transfer gate electrodes TGg has been changed from a twin gate electrode structure with two electrodes to a single gate electrode structure with one electrode. The single transfer gate electrode TGg is positioned between the well contact region 46 and the floating diffusion FD.

[0113] Figure 24 is a plan view showing a second modified example of the seventh configuration.

[0114] The second modification shown in Figure 24 is a configuration that adopts the side contact structure shown in Figure 14, in contrast to the first modification of the single gate electrode structure shown in Figure 23. Conductors 111 (first conductors) are provided in a cross shape in the region of the pixel separation area 22 to which the N-type semiconductor region 43 (floating diffusion FD) of each pixel 2, which is located close to the center of a 2x2 4-pixel area, come into contact. As shown in the cross-sectional view of Figure 15, the conductors 111 come into contact with the N-type semiconductor region 43 of the four pixels on their sides. In addition, a conductor 112 (second conductor) is provided in the region of the pixel separation area 22 that comes into contact with the well contact region 46. As shown in Figure 25, the well contact region 46 is also located close to four adjacent 2x2 pixels, and the conductors 112 are provided in a cross shape so as to come into contact with the well contact region 46 of the four pixels on their sides. The conductive material of the conductor 112 can be, for example, metallic materials such as tungsten (W), aluminum (Al), copper (Cu), or gold (Au), or silicon materials doped with P-type impurities such as BDAS (Bron Doped Amorphous Silicon) or B-poly (Bron Doped Poly-Silicon).

[0115] Although not shown in the diagram, the main transfer path PS is located near the side wall facing the floating diffusion FD among the four sides surrounding the transfer gate electrode TGg.

[0116] In the pixel 2 according to the seventh configuration example, the transfer capability of the transfer transistor TG can be improved by forming the depth of the transfer gate electrode TGg (or its embedded gate electrode TGgv) to be deeper than the first depth DP1 of the element isolation insulating film 45 of the STI structure surrounding the pixel transistor Tr, and by making the first thickness DS1 of the element isolation insulating film 45 on the main transfer path PS side of the deep part of the embedded gate electrode TGgv thinner than the second thickness DS2 on the opposite side.

[0117] Furthermore, a fourth thickness DS4 of the element isolation insulating film 45 in the shallow portion of the embedded gate electrode TGgv is made thicker than a first thickness DS1 in the deep portion of the embedded gate electrode TGgv, and the distance from the embedded gate electrode TGgv to the floating diffusion FD is increased, whereby defect noise caused by a strong electric field between the transfer gate electrode TGg and the floating diffusion FD can be prevented.

[0118] <11. Summary> The photodetector element 1 includes a gate electrode TGg of a transfer transistor TG that transfers charges photoelectrically converted in an N-type semiconductor region 42 (photoelectric conversion portion) constituting a photodiode PD to a floating diffusion FD (charge storage portion), and an element isolation insulating film 45 provided around the gate electrode TGg. At least the following relationship holds for a first thickness DS1, a second thickness DS2, and a third thickness DS3 of the element isolation insulating film 45 shown in FIG. 26. The element isolation insulating film 45 has the first thickness DS1 on a main transfer path PS side that transfers charges from the N-type semiconductor region 42 to the floating diffusion FD, and has the second thickness DS2 and the third thickness DS3 at different depths on a side opposite to the main transfer path PS. The first thickness DS1 is thinner than the second thickness DS2 (DS1<DS2), and the second thickness DS2 is thinner than the third thickness DS3 (DS2<DS3). The element isolation insulating film 45 having the second thickness DS2 is provided at a position deeper from the light incident surface of the semiconductor substrate 21 than the element isolation insulating film 45 having the third thickness DS3.

[0119] The depth of the (embedded gate electrode TGgv of the) transfer gate electrode TGg is formed deeper than a first depth DP1 of the element isolation insulating film 45 of the STI structure around the pixel transistor Tr, and the first thickness DS1 of the element isolation insulating film 45 on the main transfer path PS side in the deep portion of the embedded gate electrode TGgv is made thinner than the second thickness DS2 on the opposite side, whereby the transfer capability of the transfer transistor TG can be improved.

[0120] The element isolation insulating film 45 has a fourth thickness DS4 different from a first thickness DS1 on the main transfer path PS side, the first thickness DS1 is smaller than the fourth thickness DS4 (DS1<DS4), and the element isolation insulating film 45 having the first thickness DS1 is provided at a position deeper from the light incident surface than the element isolation insulating film 45 having the fourth thickness DS4.

[0121] By making the fourth thickness DS4 of the element isolation insulating film 45 in the shallow portion of the embedded gate electrode TGgv larger than the first thickness DS1 in the deep portion of the embedded gate electrode TGgv, and increasing the distance from the embedded gate electrode TGgv to the floating diffusion FD, defect noise caused by a strong electric field between the transfer gate electrode TGg and the floating diffusion FD can be prevented.

[0122] <12. Configuration Example of Electronic Device> The photodetector element 1 described above can be applied to various electronic devices such as, for example, an imaging apparatus like a digital still camera or a digital video camera, a mobile phone provided with an imaging function, or other equipment provided with an imaging function.

[0123] FIG. 27 is a block diagram showing a configuration example of an electronic device.

[0124] The electronic device 200 in FIG. 27 includes an optical system 201 including a lens group, a photodetecting element 202, a DSP (Digital Signal Processor) 203, a frame memory 204, a display unit 205, a recording unit 206, an operation unit 207, a power supply unit 208, and the like. The DSP 203, the frame memory 204, the display unit 205, the recording unit 206, the operation unit 207, and the power supply unit 208 are mutually connected via a bus 209. The electronic device 200 is, for example, an imaging apparatus capable of capturing still images and moving images.

[0125] The optical system 201 is composed of one or more lenses and guides image light (incident light) from the subject to the photodetector element 202, where it forms an image on the light-receiving surface (sensor part) of the photodetector element 202. The configuration of the photodetector element 1 described above is applied to the photodetector element 202. In the photodetector element 202, electrons as signal charges are accumulated for a certain period of time according to the image formed on the light-receiving surface via the optical system 201. Then, a signal corresponding to the electrons accumulated in the photodetector element 202 is supplied to the DSP circuit 203.

[0126] The DSP circuit 203 performs various signal processing on the signal from the photodetector element 202 to generate an image, and temporarily stores the image data in the frame memory 204. The image data stored in the frame memory 204 is recorded in the recording unit 206 or supplied to the display unit 205 to display the image. The operation unit 207 accepts various operations from the user and supplies operation signals to each block of the electronic device 200, and the power supply unit 208 supplies the power necessary to drive each block of the electronic device 200.

[0127] In the electronic device 200 configured in this way, by applying the above-described photodetector 1 as the photodetector 202, the transfer capability of the transfer transistor TG of the pixel 2 can be improved. As a result, high-quality captured images can be generated even in the electronic device 200.

[0128] <13. Examples of Image Sensor Use> Figure 28 shows an example of use when the above-mentioned photodetector 1 is an image sensor.

[0129] When the above-mentioned photodetector 1 is an image sensor, it can be used in various cases to sense light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows.

[0130] - Devices that capture images for viewing purposes, such as digital cameras and portable devices with camera functions. - Devices used for traffic purposes, such as in-vehicle sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. - Devices used in home appliances such as TVs, refrigerators, and air conditioners that capture user gestures and allow device operation according to those gestures. - Devices used for medical and healthcare purposes, such as endoscopes and devices that perform angiography using infrared light reception. - Devices used for security purposes, such as surveillance cameras for crime prevention and cameras for person recognition. - Devices used for beauty purposes, such as skin measuring devices that capture images of skin and microscopes that capture images of the scalp. - Devices used for sports purposes, such as action cameras and wearable cameras for sports use. - Devices used for agriculture, such as cameras that monitor the condition of fields and crops.

[0131] In the example described above, a photodetector element using electrons as the signal charge was explained with the first conductivity type being P-type and the second conductivity type being N-type. However, this disclosure can also be applied to a photodetector element using holes as the signal charge. In this case, the first conductivity type can be N-type and the second conductivity type can be P-type, and the aforementioned semiconductor regions can be composed of semiconductor regions of the opposite conductivity types.

[0132] The technology disclosed herein is not limited to applications to photodetectors that detect the distribution of incident light intensity of visible light and capture it as an image, but is also applicable to photodetectors that capture the distribution of incident light intensity of infrared rays, X-rays, or particles as an image, and in a broader sense, to all photodetectors (physical quantity distribution detection devices) such as fingerprint detection sensors that detect the distribution of other physical quantities such as pressure and capacitance and capture it as an image.

[0133] The embodiments of the technology described herein are not limited to those described above, and various modifications are possible without departing from the spirit of the technology described herein.

[0134] Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also occur.

[0135] Furthermore, the technology of this disclosure may adopt the following configurations: (1) A photodetector comprising a gate electrode of a transfer transistor that transfers charge photoelectrically converted in a photoelectric conversion unit to a charge storage unit, and an insulating film provided around the gate electrode, wherein the insulating film has a first thickness on the main transfer path side for transferring the charge from the photoelectric conversion unit to the charge storage unit, and a second thickness and a third thickness at different depths on the opposite side of the main transfer path, the first thickness being thinner than the second thickness, the second thickness being thinner than the third thickness, and the insulating film of the second thickness being provided at a position deeper from the light incident surface of the semiconductor substrate than the insulating film of the third thickness. (2) The photodetector according to (1), wherein the insulating film has a fourth thickness different from the first thickness on the main transfer path side, the first thickness being thinner than the fourth thickness, and the insulating film of the first thickness being provided at a position deeper from the light incident surface than the insulating film of the fourth thickness. (3) The photodetector element according to (1) or (2), further comprising pixel transistors other than the transfer transistors, wherein the insulating film of the first thickness is provided at a depth greater than the depth of the insulating film provided around the source and drain electrodes of the pixel transistors. (4) The photodetector element according to any one of (1) to (3), wherein the gate electrode is an embedded gate electrode embedded in the semiconductor substrate to a depth greater than the depth of the insulating film having a third thickness. (5) The photodetector element according to any one of (1) to (4), wherein the gate electrode has a triangular planar shape, and the main transfer path is a region facing the side wall which is the hypotenuse of the triangle in plan view. (6) The photodetector element according to any one of (1) to (5), wherein there are gate electrodes of two transfer transistors for one photoelectric conversion unit, and the main transfer path is provided between the gate electrodes of the two transfer transistors. (7) The photodetector element according to any one of (1) to (6), wherein there is a first conductor on the outer periphery of a square pixel region that is connected to a plurality of charge storage units on the side. (8) The photodetector according to (7), wherein the first conductor is configured to be connected to the charge storage portions of the plurality of pixels on the side.(9) A photodetector according to any one of (1) to (8), having a second conductor connected to a plurality of well contact regions on the side at the outer periphery of a square pixel region. (10) A photodetector according to (9), wherein the second conductor is configured to connect to the well contact regions of a plurality of pixels on the side. (11) A photodetector according to any one of (1) to (10), having two of the photoelectric conversion units in a square pixel region. (12) A photodetector according to any one of (1) to (10), having one of the photoelectric conversion units in a square pixel region. (13) A photodetector according to any one of (1) to (12), having a pixel separation unit that separates the photoelectric conversion unit at the outer periphery of a square pixel region. (14) A photodetector according to (13), wherein the pixel separation unit is configured by embedding an insulating film inside a trench structure formed to at least a part of the depth of a semiconductor substrate.

[0136] 1 Photodetector, 2 Pixel, 2A Subpixel region, 2B Subpixel region, 3 Pixel array, 21 Semiconductor substrate, 22 Pixel separation region, 22SL Pixel separation protrusion, 41 Substrate region, 42 N-type semiconductor region, 43 N-type semiconductor region, 44 N-type semiconductor region, 45 Element separation insulating film, 46 Well contact region, 200 Electronic device, 202 Photodetector, DP1 Second depth, DP2 Depth, DS1-DS4 Thickness, FD Floating diffusion, PD Photodiode, PS Main transfer path, TG Transfer transistor, TGg Gate electrode, TGgp Planar gate electrode, TGgv Embedded gate electrode, Tr Pixel transistor, SD1, SD2 Source-drain electrodes, RST Reset transistor, SEL Selection transistor, AMP Amplifier transistor

Claims

1. A photodetector comprising a gate electrode of a transfer transistor that transfers the charge photoelectrically converted in a photoelectric conversion unit to a charge storage unit, and an insulating film provided around the gate electrode, wherein the insulating film has a first thickness on the main transfer path side for transferring the charge from the photoelectric conversion unit to the charge storage unit, and a second thickness and a third thickness at different depths on the opposite side of the main transfer path, the first thickness being thinner than the second thickness, the second thickness being thinner than the third thickness, and the insulating film of the second thickness being provided at a deeper position from the light incident surface of the semiconductor substrate than the insulating film of the third thickness.

2. The photodetector element according to claim 1, wherein the insulating film has a fourth thickness different from the first thickness on the main transfer path side, the first thickness is thinner than the fourth thickness, and the insulating film of the first thickness is provided at a position deeper from the light incident surface than the insulating film of the fourth thickness.

3. The photodetector according to claim 1, further comprising a pixel transistor other than the transfer transistor, wherein the insulating film of the first thickness is provided at a position deeper than the depth of the insulating film provided around the source and drain electrodes of the pixel transistor.

4. The photodetector according to claim 1, wherein the gate electrode is an embedded gate electrode embedded in the semiconductor substrate to a position deeper than the depth of the insulating film having the third thickness.

5. The photodetector according to claim 1, wherein the gate electrode has a triangular planar shape, and the main transfer path is a region facing the side wall which is the hypotenuse of the triangle in a plan view.

6. The photodetector element according to claim 1, wherein one photoelectric conversion unit has two gate electrodes of the transfer transistors, and the main transfer path is provided between the gate electrodes of the two transfer transistors.

7. The photodetector according to claim 1, having a first conductor connected to a plurality of charge storage units on the side at the outer periphery of a square pixel region.

8. The photodetector according to claim 7, wherein the first conductor is configured to be connected to the charge storage portions of the plurality of pixels on its side.

9. The photodetector according to claim 1, having a second conductor connected to a plurality of well contact regions on the side of the outer periphery of a square pixel region.

10. The photodetector according to claim 9, wherein the second conductor is configured to connect to the well contact regions of the plurality of pixels on the side.

11. The photodetector according to claim 1, having two photoelectric conversion units in a square pixel area.

12. The photodetector according to claim 1, having one photoelectric conversion unit in a square pixel area.

13. The photodetector according to claim 1, having a pixel separation section that separates the photoelectric conversion section at the outer periphery of a square pixel region.

14. The photodetector element according to claim 13, wherein the pixel separation portion is configured by embedding an insulating film inside a trench structure formed to a depth of at least a portion of the semiconductor substrate.

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