Design assistance method, program, and information processing device

Abstract

This design assistance method includes: acquiring a full set library for performing timing verification in a semiconductor integrated circuit; acquiring a subset library including delay information outside the range of a condition defined in the full set library and having fewer cells than the number of cells included in the full set library; and using the subset library to complement the full set library.

Description

Design Support Method, Program, and Information Processing Apparatus

[0001] The present invention relates to a design support method, a program, and an information processing apparatus. This application claims priority based on U.S. Application No. 63 / 779,809 filed on March 28, 2025, and incorporates all the content described in said U.S. application by reference.

[0002] Conventionally, general-purpose semiconductors that can be mounted on various products have been mass-produced. Examples of general-purpose semiconductors include CPUs (Central Processing Units) mounted on personal computers. Conventional general-purpose semiconductors based on the von Neumann architecture have been designed to have high sequential processing performance. According to Moore's Law, it is believed that semiconductor production costs can be reduced by increasing the degree of integration. Accordingly, the main goal of conventional semiconductor development has been to increase the production volume of general-purpose semiconductors and reduce production costs. However, increasing semiconductor production volume requires substantial capital investment. For this reason, the fabless production system, in which companies primarily engaged in semiconductor design outsource semiconductor production to external companies, has become mainstream. Patent Document 1 discloses a technology related to lithography-based pattern optimization.

[0003] U.S. Patent No. 11449659 Specification

[0004] However, in the technology disclosed in Patent Document 1, no consideration is given to complementing the regions outside the range of conditions defined in a full-set library for timing verification in a semiconductor integrated circuit, using a subset library for the full-set library.

[0005] An object of the present disclosure is to provide a design support method and the like capable of complementing the regions outside the range of conditions defined in a full-set library for timing verification in a semiconductor integrated circuit, using a subset library for the full-set library.

[0006] A design support method according to one aspect of this disclosure involves obtaining a full set library for timing verification in a semiconductor integrated circuit, obtaining a subset library containing delay information outside the range of conditions defined in the full set library and having fewer cells than the number of cells in the full set library, and using the subset library to complement the full set library.

[0007] A program according to one aspect of this disclosure acquires a full set library for performing timing verification in a semiconductor integrated circuit, acquires a subset library containing delay information outside the range of conditions defined in the full set library and having fewer cells than the number of cells included in the full set library, and uses the subset library to complement the full set library.

[0008] An information processing apparatus according to one aspect of the present disclosure is an information processing apparatus comprising a control unit, wherein the control unit acquires a full set library for performing timing verification in a semiconductor integrated circuit, acquires a subset library which includes delay information outside the range of conditions defined in the full set library and has fewer cells than the number of cells included in the full set library, and uses the subset library to complement the full set library.

[0009] According to one aspect of this disclosure, a design support method can be provided that complements a full set library for timing verification in semiconductor integrated circuits by using a subset library to address conditions outside the scope defined in the full set library.

[0010] This is a schematic diagram illustrating the overview of the semiconductor design support system according to Embodiment 1. This is a block diagram showing the configuration of the information processing device. This is a flowchart illustrating the processing procedure by the control unit of the information processing device. This is an explanatory diagram showing the overview of the processing by the control unit regarding the selection of cells included in the subset library. This is an explanatory diagram showing the overview of the processing by the control unit regarding the distinction of cells included in the subset library. This is an explanatory diagram showing the overview of the processing by the control unit regarding the adjustment of the characteristics of cells included in the subset library (when there is no subset with different conditions). This is an explanatory diagram showing the overview of the processing by the control unit regarding the adjustment of the characteristics of cells included in the subset library (when there is a subset with different conditions). This is an explanatory diagram showing the overview of the processing by the control unit regarding the delay estimation of cells included in the subset library (estimation between drive capability and cell height). This is an explanatory diagram showing the overview of the processing by the control unit regarding the delay estimation of cells included in the subset library (estimation between different functions). This is an explanatory diagram showing the overview of the processing by the control unit regarding the delay estimation of cells included in the subset library (sequential circuit). This is an explanatory diagram illustrating the complementation of a full set library using a subset library. This is an explanatory diagram illustrating a language model according to Embodiment 2.

[0011] (Embodiment 1) Hereinafter, embodiments will be described based on the drawings. Figure 1 is a schematic diagram illustrating the overview of the semiconductor design support system S according to Embodiment 1. Figure 2 is a block diagram showing the configuration of the information processing device 1. The semiconductor design support system S is configured with an information processing device 1, which functions as a semiconductor design support server, as the main device. The information processing device 1 (semiconductor design support server) is connected to a terminal device 2 (designer PC) used by a semiconductor integrated circuit designer, for example, via a network such as the Internet or an intranet, so as to be able to communicate.

[0012] As will be explained in more detail later, library data, including a full set library for performing timing verification in semiconductor integrated circuits, is transmitted from terminal device 2 (designer PC) to information processing device 1 (semiconductor design support server). This full set library is a full set library that is supplemented by a subset library, and is a timing library in which only the condition ranges, such as voltage ranges, supported by the supplier are defined. In response, information processing device 1 generates a subset library (a subset library that includes delay information outside the condition range) that complements the full set library to be supplemented, and outputs the generated subset library, or the full set library (a full set library that includes delay information outside the condition range supported by the supplier) supplemented by the generated subset library.

[0013] The information processing device 1 may prepare a library characterized with a limited set of cells in order to estimate and supplement the library of the conditions, and estimate the delay time for all cells from the cells of this library. In this case, the limited set of cells is assumed to have about 1 / 10 to 1 / 50 the number of cells of a normal set. Therefore, the time required for characterization can be made to be much shorter than usual.

[0014] Designers using terminal device 2 can use subset libraries output from information processing device 1 to verify device performance at voltages outside the normally supported voltage range (±10% from Nominal Voltage). This allows for efficient handling of requests such as verifying PPAt (Power Performance Area and Time) at voltages outside the supported voltage range (especially low voltages) to determine the performance limits.

[0015] The information processing device 1 is a computer capable of various information processing and information transmission / reception, such as a server device or a personal computer. The server device includes not only a single server device but also a cloud server device or a virtual server device composed of multiple computers. The information processing device 1 includes a control unit 11, a storage unit 12, a communication unit 13, and an input / output interface 14.

[0016] The control unit 11 has one or more arithmetic processing units equipped with timing functions, such as a CPU (Central Processing Unit), an MPU (Micro-Processing Unit), and a GPU (Graphics Processing Unit), and performs various information processing, control processing, etc., by reading and executing a program P (program product) stored in the storage unit 12. Furthermore, the control unit 11 may include a semiconductor chip (AI chip) specialized for AI processing such as machine learning and deep learning.

[0017] The storage unit 12 includes volatile storage areas such as SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and flash memory, as well as non-volatile storage areas such as EEPROM or hard disk. The storage unit 12 pre-stores programs P (program products) and data referenced during processing, and also stores various data, including intermediate data, generated during processing. The programs P (program products) stored in the storage unit 12 may be programs P (program products) read from a recording medium M that the information processing device 1 can read. Alternatively, programs P (program products) may be downloaded from an external computer (not shown) connected to a communication network (not shown) and stored in the storage unit 12. As will be described in detail later, the storage unit 12 stores actual files such as language models 101.

[0018] The communication unit 13 is a communication module or communication interface for communicating with terminal devices 2, etc., via wired or wireless methods such as Ethernet (registered trademark), and is, for example, a narrow-area wireless communication module such as Wi-Fi (registered trademark) or Bluetooth (registered trademark), or a wide-area wireless communication module such as 4G or 5G. The control unit 11 communicates with terminal devices 2, such as personal computers used by designers, etc., via the communication unit 13, for example, through an external network such as the Internet or a LAN, and may also communicate with an external server (AI cloud server) on which LLM, etc., is implemented.

[0019] The input / output interface 14 includes terminals such as USB or serial cables, to which a display unit such as a monitor or an input / output device such as a keyboard is connected.

[0020] Figure 3 is a flowchart illustrating the processing procedure performed by the control unit 11 of the information processing device 1. The control unit 11 of the information processing device 1 receives, for example, operator input from the terminal device 2 (designer PC) or operator input via a keyboard connected to the input / output I / F 14, and performs the following processing based on the received operation.

[0021] The control unit 11 of the information processing device 1 acquires library data including a full set library of different conditions and a subset library of those conditions (S101). The control unit 11 of the information processing device 1 acquires the full set library to be supplemented, and at the same time acquires a subset library corresponding to the full set library to be supplemented, which includes conditions outside the range of the full set library (the subset library of those conditions), and a full set library of different conditions that have already been created. At this point, the subset library of those conditions is the data to be processed in the future, and may be pre-prepared as primitive data.

[0022] The conditions defined in the full set library include, for example, one or more conditions relating to voltage (operating voltage), temperature, or manufacturing process. If the condition is voltage, the full set library includes delay information within the voltage range supported by the supplier of the full set library (e.g., nominal voltage ±10%), but does not include delay information outside that voltage range (outside the condition range). In contrast, the subset library of the condition includes conditions outside that voltage range (outside the condition range), includes delay information for those conditions, and has substantially the same functionality or specifications as the full set library to be complemented. Furthermore, the number of cells included in the subset library is configured to be between one-tenth and one-twentieth of the number of cells included in the full set library. In addition, if a subset library corresponding to a full set library of a different condition (a subset library of a different condition) exists, the control unit 11 of the information processing device 1 may acquire the subset library of a different condition along with the full set library of the different condition. These various already generated full set libraries and subset libraries are pre-stored in the storage unit 12 of the information processing device 1.

[0023] The full-set library and subset library are timing libraries for timing verification in semiconductor integrated circuits, that is, libraries that describe the timing information of individual functional cells used in automatic placement and routing. The control unit 11 of the information processing device 1 extracts delays by performing simulations using a general-purpose simulator on a netlist or RTL, etc., from which resistance and capacitance have been extracted from the cell layout information of the target semiconductor integrated circuit. In this case, the control unit 11 of the information processing device 1 may perform extraction by varying the input waveform transition and output capacitance, and generate timing libraries (full-set library, subset library) in the form of a two-dimensional table. In this embodiment, the subset library is generated (configured) by applying (selecting) cells corresponding to sequential circuits (flip-flops, etc.) and combinational circuits (AND, OR, etc.) included in the full-set library to be complemented.

[0024] Figure 4 is an explanatory diagram showing an overview of the processing performed by the control unit 11 regarding the selection of cells included in a subset library. Timing libraries, such as the full set library to be supplemented, are typically composed of a group of files consisting of several dozen files. The control unit 11 of the information processing device 1 identifies cells corresponding to the full set library to be supplemented based on characterization conditions, i.e., extraction conditions. These characterization conditions (extraction conditions) include, for example, PVT (Process, Voltage, Temperature), i.e., process, voltage, and temperature, and are defined by combinations thereof (for example, [P / V / T]=[TT / 0.7V / 25C], [FF / 0.77V / -40C], [SS / 0.63V / 125C]).

[0025] The control unit 11 of the information processing device 1 may generate a subset library by developing variations based on function and driving capability for sequential circuits (such as flip-flops) and combinational circuits (such as AND or OR circuits), and selecting only the basic ones from among them. Furthermore, the control unit 11 of the information processing device 1 may also consider variations of multiheight cells and singleheight cells in relation to driving capability when selecting cells. By generating a subset library by selecting basic cells in this way, the number of cells in the subset library (the subset library under those conditions) can be reduced to one-tenth to one-twentieth of the number of cells in the full set library being complemented.

[0026] The control unit 11 of the information processing device 1 acquires a subset library of the conditions by generating such a subset library (a subset library of the conditions). Alternatively, the control unit 11 of the information processing device 1 may acquire the subset library of the conditions, which has been previously generated by a semiconductor integrated circuit designer or the like, by receiving it from the terminal device 2 (designer's PC).

[0027] Figure 5 is an explanatory diagram showing an overview of the processing performed by the control unit 11 regarding the distinction of cells included in the subset library. In the illustration of this embodiment, for example, the number of cells in the full set library to be complemented is 2000, and the number of cells in the small library (the subset library under the conditions) is 100. The lineup held in the small library (the subset library under the conditions) is limited to basic types (for example, functions [AND2, OR2, NOR2, AOI22, etc.], cell height [Single, etc.], and drive capacity [X1, X2, X4, etc.]) with respect to the function, cell height, and drive capacity of the cells.

[0028] The control unit 11 of the information processing device 1 compares the full set library and the subset library and extracts cells that are not present in the subset library (S102). The control unit 11 of the information processing device 1 compares the full set library under different conditions with the subset library under those conditions and extracts all cells that are present in the full set library under the different conditions but not in the subset library under those conditions. The control unit 11 of the information processing device 1 lists these extracted cells, distinguishing them by function, cell height, and drive capability, and stores them in the storage unit 12.

[0029] The control unit 11 of the information processing device 1 compares the full set library and the subset library and extracts cells that exist in both (S103). The control unit 11 of the information processing device 1 compares the full set library under different conditions with the subset library under those conditions and extracts all cells that exist in both the full set library under the different conditions and the subset library under those conditions. The control unit 11 of the information processing device 1 lists these extracted cells and stores them in the storage unit 12.

[0030] The control unit 11 of the information processing device 1 executes processing on the cells present in both (S104). For each cell present in both, the control unit 11 of the information processing device 1 executes processing based on whether the architecture is the same in the full set library with different conditions and the subset library with the same conditions. If the architecture is the same, the control unit 11 of the information processing device 1 simply copies the cells, meaning that for cells present in both, the characteristic information such as the delay of the cells in the full set library with different conditions may be directly applied to the characteristic information such as the delay of the cells in the subset library with the same conditions. If the architecture is not the same, i.e., the architecture is different, the control unit 11 of the information processing device 1 executes processing on the cells (cells present in both) depending on whether there is a subset library with different conditions corresponding to the full set library with different conditions.

[0031] Figure 6 is an explanatory diagram showing the processing overview by the control unit 11 regarding the adjustment of the characteristics of cells included in the subset library (when there is no subset with different conditions). Cells in the subset library can be used as is for the same process and architecture, but if the process is the same but the architecture is different (for example, if the cell is developed by a different company), the delay information may differ slightly even for cells with the same function and drive capability. In this case, the control unit 11 of the information processing device 1 refers to cells with the same function and drive capability in a full set library with different conditions (a full set library with different conditions) and adjusts the characteristics of the cells included in the subset library.

[0032] As an example in this embodiment, we will explain based on a cell (A) of a full set library with different conditions and a cell (B) of a sub-library (subset library) with the same conditions. Cell (A) has different extraction conditions but the same function, while cell (B) has the same extraction conditions and function, but with a different architecture. In this case, the control unit 11 of the information processing device 1 compares the delay characteristics of cell (A) and cell (B), and if there are characteristic differences, it modifies the characteristics of cell (B) to match the tendency of cell (A) and creates cell (C) of the full set library with the conditions. The full set library with the conditions is a timing library (a completed full set library) that is created by applying or merging corrections such as characteristic adjustments in the subset library with the conditions to be completed, using cells (cell (C) generated based on cells (A) and cell (B)).

[0033] Figure 7 is an explanatory diagram showing an overview of the processing performed by the control unit 11 regarding the adjustment of the characteristics of cells included in a subset library (when there is a subset with different conditions). The control unit 11 of the information processing device 1 may perform the adjustment of the characteristics of cells included in a subset library using a full set library with different conditions, and a subset library (full set library with different conditions) with the same conditions as the full set library with different conditions. When performing characteristic adjustment, if there is a subset library (full set library with different conditions) with the same conditions as the full set library with different conditions, characteristic adjustment can be performed with higher precision.

[0034] As an example in this embodiment, we will explain based on a cell (A) of a full set library with different conditions, a subset library (B1) with the same conditions as the full set library with different conditions (a smaller library with the same conditions as A), and a cell (B2) of the smaller library (subset library) with those conditions. Cells (A) and (B1) have different extraction conditions but the same functionality, while cell (B2) has the same extraction conditions and functionality, but a different architecture.

[0035] The control unit 11 of the information processing device 1 compares the delay characteristics of cell (A) and cell (B1), and further compares the delay characteristics of cell (B1) and cell (B2). The control unit 11 of the information processing device 1 can more accurately extract the differences due to architecture between cell (A) and cell (B1), and can grasp the differences between cell (B1) and cell (B2) due to conditions under the same architecture. The control unit 11 of the information processing device 1 takes these differences into consideration and determines the delay characteristics of cell (C) in the full set library of the conditions.

[0036] By adjusting the characteristics of each individual cell included in the subset library in this way, the subset library can be used to efficiently complement the full set library. In this embodiment, the control unit 11 of the information processing device 1 performs the above processing for each cell present in both based on whether or not the architecture is the same, but is not limited to this, and may perform the processing based on whether or not the cell processes are the same.

[0037] The control unit 11 of the information processing device 1 performs processing on cells that do not exist in the subset library (S105). The control unit 11 of the information processing device 1 stores the cells that do not exist in the subset library in the storage unit 12, for example, in list format or table format, by listing them based on their function, cell height, and driveability. For each cell determined by the combination of these functions, cell height, and driveability, the control unit 11 of the information processing device 1 broadly categorizes them into, for example, cells that have a function but lack driveability and cell height, and cells that lack a function, driveability, and cell height, and performs delay estimation processing for each individual cell.

[0038] Figure 8 is an explanatory diagram showing the processing overview by the control unit 11 regarding delay estimation (estimation of drive capability and cell height) of cells included in the subset library. The control unit 11 of the information processing device 1 performs estimation processing for drive capability and cell height in the case of cells that have functionality but lack drive capability and cell height (when the functionality is the same). The control unit 11 of the information processing device 1 estimates the difference in drive capability and cell height of a full set library with different conditions based on the delay of the small library (a subset library of the conditions in question). If the conditions, functionality, and drive capability are the same, the information from the small library (a subset library of the conditions in question) can be used as is, and that information is applied as is.

[0039] The control unit 11 of the information processing device 1 extracts the delay difference between the drive capability conditions (X8 and X16) in a full set library of different conditions for a drive capability condition (for example, X4, X8, X16), and estimates the delay difference between the drive capability conditions (X8 and X16) in a sub-library (subset library of the condition) of the condition based on the extracted delay difference. At this time, the control unit 11 of the information processing device 1 may adjust the characteristics of the target cell in the subset library of the condition based on the estimated delay difference. The control unit 11 of the information processing device 1 may generate a library of the condition (full set library of the condition) using the delay difference estimated in this way.

[0040] Figure 9 is an explanatory diagram showing the processing overview by the control unit 11 regarding delay estimation (estimation between different functions) of cells included in a subset library. The control unit 11 of the information processing device 1 performs estimation processing between different functions in the case of cells that do not have function, drive capability, and cell height (when the functions are different). The control unit 11 of the information processing device 1 makes the estimation from the delay information of the function in question in a full set library under different conditions and the delay information of the sublibrary (a subset library under the same conditions).

[0041] As an example in this embodiment, we will explain based on a cell (A) from a full-set library with different conditions and a cell (B) from a sub-library (subset library) with the same conditions. Cell (A) has the same function but different extraction conditions, and cell (B) has the same function but different extraction conditions. The control unit 11 of the information processing device 1 extracts paths from cell (A) for the following two cells (cell (A-1) and cell (A-2)). Cell (A-1) is a cell with the same function as the cell to be generated. Cell (A-2) is a cell referenced in the sub-library (subset library with the same conditions) (a cell with similar function).

[0042] The control unit 11 of the information processing apparatus 1 extracts a path of a cell (cell (B-1)) having a function similar to that of a cell to be generated from cell (B). When cell (B-1) does not have the same driving capability, cell (B-1) may be generated in advance by the process of (1) described above (the process in FIG. 8). The control unit 11 of the information processing apparatus 1 analyzes the delay of cell (A-1) and cell (A-2), and creates information for complementing the path of cell (A-1) with cell (A-2).

[0043] The control unit 11 of the information processing apparatus 1 estimates the delay of the cell (D) from the path information of cell (B-1) based on the information created in the above process. Cell (D) is a cell included in the generated library of the relevant condition (the full set library of the relevant condition). The full set library of the relevant condition is a timing library (complemented full set library) generated by applying or merging cell (B), for which delay estimation or the like has been reflected in the subset library of the relevant condition, to the full set library to be complemented.

[0044] FIG. 10 is an explanatory diagram showing an outline of processing by the control unit 11 related to delay estimation (sequential circuit) of cells included in a subset library. In the illustration of the present embodiment, a case where a cell to be subjected to estimation between different functions (delay estimation) is a sequential circuit is shown. The control unit 11 of the information processing apparatus 1 executes delay estimation of a sequential circuit (cell) in the same manner as the processing in FIG. 9 described above.

[0045] The control unit 11 of the information processing apparatus 1 creates a timing library for the relevant condition (S106). The control unit 11 of the information processing apparatus 1 merges the complemented cells by reflecting characteristic adjustment or delay estimation obtained through the above-described processing in the full set library of the relevant condition, thereby creating a timing library (the full set library of the relevant condition). When generating the full set library of the relevant condition (the complemented full set library), the control unit 11 of the information processing apparatus 1 may fuse (merge process) the subset library of the relevant condition, which reflects characteristic adjustment or delay estimation obtained through the above processing, into the full set library to be complemented (the full set library in which only the voltage range supported by the supplier is defined).

[0046] Figure 11 is an explanatory diagram illustrating the complementation of a full-set library using a subset library. In the illustration of this embodiment, the left graph shows the evaluation by the subset library, and the right graph shows the estimation from the information of the subset library. In these two graphs, the horizontal axis shows the voltage (operating voltage) in the semiconductor integrated circuit targeted by the timing library, and the vertical axis shows the speed (delay information). In this embodiment, voltage is shown as a condition, but it is not limited to this, and the horizontal axis showing the condition item may be defined by other condition items such as temperature or process conditions.

[0047] In the evaluation using a sublibrary (a subset library of the conditions in question), the voltages from the existing library (the full set library to be supplemented) (e.g., 0.63V, 0.7V, 0.77V) and the voltages from the sublibrary of the conditions to be supplemented (a subset library of the conditions in question) (0.6V, 0.8V) are shown. In this case, the voltage range supported by the supplier is from 0.63V to 0.77V, with 0.63V to 0.6V and 0.77V to 0.8V corresponding to the condition range outside the defined range in the full set library. In the estimation from the information of the sublibrary, that is, the estimation using the subset library generated by the above process, the voltages from the existing library (the full set library to be supplemented) (e.g., 0.63V, 0.7V, 0.77V) and the library estimated from the delay information of the sublibrary are shown.

[0048] A control unit 11 of the information processing apparatus 1 can output a speed (delay information) with respect to conditions such as voltage, for example, by using a general-purpose simulator for the subset library generated by the processing described above. Alternatively, the control unit 11 of the information processing apparatus 1 applies or fuses the subset library generated by the processing described above to a full set library to be complemented (a full set library in which only the voltage range supported by the supplier is defined), thereby generating a complemented full set library (a complemented full set library including outside the range of conditions defined by the supplier). Furthermore, the control unit 11 of the information processing apparatus 1 may output a speed (delay information) with respect to conditions such as voltage, for example, by using a general-purpose simulator for the complemented full set library.

[0049] According to this embodiment, the information processing device 1 includes delay information outside the condition range defined in the full set library, and complements the full set library with a subset library having fewer cells than the full set library. In this case, the conditions defined in the full set library, i.e., the timing library corresponding to all cells of the semiconductor integrated circuit subject to timing verification, include, for example, one or more conditions related to voltage (operating voltage), temperature, or manufacturing process (manufacturing variability). The number of cells in the subset library is one-tenth to one-twentieth of the number of cells in the full set library, and is a relatively small timing library, but the IP (Intellectual) corresponding to the subset library The functionality of the Property (semiconductor design block) or netlist (RTL) is configured to be the same as the functionality of IP, etc., corresponding to the full set library. In this case, the full set library may be a full set library with different conditions (voltage, etc.) than those of the subset library, and may be equivalent to an already completed full set library. Since the subset library configured in this way includes delay information outside the condition range defined in the full set library, it complements the delay information (delay information for each condition) that is not defined in the full set library outside that condition range. As a result, compared to, for example, re-characterizing the full set library, using the subset library configured in this way makes it possible to generate a high-precision timing library while suppressing excessive additional costs.

[0050] (Embodiment 2) Figure 12 is an explanatory diagram illustrating a language model 101 according to Embodiment 2. As described in Embodiment 1, the control unit 11 of the information processing device 1 basically estimates and completes characteristics from information in existing libraries. In this case, the estimation effect can be improved by referring to estimation results from other existing conditions and other processes. At this time, the control unit 11 of the information processing device 1 may store the estimation results in the system in advance as a machine learning model (language model 101) and refer to it when searching for the trend of characteristic variation during estimation. That is, the information processing device 1 has a language model 101 (library derivation model) implemented which takes a full set library and a subset library with conditions different from the conditions of the full set library as input and outputs a full set library corresponding to the conditions of the subset library, and the control unit 11 of the information processing device 1 derives a completed full set library using the language model 101 (library derivation model).

[0051] As an example in this embodiment, we will explain based on a cell (A) of a full set library with different conditions, a subset library (B1) with the same conditions as the full set library with different conditions (a smaller library with the same conditions as A), and a cell (B2) of the smaller library (subset library) with those conditions. Cells (A) and (B1) have different extraction conditions but the same functionality, while cell (B2) has the same extraction conditions and functionality, but a different architecture.

[0052] The control unit 11 of the information processing device 1 performs fitting during estimation by referring to or using a machine learning model (language model 101) that compares cell (A), cell (B1), and cell (B2) to estimate and generate a table of cell (C). This allows the control unit 11 of the information processing device 1 to generate cell (C) included in the full set library (completed full set library) of the given condition. The control unit 11 of the information processing device 1 can generate the full set library (completed full set library) of the given condition by performing fitting during estimation using the machine learning model (language model 101) for all cells included in the sub-library (subset library) of the given condition.

[0053] The language model 101 (library derivation model) may, for example, be composed of a large-scale language model (LLM) trained by self-supervised learning, and may be further fine-tuned using self-supervised learning or the like based on information for each condition in other processes, other versions in the same process, and matters related to various design information of semiconductor integrated circuits (corpus). The language model 101 (library derivation model) may generate a full set library (completed full set library) for the conditions by referencing a vector database (RAG: Retrieval-Augmented Generation) that vectorizes and stores information for each condition in other processes, other versions in the same process, and matters related to various design information of semiconductor integrated circuits.

[0054] The language model 101 (library derivation model) is not limited to being implemented in the information processing device 1, but may also be implemented in, for example, a cloud server (AI cloud server). In this case, the information processing device 1, which functions as a semiconductor design support server, may communicate with the AI ​​cloud server via an API (Application Programming Interface) and perform various processing using the language model 101 (library derivation model) which is composed of the large-scale language model (LLM) of the AI ​​cloud server.

[0055] According to this embodiment, the control unit 11 of the information processing device 1 extracts differences and fits them to the library as estimation and completion methods, but may also apply machine learning technology to explore trends and select appropriate characteristics. In this method (a method of completion using a subset library), if the above-mentioned machine learning model (language model 101) exists, it is possible to obtain more appropriate trends by using the language model 101 (library derived model).

[0056] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this disclosure is indicated by the claims and not in the sense described above, and all modifications within the meaning and scope equivalent to the claims are intended.

[0057] With respect to the multiple claims described in the claims, they may be combined with each other regardless of the form of reference. Multiple dependent claims that depend on multiple claims may be described in the claims. Multiple dependent claims that depend on multiple dependent claims may be described. Even if multiple dependent claims that depend on multiple dependent claims are not described, this does not limit the description of multiple dependent claims that depend on multiple dependent claims.

[0058] S Semiconductor Design Support System 1 Information Processing Unit (Semiconductor Design Support Server) 11 Control Unit 12 Memory Unit M Recording Medium P Program (Program Product) 13 Communication Unit 14 Input / Output I / F 101 Language Model (Library Derivation Model) 2 Terminal Device (Designer PC)

Claims

1. A design support method that involves obtaining a full set library for timing verification in a semiconductor integrated circuit, obtaining a subset library containing delay information outside the range of conditions defined in the full set library and having fewer cells than the full set library, and using the subset library to complement the full set library.

2. The design support method according to claim 1, wherein the conditions defined in the full set library include at least one of voltage conditions, temperature conditions, and process conditions, and the number of cells included in the subset library is one-tenth to one-twentieth of the number of cells included in the full set library.

3. The design support method according to claim 1, wherein a subset library is generated by applying cells corresponding to sequential circuits and combinational circuits included in the full set library.

4. The design support method according to claim 1, wherein the characteristics of the cells included in the subset library are adjusted according to the process or architecture of the cells, and the subset library in which the characteristics adjusted cells are reflected is used to complement the full set library.

5. The design support method according to claim 1, wherein a delay is estimated for the cells included in the subset library according to the function, height, or driving capability of the cells, and the subset library, to which the cells to which the delay is applied is used to complement the full set library.

6. A design support method according to any one of claims 1 to 5, wherein a language model that outputs a full set library corresponding to the conditions of a subset library by inputting a full set library and a subset library with conditions different from those of the full set library, derives a full set library with completion for the conditions outside the defined range of the full set library by inputting the full set library and the subset library which includes conditions outside the defined range of the full set library.

7. A program that causes a computer to perform a process to obtain a full set library for timing verification in a semiconductor integrated circuit, obtain a subset library containing delay information outside the range of conditions defined in the full set library and having fewer cells than the number of cells in the full set library, and use the subset library to complement the full set library.

8. An information processing apparatus comprising a control unit, wherein the control unit acquires a full set library for performing timing verification in a semiconductor integrated circuit, acquires a subset library containing delay information outside the range of conditions defined in the full set library and having fewer cells than the number of cells included in the full set library, and complements the full set library using the subset library.

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