Wiring board, array antenna, and antenna module

Abstract

This wiring board comprises: a substrate that has insulating properties; a strip line that extends in a planar direction in the substrate; and a coaxial line that extends in a vertical direction in the substrate and is connected to the strip line. The characteristic impedance of the coaxial line is higher than the characteristic impedance of the strip line.

Description

Wiring boards, array antennas, and antenna modules

[0001] This disclosure relates to a wiring board, an array antenna, and an antenna module.

[0002] Japanese Patent Publication No. 2015-050678 describes a technique for propagating high-frequency signals with low loss at a bend between a signal line extending in the planar direction of a substrate and a signal line extending in the vertical direction of a substrate.

[0003] The wiring board according to this disclosure comprises an insulating substrate, a strip line extending in the planar direction on the substrate, and a coaxial line extending in the vertical direction on the substrate and connected to the strip line, wherein the characteristic impedance of the coaxial line is higher than the characteristic impedance of the strip line.

[0004] The array antenna according to this disclosure comprises the above-mentioned wiring board and an array antenna board having a plurality of antennas.

[0005] The antenna module relating to this disclosure comprises the above-mentioned array antenna and a signal processing circuit.

[0006] This is a cross-sectional view showing a wiring board according to Embodiment 1 of the present disclosure. This is a diagram illustrating an example of the characteristic impedances of a strip line and a coaxial line in Embodiment 1. This is a longitudinal cross-sectional view showing the main part of the wiring board in Embodiment 1. This is a transverse cross-sectional view showing the main part of the wiring board in Embodiment 1. This is a longitudinal cross-sectional view showing the main part of the wiring board in Embodiment 2. This is a transverse cross-sectional view showing the main part of the wiring board in Embodiment 2. This is a graph showing the characteristic impedance of Embodiment 1 and a comparative example. This is a graph showing the characteristic impedance of Embodiment 2 and a comparative example. This is a graph showing the reflection characteristics of Embodiment 1 and a comparative example. This is a graph showing the reflection characteristics of Embodiment 2 and a comparative example. This is a transverse cross-sectional view showing the main part of the wiring board in Embodiment 3. This is a graph showing the characteristic impedance of the transmission line of the wiring board in Embodiment 3. This is a graph showing the reflection characteristics of the transmission line of the wiring board in Embodiment 3. This is a transverse cross-sectional view showing the main part of the wiring board in Embodiment 4. This is a graph showing the characteristic impedance of the transmission line of the wiring board in Embodiment 4. This is a graph showing the reflection characteristics of the wiring board in Embodiment 4. This is a transverse cross-sectional view showing one model of a coaxial line. This is a graph showing the relationship between each via diameter and characteristic impedance in one model of a coaxial line. This is a cross-sectional view showing the main part of the wiring board in Embodiment 5. This is an enlarged view of the area around the land of the wiring board in Embodiment 5. This is a graph showing the reflection characteristics of the wiring board in Embodiment 5. This is a cross-sectional view showing the main part of the wiring board in Embodiment 6. This is a cross-sectional view showing the main part of the wiring board in Embodiment 7. This is a cross-sectional view showing the main part of the wiring board in Embodiment 8. This is a graph showing the reflection characteristics of Embodiments 5 to 8. This is a cross-sectional view showing an array antenna and an antenna module according to an embodiment of the present disclosure.

[0007] Each embodiment of this disclosure will be described in detail below with reference to the drawings. In the following description, the direction along the central via 31 of the coaxial line 30 will be described as the vertical direction, and the direction perpendicular to the vertical direction will be described as the horizontal direction. The directions described herein may differ from the directions in use. In the following description, "plan view" means viewing or seeing through in the vertical direction.

[0008] (Embodiment 1) Figure 1 is a cross-sectional view showing a wiring board according to Embodiment 1 of the present disclosure. The wiring board 1 according to Embodiment 1 comprises an insulating base 10, a strip line 20 located on the base 10, and a coaxial line 30 located on the base 10 and connected to the strip line 20. As shown in Figure 1, the wiring board 1 may further have a strip line 41 located at another location, and coaxial lines 42, 43 located at another location. In the following description, a portion including a coaxial line 30 with one end located on the second surface S2 of the base 10 and a strip line 20 connected to the coaxial line 30 will be described. In the following description, the configuration combining the strip line 20 and the coaxial line 30 will also be referred to as a transmission line.

[0009] The substrate 10 may be in the shape of a plate having a first surface S1 and a second surface S2 located on the opposite side of the first surface S1. The substrate 10 may have a laminated structure in which a plurality of ceramic green sheets are laminated during the manufacturing stage and then fired. Various ceramic materials may be used for the substrate 10, such as LTCC (Low Temperature Co-fired Ceramics) including alumina ceramics, aluminum nitride ceramics, mullite ceramics, and glass ceramics.

[0010] The strip line 20 may include a signal conductor 21, a first film conductor 22 located vertically above the signal conductor 21, and a second film conductor 23 located vertically below the signal conductor 21. The signal conductor 21 may be a linear or strip-shaped conductor and may extend in a first direction X in the horizontal direction. The first film conductor 22 and the second film conductor 23 may be ground conductors extending horizontally. The signal conductor 21, the first film conductor 22, and the second film conductor 23 may be formed by a conductive paste that is formed in a film shape on a ceramic green sheet of the corresponding layer during the manufacturing stage and fired simultaneously with the green sheet. The characteristic impedance of the strip line 20 is determined based on the line width and thickness of the signal conductor 21, the distance between the first film conductor 22 and the signal conductor 21, the distance between the second film conductor 23 and the signal conductor 21, the relative permittivity of the substrate 10, etc.

[0011] The coaxial line 30 may comprise a central via 31 and a plurality of surrounding vias 32 that surround the central via 31. The central via 31 and the plurality of surrounding vias 32 may be columnar conductors extending in the vertical direction. The number of surrounding vias 32 is not limited to the six described in the embodiment. The plurality of surrounding vias 32 may be located at equidistant points from the central via 31. The central via 31 and the plurality of surrounding vias 32 may be formed by filling through-holes in the ceramic green sheet of the corresponding layer with conductor paste, which is fired simultaneously with the green sheet during the manufacturing stage. The through-holes may be formed in the ceramic green sheet by a punching process. The central via 31 and the plurality of surrounding vias 32 may be conductors in which multiple layers of via conductors are connected in the vertical direction. The plurality of surrounding vias 32 may be grounded conductors. The characteristic impedance of the coaxial line 30 is determined based on the diameter of the central via 31, the diameters of the plurality of surrounding vias 32, the distance between the central via 31 and the surrounding vias 32, the relative permittivity of the substrate 10, etc.

[0012] One end of the central via 31 in the coaxial line 30 and one end of the signal conductor 21 in the strip line 20 may be connected in the inner layer of the base body 10. This connection point is referred to as the bend C1. The central via 31 of the coaxial line 30 may extend to the second surface S2 of the base body 10. The base body 10 has an electrode pad 12 located on the second surface S2, and the other end of the central via 31 may be connected to the electrode pad 12. The electrode pad 12 may be connected to a circuit that outputs a high-frequency signal (e.g., IC: Integrated Circuit), and a high-frequency signal may be input from this circuit. The coaxial line 30 and the strip line 20 may be configured to transmit the high-frequency signal sequentially.

[0013] <Characteristic Impedance> Figure 2 illustrates an example of the characteristic impedances of the strip line 20 and coaxial line 30 of Embodiment 1. As shown in the following equation (1), the characteristic impedance Z0 of the coaxial line 30 ３０ The characteristic impedance Z0 of the strip line 20 ２０ It can be higher than that. Z0 ２０ < Z0 ３０... (1) Specifically, as shown in Figure 2, the characteristic impedance Z0 of the strip line 20 ２０ is within a first range 71 of 50Ω to 52Ω, while the characteristic impedance Z0 of the coaxial line 30 ３０ may be within a second range 72 of 55Ω to 62Ω (more specifically, 55.7Ω to 61.7Ω). The characteristic impedance Z0 of the coaxial line 30 ３０ may be greater than the characteristic impedance Z0 of the strip line 20 ２０ by at least 8% or more of the characteristic impedance Z0 ２０ .

[0014] The first range 71 corresponds to the range of characteristic impedance when 51Ω is taken as the design value and it is assumed that a manufacturing error of ±5% occurs in the width of the signal conductor 21. The second range 72 corresponds to the range of characteristic impedance when approximately 58Ω is taken as the design value and it is assumed that a manufacturing error of ±5% occurs respectively in the via diameters of the central via 31 and the peripheral vias 32, and in the distance between the central via 31 and the peripheral vias 32. The above manufacturing error means the maximum error between lots among a plurality of product lots.

[0015] <Details of Transmission Line> Hereinafter, an example of selecting parameter values for the coaxial line 30 will be described in comparison with parameter values of a coaxial line according to a comparative example. The comparative example has a configuration in which the designed characteristic impedances of both the strip line 20 and the coaxial line 30 are set to 50Ω. Parameters selectable for the coaxial line 30 include the diameter of the central via 31, the diameter of the peripheral vias 32, and the center-to-center distance from the central via 31 to the peripheral vias 32. The coaxial line 30 of the comparative example achieves a characteristic impedance of 50Ω by setting each diameter of the central via 31 and the peripheral vias 32 to 100 μm and setting the center-to-center distance from the central via 31 to the peripheral vias 32 to 360 μm. Hereinafter, the parameter values of the comparative example are referred to as "standard values". It should be noted that the "standard value" for the via diameter may be re-interpreted as the diameter applied to the largest number of vias among all vias provided in the wiring substrate 1.

[0016] In Embodiments 1 to 8 described later, the strip line 20 has the same configuration as that of the comparative example, and the relative permittivity of the base body 10 is the same as that of the comparative example.

[0017] <<Embodiments 1 and 2>> Figures 3A and 3B are a longitudinal and transverse cross-sectional view and a transverse cross-sectional view showing the main parts of the wiring board of Embodiment 1. In Embodiment 1, the coaxial line 30 maintains the center-to-center distance d1 between the central via 31 and the surrounding vias 32 at the standard value, and reduces the diameter of the central via 31 and the multiple surrounding vias 32 to a value smaller than the standard value, thereby achieving the high characteristic impedance Z0 mentioned above. ３０ This achieves the high characteristic impedance Z0 of the coaxial line 30. ３０ This may be achieved by making the diameters of the central via 31 and the multiple surrounding vias 32 smaller than the standard value. By making the diameters smaller, the capacitive component of the coaxial line 30 is reduced, and the characteristic impedance Z0 ３０ It can be increased.

[0018] In the simulation of Embodiment 1 below, the characteristic impedance Z0 of the coaxial line 30 ３０ To achieve a characteristic impedance of approximately 58Ω, the diameter of the central via 31 is set to 75μm, the diameters of the multiple surrounding vias 32 are set to 75μm, and the distance d1 between the centers of the central via 31 and the surrounding vias 32 is set to 360μm. The characteristic impedance Z0 obtained by applying these values ​​is... ３０ The resistance was 58.8Ω.

[0019] Figures 4A and 4B are longitudinal and transverse cross-sectional views, respectively, showing the main parts of the wiring board of Embodiment 2. In Embodiment 2, the coaxial line 30 has the diameters of the central via 31 and the multiple surrounding vias 32 kept at standard values, and the distance d1 between the central via 31 and the multiple surrounding vias 32 is made longer than the standard value, thereby achieving the high characteristic impedance Z0 mentioned above. ３０ This achieves the high characteristic impedance Z0 of the coaxial line 30. ２０ This may be achieved by increasing the distance between the central via 31 and the multiple surrounding vias 32. Increasing this distance reduces the capacitive component of the coaxial line 30, and the characteristic impedance Z0 ３０ It can be increased.

[0020] In the simulation of Embodiment 2 below, the characteristic impedance Z0 of the coaxial line 30 ３０To achieve a characteristic impedance of approximately 58 Ω, the diameters of the central via 31 and the multiple surrounding vias 32 are set to 100 μm, and the distance d1 between the centers of the central via 31 and the surrounding vias 32 is set to 475 μm. The characteristic impedance Z0 obtained by applying these values ​​is... ３０ The impedance was 58.4Ω.

[0021] Figure 5A is a graph showing the characteristic impedance of the transmission line of Embodiment 1 and the transmission line of the comparative example. Figure 5B is a graph showing the characteristic impedance of the transmission line of Embodiment 2 and the transmission line of the comparative example. The graphs in Figures 5A and 5B show the results of simulations showing the characteristic impedance of the transmission line using the TDR (Time Domain Reflectometry) method. In these graphs, section 81 corresponds to the measurement section of the strip line 20, section 82 corresponds to the measurement section of the coaxial line 30, and boundary point 83 corresponds to the bend C1. The same applies to the TDR graph in the embodiments described later.

[0022] Figure 6A is a graph showing the reflection characteristics of the transmission line of Embodiment 1 and the transmission line of the comparative example. Figure 6B is a graph showing the reflection characteristics of the transmission line of Embodiment 2 and the transmission line of the comparative example. The vertical axis of the graphs represents the reflection loss, and a lower reflection loss indicates higher transmission characteristics. The reflection characteristics were obtained by simulation. The same applies to the graphs of reflection characteristics in the embodiments described later.

[0023] As shown in the characteristic curves of the comparative example in Figures 5A and 5B, the comparative example's transmission line is designed so that the characteristic parameters of the strip line 20 and the coaxial line 30 are both 50Ω, but it includes a discontinuous structure around the bend C1. This discontinuous structure results in a difference in characteristic impedance. Specifically, the comparative example's transmission line shows a significant decrease in characteristic impedance around the bend C1. Furthermore, as shown in Figures 6A and 6B, in the high frequency band B1 such as 57 GHz to 71 GHz, the reflection characteristics of the comparative example's transmission line exceed -18 dB.

[0024] Also in the transmission lines of the first and second embodiments, a discontinuous structure is included around the bent portion C1. On the other hand, in the transmission lines of the first and second embodiments, the characteristic impedance Z0 of the coaxial line 30 ３０ is set to a high design value such as 58Ω. As a result, as shown in FIGS. 5A and 5B, compared with the comparative example, the significant decrease in characteristic impedance around the boundary point 83 where the bent portion C1 is located is improved. Then, as shown in FIGS. 6A and 6B, in the high frequency band B1, the reflection characteristic of the transmission line of the first embodiment is greatly reduced to -26 dB or less, and that of the transmission line of the second embodiment is about -20 dB, which is improved compared with the comparative example.

[0025] <<Third Embodiment>> FIGS. 7A to 7C are respectively a cross-sectional view showing essential parts of a wiring board according to a third embodiment, a graph representing characteristic impedance, and a graph showing reflection characteristics. As in the third embodiment, the high characteristic impedance Z0 of the coaxial line 30 ３０ may be achieved by making the diameter of the central via smaller than that of the surrounding vias. In the simulation for obtaining FIGS. 7B and 7C, each parameter value of the coaxial line 30 of the third embodiment is set such that the characteristic impedance Z0 ３０ is about 58Ω, the following values are adopted. That is, the diameter of the surrounding vias is 100 μm, the center-to-center distance between the central via and the surrounding vias is 360 μm, and the diameter of the central via is 75 μm. The characteristic impedance Z0 obtained by applying these respective values ３０ was 57.2Ω. Even with this configuration, as shown in FIG. 7B, the decrease in characteristic impedance around the boundary point 83 where the bent portion C1 is located is greatly improved, and as shown in FIG. 7C, the reflection characteristic in the high frequency band B1 is greatly improved.

[0026] <<Fourth Embodiment>> FIGS. 8A to 8C are respectively a cross-sectional view showing essential parts of a wiring board according to a fourth embodiment, a graph representing characteristic impedance, and a graph showing reflection characteristics. As in the fourth embodiment, the high characteristic impedance Z0 of the coaxial line 30 ３０This may be achieved by making the diameter of the surrounding vias 32 smaller than that of the central via 31. In the simulation to obtain Figures 8B and 8C, the parameter values ​​of the coaxial line 30 of Embodiment 4 are as follows: characteristic impedance Z0 ３０ The following values ​​are used to achieve a characteristic impedance of approximately 58Ω. Specifically, the diameter of the central via 31 is set to 100μm, the distance between the centers of the central via 31 and the surrounding via 32 is set to 360μm, while the diameter of the surrounding via 32 is set to 30μm. The characteristic impedance Z0 obtained by applying these values ​​is ３０ The impedance was 57.7Ω. In this configuration as well, as shown in Figure 8B, the decrease in characteristic impedance around the boundary point 83 where the bent portion C1 is located is improved, and as shown in Figure 8C, the reflection characteristics are improved in the high frequency band B1.

[0027] Figure 9A is a cross-sectional view showing one model M1 of a coaxial transmission line. Figure 9B shows the via diameters and characteristic impedance Z0 of each via in model M1. ３０ This graph shows the relationship between via diameter and characteristic impedance Z0 using Model M1 in Figure 9A. ３０ The relationship will be explained. Model M1 has one central via 31 with a diameter of φ1 and six peripheral vias 32 with a diameter of φ2, and the central via 31 and the peripheral vias 32 are separated by a distance d1 between their centers. In Figure 9B, "diameter φ1 and characteristic impedance Z0 ３０ The relationship line between the diameter φ1 and characteristic impedance Z0 is obtained when the other diameter φ2 and distance d1 are fixed, and only the diameter φ1 of the central via 31 is changed. ３０ This shows the relationship between the diameter φ2 and characteristic impedance Z0 in Figure 9B. ３０ The relationship line between the diameter φ2 and characteristic impedance Z0 is obtained when the other diameter φ1 and distance d1 are fixed, and only the diameter φ2 of the surrounding via 32 is changed. ３０ The relationship is shown in Figure 9B. The graph shows that if you reduce either diameter φ1 or diameter φ2, reducing the diameter φ1 of the central via 31 results in a characteristic impedance Z0 with respect to the amount of diameter reduction. ３０ This indicates a large increase in characteristic impedance Z0. ３０Means for achieving this may include means for reducing the diameter φ1 of the central via 31. The small diameter φ shown in FIG. 9B ｓｍａｌｌ of via has high manufacturing difficulty. Therefore, the above means can achieve a high characteristic impedance Z0 ３０ without significantly degrading the manufacturability of the coaxial line 30.

[0028] <<Embodiment 5>> FIGS. 10A to 10C are respectively a cross-sectional view showing a main part of a wiring board according to Embodiment 5, an enlarged cross-sectional view of the periphery of a land 34, and a graph showing reflection characteristics of Embodiment 5. As in Embodiment 5, the diameter φ34 of the land 34 at the bent portion C1 may be smaller than the line width w21 of the signal conductor 21.

[0029] The land 34 is a film conductor located in the same layer as the signal conductor 21 of the strip line 20 and connected to one end of the central via 31 of the coaxial line 30, as shown in FIG. 10B, and may be integrated with the signal conductor 21. The land 34 may correspond to a portion of a circular region, in a film conductor continuous with the signal conductor 21, that is concentric with the central via 31 in plan view and in which an end point p1 of the signal conductor 21 on the opposite side in the first direction X overlaps the circumference. The signal conductor 21 may have a tapered portion 21a whose line width gradually decreases as it approaches the land 34.

[0030] The configuration in which the diameter φ34 of the land 34 is smaller than the line width w21 may be adopted in accordance with making the diameter of the central via 31 of the coaxial line 30 smaller than a standard value. The diameter φ34 of the land 34 may be not less than the diameter φ31 of the central via 31. That is, the diameter φ34 of the land 34 may satisfy the following formula (2), where the diameter φ31 may be a value smaller than the standard value. φ31 ≦ φ34 < w21 (2) With this configuration, as described below, the reflection characteristics in the high frequency band B1 can be further improved.

[0031] Furthermore, as shown in the following equation (3), the diameter φ34 of the land 34 in the bent portion C1 may coincide with the diameter φ31 of the central via 31. However, the diameter φ31 may be smaller than the standard value. φ31 = φ34 ... (3) With this configuration, the reflection characteristics in the high frequency band B1 can be further improved, as will be explained below.

[0032] The graph line in Embodiment 5 of Figure 10C shows the simulation results for a configuration in which the diameter φ34 of the land 34 matches the diameter φ31 of the central via 31. In this simulation, the only difference in the parameters of the coaxial line 30 in Embodiment 5 is the size of the land 34; the values ​​of the other parameters are the same as in Embodiment 1. The diameter φ34 of the land 34 is the same as the diameter φ31 of the central via 31. As shown in the graph in Figure 10C, the reflection characteristics of Embodiment 5 show a further reduction in reflection loss in the high frequency band B1 compared to the reflection characteristics of Embodiment 1.

[0033] <<Embodiments 6-8>> Figures 11A to 11C are cross-sectional views showing the main parts of the wiring boards of Embodiments 6, 7, and 8.

[0034] As shown in Figure 11A, the multiple peripheral vias 32 of the coaxial line 30 may include a first peripheral via 32a located on one side of the width direction of the signal conductor 21 (i.e., the Y direction) and closest to the signal conductor 21, and a second peripheral via 32b located on the other side of the width direction (i.e., the -Y direction) and closest to the signal conductor 21. Furthermore, the multiple peripheral vias 32 may include a third peripheral via 32c located on one side of a virtual line segment A1 (i.e., the Y direction) obtained by virtually extending the signal conductor 21 in the opposite direction of the first direction X and closest to the virtual line segment A1, and a fourth peripheral via 32d located on the other side of the virtual line segment A1 (i.e., the -Y direction) and closest to the virtual line segment A1. Hereafter, the peripheral vias 32 other than the first peripheral via 32a and the second peripheral via 32b will also be referred to as the fifth peripheral via 32e (see Figures 11B and 11C).

[0035] As shown in Embodiment 6 of Figure 11A, in a plan view, the distance d32a between the first peripheral via 32a and the center of the signal conductor 21 may be shorter than the distance d32c between the third peripheral via 32c and the virtual line segment A1. In addition, in a plan view, the distance d32b between the second peripheral via 32b and the center of the signal conductor 21 may be shorter than the distance d32d between the fourth peripheral via 32d and the virtual line segment A1. This is as shown in equations (4a) and (4b) below: d32a < d32c ... (4a) d32b < d32d ... (4b) With this configuration, the reflection characteristics in the high frequency band B1 can be further improved, as will be explained below.

[0036] As shown in Embodiment 7 in Figure 11B, in a plan view, the diameter φ32a of the first peripheral via 32a and the diameter φ32b of the second peripheral via 32b may be larger than the diameter φ32e of the fifth peripheral via 32e. This is as shown in the following equations (5a) and (5b): φ32e < φ32a ... (5a) φ32e < φ32b ... (5b) This configuration also allows for further improvement of the reflection characteristics in the high frequency band B1, as will be explained below.

[0037] As shown in Embodiment 8 in Figure 11C, in a plan view, the lengths Ly32a and Ly32b of the first peripheral via 32a and the second peripheral via 32b in direction Y may coincide with the length Ly32e of the fifth peripheral via 32e in direction Y. Furthermore, in a plan view, the lengths Lx32a and Lx32b of the first peripheral via 32a and the second peripheral via 32b in the first direction X may be greater than the length Lx32e of the fifth peripheral via 32e in the first direction X. This is as shown in equations (6a) to (6c) below. In the above, direction Y indicates the direction orthogonal to the first direction X in a plan view. Lx32a > Lx32e ... (6a) Lx32b > Lx32e ... (6b) Ly32a = Ly32b = Ly32e ... (6c)

[0038] Furthermore, in Embodiment 8 as well, the shortest distance between the first peripheral via 32a and the second peripheral via 32b and the central via 31 may coincide with the minimum distance between the fifth peripheral via 32e and the central via 31. This coincidence, and the coincidence in formula (6c), is a concept that includes not only a strict coincidence but also differences smaller than tolerances or other errors.

[0039] Figure 12 is a graph showing the reflection characteristics of Embodiments 5 to 8. Figure 12 is the result of a simulation. As shown in Figure 12, the reflection characteristics of the transmission lines in Embodiments 6 to 8 are further improved compared to Embodiment 5 in the high frequency band B1. In the simulation, the parameter values ​​of the coaxial line 30 in Embodiment 6 are changed only from the values ​​of Embodiment 5, with the distances d32a and d32b being changed. More specifically, the distances d32a and d32b are reduced by 20 μm from the values ​​of Embodiment 5. The parameter values ​​of the coaxial line 30 in Embodiment 7 are changed only from the values ​​of Embodiment 5, with the diameters φ32a and φ32b being changed. More specifically, the diameters φ32a and φ32b are increased to 100 μm. The parameter values ​​of the coaxial line 30 in Embodiment 8 are configured with the lengths Lx32a and Lx32b being changed only from the values ​​of Embodiment 5. More specifically, the lengths Lx32a and Lx32b are approximately doubled.

[0040] The reason why the reflection characteristics are improved in the transmission lines of Embodiments 6 to 8 is as follows. That is, the area around the bend C1 in the transmission line includes a section 51 (see Figures 11A to 11C) immediately before the interaction between the signal conductor 21 of the strip line 20 and the first peripheral via 32a and second peripheral via 32b of the coaxial line 30. In the section 51 immediately before the interaction, the signal conductor 21 and the first peripheral via 32a and second peripheral via 32b are located close together, and a capacitive component is generated. On the other hand, if the diameter of the multiple peripheral vias 32, including the first peripheral via 32a and second peripheral via 32b, is reduced as in Embodiment 1, the capacitive component in the section 51 immediately before the interaction is reduced. Therefore, the characteristic impedance of the section 51 immediately before the interaction is increased. On the other hand, around the bend C1 (i.e., boundary point 83), the characteristic impedance is reduced as shown in Figure 5A. In other words, from the strip line 20 to the bend C1, the characteristic impedance is initially high in the section 51 immediately before the interaction, and then decreases in the subsequent bend C1. Therefore, the difference in characteristic impedance in that section becomes large, degrading the reflection characteristics.

[0041] On the other hand, in the transmission lines of embodiments 6 to 8, the capacitance component between the first peripheral via 32a and the second peripheral via 32b and the signal conductor 21 can be increased in the preceding section 51. This makes it possible to lower the characteristic impedance in the preceding section 51. Therefore, the difference in characteristic impedance from the preceding section 51 to the bent section C1 becomes smaller, and the reflection characteristics can be improved accordingly.

[0042] In the figures, the transmission lines of embodiments 6 to 8 are shown with a small diameter land 34 and a tapered portion 21a of the signal conductor 21. However, in the transmission lines of embodiments 6 to 8, the configurations of embodiments 1 to 4 may also be applied to the land 34 and the signal conductor 21. In this configuration as well, the effects of the first peripheral via 32a and the second peripheral via 32b described above will be achieved in the same way.

[0043] (Array Antenna and Antenna Module) Figure 13 is a longitudinal cross-sectional view showing an array antenna 100 and an antenna module 200 according to an embodiment of the present disclosure. The array antenna 100 of this embodiment comprises an array antenna substrate 120 and a signal line substrate 60, and the array antenna substrate 120 and the signal line substrate 60 may be stacked. The signal line substrate 60 may correspond to the wiring board 1 of the above embodiment. The array antenna substrate 120 and the signal line substrate 60 may be integrated. The antenna module 200 of this embodiment comprises an array antenna 100 and a signal processing circuit 210.

[0044] The array antenna substrate 120 may have a plurality of antennas 121. Each antenna 121 may be a patch antenna having a patch-shaped radiating conductor 122, a feeding conductor 123 that supplies power to the radiating conductor 122, and a grounding conductor 124 facing the radiating conductor 122. The plurality of antennas 121 may be arranged in a matrix on the first surface S1 side of the substrate 10 in a plan view.

[0045] The signal line board 60 includes a plurality of transmission lines 61, each of which may include the strip line 20 and coaxial line 30 of Embodiment 1. The ground conductor is not shown in Figure 13. The strip line 20 and coaxial line 30 may be replaced with the transmission lines of Embodiments 2 to 8. The signal line board 60 may have a plurality of electrode pads 62 located on the second surface S2. One end of each of the plurality of coaxial lines 30 may be connected to the plurality of electrode pads 62. A signal processing circuit (e.g., IC: Integrated Circuit) 210 may be connected to the plurality of electrode pads 62, and the signal processing circuit 210 may be configured to output high-frequency band feed signals to a plurality of antennas 121 via the plurality of transmission lines 61 and feed conductors 123.

[0046] The array antenna 100 and antenna module 200 of this embodiment have multiple transmission lines 61, including strip lines 20 extending horizontally and coaxial lines 30 extending vertically. Therefore, power can be supplied from a signal processing circuit 210 located in a small area to multiple antennas 121 extending in a large area via multiple transmission lines 61. Furthermore, the multiple transmission lines 61 include strip lines 20 and coaxial lines 30 included in the wiring board 1 of embodiments 1 to 8 described above. Therefore, the array antenna 100 and antenna module 200 of this embodiment can transmit a feed signal in a high frequency band B1 to the antenna 121 with good transmission characteristics that have low reflection loss. Therefore, good antenna gain can be obtained. Furthermore, the performance of the signal processing circuit 210 is less likely to deteriorate because reflection to the signal processing circuit 210 is reduced. The strip lines 20 are relatively long because they extend horizontally. On the other hand, the coaxial lines 30 are short because they extend in the thickness direction. Therefore, by making the characteristic impedance of the coaxial line 30 higher than that of the strip line 20, the advantage is obtained that the length of the section where the characteristic impedances are mismatched can be shortened.

[0047] The wiring board 1, array antenna 100, and antenna module 200 of the embodiments of the present disclosure have been described above. However, the wiring board, array antenna, and antenna module of the present disclosure are not limited to the above embodiments. For example, in the above embodiments, the case in which the coaxial line of the present disclosure is a coaxial line 30 with one end located on the second surface S2 of the wiring board 1 was described. However, the coaxial line of the present disclosure may be a coaxial line located in the inner layer of the wiring board, or a coaxial line with one end located on the first surface of the wiring board. Furthermore, in the above embodiments, a high characteristic impedance Z0 ３０ An example was shown where the parameter values ​​of each component that realize this are present throughout the entire coaxial line 30 from one end to the other. However, for example, when the coaxial line 30 is long, the high characteristic impedance Z0 is only present in the section connected to the strip line 20. ３０The parameter values ​​of each component that achieve this are applied, and in the remaining section, parameter values ​​of each component that result in a different characteristic impedance may be applied. High characteristic impedance Z0 ３０ The range to which the parameter values ​​of each component that achieve this are applied may be 100 μm or more in the vertical direction, or, if the substrate is a ceramic having a layered structure, it may be a range of two layers or more. Furthermore, the details shown in the embodiments can be modified as appropriate without departing from the spirit of the invention.

[0048] An embodiment of the present disclosure is described below. In one embodiment, (1) the wiring board comprises an insulating substrate, a strip line extending in the planar direction on the substrate, and a coaxial line extending in the vertical direction on the substrate and connected to the strip line, wherein the characteristic impedance of the coaxial line is higher than the characteristic impedance of the strip line.

[0049] (2) The wiring board described in (1) above, wherein the strip line has a signal conductor and extends in a first direction from the coaxial line in a plan view, the coaxial line has a central via located in the center of the coaxial line in a plan view, and a plurality of peripheral vias surrounding the central via in a plan view, the plurality of peripheral vias include a first peripheral via located on one side in the width direction of the signal conductor and closest to the signal conductor, a second peripheral via located on the other side in the width direction and closest to the signal conductor, a third peripheral via located on one side of a virtual line segment obtained by virtually extending the signal conductor in the opposite direction to the first direction and closest to the virtual line segment, and a fourth peripheral via located on the other side of the virtual line segment and closest to the virtual line segment, in a plan view, the distance between the first peripheral via and the center of the signal conductor is shorter than the distance between the third peripheral via and the virtual line segment. In a plan view, the distance between the second peripheral via and the center of the signal conductor is shorter than the distance between the fourth peripheral via and the imaginary line segment.

[0050] (3) The wiring board described in (1) above has a strip line having a signal conductor and extending in a first direction from the coaxial line in a plan view, the coaxial line having a central via located in the center of the coaxial line in a plan view, and a plurality of peripheral vias surrounding the central via in a plan view, the plurality of peripheral vias including a first peripheral via located on one side in the width direction of the signal conductor and closest to the signal conductor, a second peripheral via located on the other side in the width direction and closest to the signal conductor, and a fifth peripheral via other than the first peripheral via and the second peripheral via, wherein the diameters of the first peripheral via and the second peripheral via are greater than the diameter of the fifth peripheral via.

[0051] (4) The wiring board described in (1) above has a strip line having a signal conductor and extending in a first direction from the coaxial line in a plan view, the coaxial line having a central via located in the center of the coaxial line in a plan view, and a plurality of peripheral vias surrounding the central via in a plan view, the plurality of peripheral vias including a first peripheral via located on one side in the width direction of the signal conductor and closest to the signal conductor, a second peripheral via located on the other side in the width direction and closest to the signal conductor, and a fifth peripheral via other than the first peripheral via and the second peripheral via, in a plan view the lengths of the first peripheral via and the second peripheral via in the direction orthogonal to the first direction are the same as the length of the fifth peripheral via in the direction orthogonal to the first direction, and in a plan view the lengths of the first peripheral via and the second peripheral via in the first direction are greater than the length of the fifth peripheral via in the first direction.

[0052] In one embodiment, (5) the array antenna comprises one of the wiring boards described in (1) to (4) above, and an array antenna board having a plurality of antennas.

[0053] In one embodiment, (6) the antenna module comprises the array antenna described in (5) above, and a signal processing circuit.

[0054] This disclosure can be used in wiring boards, array antennas, and antenna modules.

[0055] 1 Wiring board 10 Base 12 Electrode pad S1 First surface S2 Second surface 20, 41 Strip line 21 Signal conductor 21a Tapered section 22 First film conductor 23 Second film conductor 30, 42, 43 Coaxial line 31 Center via 32 Surround via 32a First surround via 32b Second surround via 32c Third surround via 32d Fourth surround via 32e Fifth surround via 34 Land 51 Immediate section 60 Signal line board (wiring board) 61 Transmission line 62 Electrode pad 100 Array antenna 120 Array antenna board 121 Antenna 122 Radiating conductor 123 Feed conductor 124 Ground conductor 200 Antenna module 210 Signal processing circuit C1 Bent section

Claims

1. A wiring board comprising: an insulating substrate; strip lines extending in a planar direction on the substrate; and coaxial lines extending vertically on the substrate and connected to the strip lines, wherein the characteristic impedance of the coaxial lines is higher than the characteristic impedance of the strip lines.

2. The strip line has a signal conductor and extends in a first direction from the coaxial line in a plan view, the coaxial line has a central via located in the center of the coaxial line in a plan view, and a plurality of peripheral vias surrounding the central via in a plan view, the plurality of peripheral vias include a first peripheral via located on one side in the width direction of the signal conductor and closest to the signal conductor, a second peripheral via located on the other side in the width direction and closest to the signal conductor, a third peripheral via located on one side of a virtual line segment obtained by virtually extending the signal conductor in the opposite direction to the first direction and closest to the virtual line segment, and a fourth peripheral via located on the other side of the virtual line segment and closest to the virtual line segment, in a plan view, the distance between the first peripheral via and the center of the signal conductor is shorter than the distance between the third peripheral via and the virtual line segment, and in a plan view, the distance between the second peripheral via and the center of the signal conductor is shorter than the distance between the fourth peripheral via and the virtual line segment, the wiring board according to claim 1.

3. The wiring board according to claim 1, wherein the strip line has a signal conductor and extends in a first direction from the coaxial line in a plan view, the coaxial line has a central via located in the center of the coaxial line in a plan view, and a plurality of peripheral vias surrounding the central via in a plan view, the plurality of peripheral vias include a first peripheral via located on one side in the width direction of the signal conductor and closest to the signal conductor, a second peripheral via located on the other side in the width direction and closest to the signal conductor, and a fifth peripheral via other than the first peripheral via and the second peripheral via, the diameters of the first peripheral via and the second peripheral via are greater than the diameter of the fifth peripheral via.

4. The wiring board according to claim 1, wherein the strip line has a signal conductor and extends in a first direction from the coaxial line in a plan view, the coaxial line has a central via located in the center of the coaxial line in a plan view, and a plurality of peripheral vias surrounding the central via in a plan view, the plurality of peripheral vias include a first peripheral via located on one side in the width direction of the signal conductor and closest to the signal conductor, a second peripheral via located on the other side in the width direction and closest to the signal conductor, and a fifth peripheral via other than the first peripheral via and the second peripheral via, in a plan view, the lengths of the first peripheral via and the second peripheral via in the direction orthogonal to the first direction are the same as the length of the fifth peripheral via in the direction orthogonal to the first direction, and in a plan view, the lengths of the first peripheral via and the second peripheral via in the first direction are greater than the length of the fifth peripheral via in the first direction.

5. An array antenna comprising a wiring board according to any one of claims 1 to 4, and an array antenna board having a plurality of antennas.

6. An antenna module comprising the array antenna described in claim 5 and a signal processing circuit.

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