Semiconductor device and photodetection device

Abstract

A semiconductor device according to an embodiment of the present disclosure comprises: a first semiconductor layer that has a first element; a second semiconductor layer that is laminated on the first semiconductor layer and that has a first surface facing the first semiconductor layer and a second surface which is on the opposite side from the first surface and is provided with a second element; a connection part that extends between the first semiconductor layer and the second semiconductor layer, that has a second semiconductor layer-side end part on the same plane as the first surface of the second semiconductor layer or further on the first semiconductor layer side than the first surface, and that electrically connects the first element and the second element; and an electroconductive part that electrically connects the connection part and the second element.

Description

Semiconductor device and photodetection device

[0001] The present disclosure relates to a semiconductor device in which a plurality of semiconductor layers are stacked and a photodetection device.

[0002] For example, Patent Document 1 discloses an imaging device in which a first semiconductor substrate and a second semiconductor substrate stacked on each other penetrate an insulating layer provided therebetween, and are electrically connected by a connection portion that connects the first semiconductor substrate and the back surface of the second semiconductor substrate.

[0003] Japanese Unexamined Patent Publication No. 2022-147587

[0004] Incidentally, for example, in photodetection devices, improvement in reliability is required.

[0005] It is desirable to provide a semiconductor device and a photodetection device capable of improving reliability.

[0006] A semiconductor device according to an embodiment of the present disclosure includes: a first semiconductor layer having a first element; a second semiconductor layer stacked on the first semiconductor layer, the second semiconductor layer having a first surface facing the first semiconductor layer and a second surface opposite to the first surface, the second element being provided on the second surface; a connection portion extending between the first semiconductor layer and the second semiconductor layer, the connection portion having an end on the second semiconductor layer side that is flush with the first surface of the second semiconductor layer or closer to the first semiconductor layer than the first surface is, the connection portion electrically connecting the first element and the second element; and a conductive portion electrically connecting the connection portion and the second element.

[0007] A photodetection device according to an embodiment of the present disclosure includes: a first semiconductor layer having sensor pixels that perform photoelectric conversion; a second semiconductor layer stacked on the first semiconductor layer, the second semiconductor layer having a first surface facing the first semiconductor layer and a second surface opposite to the first surface, one transistor being provided on the second surface; a first connection portion extending between the first semiconductor layer and the second semiconductor layer, the first connection portion having an end on the second semiconductor layer side that is flush with the first surface of the second semiconductor layer or closer to the first semiconductor layer than the first surface is, the first connection portion electrically connecting the sensor pixel and the one transistor; and a first conductive portion electrically connecting the first connection portion and the one transistor.

[0008] In a semiconductor device according to one embodiment of the present disclosure and a photodetector according to one embodiment, a first element and a second element, provided on a first semiconductor layer and a second semiconductor layer stacked on top of each other, are electrically connected via a connecting portion and a conductive portion. The connecting portion extends between the first semiconductor layer and the second semiconductor layer, and its end on the second semiconductor layer side is located on the second semiconductor layer side of the first surface of the second semiconductor layer facing the first semiconductor layer. The conductive portion electrically connects this connecting portion and the second element. This reduces the connection resistance between the connecting portion and the second element while ensuring connection yield.

[0009] Figure 1 is a block diagram showing an example of the functional configuration of a photodetector according to an embodiment of the present disclosure. Figure 2 is a schematic plan view showing the general configuration of the photodetector shown in Figure 1. Figure 3 is a schematic diagram showing a cross-sectional configuration along the line A-A' shown in Figure 2. Figure 4A is an example of an equivalent circuit diagram of the pixel circuit shown in Figure 1. Figure 4B is another example of an equivalent circuit diagram of the pixel circuit shown in Figure 1. Figure 5 is a schematic cross-sectional view showing an example of the configuration of the photodetector shown in Figure 3. Figure 6 is a schematic plan view showing a specific example of the configuration of the photodetector shown in Figure 3. Figure 7 is a schematic cross-sectional view showing a specific example of the configuration of the photodetector shown in Figure 3. Figure 8 is an enlarged view of the connection portion between the connection portion and the semiconductor layer shown in Figure 7. Figure 9 is a schematic cross-sectional view showing another example of the specific configuration of the photodetector shown in Figure 3. Figure 10 is a schematic cross-sectional view showing another example of the specific configuration of the photodetector shown in Figure 3. Figure 11A is a schematic cross-sectional view illustrating an example of a method for manufacturing the photodetector shown in Figure 9. Figure 11B is a schematic cross-sectional view showing the process following Figure 11A. Figure 11C is a schematic cross-sectional diagram showing the process following Figure 11B. Figure 11D is a schematic cross-sectional diagram showing the process following Figure 11C. Figure 11E is a schematic cross-sectional diagram showing the process following Figure 11D. Figure 11F is a schematic cross-sectional diagram showing the process following Figure 11E. Figure 11G is a schematic cross-sectional diagram showing the process following Figure 11F. Figure 11H is a schematic cross-sectional diagram showing the process following Figure 11G. Figure 12 is a schematic cross-sectional diagram showing an example of the connection between elements provided on the first substrate and the second substrate, respectively, in a general photodetector. Figure 13 is a schematic cross-sectional diagram showing an example of a specific configuration of a photodetector according to Modification 1 of this disclosure. Figure 14 is an enlarged view of the connection between the connection part shown in Figure 13 and the semiconductor layer. Figure 15 is a schematic cross-sectional diagram showing an example of a specific configuration of a photodetector according to Modification 2 of this disclosure. Figure 16 is a schematic cross-sectional diagram showing an example of a specific configuration of a photodetector according to Modification 3 of this disclosure. Figure 16 is a schematic cross-sectional view showing another example of the specific configuration of the photodetector according to Modification 3 of the present disclosure. Figure 18 is a schematic plan view showing an example of the specific configuration of the photodetector according to Modification 4 of the present disclosure. Figure 19 is a schematic plan view showing another example of the specific configuration of the photodetector according to Modification 4 of the present disclosure.Figure 20 is a schematic plan view showing another example of the specific configuration of the photodetector according to Modification 4 of the present disclosure. Figure 21 is a schematic plan view showing one example of the specific configuration of the photodetector according to Modification 5 of the present disclosure. Figure 22 is a schematic plan view showing another example of the specific configuration of the photodetector according to Modification 5 of the present disclosure. Figure 23A is a schematic cross-sectional view illustrating an example of a method for manufacturing the photodetector shown in Figure 21. Figure 23B is a schematic cross-sectional view showing the process following Figure 23A. Figure 23C is a schematic cross-sectional view showing the process following Figure 23B. Figure 23D is a schematic cross-sectional view showing the process following Figure 23C. Figure 23E is a schematic cross-sectional view showing the process following Figure 23D. Figure 23F is a schematic cross-sectional view showing the process following Figure 23E. Figure 24 is a schematic plan view showing one example of the specific configuration of the photodetector according to Modification 6 of the present disclosure. Figure 25 is a schematic plan view showing another example of the specific configuration of the photodetector according to Modification 6 of the present disclosure. Figure 26 is a schematic plan view showing another example of the specific configuration of the photodetector according to Modification 6 of the present disclosure. Figure 27 is a schematic plan view showing another example of the specific configuration of the photodetector according to Modification 6 of the present disclosure. Figure 28 is a schematic plan view showing another example of the specific configuration of the photodetector according to Modification 6 of the present disclosure. Figure 29 is a block diagram showing an example of the configuration of an electronic device having the photodetector shown in Figure 1. Figure 30A is a schematic diagram showing an example of the overall configuration of a photodetector system using the photodetector shown in Figure 1, etc. Figure 30B is a diagram showing an example of the circuit configuration of the photodetector system shown in Figure 30A. Figure 31A is a diagram showing an example of the appearance of an information processing system. Figure 31B is a diagram showing another example of the appearance of an information processing system. Figure 32 is a block diagram showing an example of the hardware configuration of the information processing system shown in Figures 31A and 31B. Figure 33 is a diagram showing an example of the schematic configuration of an endoscopic surgery system. Figure 34 is a block diagram showing an example of the functional configuration of a camera head and a CCU. Figure 35 is a block diagram showing an example of the schematic configuration of a vehicle control system. Figure 36 is an explanatory diagram showing an example of the installation location of the external information detection unit and the imaging unit.

[0010] The embodiments of this disclosure will be described in detail below with reference to the drawings. The following description is one specific example of this disclosure, and this disclosure is not limited to the following embodiments. Furthermore, this disclosure is not limited to the arrangement, dimensions, dimensional ratios, etc., of each component shown in each figure. The order of description is as follows: 1. Embodiment (Example of a photodetector in which a connecting portion extending between the semiconductor layers of the first substrate and the second substrate is connected to the semiconductor layer of the second substrate via a conductive portion) 2. Modifications 2-1. Modification 1 (Another example of the configuration of a photodetector) 2-2. Modification 2 (Another example of the configuration of a photodetector) 2-3. Modification 3 (Another example of the configuration of a photodetector) 2-4. Modification 4 (Another example of the configuration of a photodetector) 2-5. Modification 5 (Another example of the configuration of a photodetector) 2-6. Modification 6 (Another example of the configuration of a photodetector) 3. Application Examples 4. Application Examples

[0011] <1. Embodiments> An optical detection device (optical detection device 1) according to one embodiment of the present disclosure is used, for example, as a CMOS (Complementary Metal Oxide Semiconductor) image sensor used in electronic devices such as digital still cameras and video cameras.

[0012] [Functional Configuration of the Light Detection Device] Figure 1 is a block diagram showing an example of the functional configuration of the light detection device 1.

[0013] The light detection device 1 in Figure 1 includes, for example, an input unit 510A, a row drive unit 520, a timing control unit 530, a pixel array unit 540, a column signal processing unit 550, an image signal processing unit 560, and an output unit 510B.

[0014] In the pixel array section 540, multiple pixels 541 are repeatedly arranged in an array. More specifically, a pixel sharing unit 539 containing multiple pixels 541 serves as the repeating unit, and these are repeatedly arranged in an array consisting of row and column directions. For convenience, in this specification, the row direction may be referred to as the H direction or X-axis direction, and the column direction, which is orthogonal to the row direction, may be referred to as the V direction or Y-axis direction. In the example in Figure 1, one pixel sharing unit 539 contains four pixels (pixels 541A to 541D). Each of the pixels 541A to 541D has a photodiode PD (illustrated in Figure 5, etc., described later). The pixel sharing unit 539 is a unit that shares one pixel circuit (pixel circuit 210 in Figures 4A and 4B, described later). In other words, there is one pixel circuit (pixel circuit 210 described later) for every four pixels (pixels 541A to 541D). By operating this pixel circuit in a time-division multiplexing manner, the pixel signals of each of the pixels 541A to 541D are read out sequentially. The pixels 541A to 541D are arranged, for example, in a 2x2 grid. The pixel array section 540 is provided with the pixels 541A to 541D, as well as a plurality of row drive signal lines 542 and a plurality of vertical signal lines (column read lines) 543. The row drive signal lines 542 drive the pixels 541 included in each of the plurality of pixel sharing units 539 that are arranged in the row direction in the pixel array section 540. The row drive signal lines 542 drive each pixel of the pixel sharing unit 539 that is arranged in the row direction. As will be explained in detail later with reference to Figures 4A and 4B, the pixel sharing unit 539 is provided with a plurality of transistors. To drive each of these plurality of transistors, a plurality of row drive signal lines 542 are connected to one pixel sharing unit 539. The pixel sharing unit 539 is connected to the vertical signal lines (column read lines) 543. Pixel signals are read out from each of the pixels 541A to 541D included in the pixel sharing unit 539 via vertical signal lines (column readout lines) 543.

[0015] The row drive unit 520 includes, for example, a row address control unit that determines the position of a row for driving pixels, in other words, a row decoder unit, and a row drive circuit unit that generates signals for driving pixels 541A to 541D.

[0016] The timing control unit 530 supplies timing control signals to the row drive unit 520 and the column signal processing unit 550 based on the reference clock signal and timing control signal input to the device.

[0017] The column signal processing unit 550 includes, for example, a load circuit section connected to the vertical signal line 543 and forming a source follower circuit with the pixels 541A to 541D (pixel sharing unit 539). The column signal processing unit 550 may also have an amplification circuit section that amplifies the signal read from the pixel sharing unit 539 via the vertical signal line 543. The column signal processing unit 550 may also have a noise processing unit. In the noise processing unit, for example, the noise level of the system is removed from the signal read from the pixel sharing unit 539 as a result of photoelectric conversion.

[0018] The column signal processing unit 550 includes, for example, an analog-to-digital converter (ADC). In the analog-to-digital converter, the signal read from the pixel sharing unit 539 or the noise-processed analog signal is converted into a digital signal. The ADC includes, for example, a comparator unit and a counter unit. In the comparator unit, the analog signal to be converted is compared with a reference signal to be compared with it. In the counter unit, the time until the comparison result in the comparator unit is reversed is measured. The column signal processing unit 550 may also include a horizontal scanning circuit unit that controls scanning of the readout column.

[0019] The image signal processing unit 560 is a circuit that performs various signal processing on the data obtained as a result of photoelectric conversion, in other words, the data obtained as a result of the imaging operation in the photodetector 1. The image signal processing unit 560 includes, for example, an image signal processing circuit unit and a data holding unit. The image signal processing unit 560 may also include a processor unit.

[0020] One example of signal processing performed in the image signal processing unit 560 is tone curve correction processing, which increases the tonal range of AD-converted imaging data if it is data of a dark subject, and decreases the tonal range if it is data of a bright subject. In this case, it is desirable to store in advance the characteristic data of the tone curve on which the tonal range of the imaging data will be corrected in the data storage unit of the image signal processing unit 560.

[0021] The input unit 510A is for inputting, for example, the above-mentioned reference clock signal, timing control signal, and characteristic data from outside the device to the light detection device 1. The timing control signal is, for example, a vertical synchronization signal and a horizontal synchronization signal. The characteristic data is, for example, stored in the data holding unit of the image signal processing unit 560. The input unit 510A includes, for example, an input terminal 511, an input circuit unit 512, an input amplitude changing unit 513, an input data conversion circuit unit 514, and a power supply unit (not shown).

[0022] The input terminal 511 is an external terminal for inputting data. The input circuit section 512 is for taking the signal input to the input terminal 511 into the photodetector 1. The input amplitude changing section 513 changes the amplitude of the signal taken in by the input circuit section 512 to an amplitude that is easy to use inside the photodetector 1. The input data conversion circuit section 514 changes the order of the data sequence of the input data. The input data conversion circuit section 514 is configured, for example, by a serial-to-parallel conversion circuit. In this serial-to-parallel conversion circuit, the serial signal received as input data is converted into a parallel signal. Note that in the input section 510A, the input amplitude changing section 513 and the input data conversion circuit section 514 may be omitted. The power supply section supplies power set to various voltages required inside the photodetector 1, based on the power supply supplied to the photodetector 1 from the outside.

[0023] When the light detection device 1 is connected to an external memory device, the input unit 510A may be provided with a memory interface circuit for receiving data from the external memory device. The external memory device may be, for example, flash memory, SRAM, or DRAM.

[0024] The output unit 510B outputs image data to the outside of the device. This image data includes, for example, image data captured by the light detection device 1 and image data processed by the image signal processing unit 560. The output unit 510B includes, for example, an output data conversion circuit unit 515, an output amplitude changing unit 516, an output circuit unit 517, and an output terminal 518.

[0025] The output data conversion circuit 515 is configured, for example, by a parallel-to-serial conversion circuit, in which the parallel signal used inside the photodetector 1 is converted into a serial signal. The output amplitude modification unit 516 modifies the amplitude of the signal used inside the photodetector 1. The signal with the modified amplitude is made easier to use by external devices connected outside the photodetector 1. The output circuit 517 is a circuit that outputs data from inside the photodetector 1 to outside the device, and the output circuit 517 drives the wiring outside the photodetector 1 connected to the output terminal 518. At the output terminal 518, data is output from the photodetector 1 to outside the device. In the output unit 510B, the output data conversion circuit 515 and the output amplitude modification unit 516 may be omitted.

[0026] When the light detection device 1 is connected to an external memory device, the output unit 510B may be provided with a memory interface circuit for outputting data to the external memory device. The external memory device may be, for example, flash memory, SRAM, or DRAM.

[0027] [Schematic Configuration of the Photodetector] Figures 2 and 3 show an example of the schematic configuration of the photodetector 1. The photodetector 1 comprises three substrates (first substrate 100, second substrate 200, and third substrate 300). Figure 2 schematically shows the planar configuration of each of the first substrate 100, second substrate 200, and third substrate 300, and Figure 3 schematically shows the cross-sectional configuration of the first substrate 100, second substrate 200, and third substrate 300 stacked on top of each other. Figure 3 corresponds to the cross-sectional configuration along the line A-A' shown in Figure 2. The photodetector 1 is a three-dimensional photodetector constructed by bonding together three substrates (first substrate 100, second substrate 200, and third substrate 300). The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. Here, the wiring contained in each of the first substrate 100, the second substrate 200, and the third substrate 300, along with the interlayer insulating film surrounding it, are conveniently referred to as the wiring layers (100T, 200T, 300T) provided on each substrate (first substrate 100, second substrate 200, and third substrate 300). The first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order, and are arranged in the order of semiconductor layer 100S, wiring layer 100T, semiconductor layer 200S, wiring layer 200T, wiring layer 300T, and semiconductor layer 300S along the stacking direction. The specific configurations of the first substrate 100, the second substrate 200, and the third substrate 300 will be described later. The arrows shown in Figure 3 indicate the direction of incidence of light L to the photodetector 1. In this specification, for convenience, the side on which light is incident in the photodetector 1 may be referred to as "bottom," "lower side," or "downward," and the side opposite to the side on which light is incident may be referred to as "top," "upper side," or "upward" in the following cross-sectional diagrams. Also, in this specification, for convenience, with respect to a substrate having a semiconductor layer and a wiring layer, the side with the wiring layer may be referred to as the front surface and the side with the semiconductor layer as the back surface. However, the description in this specification is not limited to the above terminology. The photodetector 1 is, for example, a back-illuminated photodetector in which light is incident from the back surface of a first substrate 100 having a photodiode.

[0028] The pixel array section 540 and the pixel sharing unit 539 included in the pixel array section 540 are both constructed using both the first substrate 100 and the second substrate 200. The first substrate 100 is provided with a plurality of pixels 541A to 541D of the pixel sharing unit 539. Each of these pixels 541 has a photodiode (photodiode PD described later) and a transfer transistor (transfer transistor TR described later). The second substrate 200 is provided with a pixel circuit (pixel circuit 210 described later) of the pixel sharing unit 539. The pixel circuit reads out the pixel signal transferred from the photodiode of each of the pixels 541A to 541D via the transfer transistor, or resets the photodiode. In addition to such a pixel circuit, the second substrate 200 has a plurality of row drive signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction. The second substrate 200 further has power lines 544 (power lines VDD, etc., described later) extending in the row direction. The third substrate 300 has, for example, an input unit 510A, a row drive unit 520, a timing control unit 530, a column signal processing unit 550, an image signal processing unit 560, and an output unit 510B. The row drive unit 520 is provided, for example, in a region that partially overlaps the pixel array unit 540 in the stacking direction of the first substrate 100, the second substrate 200, and the third substrate 300 (hereinafter simply referred to as the stacking direction). More specifically, the row drive unit 520 is provided in a region that overlaps near the H-direction end of the pixel array unit 540 in the stacking direction. The column signal processing unit 550 is provided, for example, in a region that partially overlaps the pixel array unit 540 in the stacking direction. More specifically, the column signal processing unit 550 is located in a region that overlaps with the vicinity of the V-direction end of the pixel array section 540 in the stacking direction. Although not shown in the figures, the input section 510A and the output section 510B may be located in a part other than the third substrate 300, for example, on the second substrate 200. Alternatively, the input section 510A and the output section 510B may be located on the back surface (light incident surface) of the first substrate 100. The pixel circuit located on the second substrate 200 may also be referred to as a pixel transistor circuit, a group of pixel transistors, a pixel transistor, a pixel readout circuit, or a readout circuit.In this specification, the term "pixel circuit" is used.

[0029] The first substrate 100 and the second substrate 200 are electrically connected, for example, by through electrodes (through electrodes 252, 253 in Figure 5, described later). The second substrate 200 and the third substrate 300 are electrically connected, for example, by contact portions 201, 202, 301, 302. Contact portions 201, 202 are provided on the second substrate 200, and contact portions 301, 302 are provided on the third substrate 300. Contact portion 201 of the second substrate 200 is in contact with contact portion 301 of the third substrate 300, and contact portion 202 of the second substrate 200 is in contact with contact portion 302 of the third substrate 300. The second substrate 200 has a contact region 201R provided with a plurality of contact portions 201, and a contact region 202R provided with a plurality of contact portions 202. The third substrate 300 has a contact region 301R provided with a plurality of contact portions 301 and a contact region 302R provided with a plurality of contact portions 302. The contact regions 201R and 301R are provided between the pixel array portion 540 and the row drive portion 520 in the stacking direction, as shown in Figure 3, for example. In other words, the contact regions 201R and 301R are provided in the region where the row drive portion 520 (third substrate 300) and the pixel array portion 540 (second substrate 200) overlap in the stacking direction, or in a nearby region. The contact regions 201R and 301R are provided, for example, at the ends in the H direction of such a region. In the third substrate 300, for example, the contact region 301R is provided at a position that overlaps with a part of the row drive portion 520, specifically the end of the row drive portion 520 in the H direction. The contact sections 201 and 301 connect, for example, the row drive unit 520 provided on the third substrate 300 to the row drive signal line 542 provided on the second substrate 200. The contact sections 201 and 301 may also connect, for example, the input unit 510A provided on the third substrate 300 to the power line 544 and the reference potential line (for example, ground GND). The contact regions 202R and 302R are provided between the pixel array unit 540 and the column signal processing unit 550 in the stacking direction.In other words, the contact areas 202R and 302R are provided, for example, in the region where the column signal processing unit 550 (third substrate 300) and the pixel array unit 540 (second substrate 200) overlap in the stacking direction, or in a nearby region. The contact areas 202R and 302R are located, for example, at the V-direction end of such a region. On the third substrate 300, for example, the contact area 301R is provided at a position overlapping with a part of the column signal processing unit 550, specifically the V-direction end of the column signal processing unit 550. The contact areas 202 and 302 are for connecting, for example, the pixel signals (signals corresponding to the amount of charge generated as a result of photoelectric conversion by a photodiode) output from each of the multiple pixel sharing units 539 of the pixel array unit 540 to the column signal processing unit 550 provided on the third substrate 300. The pixel signals are sent from the second substrate 200 to the third substrate 300.

[0030] Figure 3 is an example of a cross-sectional view of the photodetector 1, as described above. The first substrate 100, the second substrate 200, and the third substrate 300 are electrically connected via wiring layers 100T, 200T, and 300T. For example, the photodetector 1 has an electrical connection section that electrically connects the second substrate 200 and the third substrate 300. Specifically, contact sections 201, 202, 301, and 302 are formed with electrodes made of a conductive material. The conductive material is made of a metallic material such as copper (Cu), aluminum (Al), or gold (Au). The contact regions 201R, 202R, 301R, and 302R electrically connect the second substrate 200 and the third substrate 300 by directly joining wirings formed as electrodes, for example, enabling signal input and / or output between the second substrate 200 and the third substrate 300.

[0031] The electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 can be provided at any desired location. For example, as described in Figure 3 as contact regions 201R, 202R, 301R, and 302R, it may be provided in a region that overlaps with the pixel array portion 540 in the stacking direction. Alternatively, the electrical connection portion may be provided in a region that does not overlap with the pixel array portion 540 in the stacking direction. Specifically, it may be provided in a region that overlaps with the peripheral portion located outside the pixel array portion 540 in the stacking direction.

[0032] The first substrate 100 and the second substrate 200 are provided with, for example, connection holes H1 and H2. The connection holes H1 and H2 penetrate the first substrate 100 and the second substrate 200 (Figure 3). The connection holes H1 and H2 are located outside the pixel array section 540 (or the portion overlapping the pixel array section 540) (Figure 2). For example, connection hole H1 is located outside the pixel array section 540 in the H direction, and connection hole H2 is located outside the pixel array section 540 in the V direction. For example, connection hole H1 reaches the input section 510A provided on the third substrate 300, and connection hole H2 reaches the output section 510B provided on the third substrate 300. The connection holes H1 and H2 may be cavities, or they may contain conductive material in at least part of them. For example, there is a configuration in which bonding wires are connected to electrodes formed as the input section 510A and / or the output section 510B. Alternatively, there is a configuration in which electrodes formed as input section 510A and / or output section 510B are connected to conductive material provided in connection holes H1 and H2. The conductive material provided in connection holes H1 and H2 may be embedded in part or all of connection holes H1 and H2, or the conductive material may be formed on the sides of connection holes H1 and H2.

[0033] In Figure 3, the input section 510A and output section 510B are provided on the third board 300, but the design is not limited to this. For example, the input section 510A and / or output section 510B can be provided on the second board 200 by sending the signals from the third board 300 to the second board 200 via wiring layers 200T and 300T. Similarly, the input section 510A and / or output section 510B can be provided on the first board 100 by sending the signals from the second board 200 to the first board 100 via wiring layers 100T and 200T.

[0034] Figure 4A is an equivalent circuit diagram showing an example of the configuration of a pixel sharing unit 539. The pixel sharing unit 539 includes a plurality of pixels 541 (in Figure 4A, four pixels 541A to 541D are represented), a single pixel circuit 210 connected to these multiple pixels 541, and a vertical signal line 543 connected to the pixel circuit 210. The pixel circuit 210 corresponds to a specific example of a "pixel circuit" as one embodiment of the present disclosure, and is composed of a plurality of transistors (pixel transistors 211). For example, the pixel transistor 211 includes three transistors, specifically an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. As described above, the pixel sharing unit 539 operates the single pixel circuit 210 in a time-division manner, thereby sequentially outputting the pixel signals of each of the four pixels 541 (pixels 541A to 541D) included in the pixel sharing unit 539 to the vertical signal line 543. In a configuration where multiple pixels 541 are connected to a single pixel circuit 210, and the pixel signals of these multiple pixels 541 are output by the single pixel circuit 210 in a time-division manner, this is referred to as "multiple pixels 541 sharing a single pixel circuit 210."

[0035] Pixels 541A to 541D correspond to a specific example of a "sensor pixel" as one embodiment of the present disclosure, and have common components with each other. Hereafter, in order to distinguish the components of pixels 541A to 541D from each other, identification number 1 is added to the end of the code of the component of pixel 541A, identification number 2 to the end of the code of the component of pixel 541B, identification number 3 to the end of the code of the component of pixel 541C, and identification number 4 to the end of the code of the component of pixel 541D. When it is not necessary to distinguish the components of pixels 541A to 541D from each other, the identification number at the end of the code of the component of pixels 541A to 541D is omitted.

[0036] Each pixel 541A to 541D includes, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD electrically connected to the transfer transistor TR. In the photodiode PD (PD1 to PD4), the cathode is electrically connected to the source of the transfer transistor TR, and the anode is electrically connected to a reference potential line (e.g., ground GND). The photodiode PD converts incident light into electricity and generates a charge corresponding to the amount of light received. The transfer transistors TR (transfer transistors TR1 to TR4) are, for example, N-type MOS (Metal Oxide Semiconductor) transistors. The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to a drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 (see Figure 1) connected to one pixel sharing unit 539. The transfer transistor TR transfers the charge generated by the photodiode PD to the floating diffusion FD. The floating diffusion FD (floating diffusion FD1 to FD4) is an n-type diffusion layer region formed in a p-type semiconductor layer. The floating diffusion FD is a charge holding means that temporarily holds the charge transferred from the photodiode PD, and is also a charge-voltage conversion means that generates a voltage corresponding to the amount of charge due to the FD capacitance C of the floating diffusion FD.

[0037] The four floating diffusion FDs (floating diffusion FD1 to FD4) contained in one pixel sharing unit 539 are electrically connected to each other and are also electrically connected to the source of the reset transistor RST. The drain of the reset transistor RST is electrically connected to the power line VDD. The gate of the reset transistor RST is connected to the drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 connected to one pixel sharing unit 539. The gate of the amplification transistor AMP is connected to the floating diffusion FD, the drain of the amplification transistor AMP is connected to the power line VDD, and the source of the amplification transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to the vertical signal line 543, and the gate of the selection transistor SEL is connected to the drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 connected to one pixel sharing unit 539.

[0038] When the transfer transistor TR is turned ON, it transfers the charge from the photodiode PD to the floating diffusion FD. The gate (gate electrode 131) of the transfer transistor TR includes, for example, a so-called vertical electrode and extends from the surface of the semiconductor layer (semiconductor layer 100S in Figure 5) to a depth that reaches the photodiode PD, as shown in Figure 5 below. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned ON, it resets the potential of the floating diffusion FD to the potential of the power line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 210. The amplification transistor AMP generates a signal with a voltage corresponding to the level of charge held in the floating diffusion FD as the pixel signal. The amplification transistor AMP is connected to the vertical signal line 543 via the selection transistor SEL. This amplification transistor AMP forms a source follower in the column signal processing unit 550 together with the load circuit connected to the vertical signal line 543. When the selection transistor SEL is turned ON, the amplification transistor AMP outputs the voltage of the floating diffusion FD to the column signal processing unit 550 via the vertical signal line 543. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, N-type MOS transistors.

[0039] The selection transistor SEL may be provided between the power line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically connected to the row drive signal line 542. The source of the amplification transistor AMP (the output terminal of the pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. Although not shown in the figures, the number of pixels 541 that share one pixel circuit 210 may be other than four. For example, two or eight pixels 541 may share one pixel circuit 210.

[0040] Figure 4B is an equivalent circuit diagram showing another example of the configuration of the pixel sharing unit 539. An FD conversion gain switching transistor FDG may be further provided between the source of the reset transistor RST and the gate of the amplification transistor AMP.

[0041] The four floating diffusion FDs (floating diffusion FD1 to FD4) contained in one pixel sharing unit 539 are electrically connected to each other, as well as to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to a drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 connected to one pixel sharing unit 539.

[0042] The FD conversion gain switching transistor FDG is used to change the gain of charge-to-voltage conversion in a floating diffusion FD. Generally, when shooting in dark places, the pixel signal is small. Based on Q=CV, when performing charge-to-voltage conversion, if the capacitance of the floating diffusion FD (FD capacitance C) is large, the voltage V when converted by the amplification transistor AMP will be small. On the other hand, in bright places, the pixel signal is large, so if the FD capacitance C is not large enough, the floating diffusion FD will not be able to accept the charge of the photodiode PD. Furthermore, the FD capacitance C needs to be large so that the voltage V when converted by the amplification transistor AMP does not become too large (in other words, to keep it small). Considering these points, when the FD conversion gain switching transistor FDG is turned on, the gate capacitance of the FD conversion gain switching transistor FDG increases, so the overall FD capacitance C becomes large. On the other hand, when the FD conversion gain switching transistor FDG is turned off, the overall FD capacitance C becomes small. In this way, by switching the FD conversion gain switching transistor FDG on and off, the FD capacitance C can be varied, and the conversion efficiency can be switched. The FD conversion gain switching transistor FDG is, for example, an N-type MOS transistor.

[0043] [Cross-sectional configuration of the light detection device] Figure 5 schematically shows an example of the cross-sectional configuration of the light detection device 1. Note that Figure 5 is a schematic representation to make the positional relationships of the components easier to understand, and may differ from the actual cross-section. The light detection device 1 is, for example, a back-illuminated light detection device. The light detection device 1 has three substrates, namely a first substrate 100, a second substrate 200, and a third substrate 300, stacked in this order from the light incident side. The light detection device 1 further has an insulating film 181, a color filter 182, and an on-chip lens 401 on the light incident side (back side) of the first substrate 100. The on-chip lens 410 is provided, for example, for each of the multiple pixels 541.

[0044] The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The semiconductor layer 100S has a pair of opposing surfaces (a front surface 100S1 and a back surface 100S2), and the wiring layer 100T is provided on the front surface 100S1 side. The back surface 100S2 of the semiconductor layer 100S serves as a light receiving surface, and an on-chip lens 410 is disposed for each pixel 541 on the back surface 100S2 side. An insulating film 181 and a color filter 182 are provided in this order from the on-chip lens 410 side between the semiconductor layer 100S and the on-chip lens 410. The first substrate 100 is provided with a photodiode PD, a floating diffusion FD, a well contact WC, and a transfer transistor TR. The photodiode PD, the floating diffusion FD, the well contact WC, and the transfer transistor TR are provided for each pixel 541.

[0045] The semiconductor layer 100S is formed of, for example, a silicon substrate. The semiconductor layer 100S has a p-well layer 120, and includes an n-type semiconductor region 121 inside the p-well layer 120. For example, the n-type semiconductor region 121 and the p-well layer 120 constitute a pn-junction type photodiode PD. The p-well layer 120 is a p-type semiconductor region.

[0046] On the front surface 100S1 of the semiconductor layer 100S, a floating diffusion FD and a well contact WC are provided spaced apart from each other.

[0047] The floating diffusion FD is constituted by an n-type semiconductor region 122 provided in the p-well layer 120. The floating diffusion FD is electrically connected from the first substrate 100 to the second substrate 200 via an electrical means. For example, the floating diffusion FD is electrically connected to the gate of an amplification transistor AMP and the source of an FD conversion gain switching transistor FDG via a pad portion 132 and a through electrode 252 penetrating the semiconductor layer 200S constituting the second substrate 200.

[0048] Well contact WC is a region electrically connected to a reference potential line (e.g., ground GND), and is constituted by a p-type semiconductor region 123 provided in a p-well layer 120. The well contact WC is connected from the surface 200S1 side of the semiconductor layer 200S to a semiconductor region 221 provided in the semiconductor layer 200S constituting the second substrate 200 via a pad portion 133 and a connection portion 251. Note that the well contact WC may be connected to a ground potential or a fixed potential via, for example, a through electrode penetrating the semiconductor layer 200S constituting the second substrate 200. Thereby, a reference potential is supplied to the semiconductor layer 100S.

[0049] Transfer transistor TR is provided on the surface 100S1 side of the semiconductor layer 100S. The transfer transistor TR has a gate electrode 131. The gate electrode 131 includes, for example, a horizontal portion 131b facing the surface of the semiconductor layer 100S and a vertical portion 131a provided in the semiconductor layer 100S. The vertical portion 131a extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion 131a is in contact with the horizontal portion 131b, and the other end is provided in an n-type semiconductor region 121. By configuring the transfer transistor TR with such a vertical transistor, transfer failure of pixel signals is less likely to occur, and the readout efficiency of pixel signals can be improved.

[0050] The gate electrode 131 is electrically connected to a drive signal line as described above. The gate electrode 131 and the drive signal line are electrically connected via, for example, a through electrode 253 penetrating the semiconductor layer 200S constituting the second substrate 200. The gate electrode 131 is formed using, for example, impurity-doped polysilicon or the like.

[0051] Note that the transfer transistor TR may be configured by a planar transistor. In this case, the gate electrode 131 is provided on the surface of the semiconductor layer 100S. For example, the side surface of the gate electrode 131 is covered with a sidewall 135 (see, for example, FIG. 7). The sidewall 135 is formed including, for example, silicon nitride (SiN). An insulating film 129 is provided between the semiconductor layer 100S and the gate electrode 131.

[0052] The semiconductor layer 100S is further provided with a pixel separation section 171.

[0053] The pixel separation section 171 separates adjacent pixels 541 from each other and extends between the front surface 100S1 and the back surface 100S2 of the semiconductor layer 100S. The pixel separation section 171 is provided, for example, in a grid pattern to partition adjacent pixels 541 from each other. The pixel separation section 171 separates adjacent pixels 541 from each other electrically and optically. The pixel separation section 171 can be formed, for example, by embedding an insulating film in a groove provided between the front surface 100S1 and the back surface 100S2 of the semiconductor layer 100S. A light-shielding film may be further embedded in the groove with the insulating film in between. The insulating film is formed by including, for example, silicon oxide (SiO). For the light-shielding film, for example, tungsten (W) can be used. The groove constituting the pixel separation section 171 has, for example, an FTI (Full Trench Isolation) structure and penetrates the semiconductor layer 100S. Although not shown in the figures, the pixel separation portion 171 is not limited to an FTI structure that penetrates the semiconductor layer 100S. For example, it may be a DTI (Deep Trench Isolation) structure that does not penetrate the semiconductor layer 100S.

[0054] The insulating film 181 is for insulating and protecting the back surface 100S2 of the semiconductor layer 100S. The insulating film 181 is formed of, for example, silicon oxide (SiO). In addition, the insulating film 181 may be formed using hafnium oxide (HfO), zircon oxide (ZrO), aluminum oxide (AlO), titanium oxide (TiO), or tantalum oxide (TaO), etc. The color filter 182 is an optical filter placed for each pixel 541 that transmits light of a predetermined wavelength from the incident light. The on-chip lens 401 is a lens placed for each pixel 541 that focuses the incident light onto the photodiode PD.

[0055] The wiring layer 100T has, from the semiconductor layer 100S side, an insulating film 129, the gate electrode 131 described above, pad portions 132 and 133, an interlayer insulating layer 141, and a connection portion 251.

[0056] The insulating film 129 is for insulating the surface 100S1 side of the semiconductor layer 100S. The insulating film 129 includes a gate insulating film 129A provided between the semiconductor layer 100S and the gate electrode 131, and a passivation film 129B extending to the surface 100S1 of the semiconductor layer 100S and the surface of the gate electrode 131 (see, for example, Figure 7). The insulating film 129 is formed of a single layer film made of one of the following: silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or a multilayer film made of two or more of these.

[0057] The pad portions 132 and 133 are electrodes connected to semiconductor regions (n-type semiconductor region 122 and p-type semiconductor region 123) provided in the semiconductor layer 100S. Pad portion 132 is connected to the floating diffusion FD. A through electrode 252 is further connected to pad portion 132. Pad portion 133 is connected to the well contact WC. A connection portion 251 is further connected to pad portion 133. The pad portions 132 and 133 are formed using, for example, polysilicon with impurities implanted.

[0058] The interlayer insulating layer 141 is for insulating the gate electrode 131 and pad portions 132, 133, etc., which are located on the surface 100S1 side of the semiconductor layer 100S. The interlayer insulating layer 141 is formed of a single layer film made of one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or a laminated film made of two or more of these.

[0059] The connection portion 251 is one of the connection means for electrically connecting the first substrate 100 and the second substrate 200. Figure 5 shows an example in which the connection portion 251 connects a well contact WC provided in the semiconductor layer 100S and a semiconductor region 221 provided in the semiconductor layer 200S via a pad portion 133 in order to supply a reference potential to the semiconductor layer 100S. The reference potential can be the ground potential. Alternatively, a fixed potential other than the ground potential can be applied as the reference potential. The connection portion 251 can be formed using, for example, polysilicon, polysilicon with impurities implanted, or a conductive metal material. The connection portion 251 is electrically connected to the semiconductor layer 200S via a conductive portion 222 embedded in the semiconductor layer 200S, as will be described in detail later (see, for example, Figure 7).

[0060] The second substrate 200 has a semiconductor layer 200S and a wiring layer 200T. The semiconductor layer 200S has a pair of opposing surfaces (front surface 200S1 and back surface 200S2), and the wiring layer 200T is provided on the front surface 200S1 side of the semiconductor layer 200S. The front surface 200S1 of the semiconductor layer 200S is the element formation surface. In the photodetector 1, the first substrate 100 and the second substrate 200 are stacked such that the front surface 100S1 of the semiconductor layer 100S and the back surface 200S2 of the semiconductor layer 200S face each other. In other words, the first substrate 100 and the second substrate 200 are joined so that the front surface of the first substrate 100 and the back surface of the second substrate 200 face each other. This joining method is called face-to-back joining. The second substrate 200 is provided with a plurality of pixel transistors 211 and through electrodes 252, 253 that constitute a pixel circuit 210. Although specific examples will be described later, the multiple pixel transistors 211 constituting the pixel circuit 210 may be provided separately on the first substrate 100 and the second substrate 200. The through electrodes 252 and 253 each penetrate the semiconductor layer 200S.

[0061] The semiconductor layer 200S is made of, for example, a silicon substrate. The semiconductor layer 200S has a p-well layer 220. The p-well layer 220 is, for example, a p-type semiconductor region. The semiconductor layer 200S is further provided with a plurality of semiconductor regions 221 corresponding to the "impurity diffusion region" of this disclosure.

[0062] The pixel transistor 211 is composed of an n-type semiconductor region 221 and a gate electrode 231. The n-type semiconductor region 221 consists of a source region 221S and a drain region 221D. A channel is formed in the p-well layer 220 below the gate electrode 231 between the source region 221S and the drain region 221D. The gate electrode 231 is formed using, for example, polysilicon with impurities implanted.

[0063] The semiconductor layer 200S is further provided with an insulating region 260.

[0064] The insulating region 260 is a region for providing multiple through electrodes 252, 253 for electrically connecting the first substrate 100 and the second substrate 200, insulated from the semiconductor layer 200S. The insulating region 260 also serves to isolate elements between multiple pixel transistors 211 constituting the pixel circuit 210, according to the layout of the pixel circuit 210. The insulating region 213 has approximately the same thickness as the semiconductor layer 200S and divides the semiconductor layer 200S into multiple sections. The through electrodes 252, 253 are arranged in this insulating region 213. For example, silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON) are embedded in the insulating region 213.

[0065] The wiring layer 200T has an insulating film 229 and an interlayer insulating layer 241 from the semiconductor layer 200S side. Multiple wirings (for example, a first wiring layer W1 and a second wiring layer W2), contact plugs 242, 243, through electrodes 252, 253 and contact portions 201, 202 are provided within the interlayer insulating layer 241. The interlayer insulating layer 241 forms a bonding surface with the third substrate 300, and the contact portions 201, 202 are exposed on the bonding surface.

[0066] The insulating film 229 is for insulating the surface 200S1 side of the semiconductor layer 200S. Similar to the insulating film 129, the insulating film 229 includes a gate insulating film provided between the semiconductor layer 200S and the gate electrode 231, and a passivation film extending across the surface 200S1 of the semiconductor layer 200S and the surface of the gate electrode 231. The insulating film 229 is formed from, for example, a single layer film made of one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or a multilayer film made of two or more of these.

[0067] The first wiring layer W1 and the second wiring layer W2 are for transmitting electrical signals to elements provided on the semiconductor layer 200S. The first wiring layer W1 and the second wiring layer W2 include, for example, the row drive signal line 542 and vertical signal line 543, and a reference potential line (e.g., ground GND) as described above. The first wiring layer W1 and the second wiring layer W2 are formed from, for example, aluminum (Al), copper (Cu), tungsten (W), polysilicon (Poly-Si), etc. The first wiring layer W1 and the second wiring layer W2 are insulated from each other by an interlayer insulating layer 241. Wiring provided on different layers can be connected by vias made of columnar metal, for example, columnar Cu. The interlayer insulating layer 241 is formed from a single layer film made of one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), etc., or from a multilayer film made of two or more of these.

[0068] The contact plugs 242 and 243 are for connecting the first wiring layer W1 to elements provided in the semiconductor layer 200S. Contact plug 242 connects the first wiring layer W1 to the source region 221S or drain region 221D of a pixel transistor 211 provided in the semiconductor layer 200S, or to a contact region 221A provided in the semiconductor layer 200S. Contact plug 243 connects the first wiring layer W1 to the gate electrode 231 of a pixel transistor 211 provided in the semiconductor layer 200S. The contact plugs 242 and 243 have a laminated structure of, for example, a base layer 242B, 243B and a conductive film 242A, 243A. The conductive films 242A, 243A can be made of columnar metal, for example, columnar tungsten (W). The underlying layers 242B and 243B are formed using, for example, titanium (Ti) or titanium nitride (TiN).

[0069] As described above, the through electrodes 252 and 253 are arranged in the insulating region 260 and penetrate the semiconductor layer 200S in the thickness direction. The upper ends of the through electrodes 252 and 253 are connected to the wiring of the wiring layer 200T (for example, the first wiring layer W). The lower end of the through electrode 252 is connected to a pad portion 132 provided on the surface 100S1 side of the semiconductor layer 100S. The lower end of the through electrode 253 is connected to the gate electrode 131 of the transfer transistor TR. The through electrodes 252 and 253 can be made of a columnar metal, for example, columnar tungsten (W).

[0070] As described above, the contact portions 201 and 202 are connected to the contact portions 301 and 302 of the third substrate 300, respectively. Contact portion 201 is connected to the semiconductor region 221 of the semiconductor layer 200S via, for example, a contact plug 242, and transmits a reference potential. Contact portion 202 is used, for example, to transmit signals. The contact portions 201 and 202 are formed using, for example, copper (Cu).

[0071] The third substrate 300 has a semiconductor layer 300S and a wiring layer 300T. The semiconductor layer 300S has a pair of opposing surfaces, and the wiring layer 300T is provided on one of these surfaces (surface 300S1). In the photodetector 1, the second substrate 200 and the third substrate 300 are laminated together by bonding between electrodes, such that the surface 200S1 of the semiconductor layer 200S and the surface of the semiconductor layer 300S face each other. In other words, the second substrate 200 and the third substrate 300 are bonded together such that the surface of the second substrate 200 and the surface of the third substrate 300 face each other. This bonding method is called face-to-face bonding. The second substrate 200 and the third substrate 300 may also be bonded together by a so-called hybrid bonding. Specifically, electrodes (contact portions 201, 202) exposed on the bonding surface of the second substrate 200 and electrodes (contact portions 301, 302) exposed on the bonding surface of the third substrate 300 are bonded together, and the interlayer insulating layer 241 forming the bonding surface of the second substrate 200 and the interlayer insulating layer 341 forming the bonding surface of the third substrate 300 are bonded together. When both contact portions 201, 202 and contact portions 301, 302 are made of copper (Cu), the bonding between contact portions 201, 202 and contact portions 301, 302 is sometimes called a Cu-Cu bond.

[0072] The semiconductor layer 300S is made of, for example, a silicon substrate. Circuits are provided on the surface 300S1 side of the semiconductor layer 300S. Specifically, at least a portion of the following are provided on the surface side of the semiconductor layer 300S: the input unit 510A, the row drive unit 520, the timing control unit 530, the column signal processing unit 550, the image signal processing unit 560, and the output unit 510B.

[0073] The wiring layer 300T has an interlayer insulating layer 341. Multiple wiring layers and contact portions 301 and 302 are provided within the interlayer insulating layer 341. The interlayer insulating layer 341 forms a bonding surface with the second substrate 200, and the contact portions 301 and 302 are exposed on the bonding surface. The contact portions 301 and 302 are electrically connected to at least one of the input portion 510A, row drive portion 520, timing control portion 530, column signal processing portion 550, image signal processing portion 560, and output portion 510B formed on the semiconductor layer 300S, for example.

[0074] The interlayer insulating layer 341 is formed of a single layer film made of one of the following materials: silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or a laminated layer made of two or more of these materials. The contact portions 301 and 302 are formed using, for example, copper (Cu).

[0075] [Specific Configuration of the Photodetector] Figure 6 schematically shows an example of the specific planar configuration of the photodetector 1 shown in Figure 3. Figure 7 schematically shows the specific cross-sectional configuration of the photodetector 1 shown in Figure 3. Figure 8 shows an enlarged view of the connection portion between the connection portion 251B and the semiconductor layer 200S shown in Figure 7.

[0076] The photodetector 1 of this embodiment electrically connects a transistor (e.g., an amplification transistor AMP) provided on a semiconductor layer 100S and a transistor (e.g., an FD conversion gain switching transistor FDG) provided on a semiconductor layer 200S via a connecting portion 251A and a conductive portion 222. The connecting portion 251A is one of the connecting means for electrically connecting the first substrate 100 and the second substrate 200. The connecting portion 251A extends in the stacking direction (Z-axis direction) between the semiconductor layer 100S and the semiconductor layer 200S, and its upper surface 251S is formed either on the same plane as the back surface 200S2 of the semiconductor layer 200S, as shown in Figure 7, or below the back surface 200S2 of the semiconductor layer 200S, as shown in Figure 8. The conductive portion 222 is embedded in the semiconductor layer 200S so as to connect the connecting portion 251A and the semiconductor layer 200S.

[0077] Here, the semiconductor layer 100S corresponds to a specific example of the "first semiconductor layer" as one embodiment of the present disclosure. The semiconductor layer 200S corresponds to a specific example of the "second semiconductor layer" as one embodiment of the present disclosure. The surface 200S1 corresponds to a specific example of the "second surface" as one embodiment of the present disclosure, and the back surface 200S2 corresponds to a specific example of the "first surface" as one embodiment of the present disclosure. The amplification transistor AMP corresponds to a specific example of the "first element" as one embodiment of the present disclosure, and the FD conversion gain switching transistor FDG corresponds to a specific example of the "second element" as one embodiment of the present disclosure. The connection part 251A corresponds to a specific example of the "connection part" as one embodiment of the present disclosure, and the conductive part 222 corresponds to a specific example of the "conductive part" as one embodiment of the present disclosure.

[0078] In the photodetector 1 shown in Figures 6 and 7, for example, two pixels 541 arranged in a 2x1 grid share a single pixel circuit 210, and the multiple pixel transistors 211 constituting the pixel circuit 210 are provided separately on the first substrate 100 and the second substrate 200. For example, as shown in Figure 6, the amplification transistor AMP, the selection transistor SEL, and the reset transistor RST are provided on the first substrate 100, and the FD conversion gain switching transistor FDG is provided on the second substrate 200.

[0079] In the photodetector 1, the gate electrode 131 of the amplification transistor AMP is electrically connected to the source region 221S of the FD conversion gain switching transistor FDG via the connection portion 251A and the conductive portion 222. The drain region 221D of the FD conversion gain switching transistor FDG is electrically connected to the source region 122S of the reset transistor RST via the connection portion 251B and the conductive portion 222. The gate electrode 134 of the reset transistor RST is connected to the drive signal line provided on the first wiring layer W1 via the connection portion 251A, the conductive portion 222 and the contact plug 243. The drain region 122D of the reset transistor RST is connected to the power line VDD provided on the first wiring layer W1 via the connection portion 251C, the conductive portion 222 and the contact plug 242.

[0080] The connection portions 251A, 251B, and 251C are one of the connection means for electrically connecting elements provided separately on the first substrate 100 and the second substrate 200 from the back surface 200S2 side of the semiconductor layer 200S. As described above, the connection portions 251A, 251B, and 251C can be formed using polysilicon, polysilicon with impurities implanted, or a conductive metal material. Examples of conductive metal materials for forming the connection portions 251A, 251B, and 251C include tungsten (W), cobalt (Co), or copper (Cu).

[0081] The conductive portion 222 is for electrically connecting the connection portions 251A, 251B, and 251C to the semiconductor layer 200S. The conductive portion 222 is formed, for example, from single-crystal silicon epitaxially grown from the side of an opening 200H formed in the semiconductor layer 200S, and has the same polarity as the surrounding semiconductor region 221 (see, for example, Figures 11D and 11E). The conductive portion 222 may also be formed from polysilicon having the same polarity as the surrounding semiconductor region 221, or from a conductive metal material. Examples of conductive metal materials for forming the conductive portion 222 include tungsten (W), titanium (Ti), or tungsten nitride (TiN).

[0082] By electrically connecting the connection portions 251A, 251B, and 251C to the semiconductor layer 200S via the conductive portion 222 made of the above material, the connection between the connection portions 251A, 251B, and 251C and the semiconductor region 221 provided in the semiconductor layer 200S is made less resistive, and connection yield is ensured.

[0083] In Figure 6, an example is shown in which the pixel circuit 210 is configured to include four pixel transistors 211: an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG. However, the configuration is not limited to this example.

[0084] This technology can also be applied to a pixel circuit 210 comprising three pixel circuits 210, such as the one shown in Figure 4A: an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. In this case, for example, as shown in Figure 9, the amplification transistor AMP is provided on the first substrate 100, the reset transistor RST is provided on the second substrate 200, and the gate electrode 131 of the amplification transistor AMP is electrically connected to the source region 221S of the reset transistor RST via the connection portion 251A and the conductive portion 222.

[0085] Furthermore, Figure 6 shows an example in which the amplification transistor AMP, the selection transistor SEL, and the reset transistor RST are provided on the first substrate 100, and the FD conversion gain switching transistor FDG is provided on the second substrate 200, but the invention is not limited to this.

[0086] For example, as shown in Figure 10, the amplification transistor AMP may be provided on the first substrate 100, and the reset transistor RST and reset transistor RST may be provided on the second substrate 200. The selection transistor SEL may be provided on either the first substrate 100 or the second substrate 200.

[0087] In either case, the elements provided separately on the first substrate 100 and the second substrate 200 are electrically connected from the back surface 200S2 side of the semiconductor layer 200S via connecting portions 251 (connecting portions 251A, 251B, 251C) that extend in the stacking direction (Z-axis direction) between the semiconductor layer 100S and the semiconductor layer 200S, and conductive portions 222. In other words, the elements provided separately on the first substrate 100 and the second substrate 200 are electrically connected without the need for a wiring layer (for example, a first wiring layer W1) provided on the front surface 200S1 side of the semiconductor layer 200S. This reduces the wiring capacitance connected to the FD node.

[0088] [Manufacturing Method for Photodetector] Figures 11A to 11H show an example of a manufacturing method for the photodetector 1.

[0089] First, pixel transistors 211 such as amplification transistors AMP are formed on the surface 100S1 side of the semiconductor layer 100S, and then a passivation film 129B and an interlayer insulating layer 141 are deposited in sequence. Next, the interlayer insulating layer 141 and the passivation film 129B are processed by photolithography and etching (e.g., dry etching) to form contact holes. Subsequently, a conductive film is embedded in the contact holes by, for example, chemical vapor deposition (CVD), and then the conductive film deposited on the interlayer insulating layer 141 is removed and the surface is flattened by, for example, chemical mechanical polishing (CMP). As a result, a connection portion 251A is formed as shown in Figure 11A.

[0090] Next, as shown in Figure 11B, after bonding the semiconductor layers 200S, the semiconductor layers 200S are thinned to a predetermined thickness, for example, by CMP.

[0091] Next, as shown in Figure 11C, impurities are diffused into the semiconductor layer 200S by means of ion implantation, for example, to form semiconductor regions 221 such as the source region 221S, the drain region 221D, and a contact region 221A (not shown). Then, as shown in Figure 11C, the gate insulating film (insulating film 229), the gate electrode 231, and the side wall 232 are formed. This forms the FD conversion gain switching transistor FDG.

[0092] Next, as shown in Figure 11D, a protective film 601 is formed to cover the semiconductor layer 200S and the FD conversion gain switching transistor FDG. Then, the protective film 601 and the semiconductor layer 200S are patterned by photolithography and etching to form an opening 200H.

[0093] Next, as shown in Figure 11E, single-crystal silicon 222X is grown by epitaxial growth to fill the opening 200H from the side surface of the semiconductor layer 200S.

[0094] Next, as shown in Figure 11F, after removing the protective film 601, impurities are diffused into the single-crystal silicon 222X, semiconductor layer 200S, and gate electrode 231 by means of ion implantation, for example, to activate them. This forms the conductive portion 222.

[0095] Next, as shown in Figure 11G, an interlayer insulating layer 241 is formed, for example by CVD, to fill the gaps between the separated semiconductor layers 200S.

[0096] Next, the interlayer insulating layer 241 is processed by photolithography and etching (e.g., dry etching) to form contact holes. Then, a conductive film is embedded in the contact holes by, for example, CVD, and the conductive film formed on the interlayer insulating layer 241 is removed and the surface is planarized by, for example, CMP. As a result, contact plugs 242 and 243 are formed as shown in Figure 11H.

[0097] Subsequently, the first wiring layer W1, the second wiring layer W2, and contact portions 201, 202, etc., are formed inside the interlayer insulating layer 241 by the BEOL process. Then, the contact portions 201, 202 are exposed on the surface of the interlayer insulating layer 241 and bonded to a separately prepared third substrate. With these steps completed, the photodetector 1 shown in Figure 5 is completed.

[0098] [Function and Effects] In the photodetector 1 of this embodiment, for example, a transistor provided in semiconductor layer 100S and a transistor provided in semiconductor layer 200S are electrically connected via a connecting portion 251 and a conductive portion 222. The connecting portion 251 extends in the stacking direction between semiconductor layer 100S and semiconductor layer 200S, and its upper surface 251S is formed either on the same plane as the back surface 200S2 of semiconductor layer 200S, as shown in Figure 7, or below the back surface 200S2 of semiconductor layer 200S, as shown in Figure 8. The conductive portion 222 is embedded in semiconductor layer 200S to electrically connect the connecting portion 251 and semiconductor layer 200S. This reduces the connection resistance between the connecting portion 251 and, for example, the transistor provided in semiconductor layer 100S, while ensuring connection yield. This will be explained below.

[0099] To achieve low noise in imaging devices, one solution is to increase the conversion efficiency (CG). To increase conversion efficiency, it is important to reduce the capacity of the FD node.

[0100] When multiple pixel transistors are formed on a silicon substrate on which photodetectors (PDs) are provided, there are wires connecting the pixel transistors, and the capacitance of these wires, including those connected to the FD node, also affects the conversion efficiency. Therefore, in order to reduce the capacitance of the wires connected to the FD node, a structure that minimizes the wiring distance is desirable.

[0101] Incidentally, in imaging devices having a so-called three-dimensional structure, for example, as shown in Figure 12, structures have been considered that attempt to reduce wiring capacitance by shortening the wiring distance by providing an amplification transistor AMP on the first substrate side and arranging an FD conversion gain switching transistor FDG (or reset transistor RST) above the amplification transistor AMP. However, in the structure shown in Figure 12, capacitance is unavoidable between the contact plug 242, which electrically connects the gate electrode 134 of the amplification transistor AMP and the source region 221S of the FD conversion gain switching transistor FDG, and the gate electrode 231, making further reduction of capacitance difficult.

[0102] On the other hand, as mentioned above, a structure has been proposed in which a first semiconductor substrate and a second semiconductor substrate, which are stacked on top of each other, are electrically connected to the back surfaces of the first and second semiconductor substrates by a connection portion that penetrates an insulating layer provided between them. However, in this structure, the high connection resistance between the connection portion and the second semiconductor substrate, and the yield of the connection portion have been problematic.

[0103] In contrast, in this embodiment, as described above, for example, a transistor provided in semiconductor layer 100S and a transistor provided in semiconductor layer 200S are electrically connected via a connecting portion 251 and a conductive portion 222. The conductive portion 222 electrically connects semiconductor layer 200S and the connecting portion 251 which extends in the stacking direction between semiconductor layer 100S and semiconductor layer 200S, and is embedded in semiconductor layer 200S. This makes it possible to reduce the connection resistance between the connecting portion 251 and, for example, the transistor provided in semiconductor layer 100S, while ensuring connection yield.

[0104] As a result of the above, the reliability of the light detection device 1 in this embodiment can be improved.

[0105] Modifications 1 to 6 of this disclosure, as well as application examples and application examples, will be described below. In the following modifications, components common to the above embodiments will be denoted by the same reference numerals.

[0106] <2. Modifications> (2-1. Modification 1) Figure 13 schematically shows an example of the cross-sectional configuration of the photodetector 1A according to Modification 1 of the present disclosure. Figure 14 shows an enlarged view of the connection portion between the connection portion 251B and the semiconductor layer 200S shown in Figure 13.

[0107] In the above embodiment, for example, an amplification transistor AMP is provided on the first substrate 100, and its gate electrode 134 is electrically connected to the source region 211S of an FD conversion gain switching transistor FDG or a reset transistor RST provided on the second substrate 200 via a connection portion 251A and a conductive portion 222. However, the embodiment is not limited to this.

[0108] In this modified photodetector 1A, the amplification transistor AMP is provided on the second substrate 200, and its gate electrode 231 is electrically connected to the floating diffusion FD provided on the first substrate 100 via a connecting portion 251B and a conductive portion 222. In this modified example, a notch 232X is provided in the side wall 232 covering the side surface 231S3 of the gate electrode 231, exposing a part of the side surface 231S3 of the gate electrode 231, and the conductive portion 222 and the gate electrode 231 are connected via this notch 232X. Except for this point, the photodetector 1A has substantially the same configuration as the photodetector 1 of the above embodiment.

[0109] Thus, in addition to connecting the gate electrode 134, source region 122S, or drain region 122D of a transistor provided on the first substrate 100 with the source region 122S or drain region 122D of a transistor provided on the second substrate 200, or a semiconductor region 221 provided on a semiconductor layer 200S such as a contact region 211A connected to a power line VDD, etc., this technology can also be applied to connecting a semiconductor region provided on the first substrate 100 (for example, an n-type semiconductor region 122) with the gate electrode 231 of a transistor provided on the second substrate 200.

[0110] Even with this configuration, the modified photodetector 1A can achieve the same effects as the photodetector 1 of the above embodiment.

[0111] (2-2. Modification 2) Figure 15 schematically shows an example of the cross-sectional configuration of the photodetector 1B according to Modification 2 of the present disclosure.

[0112] In the above embodiment, for example, as shown in Figure 7, an example is shown in which the connection part 251A or the connection part 251B and the contact plug 242 are electrically connected via a single conductive part 222, but the embodiment is not limited to this.

[0113] In this modified example, the photodetector 1B has a connection portion 251A or 251B and a contact plug 242 connected to different conductive portions 222. Specifically, the connection portion 251A connected to the gate electrode 134 of the reset transistor RST is connected to the conductive portion 222A, and the contact plug 242 connected to the drive signal line is connected to the conductive portion 222B. The gate electrode 134 of the reset transistor RST and the drive signal line are connected to each other via the connection portion 251A, the conductive portion 222A, the contact region 221A, the conductive portion 222B, and the contact plug 242. Furthermore, the connection portion 251B connected to the drain region 122D of the reset transistor RST is connected to the conductive portion 222C, and the contact plug 242 connected to the power line VDD is connected to the conductive portion 222G, thereby connecting the drain region 122D of the reset transistor RST and the power line VDD to each other via the connection portion 251B, the conductive portion 222C, the contact region 221A, the conductive portion 222D, and the contact plug 242. Except for this point, the photodetector 1B has substantially the same configuration as the photodetector 1 of the above embodiment.

[0114] Even with this configuration, the modified photodetector 1B can obtain the same effects as the photodetector 1 of the above embodiment.

[0115] (2-3. Modification 3) Figure 16 schematically shows an example of the cross-sectional configuration of the photodetector 1C according to Modification 3 of the present disclosure. Figure 17 schematically shows another example of the cross-sectional configuration of the photodetector 1C according to Modification 3 of the present disclosure.

[0116] In the above embodiment, an example was shown in which semiconductor regions 122 and 221 having the same polarity are electrically connected via a connecting portion 251 and a conductive portion 222, but the invention is not limited to this. Furthermore, this technology can be applied to electrical connections between pixel transistors 211 provided separately on the first substrate 100 and the second substrate 200, as well as to connections other than those between the floating diffusion FD provided on the first substrate 100 and the pixel transistors 211 provided on the second substrate 200.

[0117] This technology can be applied, for example, to the connections between transistors and wiring that make up so-called logic circuits, such as inverter circuits, NAND circuits, NOR circuits, SRAM circuits, and analog circuits.

[0118] Figure 16 shows the connection structure of the Vin portion, in which transistors with different polarities are provided on the first substrate 100 and the second substrate 200, and they are electrically connected via a connection portion 251A and a conductive portion 222E having the same polarity as the transistor provided on the second substrate 200. Specifically, the transistor provided on the first substrate 100 is an N-type MOS transistor, the transistor provided on the second substrate 200 is a P-type MOS transistor, and the conductive portion 222E contains p-type impurities.

[0119] Figure 17 shows the connection structure to the Vout section, power line VDD, and ground GND. Transistors with different polarities are provided on the first substrate 100 and the second substrate 200, and they are electrically connected via a connection part 251B or connection part 251C and a conductive part 222E having the same polarity as the transistor provided on the second substrate 200. Specifically, as in Figure 16, the transistor provided on the first substrate 100 is an N-type MOS transistor, the transistor provided on the second substrate 200 is a P-type MOS transistor, and the conductive part 222E contains p-type impurities, similar to the source region 221S and drain region 221D of the transistor provided on the second substrate 200.

[0120] In Figures 16 and 17, an example is shown where the transistor provided on the first substrate 100 is an N-type MOS transistor and the transistor provided on the second substrate 200 is a P-type MOS transistor, but the invention is not limited to this. The transistor provided on the first substrate 100 may be a P-type MOS transistor, and the transistor provided on the second substrate 200 may be an N-type MOS transistor. In that case, the conductive portion 222E contains n-type impurities.

[0121] Even with this configuration, the modified photodetector 1C can achieve the same effects as the photodetector 1 of the above embodiment.

[0122] (2-4. Modification 4) Figure 18 schematically shows an example of the cross-sectional configuration of the photodetector 2 according to Modification 4 of the present disclosure.

[0123] In the above embodiment, an example was shown in which the conductive portion 222, which electrically connects the connecting portion 251 to, for example, the semiconductor region 221 of the semiconductor layer 200S, is provided so as to embed the opening 200H formed in the semiconductor layer 200S, but the embodiment is not limited to this.

[0124] In this modified example, the photodetector 2 has a conductive portion 223 that electrically connects the connection portion 251 to, for example, the semiconductor region 221 of the semiconductor layer 200S, formed along the outer surface of the semiconductor layer 200S, with a portion of the conductive portion 223 further extending onto the surface 200S1 of the semiconductor layer 200S. Except for this point, the photodetector 2 has substantially the same configuration as the photodetector 1 of the above embodiment.

[0125] In the photodetector 2, the insulating film 229 includes a gate insulating film 229A provided between the semiconductor layer 200S and the gate electrode 231, and a protective film 229B extending to the surface 200S1 of the semiconductor layer 200S and the surface of the gate electrode 231.

[0126] In the photodetector 2, for example, as shown in Figure 18, an opening 229H is provided in the protective film 229B on and around the connection portion 251A to be connected, exposing the semiconductor layer 200S. By selectively epitaxially growing single-crystal silicon on the outer peripheral side and surface 200S1 of the exposed semiconductor layer 200S, a self-aligned conductive portion 223 can be formed.

[0127] Note that while Figure 18 shows an example where the side surface of the conductive portion 223 is in contact with the side surface of the protective film 229B, the design is not limited to this. The conductive portion 223 may, for example, have a portion overlapping the protective film 229B, as shown in Figure 19. Alternatively, the side wall 232 near the connection portion 251A to be connected may be extended in the direction of the connection portion 251A, and the extended side wall 232 may be processed to form the conductive portion 223 in a self-aligned manner. In that case, for example, as shown in Figure 20, the side surface of the conductive portion 223 is in contact with the side surface of the side wall 232, and the protective film 229B is formed on the conductive portion 223.

[0128] Even with this configuration, the photodetector 2 of this modified example can obtain the same effects as the photodetector 1 of the above embodiment.

[0129] Furthermore, in this modified photodetector 2, the conductive portion 223 is formed along the side surface of the outer periphery of the semiconductor layer 200S. Compared to the photodetector 1 of the above embodiment, in which an opening 200H is formed in the semiconductor layer 200S and the conductive portion 222 is provided to fill the opening 200H, the process difficulty can be reduced. Therefore, it is possible to ensure a higher connection yield compared to the photodetector 1 of the above embodiment.

[0130] (2-5. Modification 5) Figure 21 schematically shows an example of the cross-sectional configuration of the photodetector 3 according to Modification 5 of the present disclosure. Figure 22 schematically shows another example of the cross-sectional configuration of the photodetector 3 according to Modification 5 of the present disclosure.

[0131] In the above embodiment, the conductive portion 222 that electrically connects the connecting portion 251 to, for example, the semiconductor region 221 of the semiconductor layer 200S is shown to be formed using single-crystal silicon, polysilicon having the same polarity as the surrounding semiconductor region 221, or a conductive metal material, but the embodiment is not limited to this.

[0132] In this modified example, the photodetector 3 uses a silicided semiconductor layer 200S as the conductive portion 224. Furthermore, in the photodetector 3, at least a portion of the silicon-containing components, including the conductive portion 224, is silicided. For example, the pixel transistor 211 connected to the connection portion 251 by the conductive portion 224 has a gate electrode 231 with a laminated structure of a polysilicon film 231A and a silicide layer 231B, and the source region (source region 271S) and drain region (drain region 271D) are silicided. Except for this point, the photodetector 3 has substantially the same configuration as the photodetector 1 of the above embodiment.

[0133] Furthermore, the conductive portion 224 may be formed by silicideizing a portion of the connecting portion 251A made of polysilicon that protrudes from the semiconductor layer 200S, as shown in Figure 22, for example.

[0134] The photodetector 3 can be manufactured, for example, as follows. Figures 23A to 23F show an example of a method for manufacturing the photodetector 1.

[0135] First, in the same manner as in the above embodiment, a plurality (in this case, two) of pixel transistors 211 are formed on the surface 100S1 side of the semiconductor layer 100S, as shown in Figure 23A.

[0136] Next, a protective film 229B is formed on the interlayer insulating layer 141 so as to cover the two pixel transistors 211. Subsequently, as shown in Figure 23B, the protective film 229B formed on the pixel transistors 211 that are electrically connected to the connection portion 251A is selectively removed, for example, by photolithography and dry etching.

[0137] Next, as shown in Figure 23C, a high-melting-point metal film 272 and a titanium nitride (TiN) film 273 are sequentially deposited to cover the two pixel transistors 211, for example by sputtering. The high-melting-point metal film 272 includes, for example, tungsten (W), molybdenum (Mo), tantalum (Ta), titanium (Ti), cobalt (Co), nickel (Ni), platinum (Pt), or gold (Au).

[0138] Next, a heat treatment is performed. As a result, as shown in Figure 23D, a portion of the gate electrode 231 of the pixel transistor 211, on which the high-melting-point metal film 272 is directly laminated, as well as the silicon constituting the source region 221S and drain region 221D, are alloyed with the metal material, forming a silicide layer 231B and the silicided source region 271S and drain region 271D.

[0139] Next, as shown in Figure 23E, the TiN film 273 and the unreacted high-melting-point metal film 272 are removed, for example, by washing with sulfuric acid and hydrogen peroxide.

[0140] Next, as shown in Figure 23F, an interlayer insulating layer 241 is formed to fill the gaps between the separated semiconductor layers 200S, for example by CVD. Then, the interlayer insulating layer 241 is processed by photolithography and etching (for example, dry etching) to form contact holes. After that, a conductive film is embedded in the contact holes, for example by CVD, and the conductive film formed on the interlayer insulating layer 241 is removed and the surface is planarized, for example by CMP. As a result, a contact plug 242 is formed, as shown in Figure 23F.

[0141] Subsequently, the BEOL process forms the first wiring layer W1, etc., inside the interlayer insulating layer 241. With the above steps, the photodetector 3 shown in Figure 21 is completed.

[0142] Thus, in this modified photodetector 3, the silicided semiconductor layer 200S is used as the conductive part 224, making it possible to further reduce the connection resistance between the connection part 251 and, for example, the transistor provided on the semiconductor layer 100S, compared to the photodetector 1 of the above embodiment. Also, similar to the modified example 4, the conductive part 224 can be formed by self-alignment, making it possible to secure a higher connection yield compared to the photodetector 1 of the above embodiment.

[0143] Furthermore, in this modified photodetector 3, the surface of the gate electrode 231 and the source region 221S and drain region 231D are silicided (silicide layer 231B, source region 271S, drain region 271D), which reduces the series resistance with other pixel transistors 211. Therefore, it is possible to improve the characteristics.

[0144] (2-6. Modification 6) Figure 24 schematically shows an example of the cross-sectional configuration of the photodetector 4 according to Modification 6 of the present disclosure.

[0145] In this modified photodetector 4, the conductive portion 225A, which electrically connects the connection portion 251 to, for example, the semiconductor region 221 of the semiconductor layer 200S, is formed using, for example, polysilicon having the same polarity as the surrounding semiconductor region 221, or a conductive metal material, and its upper surface 225AS is formed at a lower position than the upper surface 231S1 of the gate electrode 231. The upper surface 225AS of the conductive portion 225A can be controlled by etching after the deposition of the conductive film (for example, a polysilicon film or a conductive metal film) constituting the conductive portion 225A.

[0146] Thus, in this modified photodetector 4, the upper surface 2225AS of the conductive portion 225A, which electrically connects the connection portion 251 to, for example, the semiconductor region 221 of the semiconductor layer 200S, is formed at a lower position than the upper surface 231S1 of the gate electrode 231. As a result, compared to the case where, for example, the upper surface 2225AS of the conductive portion 225A is formed at the same height as the upper surface 231S1 of the gate electrode 231, the conversion efficiency can be improved and the wiring capacitance can be reduced.

[0147] Specifically, for example, if the bottom surface 231S2 of the gate electrode 231 is taken as the reference plane and its top surface 231S1 is set to 1, then by forming the top surface 2225AS of the conductive portion 225A at a position 95% from the top surface 231S1, the wiring capacitance can be reduced by 14%. This improves the conversion efficiency by approximately 5% and reduces random noise by approximately 4%. This improvement in conversion efficiency and reduction of random noise can be further improved by forming the top surface 2225AS of the conductive portion 225A at a position lower than 95% from the top surface 231S1 of the gate electrode 231.

[0148] In Figure 24, an example is shown in which the conductive portion 225B, which electrically connects the connection portion 251A, for example, connected to the gate electrode 134 of the transistor provided on the first substrate 100, to the contact plug 242 connected to the first wiring layer W1, has a configuration similar to that of the conductive portion 225A, but the invention is not limited to this example.

[0149] For example, as shown in Figure 25, the conductive portion 225B may be extended through to the gate electrode 134 of the transistor provided on the first substrate 100, thereby replacing the connection portion 251A with the conductive portion 225B. This reduces the connection resistance between the gate electrode 134 of the transistor provided on the first substrate 100 and the first wiring layer W1.

[0150] Furthermore, unlike the conductive portion 225A, the conductive portion 225B does not affect the wiring capacitance, so its upper surface 225BS may be at the same height as the upper surface 231S1 of the gate electrode 231, for example, as shown in Figure 26. In other words, the positions of the upper surface 225AS of the conductive portion 225A and the upper surface 225BS of the conductive portion 225B may be different from each other.

[0151] Furthermore, although Figure 24 shows an example in which the connection portion 251A is replaced with the conductive portion 225B, the method is not limited to this, and for example, as shown in Figure 27, the contact plug 242 may also be replaced with the conductive portion 225B. In either case, the connection resistance between the gate electrode 134 of the transistor provided on the first substrate 100 and the first wiring layer W1 can be reduced.

[0152] Furthermore, as shown in Figure 28, the connection portion 251A and the contact plug 242 may be replaced with the conductive portion 225B. In other words, the gate electrode 134 of the transistor provided on the first substrate 100 and the first wiring layer W1 may be electrically connected using only the conductive portion 225. In that case, it is also preferable to replace the connection portion 251A, which electrically connects the gate electrode 134 of the transistor provided on the first substrate 100 and, for example, the source region 221S of the transistor provided on the second substrate 200, with the conductive portion 225A. This reduces the number of steps compared to the manufacturing method of the above embodiment.

[0153] <3. Application Examples> (Application Example 1) The above-mentioned light detection device 1 can be applied to any type of electronic device equipped with an imaging function, such as camera systems like digital still cameras and video cameras, or mobile phones with imaging capabilities. Figure 29 shows a schematic configuration of the electronic device 1000.

[0154] The electronic device 1000 includes, for example, a lens group 1001, a light detection device 1, a DSP (Digital Signal Processor) circuit 1002, a frame memory 1003, a display unit 1004, a recording unit 1005, an operation unit 1006, and a power supply unit 1007, all of which are interconnected via a bus line 1008.

[0155] The lens group 1001 captures incident light (image light) from the subject and forms an image on the imaging surface of the light detection device 1. The light detection device 1 converts the amount of incident light formed on the imaging surface by the lens group 1001 into an electrical signal on a pixel-by-pixel basis and supplies it as a pixel signal to the DSP circuit 1002.

[0156] The DSP circuit 1002 is a signal processing circuit that processes signals supplied from the light detection device 1. The DSP circuit 1002 outputs image data obtained by processing the signals from the light detection device 1. The frame memory 1003 temporarily holds the image data processed by the DSP circuit 1002 in frame units.

[0157] The display unit 1004 consists of a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and records the video or still image data captured by the light detection device 1 onto a recording medium such as a semiconductor memory or a hard disk.

[0158] The operation unit 1006 outputs operation signals for various functions possessed by the electronic device 1000 in accordance with user operations. The power supply unit 1007 appropriately supplies various power sources to the DSP circuit 1002, frame memory 1003, display unit 1004, recording unit 1005, and operation unit 1006.

[0159] (Application Example 2) Figure 30A schematically shows an example of the overall configuration of a photodetection system 2000 equipped with a photodetector 1. Figure 30B shows an example of the circuit configuration of the photodetection system 2000. The photodetection system 2000 includes a light-emitting device 2001 as a light source that emits infrared light L2, and a photodetector 2002 as a light-receiving unit having a photoelectric conversion element. The photodetector 1 described above can be used as the photodetector 2002. The photodetection system 2000 may further include a system control unit 2003, a light source drive unit 2004, a sensor control unit 2005, a light source side optical system 2006, and a camera side optical system 2007.

[0160] The photodetector 2002 can detect light L1 and light L2. Light L1 is light reflected from ambient light from the outside by the subject (object to be measured) 2100 (Figure 30A). Light L2 is light that has been emitted by the light-emitting device 2001 and then reflected by the subject 2100. Light L1 is, for example, visible light, and light L2 is, for example, infrared light. Light L1 is detectable in the photoelectric conversion unit of the photodetector 2002, and light L2 is detectable in the photoelectric conversion region of the photodetector 2002. Image information of the subject 2100 can be obtained from light L1, and distance information between the subject 2100 and the photodetector system 2000 can be obtained from light L2. The photodetector system 2000 can be mounted on, for example, electronic devices such as smartphones or mobile devices such as cars. The light-emitting device 2001 can be, for example, a semiconductor laser, a surface-emitting semiconductor laser, or a vertical-cavity surface-emitting laser (VCSEL). As a detection method for the light L2 emitted from the light-emitting device 2001 by the photodetector 2002, for example, the iTOF method can be used, but is not limited to this. In the iTOF method, the photoelectric conversion unit can measure the distance to the subject 2100 by, for example, the time-of-flight (TOF). As a detection method for the light L2 emitted from the light-emitting device 2001 by the photodetector 2002, for example, the structured light method or the stereo vision method can also be used. For example, in the structured light method, the distance between the photodetector 2000 and the subject 2100 can be measured by projecting a predetermined pattern of light onto the subject 2100 and analyzing the degree of distortion of the pattern. In the stereo vision method, for example, the distance between the photodetector 2000 and the subject can be measured by using two or more cameras to acquire two or more images of the subject 2100 from two or more different viewpoints. Furthermore, the light-emitting device 2001 and the light-detecting device 2002 can be synchronously controlled by the system control unit 2003.

[0161] <4. Application Examples> Figure 31A is a diagram illustrating an example of the appearance of the information processing system 3001 of the present disclosure. As shown in Figure 31A, the information processing system 3001 according to this embodiment is configured as a head-mounted display (HMD). Referring to Figure 31A, an example of the appearance of the head-mounted display (HMD) of this embodiment will be described.

[0162] In this example, the HMD 3001 consists of an output mechanism 3011 and a mounting mechanism 3012. The mounting mechanism 3012 includes a mounting band 3013 that wraps around the head when worn by the user, securing the device. However, it does not have to wrap around the head as long as it is secured to the head.

[0163] The output mechanism 3011 includes a housing 3014 shaped to cover the left and right eyes when the HMD 3001 is worn by the user, and has a display panel inside that faces the eyes when worn. The housing 3014 may also be further equipped with a lens that is positioned between the display panel (display unit 4005 (Figure 32)) and the user's eyes when the HMD 3001 is worn, to widen the user's field of view. Stereo images corresponding to the parallax between the two eyes may be displayed in each of the regions formed by dividing the display panel into left and right sections, and stereoscopic vision may be realized by such a display.

[0164] The HMD 3001 may also be equipped with speakers or earphones positioned to correspond to the user's ears when worn. In this example, the HMD 3001 has a camera 3015 on the front of the housing 3014, and captures the surrounding real space as a video in a field of view corresponding to the user's line of sight.

[0165] Camera 3015 includes, for example, an image sensor such as a CCD (Charge Coupled Device) sensor or a CMOS (Complementary Metal Oxide Semiconductor) sensor, a light detection device such as a distance measuring sensor, and an optical system such as an imaging lens. For example, in Figure 31A, it is configured as a stereo camera that images the space in front from left and right viewpoints corresponding to the left and right eyes of the user. However, camera 3015 is not limited to this and may be a monocular camera or a multi-camera with three or more lenses. Furthermore, it may be a combination of multiple types of sensors. In hand tracking applications, camera 3015 may be configured to image the space below the information processing system. In eye tracking and face tracking applications, camera 3015 may be configured to image the user's eyes or face.

[0166] The HMD3001 also includes a sensor 4008 (Figure 32). The sensor may include at least one of various sensors for determining the movement, attitude, position, etc., of the HMD3001, such as an accelerometer, gyroscope, angular velocity sensor, and geomagnetic sensor.

[0167] The HMD3001 may be connected to other processing devices via wireless communication, or it may be connected via a wired connection such as USB (Universal Serial Bus).

[0168] In this case, the HMD 3001 may be configured to run online applications such as games that can be played by multiple users via a network. In this case, the HMD 3001 performs predetermined processing on the image captured by the camera 3015, generates a display image within the field of view of the camera 3015, and displays it.

[0169] The content of the displayed image is not particularly limited and can vary depending on the functions the user requests from the system and the content of the application launched.

[0170] For example, the HMD 3001 may perform some processing on the image captured by the camera 3015, or superimpose virtual objects that interact with images of real objects. Alternatively, the HMD 3001 may render a virtual world in a field of view corresponding to the user's field of view, based on the captured image or measurements from motion sensors included in the sensor group of the HMD 3001.

[0171] Representative examples of these embodiments include virtual reality (VR), augmented reality (AR), and mixed reality (MR). Furthermore, by using the image captured by the camera 3015 as the display image, a see-through form (VST: VideoSeeThrough) in which the real world can be seen through the screen of the HMD 3001 may be realized.

[0172] Figure 31B is a diagram illustrating an example of the external appearance of the information processing system 3101 of the present disclosure. As shown in Figure 31B, the information processing system 3101 according to this embodiment is configured as a glasses-type HMD.

[0173] The HMD body 3111 is worn on the user's head. The HMD body 3111 has a front section 3112, a right temple section 3113 provided on the right side of the front section 3112, a left temple section 3114 provided on the left side of the front section 3112, and a glasses section 3115 attached to the bottom of the front section 3112. In Figure 31B, the glasses are a single unit, but they may have two separate glasses for each eye, or they may be configured to cover only one eye.

[0174] The display unit 3103 is a see-through type display unit and is provided on the surface of the glass unit 3115. The display unit 3103 performs AR display of virtual objects in accordance with the control of the processing circuit 4001. The display unit 3103 may also be a non-see-through type display unit. In this case, AR display is performed by displaying an image on the display unit 3103 in which the virtual object is superimposed on the image currently being captured by the camera 3104.

[0175] Camera 3104 includes, for example, an image sensor such as a CCD (Charge Coupled Device) sensor or a CMOS (Complemented Metal Oxide Semiconductor) sensor, a light detection device such as a distance measuring sensor, and an optical system such as an imaging lens. Camera 3104 is provided facing outward on the outer surface of the front section 3112, and captures images of objects in real space and outputs the image information obtained by the capture to the processing circuit 4001. In Figure 31B, for example, two cameras 3104 are provided on the front section 3112 with a predetermined distance between them in the lateral direction. Camera 3104 is not limited to this, and may be a monocular camera or a multi-lens camera with three or more lenses. Furthermore, it may be a combination of multiple types of sensors. In hand tracking applications, camera 3104 may be provided to capture images of the space below the information processing system. In applications such as eye tracking or face tracking, the camera 3104 may be configured to capture images of the user's eyes or face.

[0176] The glasses-type HMD3101 also includes a sensor 4008 (Figure 32). The sensor may include at least one of various sensors for determining the movement, attitude, position, etc., of the HMD3001, such as an accelerometer, gyroscope, angular velocity sensor, and geomagnetic sensor.

[0177] Next, with reference to Figure 32, an example of the hardware configuration of the information processing system (HMD 3001 or glasses-type HMD 3101) will be described. As shown in Figure C, the hardware of the information processing system consists of a processing circuit 4001, memory 4002, camera 4003, display unit 4005, input unit 4006, output unit 4007, sensor 4008, communication interface (IF) 4009, external network 4010, and secondary storage device 4011, which are connected to each other via a bus 4012, and can send and receive data and programs.

[0178] The processing circuit 4001 operates based on a program stored in the memory 4002 or the secondary storage device 4011, and controls the overall operation of the information processing systems 3001 and 3101. The processing circuit is, for example, a processor, which reads each program from the memory 4002 and executes it, thereby realizing the functions corresponding to each program read. The processor may include, for example, one or more of the following: a multicore processor, a controller, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or equivalent discrete logic circuits or integrated logic circuits. The processing circuit may be implemented on multiple chips.

[0179] The memory 4002 can be implemented using semiconductor memory elements such as random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electronically erasable programmable read-only memory (EEPROM), or flash memory, as well as a hard disk, optical disk, etc., and may include any form of memory for storing data and executable software instructions.

[0180] Camera 4003 corresponds to camera 3015 in Figure 31A and camera 3104 in Figure 31B, and includes an image sensor such as a CCD (Charge Coupled Device) sensor or a CMOS (Complemented Metal Oxide Semiconductor) sensor, a light detection device such as a distance measuring sensor, and an optical system such as an imaging lens.

[0181] The display unit 4005 is a display panel located inside the housing and consists of a display device such as an LCD (Liquid Crystal Display) or an organic EL (Electroluminescence).

[0182] The input unit 4006, although not shown in Figures 31A and 31B, consists of input devices such as a keyboard, mouse, touch panel, microphone, and controller into which the user inputs operation commands, and supplies the various input signals to the processing circuit 4001.

[0183] The output unit 4007 consists of an audio output device such as a speaker, a force feedback device, an odor feedback device, etc., and is controlled by the processing circuit 4001, outputting the processing results as sound, force feedback, or odor.

[0184] Sensor 4008 may include at least one of various sensors for determining the movement, orientation, and position of HMDs 3001 and 3101, such as an acceleration sensor, gyroscope, angular velocity sensor, and geomagnetic sensor. It may also include a biosensor for sensing human biological information and a pressure sensor for sensing input.

[0185] The communication interface 4009 is an interface for the information processing systems 3001 and 3101 to connect to the external network 4010. It communicates with smartphones and other external devices (for example, PCs (Personal Computers) or server devices on the network) via wired or wireless connections. For example, the processing circuit 4001 receives data from other devices or transmits data it generates to other devices via the communication interface 4009.

[0186] The above describes an example of an information processing system to which the technology described herein may be applied. The technology described herein may be applied to, for example, the photodetector 4004 in the configuration described above.

[0187] (Examples of application to endoscopic surgical systems) The technology described herein (the technology) can be applied to various products. For example, the technology described herein may be applied to endoscopic surgical systems.

[0188] Figure 33 is a diagram showing an example of a schematic configuration of an endoscopic surgical system to which the technology described herein (the technology) may be applied.

[0189] Figure 33 illustrates a surgeon (physician) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgical system 11000. As shown in the figure, the endoscopic surgical system 11000 consists of an endoscope 11100, other surgical instruments 11110 such as an insufflation tube 11111 and an energy treatment device 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 equipped with various devices for endoscopic surgery.

[0190] The endoscope 11100 consists of a barrel 11101, the tip of which is inserted into the body cavity of the patient 11132 for a predetermined length, and a camera head 11102 connected to the base end of the barrel 11101. In the illustrated example, the endoscope 11100 is shown as a so-called rigid endoscope having a rigid barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible endoscope having a flexible barrel.

[0191] An opening into which an objective lens is fitted is provided at the tip of the microscope tube 11101. A light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the tip of the microscope tube by a light guide extending inside the microscope tube 11101, and is irradiated through the objective lens towards the object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a straight-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0192] The camera head 11102 contains an optical system and an image sensor. Reflected light from the object being observed (observation light) is focused onto the image sensor by the optical system. The image sensor converts the observation light into electrical signals, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0193] The CCU 11201 is composed of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and other components, and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various image processing operations on that image signal, such as development processing (demosaic processing), to display an image based on that image signal.

[0194] The display device 11202 displays an image based on an image signal that has been processed by the CCU 11201, under control from the CCU 11201.

[0195] The light source device 11203 is composed of a light source such as an LED (light-emitting diode) and supplies illumination light to the endoscope 11100 when photographing the surgical area, etc.

[0196] The input device 11204 is an input interface for the endoscopic surgical system 11000. The user can input various types of information and instructions to the endoscopic surgical system 11000 via the input device 11204. For example, the user can input instructions to change the imaging conditions (type of light, magnification, focal length, etc.) of the endoscope 11100.

[0197] The treatment instrument control device 11205 controls the drive of the energy treatment instrument 11112 for purposes such as tissue cauterization, incision, or blood vessel sealing. The insufflation device 11206 injects gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity for the purpose of securing a field of view by the endoscope 11100 and securing the operator's workspace. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, images, or graphs.

[0198] The light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical area can be configured as a white light source consisting of, for example, an LED, a laser light source, or a combination thereof. When the white light source is configured as a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to capture images corresponding to each of the RGB colors in time-division by irradiating the observation target with laser light from each of the RGB laser light sources in time-division and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter on the image sensor.

[0199] Furthermore, the light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the drive of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity, images can be acquired in time-division order, and these images can be combined to generate high dynamic range images without so-called black crushing and white clipping.

[0200] Furthermore, the light source device 11203 may be configured to supply light in a predetermined wavelength range corresponding to special light observation. In special light observation, for example, so-called narrow-band imaging is performed, in which a predetermined tissue such as blood vessels on the surface of the mucosa is imaged with high contrast by irradiating with narrow-band light compared to the irradiation light used in normal observation (i.e., white light), utilizing the wavelength dependence of light absorption in body tissue. Alternatively, fluorescence observation may be performed in special light observation, in which an image is obtained from fluorescence generated by irradiation with excitation light. In fluorescence observation, fluorescence can be obtained by irradiating body tissue with excitation light and observing the fluorescence from the body tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into body tissue and irradiating the body tissue with excitation light corresponding to the fluorescence wavelength of the reagent to obtain a fluorescence image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0201] Figure 34 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in Figure 33.

[0202] The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0203] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and then incident on the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses, including a zoom lens and a focus lens.

[0204] The imaging unit 11402 may consist of one image sensor (a so-called single-chip type) or multiple image sensors (a so-called multi-chip type). If the imaging unit 11402 is configured as a multi-chip type, for example, each image sensor may generate image signals corresponding to RGB, and these may be combined to obtain a color image. Alternatively, the imaging unit 11402 may be configured to have a pair of image sensors for acquiring image signals for the right eye and left eye, respectively, corresponding to 3D (dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical area. In addition, if the imaging unit 11402 is configured as a multi-chip type, multiple lens units 11401 may be provided corresponding to each image sensor.

[0205] Furthermore, the imaging unit 11402 does not necessarily have to be located on the camera head 11102. For example, the imaging unit 11402 may be located inside the lens barrel 11101, directly behind the objective lens.

[0206] The drive unit 11403 is composed of actuators and, under control from the camera head control unit 11405, moves the zoom lens and focus lens of the lens unit 11401 along the optical axis by a predetermined distance. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted as appropriate.

[0207] The communication unit 11404 is composed of communication devices for sending and receiving various types of information with the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0208] Furthermore, the communication unit 11404 receives a control signal from the CCU 11201 to control the drive of the camera head 11102 and supplies it to the camera head control unit 11405. The control signal includes information about imaging conditions, such as information to specify the frame rate of the captured image, information to specify the exposure value at the time of imaging, and / or information to specify the magnification and focus of the captured image.

[0209] The imaging conditions such as frame rate, exposure value, magnification, and focus may be specified by the user as appropriate, or they may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with so-called AE (Auto Exposure), AF (Auto Focus), and AWB (Auto White Balance) functions.

[0210] The camera head control unit 11405 controls the drive of the camera head 11102 based on the control signal received from the CCU 11201 via the communication unit 11404.

[0211] The communication unit 11411 is comprised of a communication device for sending and receiving various types of information with the camera head 11102. The communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400.

[0212] Furthermore, the communication unit 11411 transmits control signals to the camera head 11102 to control the driving of the camera head 11102. Image signals and control signals can be transmitted by telecommunications, optical communications, etc.

[0213] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102.

[0214] The control unit 11413 performs various controls related to imaging the surgical area, etc., by the endoscope 11100, and the display of the images obtained from imaging the surgical area, etc. For example, the control unit 11413 generates a control signal to control the driving of the camera head 11102.

[0215] Furthermore, the control unit 11413 displays the captured image showing the surgical area, etc., on the display device 11202 based on the image signal processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical instruments such as forceps, specific biological sites, bleeding, mist when using the energy treatment device 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When the control unit 11413 displays the captured image on the display device 11202, it may use the recognition results to superimpose various surgical support information onto the image of the surgical area. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can proceed with the surgery reliably.

[0216] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable thereof.

[0217] In the illustrated example, communication was performed via a wired connection using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.

[0218] The above describes an example of an endoscopic surgical system to which the technology described herein may be applied. The technology described herein can be applied to the imaging unit 11402 of the configuration described above. By applying the technology described herein to the imaging unit 11402, the detection accuracy is improved.

[0219] While an endoscopic surgical system has been described here as an example, the technology described herein may also be applied to other systems, such as microsurgical systems.

[0220] (Examples of application to mobile devices) The technology disclosed herein can be applied to a variety of products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile device, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, robots, construction machinery, or agricultural machinery (tractors).

[0221] Figure 35 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0222] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 35, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0223] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0224] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0225] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0226] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0227] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0228] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0229] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0230] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0231] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 35, the output devices are exemplified as an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0232] Figure 36 shows an example of the installation position of the imaging unit 12031.

[0233] In Figure 36, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0234] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0235] Figure 36 shows an example of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0236] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0237] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, etc., that drives autonomously without driver operation, can be performed.

[0238] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0239] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0240] The above describes an example of a mobile object control system to which the technology of this disclosure may be applied. The technology of this disclosure can be applied to the imaging unit 12031 of the configuration described above. Specifically, the light detection device according to the above embodiment and its modified example 1 can be applied to the imaging unit 12031. By applying the technology of this disclosure to the imaging unit 12031, high-resolution images with low noise can be obtained, so that high-precision control using the captured images can be performed in the mobile object control system.

[0241] The present disclosure has been described above with reference to embodiments and their modifications 1 to 6, as well as application examples and usage examples. However, the present disclosure is not limited to the above embodiments, and various modifications are possible. For example, the above embodiments and their modifications 1 to 6 can be combined with each other.

[0242] The effects described herein are for illustrative purposes only. The effects of this disclosure are not limited to those described herein. This disclosure may have effects other than those described herein.

[0243] Furthermore, for example, the present disclosure can take the following configuration. In a photodetector having the following configuration, it is possible to improve reliability by ensuring connection yield while reducing the connection resistance between the connection part and the second element. (1) A semiconductor device comprising: a first semiconductor layer having a first element; a second semiconductor layer laminated on the first semiconductor layer and having a first surface facing the first semiconductor layer and a second surface opposite to the first surface, with a second element provided on the second surface; a connection part extending between the first semiconductor layer and the second semiconductor layer and having an end on the second semiconductor layer side that is on the same surface as the first surface of the second semiconductor layer or on the first semiconductor layer side that is on the first surface than the first surface, for electrically connecting the first element and the second element; and a conductive part for electrically connecting the connection part and the second element. (2) The semiconductor device according to (1), wherein the connection part is formed of polysilicon, polysilicon containing impurities, or a conductive metal material. (3) The semiconductor device according to (2), wherein the conductive metal material is tungsten, cobalt, or copper. (4) The semiconductor device according to any one of (1) to (3), wherein the conductive portion comprises epitaxially grown single-crystal silicon, polysilicon, or a conductive metal material. (5) The semiconductor device according to (4), wherein the conductive metal material is tungsten, titanium, or titanium nitride. (6) The semiconductor device according to any one of (1) to (5), wherein the first element and the second element are each transistors, and the connection portion and the conductive portion electrically connect any of the gate, source region, and drain region of the first element to any of the gate, source region, and drain region of the second element. (7) The semiconductor device according to (6), wherein the source region and the drain region of the second element each consist of an impurity diffusion region formed in the second semiconductor layer, and the conductive portion comprises a semiconductor having the same polarity as the impurity diffusion region.(8) The semiconductor device according to (6) or (7), further comprising an insulating portion covering the side surface of the gate of the second element, wherein the insulating portion has a notch through which the side surface of the gate is exposed, and the conductive portion is connected to the side surface of the gate via the notch. (9) The semiconductor device according to any one of (6) to (8), wherein the first element and the second element have different polarities. (10) The semiconductor device according to any one of (1) to (9), wherein the conductive portion is embedded in an opening that penetrates the second semiconductor layer. (11) The semiconductor device according to any one of (1) to (10), wherein the conductive portion is connected to a part of the side surface of the outer periphery of the second semiconductor layer and to the second surface of the second semiconductor layer in the vicinity of the side surface. (12) The semiconductor device according to (11), further comprising an interlayer film provided between the first semiconductor layer and the second semiconductor layer, and an insulating film covering the second surface of the second semiconductor layer and the surface of the second element and extending on the interlayer film, wherein the conductive portion is embedded in an opening that penetrates the insulating film and is provided along the side surface of the outer periphery of the second semiconductor layer. (13) The semiconductor device according to (12), further comprising an insulating portion covering the side surface of the gate of the second element, wherein the conductive portion extends on the second surface of the second semiconductor layer and is in contact with the insulating portion. (14) The semiconductor device according to (12) or (13), wherein a portion of the conductive portion extends on the insulating film. (15) The semiconductor device according to any one of (1) to (14), wherein the conductive portion includes a silicide. (16) The semiconductor device according to (15), wherein the silicide is an alloy of silicon with tungsten, molybdenum, tantalum, titanium, cobalt, nickel, platinum, or gold. (17) The semiconductor device according to (15) or (16), wherein the second element is a transistor, and the gate, source region and drain region of the second element include the silicide. (18) The semiconductor device according to (17), wherein the gate of the second element has a laminated structure in which polysilicon and the silicide are stacked in order from the second semiconductor layer side.(19) The semiconductor device according to any one of (1) to (18), wherein the second element is a transistor, and the conductive part has an upper surface at a position lower than the upper surface of the gate of the transistor. (20) The semiconductor device according to (19), wherein when the bottom surface of the gate of the transistor is taken as a reference plane and the upper surface of the gate is set to 1, the upper surface of the conductive part is located at a position of 95% or less from the upper surface of the gate. (21) A photodetector comprising: a first semiconductor layer having a sensor pixel that performs photoelectric conversion; a second semiconductor layer laminated on the first semiconductor layer and having a first surface facing the first semiconductor layer and a second surface opposite to the first surface, with one transistor provided on the second surface; a first connection portion extending between the first semiconductor layer and the second semiconductor layer and having an end on the second semiconductor layer side that is on the same surface as the first surface of the second semiconductor layer or on the side of the first semiconductor layer that is on the first surface than the first surface, for electrically connecting the sensor pixel and the one transistor; and a first conductive portion for electrically connecting the first connection portion and the one transistor. (22) The photodetector according to (21), further comprising a pixel circuit that outputs a pixel signal based on a charge output from the sensor pixel, wherein the pixel circuit includes a plurality of pixel transistors, and the one transistor is at least one of the plurality of pixel transistors. (23) The photodetector according to (22), wherein the first semiconductor layer comprises a photoelectric conversion element, a transfer transistor electrically connected to the photoelectric conversion element, and a charge holding portion that temporarily holds the charge output from the photoelectric conversion element via the transfer transistor. (24) The photodetector according to (23), wherein the photoelectric conversion element is formed within the first semiconductor layer, and the transfer transistor and the charge holding portion are provided on the surface of the first semiconductor layer facing the first surface of the second semiconductor layer.(25) The photodetector according to (24), wherein the pixel circuit comprises a reset transistor for resetting the potential of the charge holding portion to a predetermined potential, an amplification transistor for generating a signal of voltage corresponding to the level of the charge held in the charge holding portion as the pixel signal, and a selection transistor for controlling the output timing of the pixel signal from the amplification transistor. (26) The photodetector according to (25), wherein the first transistor is the amplification transistor, and the charge holding portion is electrically connected to the gate of the amplification transistor via the first connection portion and the first conductive portion. (27) The photodetector according to (25), wherein the first transistor is the reset transistor, and the amplification transistor is provided in the first semiconductor layer, and the gate of the amplification transistor is electrically connected to the source region of the reset transistor via the first connection portion and the first conductive portion. (28) The photodetector according to (25), wherein the pixel circuit further includes a conversion efficiency switching transistor that switches the conversion efficiency between the charge and the electrical voltage, the first transistor being the conversion efficiency switching transistor, and the amplification transistor being provided on the first semiconductor layer, with the gate of the amplification transistor being electrically connected to the source region of the conversion efficiency switching transistor via the first connection portion and the first conductive portion. (29) The photodetector according to (28), wherein the sensor pixel is extended between the first semiconductor layer and the second semiconductor layer, and has an end on the second semiconductor layer side that is on the same plane as the first surface of the second semiconductor layer or on the first semiconductor layer side that is on the first surface, and further includes a second connection portion that electrically connects the sensor pixel and the first transistor, and a second conductive portion that electrically connects the second connection portion and the first transistor, the reset transistor being provided on the first semiconductor layer, with the drain region of the reset transistor being electrically connected to the source region of the conversion efficiency switching transistor via the second connection portion and the second conductive portion.

[0244] This application claims priority based on Japanese Patent Application No. 2025-054257, filed with the Japan Patent Office on 27 March 2025, and all contents of that application are incorporated herein by reference.

[0245] Those skilled in the art will understand that various modifications, combinations, subcombinations, and changes can be conceived depending on design requirements and other factors, and that these fall within the scope of the attached claims and their equivalents.

Claims

1. A semiconductor device comprising: a first semiconductor layer having a first element; a second semiconductor layer laminated on the first semiconductor layer, having a first surface facing the first semiconductor layer and a second surface opposite to the first surface, with a second element provided on the second surface; a connecting portion extending between the first semiconductor layer and the second semiconductor layer, having an end on the second semiconductor layer side that is on the same surface as the first surface of the second semiconductor layer or on the side of the first semiconductor layer that is on the first surface than the first surface, for electrically connecting the first element and the second element; and a conductive portion for electrically connecting the connecting portion and the second element.

2. The semiconductor device according to claim 1, wherein the connecting portion is formed of polysilicon, polysilicon containing impurities, or a conductive metal material.

3. The semiconductor device according to claim 1, wherein the conductive portion comprises epitaxially grown single-crystal silicon, polysilicon, or a conductive metal material.

4. The semiconductor device according to claim 1, wherein the first element and the second element are each transistors, and the connection portion and the conductive portion electrically connect any of the gate, source region and drain region of the first element to any of the gate, source region and drain region of the second element.

5. The semiconductor device according to claim 4, wherein the source region and the drain region of the second element each consist of an impurity diffusion region formed in the second semiconductor layer, and the conductive portion includes a semiconductor having the same polarity as the impurity diffusion region.

6. The semiconductor device according to claim 4, further comprising an insulating portion covering the side surface of the gate of the second element, wherein the insulating portion has a notch through which the side surface of the gate is exposed, and the conductive portion is connected to the side surface of the gate via the notch.

7. The semiconductor device according to claim 4, wherein the first element and the second element have different polarities.

8. The semiconductor device according to claim 1, wherein the conductive portion is embedded in an opening that penetrates the second semiconductor layer.

9. The semiconductor device according to claim 1, wherein the conductive portion is connected to a part of the side surface of the outer periphery of the second semiconductor layer and the second surface of the second semiconductor layer in the vicinity of the side surface.

10. The semiconductor device according to claim 9, further comprising an interlayer film provided between the first semiconductor layer and the second semiconductor layer, and an insulating film covering the second surface of the second semiconductor layer and the surface of the second element and extending on the interlayer film, wherein the conductive portion is embedded in an opening that penetrates the insulating film and is provided along the outer surface of the second semiconductor layer.

11. The semiconductor device according to claim 10, further comprising an insulating portion covering the side surface of the gate of the second element, wherein the conductive portion extends on the second surface of the second semiconductor layer and is in contact with the insulating portion.

12. The semiconductor device according to claim 10, wherein a portion of the conductive portion extends onto the insulating film.

13. The semiconductor device according to claim 1, wherein the conductive portion includes a silicide.

14. The semiconductor device according to claim 13, wherein the silicide is an alloy of silicon with tungsten, molybdenum, tantalum, titanium, cobalt, nickel, platinum, or gold.

15. The semiconductor device according to claim 13, wherein the second element is a transistor, and the gate, source region and drain region of the second element include the silicide.

16. The semiconductor device according to claim 15, wherein the gate of the second element has a laminated structure in which polysilicon and the silicide are stacked in order from the second semiconductor layer side.

17. The semiconductor device according to claim 1, wherein the second element is a transistor, and the conductive portion has an upper surface located lower than the upper surface of the gate of the transistor.

18. The semiconductor device according to claim 17, wherein, when the bottom surface of the gate of the transistor is taken as a reference plane and the top surface of the gate is set to 1, the top surface of the conductive part is located at a position of 95% or less from the top surface of the gate.

19. A photodetector comprising: a first semiconductor layer having a sensor pixel that performs photoelectric conversion; a second semiconductor layer laminated on the first semiconductor layer, having a first surface facing the first semiconductor layer and a second surface opposite to the first surface, with one transistor provided on the second surface; a first connection portion extending between the first semiconductor layer and the second semiconductor layer, having an end on the second semiconductor layer side that is on the same surface as the first surface of the second semiconductor layer or on the side of the first semiconductor layer that is on the first surface than the first surface, and electrically connecting the sensor pixel and the one transistor; and a first conductive portion electrically connecting the first connection portion and the one transistor.

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