Photodetection device, manufacturing method, and electronic apparatus

Abstract

The present technology relates to a photodetection device, a manufacturing method, and an electronic apparatus that make it possible to suppress variations in the processing depth of a trench. A semiconductor substrate of the photodetection device includes: a plurality of pixels that perform photoelectric conversion; a first trench that separates the pixels in a first direction in a plan view; and a second trench that separates the pixels in a second direction different from the first direction in a plan view, the second trench having a length in the longitudinal direction different from that of the first trench. Of the first trench and the second trench, the width of the trench shorter in the longitudinal direction is greater than the width of the other trench, the width being the length in the transverse direction of the trench. The present technology can be applied to, for example, a photodetection device that photoelectrically converts light and outputs a pixel signal or the like corresponding to the amount of light.

Description

Photodetection device, manufacturing method, and electronic device

[0001] The present technology relates to a photodetection device, a manufacturing method, and an electronic device, and particularly relates to a photodetection device, a manufacturing method, and an electronic device that can, for example, suppress variation in the processing depth of trenches.

[0002] For example, Patent Document 1 describes an image sensor in which, in a recessed region having a plurality of recesses provided on a light-receiving surface side, the recesses are formed such that there are no intersecting portions between the recesses in plan view. In the recessed region, if there is an intersecting portion where the recesses intersect each other, the intersecting portion of the recesses becomes deeper than portions other than the intersecting portion. If the depth of the recesses varies, there is a possibility that the diffraction effect of silicon may be reduced, or dark current may increase. By forming the recesses such that there are no intersecting portions, the depth of the recesses can be made uniform, and reduction in the diffraction effect of silicon and increase in dark current can be suppressed.

[0003] International Publication No. 2023 / 276240

[0004] In a photodetection device that senses (detects) light, such as an image sensor having pixels that perform photoelectric conversion, a trench that serves as a pixel separation portion (constitutes a pixel separation portion) for separating pixels from each other is formed.

[0005] As a trench that separates pixels from each other (serves as a pixel separation portion), for example, in plan view, there are a trench that separates pixels in the vertical direction and a trench that separates pixels in the horizontal direction. The trench that separates pixels in the vertical direction and the trench that separates pixels in the horizontal direction may have different lengths (in the longitudinal direction). In such a case, due to the micro-loading effect, the trenches end up having different processing depths.

[0006] When the trench separating pixels in the vertical direction and the trench separating pixels in the horizontal direction have different processing depths, various adverse effects may occur. Therefore, there is a demand for the proposal of a technology that can suppress variation in processing depth of trenches having different lengths.

[0007] This technology was developed in light of these circumstances and aims to suppress variations in the machining depth of trenches of different lengths.

[0008] The photodetector of this technology comprises a semiconductor substrate having a plurality of pixels that perform photoelectric conversion, a first trench that separates the pixels in a first direction in a plan view, and a second trench that separates the pixels in a second direction different from the first direction in a plan view, wherein the length of the second trench in the longitudinal direction is different from that of the first trench, and the width of the trench with the shorter length in the longitudinal direction is wider than the width of the other trench.

[0009] The present invention relates to a method for manufacturing a photodetector comprising a semiconductor substrate having a plurality of pixels that perform photoelectric conversion, a first trench that separates the pixels in a first direction in a plan view, and a second trench that separates the pixels in a second direction different from the first direction in a plan view, wherein the second trench is formed to have a different longitudinal length from the first trench, and the shorter of the two trenches is formed such that its width in the shorter direction is wider than the width of the other trench.

[0010] The electronic device of this technology comprises a semiconductor substrate having a plurality of pixels that perform photoelectric conversion, a first trench that separates the pixels in a first direction in a plan view, and a second trench that separates the pixels in a second direction different from the first direction in a plan view, wherein the second trench has a different longitudinal length from the first trench, and the width of the shorter of the two trenches, which is the longitudinal length of the trench, is wider than the width of the other trench, an optical detection device, and a processing unit that processes the signal output by the optical detection device.

[0011] In this technology, a photodetector is provided with a semiconductor substrate having a plurality of pixels that perform photoelectric conversion, a first trench that separates the pixels in a first direction in a plan view, and a second trench that separates the pixels in a second direction different from the first direction in a plan view, wherein the width of the shorter of the two trenches is greater than the width of the other trench.

[0012] The light detection device and the electronic equipment may be a single independent device, or they may be internal blocks constituting a single independent device. Furthermore, the electronic equipment may consist of multiple independent devices.

[0013] This figure shows a schematic configuration example of a photodetector to which this technology is applied. This figure shows a schematic configuration example of the pixel array section 3. This figure illustrates the case where the aspect ratio of the first trench 31 and the aspect ratio of the second trench 32 are not appropriate. This figure illustrates the case where the aspect ratio of the first trench 31 and the aspect ratio of the second trench 32 are appropriate. This figure shows a first configuration example of the pixel array section 3. This figure shows a second configuration example of the pixel array section 3. This figure illustrates the first effect when the processing depth of the first trench 31 and the second trench 32 is made uniform. This figure illustrates the second effect when the processing depth of the first trench 31 and the second trench 32 is made uniform. This is a plan view showing the third to fifth configuration examples of the pixel array section 3. This is a plan view showing the sixth to eighth configuration examples of the pixel array section 3. This figure shows a ninth configuration example of the pixel array section 3. This figure illustrates the outline of the method for forming a lateral trench starting from the second trench 32. This figure illustrates the outline of the process for forming the lateral trench 112. This is a plan view showing an example configuration of the first lateral trench 71 and the second lateral trench 72. This is a plan view showing an example configuration of the pixel array section 3 having the first lateral trench 71 and the second lateral trench 72. This is a plan view showing another example configuration of the pixel array section 3 having the first lateral trench 71 and the second lateral trench 72. This figure illustrates the method for forming the first lateral trench 71 and the second lateral trench of the pixel array section 3. This is a cross-sectional view showing an example configuration of the first lateral trench 71 and the second lateral trench 72 when there is a large variation in the processing depth between the first trench 31 and the second trench 32. This is a cross-sectional view showing an example configuration of the first lateral trench 71 and the second lateral trench 72 when there is a small variation in the processing depth between the first trench 31 and the second trench 32. This is a block diagram showing an example configuration of an electronic device. This figure shows an example of using the light detection device 1.

[0014] <One embodiment of a photodetector applying this technology>

[0015] Figure 1 shows a schematic example of a photodetector that applies this technology.

[0016] In this specification and the drawings, identical or similar parts are denoted by the same or similar reference numerals, thereby omitting redundant explanations as appropriate. The drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from the actual ones. Furthermore, there may be parts where the dimensional relationships and ratios differ between drawings.

[0017] The definitions of directions such as up and down in the following explanation are merely for explanatory convenience and do not limit the technical concept of this technology. For example, if an object is rotated 90° and observed, up and down will be converted to left and right and read accordingly, and if it is rotated 180° and observed, up and down will be inverted and read accordingly.

[0018] This technology can be applied to all types of photodetectors that have a pixel array section in which multiple pixels are arranged, and that convert incident light into photoelectric light to output a pixel signal corresponding to the amount of light. The light to be sensed by the photodetector may be light in the visible light region including wavelengths such as R (Red), G (Green), and B (Blu), light in the invisible light region such as infrared light, or light in both the visible and invisible light regions. The photodetector can be configured as an image sensor that generates and outputs a pixel signal corresponding to the amount of incident light in the visible light region, or as an event-based vision sensor that detects changes in the brightness of each pixel and outputs the signal, coordinates, and time information of the pixel where the brightness has changed, or as a distance measuring sensor in a distance measuring system that receives reflected light (light reflected from an object) that was irradiated as active light and measures the distance to the subject using a direct ToF (time of flight) method or an indirect ToF method.

[0019] The photodetector 1 in Figure 1 is configured with a pixel array section 3 on a semiconductor substrate 21 made of silicon (Si) as the semiconductor, in which multiple pixels 2 are arranged in the row and column directions, and a peripheral circuit section around it. The peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

[0020] Pixel 2 consists of a photodiode and a plurality of pixel transistors. The plurality of pixel transistors consist of, for example, four transistors: a transfer transistor, a selection transistor, a reset transistor, and an amplification transistor, each of which is a MOS transistor (MOS FET (metal oxide semiconductor field effect transistor)).

[0021] Pixel 2 can also be a shared pixel structure. A shared pixel structure consists of multiple photodiodes, multiple transfer transistors, one shared FD (floating diffusion) layer, and one shared other pixel transistor. In other words, in a shared pixel structure, each pixel 2 has a photodiode and a transfer transistor, and the other pixel transistors are shared and used by multiple pixels 2.

[0022] The control circuit 8 receives the input clock and data that commands the operating mode, etc., and outputs data such as internal information of the light detection device 1. In other words, the control circuit 8 generates clock signals and control signals that serve as the reference for the operation of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock. The control circuit 8 then outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0023] The vertical drive circuit 4 is configured, for example, by a shift register, and selects a predetermined pixel drive wiring 10 from among the pixel drive wiring 10 wired for each row of pixels 2, and supplies pulses to drive the pixels 2 to the selected pixel drive wiring 10, thereby driving the pixels 2 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 2 of the pixel array 3 row by row in the vertical direction, and supplies a signal based on the signal charge generated in the photoelectric conversion of each pixel 2 according to the amount of light received to the column signal processing circuit 5 through the vertical signal line 9.

[0024] The column signal processing circuit 5 is located for each column of pixels 2 and performs signal processing such as noise reduction on the signal output from one row of pixels 2 for each pixel column. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and AD conversion to remove pixel-specific fixed pattern noise.

[0025] The horizontal drive circuit 6 is composed of, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, causing each of the column signal processing circuits 5 to output a pixel signal to the horizontal signal line 11.

[0026] The output circuit 7 processes the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 11 and outputs them. The output circuit 7 may, for example, only perform buffering, or it may perform black level adjustment, column variation correction, various digital signal processing, etc. The input / output terminal 13 is a terminal for exchanging signals with the outside.

[0027] The photodetector 1 in Figure 1 has a configuration called a column AD system, in which column signal processing circuits 5 that perform CDS processing and AD conversion processing are arranged in rows. The photodetector 1 generates a signal (pixel signal) corresponding to the amount of light received by each pixel 2 in the pixel array 3 and outputs it to the outside. The photodetector 1 can be configured as a front-illuminated type in which light is incident from the front side of the semiconductor substrate 21 on which the pixel transistors are formed, or as a back-illuminated type in which light is incident from the back side opposite to the front side of the semiconductor substrate 21.

[0028] <Example of the configuration of the pixel array section 3>

[0029] Figure 2 shows a schematic example of the pixel array section 3 in Figure 1.

[0030] Figure 2A is a plan view showing a schematic configuration example of the pixel array section 3, and Figure 2B is a cross-sectional view of the section along line AA in the plan view of Figure 2A.

[0031] Trenches that separate the pixels 2 of the pixel array 3 (which form pixel separation sections) are formed on the semiconductor substrate 21 (Si bulk) by (dry) etching.

[0032] Trenches for separating pixels 2 from each other include, in a plan view, a trench that separates pixels 2 in a first direction, for example, vertically (up and down), and a trench that separates pixels 2 in a second direction different from the first direction, for example, horizontally (left and right).

[0033] In the semiconductor substrate 21 shown in Figure 2, a first trench 31 is formed as a trench separating the pixels 2 in the vertical direction, and a second trench 32 is formed as a trench separating the pixels 2 in the horizontal direction. Hereafter, in a plan view, the longitudinal length of the second trench 32 is assumed to be longer than the longitudinal length of the first trench 31 (and the longitudinal length of the first trench 31 is shorter than the longitudinal length of the second trench 32).

[0034] Note that the first and second directions are not limited to orthogonal directions. For example, if pixel 2 is configured as a rhombus in plan view, the direction of one of the two sides of the rhombus with different orientations can be designated as the first direction, and the direction of the other side as the second direction.

[0035] In Figure 2, the first trench 31 that separates the pixels 2 vertically has its longitudinal direction oriented horizontally in a plan view, and its longitudinal length is less than the horizontal pixel pitch. For example, it is shorter than the (horizontal) pixel pitch by a value obtained by adding a predetermined margin to the width, which is the length of the second trench 32 in the short direction (hereinafter also referred to as a length slightly less than the pixel pitch).

[0036] Here, in a plan view, the length of the trench in the longitudinal direction is simply called the trench length, and the length in the transverse direction is called the trench width. Also, for the sake of simplicity, in a plan view, the aspect ratio of pixel 2 is assumed to be horizontal:vertical = 1:1. That is, the pixel pitch in the horizontal direction and the pixel pitch in the vertical direction are assumed to be the same.

[0037] The second trench 32, which separates the pixels 2 horizontally, has its longitudinal direction oriented vertically in a plan view, and its length is approximately twice or more the (vertical) pixel pitch, for example, slightly less than twice or slightly less than three times the pixel pitch.

[0038] Furthermore, in Figure 2, the first trench 31 and the second trench 32 are formed so as not to intersect (so that no intersecting sections are created).

[0039] If the width (length in the shorter direction) of the first trench 31 and the second trench 32 are the same, then in the formation of the first trench 31 and the second trench 32 by etching, variations in machining depth will occur due to the microloading phenomenon for the first trench 31 and the second trench 32, which have different lengths. That is, the machining depth of the first trench 31, which is shorter in length (in the longer direction) than the second trench 32, will be shallower (shorter) than that of the second trench 32, and the machining depth of the second trench 32, which is longer than the first trench, will be deeper (longer) than that of the first trench 31.

[0040] As the length of the second trench 32 is longer than the length of the first trench 31, the width of the first trench 31 can be increased compared to before the width was increased, due to the microloading phenomenon. As a result, as shown by the arrow in the figure, the machining depth of the first trench 31 can be increased and brought closer to the machining depth of the second trench 32.

[0041] In other words, by making the width of the shorter trench 31 of the two trenches, the first trench 31, wider than the width of the other trench (the longer trench), the second trench 32, the machining depth of the first trench 31 and the second trench 32 can be adjusted, thereby suppressing variations in machining depth. As a result, for example, the machining depth of the first trench 31 and the second trench 32 can be made uniform to a similar extent.

[0042] Of the two trenches having different lengths, making the width of the shorter trench larger than the width of the other trench (the longer trench) relatively includes making the width of the longer trench smaller than the width of the other trench (the shorter trench).

[0043] For trenches having different lengths, such as the first trench 31 which is shorter (than the second trench 32) and the second trench 32 which is longer (than the first trench 31), setting the aspect ratio, which is the ratio of the trench length to the trench width, to an appropriate aspect ratio, that is, an aspect ratio that equalizes the processing depths of the first trench 31 and the second trench 32 to a similar level, can suppress variations in processing depth and achieve uniform processing depth.

[0044] FIG. 3 is a diagram illustrating a case where the aspect ratio of the first trench 31 and the aspect ratio of the second trench 32 are not appropriate aspect ratios.

[0045] 3A is a plan view showing a configuration example of the pixel array section 3, and 3B is a cross-sectional view taken along line AA in the plan view of FIG. 3A.

[0046] In FIG. 3, the first trench 31 has a length slightly less than the pixel pitch, and the second trench 32 has a length slightly less than three times the pixel pitch, for example. Further, the first trench 31 and the second trench 32 are formed so as not to intersect with each other.

[0047] In FIG. 3, since the aspect ratio of the first trench 31 and the aspect ratio of the second trench 32 are not appropriate aspect ratios, (large) variations occur in the processing depths of the first trench 31 and the second trench 32. That is, the processing depth of the first trench 31 is shallower than the processing depth of the second trench 32 (the processing depth of the second trench 32 is deeper than the processing depth of the first trench 31).

[0048] FIG. 4 is a diagram illustrating a case where the aspect ratio of the first trench 31 and the aspect ratio of the second trench 32 are appropriate aspect ratios.

[0049] Figure 4A is a plan view showing an example of the configuration of the pixel array section 3, and Figure 4B is a cross-sectional view of the section along line AA in the plan view of Figure 4A.

[0050] In Figure 4, the length of the first trench 31 is slightly less than the pixel pitch, as in Figure 3, but the width of the first trench 31 is slightly wider than in Figure 3 and wider than the width of the second trench 32.

[0051] Furthermore, in Figure 4, the length of the second trench 32 is shorter than in Figure 3, being slightly less than twice the pixel pitch, but the width of the second trench 32 is the same as in Figure 3.

[0052] In Figure 4, as in Figure 3, the first trench 31 and the second trench 32 are formed so as not to intersect.

[0053] In Figure 4, the aspect ratios of the first trench 31 and the second trench 32 are appropriate, resulting in uniform machining depths for both the first trench 31 and the second trench 32.

[0054] In other words, in Figure 4, the length of the first trench 31 is the same as in Figure 3, but the width is wider than in Figure 3. As a result, the etching speed is faster than in Figure 3, and the machining depth is deeper, as indicated by the arrow at B in Figure 4.

[0055] On the other hand, for the second trench 32, the width is the same as in Figure 3, but the length is shorter than in Figure 3. As a result, the etching speed is slower than in Figure 3, and the machining depth is shallower, as indicated by the arrow in Figure 4B.

[0056] As a result, in Figure 4, variations in the machining depth of the first trench 31 and the second trench 32 are suppressed and made uniform.

[0057] Figure 5 shows a first example configuration of the pixel array section 3.

[0058] Figure 5A is a plan view showing a first configuration example of the pixel array section 3, and Figure 5B is a cross-sectional view of the section along line AA in the plan view of Figure 5A.

[0059] In Figure 5, the length of the first trench 31 is slightly less than the pixel pitch, and the length of the second trench 32 is slightly less than three times the pixel pitch. The widths of the first trench 31 and the second trench 32 are the same. Furthermore, the first trench 31 and the second trench 32 are formed so as not to intersect.

[0060] In the formation of the first trench 31 and the second trench 32 by etching (performed for the same amount of time), the etching rate increases as the length and width of the trench increase due to the microloading phenomenon. In the formation of the first trench 31 and the second trench 32, which have different lengths but the same width, the etching rate of the second trench 32, which is longer than the first trench 31, is faster than that of the first trench 31. As a result, the machining depth of the first trench 31 becomes shallower than that of the second trench 32 (and the machining depth of the second trench 32 becomes deeper than that of the first trench 31), resulting in variations in the machining depths of the first trench 31 and the second trench 32.

[0061] Figure 6 shows a second example configuration of the pixel array section 3.

[0062] Figure 6A is a plan view showing a second configuration example of the pixel array section 3, and Figure 6B is a cross-sectional view of the section along line AA in the plan view of Figure 6A.

[0063] In Figure 6, as in Figure 5, the length of the first trench 31 is slightly less than the pixel pitch, and the length of the second trench 32 is slightly less than three times the pixel pitch. Furthermore, the first trench 31 and the second trench 32 are formed so as not to intersect. However, in Figure 6, the width of the second trench 32 is the same as in Figure 5, but the width of the first trench 31 is wider than in Figure 5. Therefore, the width of the first trench 31, which is shorter in length than the second trench 32, is wider than the width of the second trench 32.

[0064] In Figure 6, the width of the first trench 31 is wider than the width of the second trench 32. As a result, the etching speed of the first trench 31 is faster than in Figure 5, and consequently, the machining depth of the first trench 31 is deeper than in Figure 5. This suppresses variations in the machining depth of the first trench 31 and the second trench 32, and allows for uniform machining depth. Note that the etching time is assumed to be the same in Figures 5 and 6.

[0065] Here, the machining depth of the trench is not simply determined by the area of ​​the trench in a plan view. Furthermore, the aspect ratio of the first trench 31 and the second trench 32, that is, the specific numerical values ​​of the length and width of the first trench 31 and the second trench 32, which equalize the machining depth of the first trench 31 and the second trench 32, differs depending on the target machining depth. The specific numerical values ​​of the length and width of the first trench 31 and the second trench 32 that equalize the machining depth can be obtained by simulations, experiments, etc., or by using a learning model that has been trained using machine learning such as deep learning with data obtained from such simulations and experiments.

[0066] According to this technology, as shown in Figure 6, by making the width of the first trench 31, which is shorter in length (than the second trench 32), wider than the width of the second trench 32, which is longer in length (than the first trench 31), variations in the machining depth of the first trench 31 and the second trench 32, which are of different lengths, can be suppressed and, consequently, made uniform.

[0067] Furthermore, the uniformization of the machining depth of the first trench 31 and the second trench 32 can be applied to the entire area of ​​the pixel array section 3, or to only a portion of the area. That is, the machining depth of all the first trenches 31 and the second trenches 32 of the pixel array section 3 can be set to a predetermined depth, or the machining depth of some sets of the first trenches 31 and the second trenches 32 of the pixel array section 3 can be set to a certain depth L1, while the machining depth of other sets can be set to a different depth L2.

[0068] For example, in Figure 6A, the machining depth of the set of the second trench 32, which is the first from the top in the first column from the left, and the three first trenches 31 in the third row from the top adjacent to the right of the second trench 32, can be set to depth L1, and the machining depth of the set of the second trench 32, which is the first from the top in the second column from the left, and the three first trenches 31 in the third row from the top adjacent to the right of the second trench 32, can be set to depth L2.

[0069] Figure 7 illustrates the first effect when the machining depths of the first trench 31 and the second trench 32 are made uniform.

[0070] Figure 7 is a cross-sectional view of the pixel array portion 3, showing the first trench 31 and the second trench 32, when the first trench 31 and the second trench 32 are formed from the front surface (upper side of the drawing) of the semiconductor substrate 21. Figure 7A is a cross-sectional view when the variation in the processing depth of the first trench 31 and the second trench 32 is greater than a predetermined variation. Figure 7B is a cross-sectional view when the variation in the processing depth of the first trench 31 and the second trench 32 is suppressed and the processing depth is made uniform.

[0071] For example, in Figure 7A, the width of the first trench 31, which is shorter in length than the second trench 32, is the same as the width of the second trench 32. For the first trench 31 and the second trench 32, which have the same width, the etching speed of the first trench 31, which is shorter in length than the second trench 32, will be slower. Therefore, the machining depth of the first trench 31 will be shallower than the machining depth of the second trench 32.

[0072] In etching to form the first trench 31 and the second trench 32 from the front surface of the semiconductor substrate 21, the etching time is extended in order to reach the target depth (target depth) of the first trench 31, which has a shallow processing depth. In etching to reach the target depth of the first trench 31, the processing depth of the second trench 32 becomes significantly greater than the target depth (by a predetermined depth). Therefore, the processing depth of the first trench 31 becomes (almost) the target depth, and the processing depth of the second trench 32 becomes significantly greater than the target depth, resulting in a large variation in processing depth (a variation corresponding to a predetermined depth).

[0073] After the formation of the first trench 31 and the second trench 32, chemical mechanical planarization (CMP) is performed on the back side of the semiconductor substrate 21, and the back side of the semiconductor substrate 21 is thinned (Si thinning) by etching, etc., until the first trench 31 and the second trench 32, which form FFTI (front full trench isolation), are exposed.

[0074] In Figure 7A, the thinning of the back side of the semiconductor substrate 21 is carried out to a processing depth that far exceeds the target depth, reaching just above the bottom of the second trench 32.

[0075] In this case, regarding the amount of CMP (Chemical Modulation), which is the thickness from the bottom of the trench to the surface (bottom) of the semiconductor substrate 21 after CMP, the amount of CMP in the second trench 32 becomes smaller, but the amount of CMP in the first trench 31 becomes larger. That is, the amount of CMP in the first trench 31 becomes larger than the amount of CMP in the second trench 32 by the amount of variation (difference) in the processing depth of the first trench 31 and the second trench 32. As a result, the variation in the amount of CMP in the first trench 31 and the second trench 32 becomes larger (than a predetermined value).

[0076] If there is a large variation in the amount of CMP in the first trench 31 and the second trench 32, the variation in optical properties such as Qe (quantum efficiency) will worsen.

[0077] On the other hand, in Figure 7B, the width of the first trench 31, which is shorter in length than the second trench 32, is wider than the width of the second trench 32. As a result, the aspect ratio of the first trench 31 and the aspect ratio of the second trench 32 are appropriate. Because the width of the first trench 31 is wider than the width of the second trench 32, the etching speed of the first trench 31 is faster than in the case of Figure 7A. Therefore, in Figure 7B, the machining depth of the first trench 31 and the second trench 32 reach the target depth almost simultaneously and are uniform.

[0078] Therefore, in Figure 7B, where the machining depths of the first trench 31 and the second trench 32 are uniform, the etching time for forming the first trench 31 and the second trench 32 can be shortened compared to Figure 7A, where the machining depths vary.

[0079] Furthermore, in Figure 7B, the amount of CMP in the first trench 31 and the second trench 32 becomes similarly small, and as a result, the variation in the amount of CMP also becomes smaller (than a predetermined value).

[0080] By reducing the variation in the amount of CMP in the first trench 31 and the second trench 32, variations in optical properties such as Qe can be improved.

[0081] Figure 8 illustrates the second effect when the machining depths of the first trench 31 and the second trench 32 are made uniform.

[0082] Figure 8 is a cross-sectional view of the pixel array portion 3, showing the first trench 31 and the second trench 32, when the first trench 31 and the second trench 32 are formed from the back surface (bottom side of the drawing) of the semiconductor substrate 21. Figure 8A is a cross-sectional view when there is a large variation in the processing depth of the first trench 31 and the second trench 32. Figure 8B is a cross-sectional view when the variation in the processing depth of the first trench 31 and the second trench 32 is suppressed and the processing depth is made uniform.

[0083] For example, in Figure 8A, the width of the first trench 31, which is shorter in length than the second trench 32, is the same as the width of the second trench 32. For the first trench 31 and the second trench 32, which have the same width, the etching speed of the first trench 31, which is shorter in length than the second trench 32, will be slower. Therefore, the machining depth of the first trench 31 will be shallower than the machining depth of the second trench 32 (the machining depth of the second trench 32 will be deeper than the machining depth of the first trench 31).

[0084] In etching to form the first trench 31 and the second trench 32 from the back surface of the semiconductor substrate 21, etching is terminated when the remaining thickness of the second trench 32, which has a deeper processing depth, reaches a predetermined thickness in order to maintain a predetermined thickness as the thickness remaining on the front surface side of the semiconductor substrate 21. As a result, the remaining thickness of the first trench 31, which has a shallower processing depth than the second trench 32, becomes significantly thicker (by a predetermined thickness) than the remaining thickness of the second trench 32, resulting in a large variation in the remaining thickness.

[0085] If there is a large variation in the remaining thickness of the first trench 31 and the second trench 32, the element isolation (separation between pixels 2) of the first trench 31, which has a thicker remaining thickness, will deteriorate.

[0086] On the other hand, in Figure 8B, the width of the first trench 31, which is shorter in length than the second trench 32, is wider than the width of the second trench 32. As a result, the aspect ratio of the first trench 31 and the aspect ratio of the second trench 32 are appropriate. Because the width of the first trench 31 is wider than the width of the second trench 32, the etching speed of the first trench 31 is faster than in the case of Figure 8A. Therefore, in Figure 8B, the machining depth of the first trench 31 and the second trench 32 reach a depth that leaves a predetermined thickness almost simultaneously, resulting in uniformity.

[0087] Therefore, in Figure 8B, where the machining depths of the first trench 31 and the second trench 32 are uniform, the remaining thickness of the first trench 31 can be reduced compared to Figure 8A, where the machining depths vary. This improves the element isolation of the first trench 31 compared to Figure 8A, where the remaining thickness of the first trench 31 is thicker.

[0088] Figure 9 is a plan view showing the third to fifth configuration examples of the pixel array section 3.

[0089] Figure 9A shows a third configuration example of the pixel array section 3.

[0090] In Figure 9A, the length of the first trench 31 is slightly less than the pixel pitch, and the length of the second trench 32 is slightly less than three times the pixel pitch. The width of the first trench 31, which is shorter in length than the second trench 32, is wider than the width of the second trench 32. As a result, the aspect ratio of the first trench 31 and the aspect ratio of the second trench 32 are appropriate aspect ratios that make the machining depth of the first trench 31 and the second trench 32 roughly the same.

[0091] Furthermore, in Figure 9A, the first trench 31 and the second trench 32 are formed so as not to intersect.

[0092] Figure 9B shows a fourth configuration example of the pixel array section 3.

[0093] In Figure 9B, the length of the first trench 31 is slightly less than the pixel pitch, and the length of the second trench 32 is more than six times the pixel pitch, for example, the vertical length of the pixel array section 3 (the vertical length of the area in which multiple pixels 2 are arranged in both the row and column directions). The width of the first trench 31, which is shorter than the second trench 32, is wider than the width of the second trench 32. As a result, the aspect ratio of the first trench 31 and the aspect ratio of the second trench 32 are appropriate aspect ratios that make the machining depth of the first trench 31 and the second trench 32 roughly the same.

[0094] Furthermore, in Figure 9B, the first trench 31 and the second trench 32 are formed so as not to intersect.

[0095] Figure 9C shows a fifth configuration example of the pixel array section 3.

[0096] In Figure 9C, the length of the first trench 31 is slightly less than twice the pixel pitch, and the length of the second trench 32 is more than six times the pixel pitch, for example, the vertical length of the pixel array section 3. The width of the first trench 31, which is shorter in length than the second trench 32, is wider than the width of the second trench 32. As a result, the aspect ratio of the first trench 31 and the aspect ratio of the second trench 32 are appropriate aspect ratios that make the machining depth of the first trench 31 and the second trench 32 roughly the same.

[0097] In Figure 9C, the first trench 31, which is slightly less than twice the length of the pixel pitch, is formed between the leftmost and rightmost second trenches 32 of the three horizontally aligned second trenches 32, so as not to intersect with the leftmost and rightmost second trenches 32. However, the first trench 31, which is slightly less than twice the length of the pixel pitch, intersects with the central second trench 32 of the three horizontally aligned second trenches 32.

[0098] As shown in Figures 9B and 9C, the length of the second trench 32, which is wider than the first trench 31 (and longer than the second trench 32), can be any length longer than the first trench 31. Also, as shown in Figure 9C, the first trench 31 and the second trench may partially intersect.

[0099] Figure 10 is a plan view showing the sixth to eighth configuration examples of the pixel array section 3.

[0100] In Figure 10, the semiconductor substrate 21 has trenches forming that separate the pixels 2 vertically. These trenches include a first trench 31 with a length less than the pixel pitch, for example, slightly less than the pixel pitch, and a third trench 33 (or 33-1 and 33-2) that is shorter in length and wider than the first trench 31. The first trench 31 and the third trench 33, which separate the pixels 2 vertically, are formed alternately in each row.

[0101] Furthermore, in Figure 10, the length of the second trench 32 is more than four times the pixel pitch, for example, the vertical length of the pixel array section 3. In Figure 10, the length and thickness increase in the order of the second trench 32, the first trench 31, and the third trench 33.

[0102] Furthermore, in Figure 10, the first trench 31 and the second trench 32 are formed so as not to intersect, and the first trench 31 and the third trench 33 are also formed so as not to intersect.

[0103] Figure 10A shows a sixth configuration example of the pixel array section 3.

[0104] In Figure 10A, a third trench 33 is formed along with the first trench 31, with a length slightly longer than half the pixel pitch, as a trench that vertically separates the pixels 2 from each other. The third trench 33 is formed in a manner that is close to the second trench 32 to the right, in a manner that does not intersect with the second trench 32 to the right, in a portion corresponding to one side of the pixel 2. Therefore, there is a gap between the third trench 33 and the second trench 32 to the left that is wider than the gap between it and the second trench 32 to the right.

[0105] In Figure 10A, the aspect ratios of the first trench 31, the second trench 32, and the third trench 33 are appropriate aspect ratios that make the machining depths of the first trench 31, the second trench 32, and the third trench 33 roughly the same.

[0106] Figure 10B shows a seventh configuration example of the pixel array section 3.

[0107] In Figure 10B, along with the first trench 31, two identical third trenches 33-1 and 33-2 are formed horizontally, each shorter than half the pixel pitch, for example, about one-third the length of the pixel pitch, to separate the pixels 2 vertically. The two third trenches 33-1 and 33-2 are formed with a gap between them in the portion corresponding to one side of the pixel 2. That is, the third trench 33-1 is formed so as to be close to the left second trench 32 without intersecting it, and the third trench 33-2 is formed so as to be close to the right second trench 32 without intersecting it. As a result, there is a gap between the third trenches 33-1 and 33-2 that is wider than the gap between the right and left second trenches 32.

[0108] In Figure 10B, the aspect ratios of the first trench 31, the second trench 32, and the third trenches 33-1 and 33-2 are appropriate aspect ratios that make the machining depths of the first trench 31, the second trench 32, and the third trenches 33-1 and 33-2 uniformly equal.

[0109] Figure 10C shows an eighth configuration example of the pixel array section 3.

[0110] In Figure 10C, the same first trench 31, second trench 32, and third trenches 33-1 and 33-2 are formed as in Figure 10B. Therefore, the aspect ratios of the first trench 31, the second trench 32, and the third trenches 33-1 and 33-2 are appropriate aspect ratios that make the machining depth of the first trench 31, the second trench 32, and the third trenches 33-1 and 33-2 uniform to a similar degree.

[0111] Furthermore, in Figure 10C, an FD (floating diffusion) layer 41 is formed in the gap between the third trenches 33-1 and 33-2. The pixel array 3 can adopt a shared pixel configuration in which the FD layer 41 in the gap between the third trenches 33-1 and 33-2 is shared by two pixels, the upper pixel 2 and the lower pixel 2 of the third trenches 33-1 and 33-2, which are separated vertically by the third trenches 33-1 and 33-2.

[0112] Furthermore, in the pixel array section 3 shown in Figure 10A, an FD layer can be formed in the gap between the third trench 33 and the second trench 32 on the left, and this FD layer can be shared by two pixels, the upper pixel 2 and the lower pixel 2 of the third trench 33, which are separated vertically by the third trench 33.

[0113] Furthermore, while Figure 10 shows a first trench 31 with a length slightly less than the pixel pitch, other lengths of the first trench 31 can be used, such as the first trench 31 with a length slightly less than twice the pixel pitch, as shown in Figure 9C.

[0114] Furthermore, although the above describes the case in which two types of trenches (of length), the first trench 31 and the second trench 32, or three types of trenches, the first trench 31 to the third trench 33 (or 33-1 and 33-2), there may be four or more types of trenches. Even with four or more types of trenches, the machining depth can be made uniform to a similar degree by adopting an appropriate aspect ratio.

[0115] Figure 11 shows a ninth example configuration of the pixel array section 3.

[0116] Figure 11A is a cross-sectional view showing a ninth configuration example of the pixel array section 3, and Figure 11B is a simplified perspective view of the ninth configuration example of the pixel array section 3.

[0117] In the semiconductor substrate 21, for example, an N-type (second conductivity type) semiconductor region is formed in a P-type (first conductivity type) semiconductor region for each pixel 2, thereby forming a photoelectric conversion region 61 (PD (photodiode)) that performs photoelectric conversion on a pixel-by-pixel basis.

[0118] Below the photoelectric conversion region 61 of pixel 2, a charge holding section (MEM) 62 is formed to hold the charge obtained by the photoelectric conversion in the photoelectric conversion region 61, for example, for a global shutter. Light incident on the pixel array section 3 from the top in the figure is photoelectrically converted in the photoelectric conversion region 61. The charge obtained by the photoelectric conversion in the photoelectric conversion region 61 is transferred to the charge holding section 62 by passing through the inside of the photoelectric conversion region 61.

[0119] In Figure 11, a trench (planar trench) 71 is formed in the semiconductor substrate 21, starting from a second trench 32 in a certain row, extending to a first depth from the top surface of the semiconductor substrate 21 in a planar view. Furthermore, a trench (planar trench) 72 is formed, starting from a second trench 32 in the row to the right, extending to a second depth different from the first depth of trench 71, for example, a second depth deeper than the first depth, in a planar view. Trenches 71 and 72 are formed alternately in each row.

[0120] A trench that extends in the planar direction when viewed from above appears to extend laterally when viewed in cross-section. Therefore, a trench that extends in the planar direction when viewed from above is also called a lateral trench. A lateral trench 71 of the first depth is also called the first lateral trench 71, and a lateral trench 72 of a second depth which is deeper than the first depth is also called the second lateral trench 72. The first lateral trench 71 and the second lateral trench 72 constitute a light-shielding film.

[0121] In a cross-sectional view, the first lateral trench 71 and the second lateral trench 72 are formed alternately at different depths of the pixel 2. Furthermore, in a plan view, the first lateral trench 71 and the second lateral trench 72 are formed such that the first lateral trench 71 covers a portion of the pixel 2, while the second lateral trench 72 covers another portion of the pixel 2 that is different from the first lateral trench 71, so that both the first lateral trench 71 and the second lateral trench 72 cover the entire pixel 2. Therefore, the first lateral trench 71 and the second lateral trench 72 are formed alternately so that the charge holding portion 62 formed at the bottom of the photoelectric conversion region 61 is not visible from the upper part of the figure where light is incident on the pixel array portion 3.

[0122] An insulating film 81 is placed on top of the semiconductor substrate 21, and a planarization film 82 is placed on top of the insulating film 81. A color filter 91 is placed on top of the planarization film 82, and an OCL (on-chip lens) 92 is placed on top of the color filter 91.

[0123] In the pixel array section 3 configured as described above, the first lateral trench 71 and the second lateral trench 72 are formed alternately in a plan view such that the charge holding section 62 formed at the bottom of the photoelectric conversion region 61 is not visible from the upper part where light enters the pixel array section 3. Furthermore, the first lateral trench 71 and the second lateral trench 72 constitute a light-shielding film. Therefore, light entering the pixel array section 3 from above is blocked by the light-shielding film formed by the first lateral trench 71 and the second lateral trench 72, thus preventing light from entering the charge holding section 62 formed at the bottom of the photoelectric conversion region 61 of the pixel 2. As a result, the generation of photocharge in the charge holding section 62 due to light entering the charge holding section 62 is prevented, and parasitic light sensitivity (PLS) in the global shutter can be suppressed.

[0124] <Method for forming a lateral trench>

[0125] Figure 12 is a diagram illustrating the outline of the method for forming a lateral trench starting from the second trench 32.

[0126] In forming the lateral trench 112, which is either the first lateral trench 71 or the second lateral trench 72, for example, the second trench 32, which serves as the starting point for the lateral trench 112, is formed by etching the front surface of the semiconductor substrate 21. Although the first trench 31 is also formed when the second trench 32 is formed, the first trench 31 will not be explained here.

[0127] The second trench 32 can be formed by forming a hard mask having an opening in the region where the second trench 32 is to be formed on the front surface of the semiconductor substrate 21 and performing dry etching. The second trench 32 is configured in a direction along the crystal orientation <112> of the semiconductor substrate 21. In Figure 12, the direction perpendicular to the drawing is the direction along the crystal orientation <112>.

[0128] After the formation of the second trench 32, an insulating film 111 made of SiN, SiO2, or the like is formed on the front surface of the semiconductor substrate 21.

[0129] Subsequently, the insulating film 111 at the bottom of the second trench 32 is removed, and the bottom of the second trench 32 is deepened by dry etching (etch-back) (the depth of the second trench 32 is increased).

[0130] Then, by etching the bottom of the second trench 32, a lateral trench 112 is formed starting from the second trench 32.

[0131] The etching of the bottom of the second trench 32, which forms the lateral trench 112, can be performed by wet etching using a chemical solution. Wet etching is performed using a chemical solution such as potassium hydroxide, in which the etching rate in the direction of crystal orientation <110> is higher than in the direction of crystal orientation <111>. With such wet etching, etching proceeds in the direction of crystal orientation <110>, thereby forming a lateral trench 112 that extends in the planar direction starting from the second trench 32, whose length direction is perpendicular to the crystal orientation, in a planar view.

[0132] By configuring the second trench 32 in a direction aligned with the crystal orientation <112>, the wall surface of the second trench 32 can be etched in the direction of the crystal orientation <110>. The upper and lower surfaces of the lateral trench 112 become planes with the plane orientation (111) and are hardly etched.

[0133] Figure 13 is a diagram illustrating the general process of forming the lateral trench 112.

[0134] Figure 13 is a plan view showing the semiconductor substrate 21 in which the second trench 32 is formed.

[0135] In Figure 13, the horizontal direction is the direction of crystal orientation <110>, and the vertical direction is the direction of crystal orientation <112>. The second trench 32 is formed in a direction along crystal orientation <112>.

[0136] When wet etching of the bottom of the second trench 32 to form the lateral trench 112 is initiated, the formation of the lateral trench 112 begins at the bottom of the second trench 32. The etching proceeds in the direction of the crystal orientation <110>, starting from the second trench 32. That is, in etching, a triangular cavity is formed in the semiconductor substrate 21, with the longitudinal direction of the second trench 32 as one side in a plan view, and the vertex being a position perpendicular to the midpoint of the longitudinal direction of the second trench 32. The etching proceeds so that the vertex of this triangle moves away from the second trench 32, as indicated by the white dotted arrow in the figure. On the other hand, the etching hardly progresses in the direction of the crystal orientation <112>.

[0137] As etching progresses further, a plane with the next orientation (111) appears on the etched surface, and the etching stops.

[0138] As a result, a lateral trench 112 is formed, starting from the second trench 32, and in a plan view, it is shaped like a rhombus (shown with diagonal lines in the figure) or a hexagon (shown with dashed lines).

[0139] Figure 14 is a plan view showing an example configuration of the first lateral trench 71 and the second lateral trench 72.

[0140] The first lateral trench 71 is formed in a hexagonal shape that extends over a 2x2 pixel unit in a plan view, with the horizontal x vertical dimensions being 2x2 pixels. The second lateral trench 72 is formed in a hexagonal shape that extends over a 2x2 pixel unit that is shifted diagonally by 1 pixel from the 2x2 pixels where the first lateral trench 71 is formed, in a plan view.

[0141] The first lateral trench 71 and the second lateral trench 72 are both hexagonal trenches, which, in plan view, have sides that are inclined from the longitudinal direction of the first trench 31 and the second trench 32, respectively.

[0142] As explained in Figure 11, the first lateral trench 71 is formed at a first depth in the semiconductor substrate 21, and the second lateral trench 72 is formed at a second depth in the semiconductor substrate 21, which is deeper than the first depth. Furthermore, in a plan view, the first lateral trench 71 is formed in a hexagonal shape in units of 2 x 2 pixels, and the second lateral trench 72 is formed in a hexagonal shape in units of 2 x 2 pixels, which are shifted by 1 pixel diagonally from the 2 x 2 pixels in which the first lateral trench 71 is formed.

[0143] Therefore, the first lateral trench 71 and the second lateral trench 72 are formed so as to cover the entire surface of each pixel 2 in a plan view, without colliding within the semiconductor substrate 21. As a result, as explained in Figure 11, the light-shielding film composed of the first lateral trench 71 and the second lateral trench 72 prevents the charge-holding portion 62 formed at the bottom of the photoelectric conversion region 61 from being visible from the upper part where light is incident on the pixel array portion 3, thereby preventing light from entering the charge-holding portion 62.

[0144] Furthermore, as explained in Figure 13, the first lateral trench 71 and the second lateral trench 72 can be configured in a hexagonal shape in plan view, or they can be configured in a rhombus (square) shape.

[0145] Figure 15 is a plan view showing an example of the configuration of a pixel array section 3 having a first lateral trench 71 and a second lateral trench 72.

[0146] In Figure 15, the pixel array section 3 has a first trench 31 that separates the pixels 2 vertically, and a second trench 32 that is longer than the first trench 31 that separates the pixels 2 horizontally.

[0147] The length of the first trench 31 is slightly less than the pixel pitch, and the length of the second trench 32 is slightly less than twice the pixel pitch. The width of the first trench 31, which is shorter in length than the second trench 32, is wider than the width of the second trench 32. As a result, the aspect ratio of the first trench 31 and the aspect ratio of the second trench 32 are appropriate aspect ratios that make the machining depth of the first trench 31 and the second trench 32 roughly the same. Furthermore, the first trench 31 and the second trench 32 are formed so as not to intersect.

[0148] Here, the two adjacent rows of the second trench 32 will be referred to as the first row and the second row, respectively. Furthermore, the second trench 32 formed in the first row will be described as second trench 32-1, and the second trench 32 formed in the second row will be described as second trench 32-2.

[0149] The second trench 32-1 in the first column, which has a length of slightly less than twice the pixel pitch, and the second trench 32-2 in the second column, which also has a length of slightly less than twice the pixel pitch, are formed to be in a positional relationship that is shifted vertically by one pixel.

[0150] The first transverse trench 71 is formed by etching starting from the second trench 32-1 of the first row, as described in Figures 12 and 13.

[0151] Specifically, the second trench 32-1 and the first trenches 31 adjacent to it on the left and right at the midpoint of the longitudinal direction of the second trench 32-1 are formed such that their processing depths are uniform to a first depth. Then, etching is performed starting from the second trench 32-1 at the first depth. The etching ends at the ends of the first trenches 31 adjacent to the second trench 32-1 on the left and right at the midpoint of the longitudinal direction of the second trench 32-1, and as a result, a hexagonal first lateral trench 71 is formed at the first depth.

[0152] A hexagonal first transverse trench 71 is formed at a first depth, and through this first transverse trench 71, the second trench 32-1, which served as the starting point for etching, and the first trench 31 adjacent to it on the left and right at the midpoint of the longitudinal direction of the second trench 32-1 are connected.

[0153] The second transverse trench 72 is formed by etching starting from the second trench 32-2 of the second row, as described in Figures 12 and 13.

[0154] Specifically, the second trench 32-2 and the first trenches 31 adjacent to it on the left and right at the midpoint of the longitudinal direction of the second trench 32-2 are formed such that their processing depths are uniformly reduced to a second depth which is deeper than the first depth. Then, etching is performed starting from the second trench 32-2 at the second depth. The etching ends at the ends of the first trenches 31 adjacent to the second trench 32-2 on the left and right at the midpoint of the longitudinal direction of the second trench 32-2, thereby forming a hexagonal second lateral trench 72 at the second depth.

[0155] A hexagonal second lateral trench 72 is formed at a second depth, and through this second lateral trench 72, the second trench 32-2, which was the starting point of etching, and the first trench 31, which is adjacent to the second trench 32-2 at its longitudinal midpoint, are connected.

[0156] Figure 16 is a plan view showing another configuration example of the pixel array section 3 having a first lateral trench 71 and a second lateral trench 72.

[0157] In Figure 16, the pixel array section 3 has a first trench 31 that separates the pixels 2 vertically, and a second trench 32 that is longer than the first trench 31 that separates the pixels 2 horizontally.

[0158] Furthermore, in Figure 16, similar to the cases of Figures 10B and C, the pixel array section 3, along with the first trench 31, has two identical third trenches 33-1 and 33-2, which are shorter than half the pixel pitch, for example, about one-third the pixel pitch in length, and serve as trenches to vertically separate the pixels 2 from each other. The first trench 31 and the third trenches 33-1 and 33-2 are formed alternately in each row, similar to the cases of Figures 10B and C.

[0159] Similar to the case in Figure 15, the length of the first trench 31 is slightly less than the pixel pitch, and the length of the second trench 32 is slightly less than twice the pixel pitch. The width of the first trench 31, which is shorter in length than the second trench 32, is wider than the width of the second trench 32. Also, the widths of the third trenches 33-1 and 33-2, which are about 1 / 3 the pixel pitch and shorter than the length of the first trench 31, are wider than the width of the first trench 31. As a result, the aspect ratios of the first trench 31, the second trench 32, and the third trenches 33-1 and 33-2 are appropriate aspect ratios that make the machining depth of the first trench 31 and the second trench 32 roughly uniform, and also appropriate aspect ratios that make the machining depth of the first trench 31 and the third trenches 33-1 and 33-2 roughly uniform.

[0160] Furthermore, the first trench 31 and the second trench 32 are formed so as not to intersect, and the first trench 31, as well as the third trenches 33-1 and 33-2, are also formed so as not to intersect.

[0161] In Figure 16, as in Figure 15, the second trench 32-1 in the first column, which has a length of slightly less than twice the pixel pitch, and the second trench 32-2 in the second column, which also has a length of slightly less than twice the pixel pitch, are formed to be offset vertically by one pixel.

[0162] In Figure 16, the trenches that vertically separate pixels 2 adjacent to each other at the midpoint of the longitudinal direction of the second trench 32-1 in the first column are the third trenches 33-1 and 33-2. Also, the trench that vertically separates pixels 2 adjacent to each other at the midpoint of the longitudinal direction of the second trench 32-2 in the second column is the first trench 31.

[0163] In Figure 16, the first transverse trench 71 is formed by etching starting from the second trench 32-1 of the first row, as described in Figures 12 and 13.

[0164] Specifically, the second trench 32-1 and the third trenches 33-1 and 33-2, which are adjacent to the second trench 32-1 on the left and right at the midpoint of the second trench 32-1 in the longitudinal direction, are formed such that their processing depths are uniform to a first depth. Then, etching is performed starting from the second trench 32-1 at the first depth. The etching ends at the ends of the third trenches 33-1 and 33-2, which are adjacent to the second trench 32-1 on the left and right at the midpoint of the second trench 32-1 in the longitudinal direction, furthest from the second trench 32-1, thereby forming a hexagonal first lateral trench 71 at the first depth.

[0165] A hexagonal first transverse trench 71 is formed at a first depth, and through this first transverse trench 71, the second trench 32-1, which served as the starting point for etching, is connected to the third trenches 33-1 and 33-2, which are adjacent to each other on the left and right at the midpoint of the longitudinal direction of the second trench 32-1.

[0166] The second transverse trench 72 is formed by etching starting from the second trench 32-2 of the second row, as described in Figures 12 and 13. That is, in Figure 16, the second transverse trench 72 is formed in the same way as in Figure 15.

[0167] Figure 17 is a diagram illustrating the method for forming the first lateral trench 71 and the second lateral trench of the pixel array section 3 shown in Figure 15.

[0168] First, by etching the semiconductor substrate 21, a second trench 32, that is, the second trench 32-1 of the first row and the second trench 32-2 of the second row, are formed to a depth somewhat shallower than the first depth. Although the first trench 31 is also formed when the second trench 32 is formed, the explanation of the first trench 31 will be omitted here.

[0169] Subsequently, the surface of the semiconductor substrate 21, including the second trenches 32-1 and 32-2, is subjected to hard mask processing to form the hard mask 151.

[0170] After hard mask processing, the hard mask 151 at the bottom of the second trenches 32-1 and 32-2 is removed, and the second trenches 32-1 and 32-2 are excavated to a desired depth by dry etching. Specifically, the second trench 32-1 is excavated to a first depth to form the first lateral trench 71, and the second trench 32-2 is excavated to a second depth, which is deeper than the first depth, to form the second lateral trench 72. The depths of the second trenches 32-1 and 32-2 are differentiated using resist.

[0171] Subsequently, a protective film 152 is formed on the surface of the semiconductor substrate 21, including the second trenches 32-1 and 32-2, by sidewall deposition, and the protective film 152 at the bottom of the second trenches 32-1 and 32-2 is removed by dry etching.

[0172] After removing the protective film 152 at the bottom of the second trenches 32-1 and 32-2, wet etching is performed from the bottom using an alkaline solution with different etching rates depending on the surface orientation. As a result, a first transverse trench 71 is formed starting from the second trench 32-1 at a first depth, and a second transverse trench 72 is formed starting from the second trench 32-2 at a second depth.

[0173] Subsequently, the second trenches 32-1 and 32-2 are uniformly deepened by dry etching.

[0174] Figure 18 is a cross-sectional view showing an example configuration of the first lateral trench 71 and the second lateral trench 72 when there is a large variation in the machining depth between the first trench 31 and the second trench 32.

[0175] For example, in the pixel array section 3 of Figure 15, if the variation in machining depth between the second trench 32-1 of the first row and the first trench 31 adjacent to it on the left and right at the midpoint of the longitudinal direction of the second trench 32-1 is greater than a predetermined variation, then a first lateral trench 71 is formed to connect the second trench 32-1 and the first trench 31 where the variation in machining depth is large. As a result, the thickness (length in the depth direction) of the first lateral trench 71 becomes thicker than when the variation in machining depth is small.

[0176] In the pixel array section 3 of Figure 15, if there is a large variation in the machining depth between the second trench 32-2 of the second row and the first trench 31 adjacent to it on the left and right at the midpoint of the longitudinal direction of the second trench 32-2, the thickness of the second lateral trench 72 will similarly increase.

[0177] When the thickness of the first lateral trench 71 and the second lateral trench 72 is thick, the transfer path for the charge obtained by photoelectric conversion in the photoelectric conversion region 61 to be transferred to the charge holding unit 62 becomes narrower (than when the variation in processing depth is small). When the charge transfer path is narrow, (the difficulty of charge transfer increases,) and problems may occur in transferring charge to the charge holding unit 62.

[0178] Figure 19 is a cross-sectional view showing an example configuration of the first lateral trench 71 and the second lateral trench 72 when the variation in machining depth between the first trench 31 and the second trench 32 is small.

[0179] For example, in the pixel array section 3 of Figure 15, if the variation in machining depth between the second trench 32-1 of the first row and the first trench 31 adjacent to it on the left and right at the midpoint of the longitudinal direction of the second trench 32-1 is small (less than a predetermined variation), then a first lateral trench 71 is formed to connect the second trench 32-1 and the first trench 31, where the variation in machining depth is small. As a result, the thickness of the first lateral trench 71 becomes thinner (than when the variation in machining depth is large).

[0180] In the pixel array section 3 of Figure 15, if the variation in machining depth between the second trench 32-2 of the second row and the first trench 31 adjacent to it on the left and right at the midpoint of the longitudinal direction of the second trench 32-2 is small, then similarly, the thickness of the second lateral trench 72 becomes thinner.

[0181] When the thickness of the first lateral trench 71 and the second lateral trench 72 is thin, the transfer path for the charge obtained by photoelectric conversion in the photoelectric conversion region 61 to be transferred to the charge holding section 62 becomes wider (than when there is a large variation in the processing depth). When the charge transfer path is wide, (charge transfer is improved,) and it is possible to suppress problems that may occur in the transfer of charge to the charge holding section 62.

[0182] <Example of electronic device configuration>

[0183] The above-described light detection device 1 can be applied to various electronic devices, such as imaging devices like digital still cameras and digital video cameras, mobile phones equipped with imaging functions, or game devices equipped with imaging functions.

[0184] Figure 20 is a block diagram showing an example of the configuration of an electronic device.

[0185] As shown in Figure 20, the electronic device 301 comprises an optical system 302, a photodetector 303, a DSP (Digital Signal Processor) 304, a display device 305, an operating system 306, a memory 307, a recording device 308, and a power supply system 309. The DSP 304, display device 305, operating system 306, memory 307, recording device 308, and power supply system 309 are interconnected via a bus 310. The electronic device 301 is, for example, an imaging device capable of capturing still images and moving images.

[0186] The optical system 302 is composed of one or more lenses and guides the image light (incident light) from the subject to the photodetector element 303, and forms an image on the light-receiving surface (sensor part) of the photodetector element 303.

[0187] The photodetector element 303 is configured as the photodetector device 1 described above. In the photodetector element 303, electrons are accumulated as signal charges for a certain period of time, corresponding to the image formed on the light-receiving surface via the optical system 302. A signal corresponding to the electrons accumulated in the photodetector element 303 is then supplied to the DSP 304.

[0188] The DSP 304 performs various signal processing on the signal from the photodetector 303 to generate an image, and temporarily stores the image data in the memory 307. The image data stored in the memory 307 is recorded in the recording device 308 or supplied to the display device 305 to display the image. The operation system 306 receives various operations from the user and supplies operation signals to each block of the electronic device 301, and the power supply system 309 supplies the power necessary to drive each block of the electronic device 301.

[0189] In the electronic device 301 configured in this way, by applying the above-described photodetector 1 as the photodetector element 303, various adverse effects that occur when the processing depth differs (significantly) between the trench that separates pixels vertically and the trench that separates them horizontally can be suppressed, such as the deterioration of optical characteristics and deterioration of element isolation as explained in Figures 7 and 8.

[0190] <Examples of image sensor usage>

[0191] Figure 21 shows an example of the use of the light detection device 1 described above.

[0192] The above-described light detection device 1 can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows.

[0193] - Devices that capture images for viewing purposes, such as digital cameras and portable devices with camera functions. - Devices used for traffic purposes, such as in-vehicle sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. - Devices used in home appliances such as TVs, refrigerators, and air conditioners that capture user gestures and allow device operation according to those gestures. - Devices used for medical and healthcare purposes, such as endoscopes and devices that perform angiography using infrared light reception. - Devices used for security purposes, such as surveillance cameras for crime prevention and cameras for person recognition. - Devices used for beauty purposes, such as skin measuring devices that capture images of skin and microscopes that capture images of the scalp. - Devices used for sports purposes, such as action cameras and wearable cameras for sports use. - Devices used for agriculture, such as cameras that monitor the condition of fields and crops.

[0194] Furthermore, the embodiments of this technology are not limited to those described above, and various modifications are possible without departing from the spirit of this technology.

[0195] Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also occur.

[0196] Furthermore, this technology can take the following configuration.

[0197] <1> A photodetector comprising a semiconductor substrate having a plurality of pixels that perform photoelectric conversion, a first trench that separates the pixels in a first direction in a plan view, and a second trench that separates the pixels in a second direction different from the first direction in a plan view, wherein the length of the second trench in the longitudinal direction is different from that of the first trench, and the width of the trench with the shorter length in the longitudinal direction is greater than the width of the other trench. <2> The photodetector according to <1>, wherein the first trench and the second trench are trenches formed from the front surface of the semiconductor substrate. <3> The photodetector according to <1>, wherein the first trench and the second trench are trenches formed from the back surface of the semiconductor substrate. <4> The photodetector according to any one of <1> to <3>, wherein the semiconductor substrate further has a planar trench extending in the planar direction when viewed from above, and the first trench and the second trench are connected via the planar trench. <5> The photodetector according to <4>, wherein the semiconductor substrate has a first trench having a length less than the pixel pitch and a third trench that is shorter in length and wider than the first trench, which separates the pixels from each other in a first direction when viewed from above. <6> The photodetector according to <5>, wherein the third trench is a trench having a length less than half the pixel pitch, and the semiconductor substrate has two of the third trenches formed with a gap between them in a portion corresponding to one side of the pixel, and the gap has an FD (floating diffusion) layer. <7> The optical detection device according to any one of <4> to <6>, wherein the planar trench is a polygonal trench having sides inclined from the longitudinal direction of the first trench and the second trench in a planar view. <8> The optical detection device according to <7>, wherein the planar trench is arranged alternately at different depths of the pixels in a cross-sectional view. <9> The optical detection device according to any one of <1> to <8>, wherein the first trench separates the pixels in the vertical direction as the first direction, and the second trench separates the pixels in the horizontal direction as the second direction.<10> The first trench and the second trench do not intersect. The photodetector according to any one of <1> to <9>. <11> The photodetector according to any one of <1> to <10>, wherein the first trench is a trench with a length less than the pixel pitch, and the second trench is a trench with a length approximately twice or more the pixel pitch. <12> A method for manufacturing the photodetector, comprising a semiconductor substrate having a plurality of pixels that perform photoelectric conversion, a first trench that separates the pixels from each other in a first direction in a plan view, and a second trench that separates the pixels from each other in a second direction different from the first direction in a plan view, wherein the second trench is formed to have a different longitudinal length from the first trench, and the trench with the shorter length among the first trench and the second trench is formed to have a width that is wider in the short direction than the width of the other trench. <13> An electronic device comprising a semiconductor substrate having a plurality of pixels that perform photoelectric conversion, a first trench that separates the pixels in a first direction in a plan view, and a second trench that separates the pixels in a second direction different from the first direction in a plan view, wherein the length of the second trench in the longitudinal direction is different from that of the first trench, and the width of the trench with the shorter length in the short direction of the first trench and the second trench is wider than the width of the other trench, an optical detection device, and a processing unit that processes the signal output by the optical detection device.

[0198] 1. Photodetector, 2. Pixel, 3. Pixel array section, 4. Vertical drive circuit, 5. Column signal processing circuit, 6. Horizontal drive circuit, 7. Output circuit, 8. Control circuit, 9. Vertical signal line, 10. Pixel drive wiring, 11. Horizontal signal line, 13. Input / output terminals, 21. Semiconductor substrate, 31. First trench, 32. Second trench, 32. Second trench, 33. Third trench, 33. Third trench, 33. Photoelectric conversion region, 62. Charge holding section, 71. First lateral trench, 72. Second lateral trench, 81. Insulating film, 82. Planarization film, 91. Color filter, 92. OCL, 111. Insulating film, 112. Lateral trench, 151. Hard mask, 152. Protective film, 301. Electronic equipment, 302. Optical system. 303 Photodetector, 304 DSP, 305 Display device, 306 Operating system, 307 Memory, 308 Recording device, 309 Power supply system, 310 Bus

Claims

1. A light detection device comprising a semiconductor substrate having a plurality of pixels that perform photoelectric conversion, a first trench that separates the pixels in a first direction in a plan view, and a second trench that separates the pixels in a second direction different from the first direction in a plan view, wherein the length of the second trench in the longitudinal direction is different from that of the first trench, and the width of the shorter trench of the first trench and the second trench is wider than the width of the other trench.

2. The photodetector according to claim 1, wherein the first trench and the second trench are trenches formed from the front surface of the semiconductor substrate.

3. The photodetector according to claim 1, wherein the first trench and the second trench are trenches formed from the back surface of the semiconductor substrate.

4. The photodetector according to claim 1, wherein the semiconductor substrate further has planar trenches extending in a planar direction when viewed from above, and the first trench and the second trench are connected via the planar trenches.

5. The photodetector according to claim 4, wherein the semiconductor substrate has a first trench having a length less than the pixel pitch and a third trench that is shorter in length and wider than the first trench, which serve as trenches separating the pixels in a first direction in a plan view.

6. The photodetector according to claim 5, wherein the third trench is a trench with a length of less than half the pixel pitch, and the semiconductor substrate has two of the third trenches formed with a gap between them in a portion corresponding to one side of the pixel, and the gap has an FD (floating diffusion) layer.

7. The light detection device according to claim 4, wherein the planar trench is a polygonal trench having sides inclined from the longitudinal direction of the first trench and the second trench in a plan view.

8. The light detection device according to claim 7, wherein the planar trenches are arranged alternately at different depths of the pixels in a cross-sectional view.

9. The light detection device according to claim 1, wherein the first trench separates the pixels in the vertical direction as the first direction, and the second trench separates the pixels in the horizontal direction as the second direction.

10. The light detection device according to claim 1, wherein the first trench and the second trench do not intersect.

11. The photodetector according to claim 1, wherein the first trench is a trench with a length less than the pixel pitch, and the second trench is a trench with a length approximately twice or more the pixel pitch.

12. A method for manufacturing a photodetector comprising a semiconductor substrate having a plurality of pixels that perform photoelectric conversion, a first trench that separates the pixels in a first direction in a plan view, and a second trench that separates the pixels in a second direction different from the first direction in a plan view, wherein the second trench is formed to have a different longitudinal length from the first trench, and the trench with the shorter length of the first trench and the second trench is formed to have a width in the shorter direction that is wider than the width of the other trench.

13. An electronic device comprising a semiconductor substrate having a plurality of pixels that perform photoelectric conversion, a first trench that separates the pixels in a first direction in a plan view, and a second trench that separates the pixels in a second direction different from the first direction in a plan view, wherein the second trench has a different longitudinal length from the first trench, and the width of the shorter of the two trenches is greater than the width of the other trench, a photodetector, and a processing unit that processes the signal output by the photodetector.

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