Semiconductor apparatus

Abstract

The present disclosure relates to a semiconductor apparatus that makes it possible to improve the characteristics of a semiconductor device. Provided is a semiconductor apparatus having a semiconductor structure including at least one layer of a conductive film, in which a two-dimensional conductive film is used for at least one layer of a thin film that covers a side wall and a bottom surface in the conductive film, and, in a second direction perpendicular to a first direction which is the thickness direction of the semiconductor structure, the conductive film is in contact with an etch stop layer that divides the semiconductor structure in the first direction. The present disclosure can be applied to, for example, a laminate in which semiconductor substrates or semiconductor chips are arbitrarily combined.

Description

Semiconductor device

[0001] The present disclosure relates to semiconductor devices, and particularly relates to a semiconductor device configured to be capable of improving characteristics of semiconductor devices.

[0002] In semiconductor devices, it is known that characteristics of semiconductor devices such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) change when exposed to gas molecules such as hydrogen, and various structures have been proposed as countermeasures against this phenomenon.

[0003] For example, Patent Document 1 discloses a structure in which a diffusion prevention film made of a material suitable for preventing hydrogen diffusion is inserted between a first semiconductor substrate having a pixel portion and a second semiconductor substrate having a logic circuit.

[0004] International Publication No. 2014 / 050694

[0005] In conventional semiconductor devices, diffusion of gas molecules such as hydrogen cannot be suppressed, and there is a risk that characteristics of semiconductor devices may deteriorate. Therefore, there has been a demand for proposals of structures for improving characteristics of semiconductor devices.

[0006] The present disclosure has been made in view of such circumstances, and aims to enable improvement of characteristics of semiconductor devices.

[0007] A semiconductor device according to one aspect of the present disclosure has a semiconductor structure including at least one conductive film, a two-dimensional conductive film is used for at least one of thin films covering sidewalls and a bottom surface in the conductive film, and the conductive film is in contact with an etch stop layer that separates the semiconductor structure in a first direction which is the thickness direction of the semiconductor structure, in a second direction which is a direction perpendicular to the first direction.

[0008] Note that the semiconductor device according to one aspect of the present disclosure may be an independent device, or may be an internal block that constitutes a single device.

[0009] This figure shows an example configuration of one embodiment of a semiconductor device to which the present disclosure is applied. This is a cross-sectional view showing the semiconductor structure of a conventional semiconductor device. This is a cross-sectional view showing the semiconductor structure of a conventional semiconductor device. This is a cross-sectional view showing an example of a semiconductor structure in a semiconductor device to which the present disclosure is applied. This is a cross-sectional view showing an example of a semiconductor structure with an embedded two-dimensional conductive film. This is an enlarged cross-sectional view of a part of the structure of the conductive film in Figure 5. This is a figure showing an example of a detailed structure of the conductive film in Figure 6. This is a figure showing another example of the structure of the conductive film in Figure 5. This is a figure showing an example configuration of a semiconductor device configured as a single-layer semiconductor chip. This is a figure showing an example configuration of a semiconductor device configured as a semiconductor chip formed by stacking two semiconductor substrates. This is a figure showing an example configuration of a semiconductor device configured by stacking multiple semiconductor chips. This is a figure showing an example configuration of a semiconductor device configured as a semiconductor chip formed by stacking multiple semiconductor substrates. This is a cross-sectional view showing an example of a semiconductor structure in a semiconductor device to which the present disclosure is applied. This is a figure showing an example of applying the structure of the present disclosure when forming wiring using dual damascene. This is a figure showing an example of applying the structure of the present disclosure when forming wiring using single damascene. This is a figure showing an example of a semiconductor structure in which the structure of the present disclosure is applied to global wiring. This is a figure showing an example of a semiconductor structure in which the structure of the present disclosure is applied to semi-global wiring. This is a figure showing a first example of a semiconductor structure in which the structure of the present disclosure is applied to intermediate wiring. This figure shows a second example of a semiconductor structure in which the structure of the present disclosure is applied to intermediate wiring. This figure shows an example of a semiconductor structure in which the structure of the present disclosure is applied to local wiring. This figure shows an example of a semiconductor structure in which the structure of the present disclosure is applied to contact wiring. This figure shows an example of a semiconductor structure in which two semiconductor substrates are stacked and the structure of the present disclosure is applied to the lower layer. This figure shows an example of a semiconductor structure in which two semiconductor substrates are stacked and the structure of the present disclosure is applied to the upper layer. This figure shows an example of a semiconductor structure in which two semiconductor substrates are stacked and the structure of the present disclosure is applied to both the upper and lower layers. This figure shows an example of a semiconductor structure in which multiple semiconductor chips are stacked and the structure of the present disclosure is applied to the upper layer. This figure shows an example of a semiconductor structure in which multiple semiconductor chips are stacked and the structure of the present disclosure is applied to the lower layer. This figure shows an example of a semiconductor structure in which multiple semiconductor chips are stacked and the structure of the present disclosure is applied to a part of the lower layer.This figure shows an example of a semiconductor structure in which three semiconductor substrates are stacked and the structure of the present disclosure is applied to the middle layer. This figure shows an example of a semiconductor structure in which three semiconductor substrates are stacked and the structure of the present disclosure is applied to the bottom layer. This figure shows an example of a semiconductor structure in which three semiconductor substrates are stacked and the structure of the present disclosure is applied to the middle and bottom layers. This figure shows an example of a semiconductor structure in which three semiconductor substrates are stacked and the structure of the present disclosure is applied to through-silicon vias. This figure shows an example of a semiconductor structure in which three semiconductor substrates are stacked and the structure of the present disclosure is applied to back-side wiring. This figure shows a first example of a semiconductor structure in which application and non-application areas are mixed within the same planar wiring layer. This figure shows an example of the configuration of a semiconductor device having the semiconductor structure of Figure 33. This figure shows a second example of a semiconductor structure in which application and non-application areas are mixed within the same planar wiring layer. This figure shows an example of a semiconductor structure in which the structure of the present disclosure is applied to the structure of the circuit body and seal ring. This figure shows an example of a semiconductor structure in which the structure of the present disclosure is applied to a single-layer semiconductor chip. This figure shows an example of a semiconductor structure in which the structure of the present disclosure is used in a structure in which multiple semiconductor chips are stacked. This figure shows an example of a structure in which a two-dimensional conductive film is used as a cap material. This figure shows another example of a semiconductor structure in which the structure of the circuit body and seal ring is applied to the structure of the present disclosure. This figure shows an example of a semiconductor structure in which the structure of the circuit body, seal ring and partition is applied to the structure of the circuit body and seal ring and partition. This figure illustrates a structure of the present disclosure that protects semiconductor devices and wiring from various gas molecules. This is a plan view showing a first example of the shape of the seal ring and partition. This is a plan view showing a second example of the shape of the seal ring and partition. This is a plan view showing a third example of the shape of the seal ring and partition. This figure illustrates the state of a semiconductor structure before heat treatment in which an interlayer insulating film containing an arbitrary gas is formed. This figure illustrates the state of a semiconductor structure after heat treatment in which an interlayer insulating film containing an arbitrary gas is formed.

[0010] <Semiconductor Structure of the Disclosure> Figure 1 is a diagram showing an example configuration of one embodiment of a semiconductor device to which the disclosure is applied.

[0011] As shown in Figure 1, the semiconductor device 1 is constructed by bonding together a semiconductor substrate 11 having a semiconductor structure and a semiconductor substrate 12 having a semiconductor structure. That is, the semiconductor substrates 11 and 12 are stacked and electrically connected.

[0012] Details of the semiconductor structure in semiconductor substrates 11 and 12 will be described. Here, for comparison, the conventional structure will be described with reference to Figures 2 and 3, and then the structure of the present disclosure will be described with reference to Figure 4.

[0013] Figures 2 and 3 are cross-sectional views showing the semiconductor structure of a conventional semiconductor device. In Figures 2 and 3, semiconductor substrates 11 and 12 are stacked, and their bonding surface is indicated by the dashed line in the figures.

[0014] As shown in Figure 2, the semiconductor substrate 11 has a semiconductor layer 21 and a multilayer wiring layer 22. Conductive films 23, such as wiring and vias, are formed on the multilayer wiring layer 22. In the multilayer wiring layer 22, an interlayer film 24 made of an insulating film is formed in the portion where the conductive film 23 is not present. MOS transistors 25 are provided on the semiconductor layer 21. The MOS transistors 25 are N-channel or P-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors).

[0015] The semiconductor substrate 12 has a semiconductor layer 31 and a multilayer wiring layer 32. Conductive films 33, such as wiring and vias, are formed on the multilayer wiring layer 32. In the multilayer wiring layer 32, an interlayer film 34 made of an insulating film is formed in the portion where the conductive film 33 is not present. A MOS transistor 35, which is an N-channel or P-channel MOSFET, is provided on the semiconductor layer 31.

[0016] The multilayer wiring layer 22 of the semiconductor substrate 11 and the multilayer wiring layer 32 of the semiconductor substrate 12 are bonded together by the dashed lines in the figure, and the conductive film 23 and interlayer film 24 of the multilayer wiring layer 22 and the conductive film 33 and interlayer film 34 of the multilayer wiring layer 32 are bonded at the bonding surface.

[0017] It is known that semiconductor devices such as MOSFETs change their properties when exposed to gas molecules such as hydrogen. For example, semiconductor devices change various properties depending on the amount of hydrogen they are exposed to. Specifically, the hydrogen sensitivity of a MOSFET is as follows:

[0018] In other words, stress tolerance (reliability) worsens as the hydrogen content increases and improves as the hydrogen content decreases. Threshold voltage fluctuations increase as the hydrogen content increases and decrease as the hydrogen content decreases. Driving force (Gm) increases as the hydrogen content increases and decreases as the hydrogen content decreases. Interface states improve as the hydrogen content increases and worsen as the hydrogen content decreases. Thus, each characteristic of the MOSFET is in a trade-off relationship with respect to the hydrogen content.

[0019] In Figure 2, circles labeled with the letter "H" represent hydrogen, and as indicated by the arrows in the figure, the conductive film 23 and interlayer film 24 in the multilayer wiring layer 22, and the conductive film 33 and interlayer film 34 in the multilayer wiring layer 32, act as hydrogen diffusion pathways, allowing hydrogen to diffuse to both the semiconductor layer 21 and the semiconductor layer 31. In particular, conductive films 23 and 33 in wiring and vias are made of common metal materials, but these have poor hydrogen barrier properties. When hydrogen is supplied, the wiring acts as a hydrogen diffusion pathway, making it impossible to separate the amount of hydrogen between each layer of the semiconductor substrate 11 and each layer of the semiconductor substrate 12.

[0020] In a semiconductor device 1 formed by stacking semiconductor substrates 11 and 12, each substrate has a distinct role and function, requiring optimization of its characteristics. For example, in semiconductor substrate 11, it may be desirable to reduce the amount of hydrogen to prioritize the high reliability of the MOSFET, while in semiconductor substrate 12, it may be desirable to increase the amount of hydrogen to prioritize the driving force of the MOSFET. Therefore, in order to independently control the amount of hydrogen reaching each layer of each substrate according to the characteristic target of the semiconductor device (MOSFET, etc.) on each substrate, it is necessary to realize a wiring structure with hydrogen barrier properties.

[0021] In Figure 3, an etch stop layer 51 is formed on the multilayer wiring layer 22 of the semiconductor substrate 11. The etch stop layer (ESL) 51 is a layer used to protect the substrate and other layers during a specific etching process. As the material for the etch stop layer 51, hydrogen-sealing materials such as silicon nitride (SiN) and aluminum oxide (AlO) can be used to suppress hydrogen diffusion in the insulating layer.

[0022] As shown in Figure 3, the semiconductor substrate 11 can be structured to form a hydrogen-sealing etch-stop layer 51 in the horizontal direction of the multilayer wiring layer 22. This prevents hydrogen from moving between the interlayer film 24 and the interlayer film 34, and is an effective means of independently controlling the amount of hydrogen reaching each layer of each substrate according to the characteristic target of the semiconductor device (MOSFET, etc.) of each substrate. However, in the semiconductor structure shown in Figure 3, although it is possible to reduce the amount of hydrogen moving between the interlayer film 24 and the interlayer film 34, the general metal materials used for conductive films 23 and 33 such as wiring and vias have poor hydrogen barrier properties. Therefore, when hydrogen is supplied, the wiring may become a hydrogen diffusion path, and there is a risk that the amount of hydrogen cannot be separated for each layer of the substrate.

[0023] Thus, in conventional semiconductor structures for semiconductor devices, the diffusion of gas molecules such as hydrogen cannot be completely suppressed. When gas molecules are supplied, the wiring acts as a diffusion path, making it impossible to separate the gas molecules from each substrate layer. As a result, the diffusion of gas molecules such as hydrogen cannot be suppressed, which may lead to a deterioration in the performance of semiconductor devices on each substrate. Therefore, this disclosure proposes a structure that can improve the performance of semiconductor devices.

[0024] Figure 4 is a cross-sectional view showing an example of a semiconductor structure in a semiconductor device to which the present disclosure is applied. In Figure 4, the same reference numerals are used for parts corresponding to those in Figures 2 and 3, and their descriptions are omitted as appropriate.

[0025] As shown in Figure 4, the semiconductor device 1 is constructed by stacking a semiconductor substrate 11 and a semiconductor substrate 12. On the semiconductor substrate 11, an etch stop layer 51 is provided on the multilayer wiring layer 22. In addition, on the multilayer wiring layer 22, at least one of the thin films covering the side walls and bottom surface within the conductive film 23 is a two-dimensional conductive film 61.

[0026] The two-dimensional conductive film 61 may be, for example, graphene, graphene oxide, or a transition metal dichalcogenide. The two-dimensional conductive film used in the two-dimensional conductive film 61 may also contain semiconductors. More specifically, the two-dimensional conductive film may include single-layer graphene, multi-layer graphene, graphene oxide, molybdenum sulfide (MoS2), tungsten sulfide (WS2), hexagonal boron nitride (h-BN), two-dimensional layered perovskite, germanene, MXene, and the like.

[0027] Furthermore, when suppressing the diffusion of hydrogen as a gas molecule, it is more preferable to apply multilayer graphene from the viewpoint of achieving both hydrogen blocking properties and conductivity. A two-dimensional conductive film 61 using graphene such as multilayer graphene can achieve both hydrogen barrier properties and conductivity with an extremely thin film thickness, thus enabling the realization of a wiring structure effective in suppressing hydrogen diffusion. Specifically, graphene has high conductivity, such as 1.3 times that of Cu, 30 times that of TiN, and 150 times that of TaN. In addition, graphene has a permeation flux of 10 times that of TiN. -8 It is estimated to have a high hydrogen barrier property, such as twice the amount of hydrogen.

[0028] The conductive film 23, which uses a two-dimensional conductive film 61, is in contact with the etch stop layer 51 in the horizontal direction. The horizontal direction is perpendicular to the thickness direction of the semiconductor structure of the substrate, such as the semiconductor substrate 11. The vertical direction is the thickness direction of the semiconductor structure of the substrate. The etch stop layer 51 separates the semiconductor structure in the thickness direction.

[0029] The etch stop layer 51 is composed of an insulating film having gas sealing properties (e.g., hydrogen sealing properties). The etch stop layer 51 can be any combination of oxides, nitrides, and carbides of semiconductors and metal elements. More specifically, the etch stop layer 51 can be, for example, silicon nitride (SiN), silicon oxide nitride (SiON), silicon carbide nitride (SiCN), silicon oxide carbide nitride (SiCON), aluminum oxide (AlO), aluminum nitride (AlN), hafnium oxide (HfO), zirconium oxide (ZrO), lanthanum oxide (LaO), etc.

[0030] As shown in Figure 4, by using a two-dimensional conductive film 61 as a thin film covering the side walls and bottom surface within the conductive film 23 on the semiconductor substrate 11, hydrogen diffusion is suppressed as indicated by the arrows in the figure, because the wiring does not become a hydrogen diffusion path. This structure realizes a wiring structure with hydrogen barrier properties. In this way, by covering the bottom and sides of the wiring and vias with the two-dimensional conductive film 61, and by forming an etch-stop layer 51, which is a gas-sealing insulating layer, around the two-dimensional conductive film 61, the diffusion of gas molecules such as hydrogen can be suppressed, and the characteristics (reliability, etc.) of the semiconductor device can be improved.

[0031] Here, with reference to Figures 5 to 8, the details of the two-dimensional conductive film 61 will be described. Figure 5 is a cross-sectional view showing an example of a semiconductor structure in which the two-dimensional conductive film 61 is embedded. As shown in Figure 5, in the semiconductor structure of the semiconductor device 1, the two-dimensional conductive film 61 is used in at least one thin film covering the side and bottom surfaces of the conductive film 23, for at least one layer of conductive film 23. Specifically, the two-dimensional conductive film 61 is used in the thin film covering the side and bottom surfaces of the conductive film 23A. Furthermore, the conductive film 23A in which the two-dimensional conductive film 61 is used is in contact with the etch stop layer 51 in the horizontal direction. Hereinafter, this structure will also be referred to as the structure of the present disclosure.

[0032] Figure 6 is an enlarged cross-sectional view of a portion of the conductive film 23A in Figure 5. As shown in Figure 6, the two-dimensional conductive film 61 is used as a thin film covering the sides and bottom surface within the conductive film 23A. For example, graphene is known to be able to be selectively grown on metallic materials, and by utilizing this property, a two-dimensional conductive film 61 can be formed by depositing graphene in a barrier-like manner, so as to cover the inside of wiring or vias. By covering the in-plane with the two-dimensional conductive film 61 and the etch-stop layer 51 formed around it, the diffusion of gas molecules in the vertical direction (hydrogen diffusion) can be suppressed.

[0033] In Figure 6, when the region within frame A, indicated by the dashed line, is magnified, it becomes as shown in Figure 7. In Figure 7, the two-dimensional conductive film 61 is used as at least one layer of thin film covering the side and bottom surfaces within the conductive film 23A. Specifically, for example, when the conductive film 23A as a wiring metal includes a bulk wiring layer 65 and a thin film layer 66, the thin film layer 66 covering the side and bottom surfaces within the conductive film 23A is composed of a barrier metal 62, a two-dimensional material seed layer 63, a two-dimensional conductive film 61, and a wiring seed layer 64.

[0034] When considering the barrier metal 62 and two-dimensional material seed layer 63 formed on the outermost periphery, the two-dimensional conductive film 61 and the etch stop layer 51 are in a structure where they do not come into direct contact. Even with such a structure, vertical hydrogen diffusion can be reduced compared to when the two-dimensional conductive film 61 is not provided.

[0035] Figure 8 is a cross-sectional view showing another example of the structure of the conductive film 23A in Figure 5. In Figure 8, the thin film covering the sides and bottom of the conductive film 23A is composed of a two-dimensional conductive film 61 and a wiring seed layer 64, and the two-dimensional conductive film 61 is used as at least one layer of the thin film covering the sides and bottom of the conductive film 23A. That is, in the conductive film 23A, the structure may not include a barrier metal 62 or a two-dimensional material seed layer 63 formed on the outermost periphery as the thin film covering the sides and bottom, and the two-dimensional conductive film 61 and the etch stop layer 51 may be in direct physical contact.

[0036] Thus, the etch stop layer 51 may be in direct physical contact with the two-dimensional conductive film 61, or it may include a thin film of at least one of the conductive film and the insulating film between itself and the two-dimensional conductive film 61. For the sake of simplification, the barrier metal 62 and the two-dimensional material seed layer 63 will be omitted in the following description.

[0037] <Chip Configuration> In the above description, the semiconductor device 1 was described as being constructed by stacking semiconductor substrates 11 and 12. However, other configurations such as single-layer or multi-layer stacking may also be used. In other words, the semiconductor structure of the semiconductor device 1 may be a stack of semiconductor substrates (including semiconductor wafers) or semiconductor chips in any combination.

[0038] Figure 9 shows an example of the configuration of a semiconductor device configured as a single-layer semiconductor chip. In Figure 9, the semiconductor device 1A is configured as a single-layer semiconductor chip including an analog circuit 11A-1 and a logic circuit 11A-2. The analog circuit 11A-1 is an electronic circuit that processes analog signals. The logic circuit 11A-2 is an electronic circuit that processes digital signals.

[0039] The analog circuit 11A-1 and the logic circuit 11A-2 are electrically connected, and at least one of the thin films covering the sides and bottom of the conductive film within the semiconductor structure is a two-dimensional conductive film, which is in contact with the etch stop layer in the horizontal direction of the conductive film. With this structure, for example, if the characteristic target of the analog circuit 11A-1 is low noise and the characteristic target of the logic circuit 11A-2 is highly reliable, the hydrogen content of the analog circuit 11A-1 can be increased while the hydrogen content of the logic circuit 11A-2 can be decreased.

[0040] Figure 10 shows an example of the configuration of a semiconductor device configured as a semiconductor chip formed by stacking two semiconductor substrates. In Figure 10, the semiconductor device 1B is configured by stacking a logic circuit 11B and a pixel circuit 12B. The logic circuit 11B is an electronic circuit that processes digital signals from the pixel circuit 12B. The pixel circuit 12B is an electronic circuit in which multiple pixels are formed, including photoelectric conversion units such as photodiodes.

[0041] The logic circuit 11B and the pixel circuit 12B are electrically connected, and at least one of the thin films covering the sides and bottom of the conductive film within the semiconductor structure is a two-dimensional conductive film, which is in contact with the etch stop layer in the horizontal direction of the conductive film. With this structure, for example, if the characteristic target of the logic circuit 11B is highly reliable and the characteristic target of the pixel circuit 12B is low noise, the amount of hydrogen in the logic circuit 11B can be reduced and the amount of hydrogen in the pixel circuit 12B can be increased. In particular, by reducing noise in the pixel circuit 12B, the image quality of the captured image can be improved.

[0042] FIG. 11 is a diagram showing a configuration example of a semiconductor device configured by stacking a plurality of semiconductor chips. In FIG. 11, the semiconductor device 1C is configured by stacking a logic circuit 11C-1, an external chip 11C-2, and a pixel circuit 12C. The logic circuit 11C-1 is an electronic circuit that processes digital signals from the pixel circuit 12C. The pixel circuit 12C is an electronic circuit in which a plurality of pixels are formed. The logic circuit 11C-1 and the pixel circuit 12C are stacked to form a semiconductor chip. The external chip 11C-2 is an electronic circuit that performs predetermined signal processing. The external chip 11C-2 may be manufactured by a different manufacturer from the semiconductor chip including the logic circuit 11C-1 and the pixel circuit 12C.

[0043] The logic circuit 11C-1, the external chip 11C-2, and the pixel circuit 12C are electrically connected. For at least one layer of conductive film in the semiconductor structure, a two-dimensional conductive film is used for at least one layer of a thin film covering a side surface and a bottom surface in the conductive film, and is in contact with an etch stop layer in the horizontal direction of the conductive film. With such a structure, for example, when the characteristic target of the logic circuit 11C-1 is high reliability and the characteristic target of the pixel circuit 12C is low noise, the amount of hydrogen in the logic circuit 11C-1 can be reduced and the amount of hydrogen in the pixel circuit 12C can be increased. In particular, in the pixel circuit 12C, noise can be reduced and the image quality of a captured image can be improved. Further, it is also possible to realize a hydrogen amount corresponding to the characteristic target of the external chip 11C-2. The number of stacked semiconductor chips is not limited to two, and may be three or more.

[0044] FIG. 12 is a diagram showing a configuration example of a semiconductor device configured as a semiconductor chip in which semiconductor substrates are stacked in multiple layers. In FIG. 12, the semiconductor device 1D is configured by stacking, for example, a logic circuit 11D, an analog circuit 12D, and a pixel circuit 13D. The logic circuit 11D is an electronic circuit that processes a digital signal obtained by converting an analog signal from the analog circuit 12D. The analog circuit 12D is an electronic circuit that processes an analog signal from the pixel circuit 13D. The pixel circuit 13D is an electronic circuit in which a plurality of pixels are formed.

[0045] The analog circuit 12D is electrically connected to each of the logic circuit 11D and the pixel circuit 13D. For at least one layer of conductive film in the semiconductor structure, a two-dimensional conductive film is used for at least one layer of a thin film covering a side surface and a bottom surface within the conductive film, and the conductive film is in contact with an etch stop layer in a horizontal direction thereof. With such a structure, for example, when the characteristic target of the logic circuit 11D is high reliability, and the characteristic targets of the analog circuit 12D and the pixel circuit 13D are low noise, the hydrogen content of the logic circuit 11D can be reduced, and the hydrogen content of the analog circuit 12D and the pixel circuit 13D can be increased. In particular, in the analog circuit 12D and the pixel circuit 13D, noise can be reduced, thereby improving the image quality of captured images. Note that the number of stacked semiconductor substrates is not limited to three layers, and may be four or more layers.

[0046] <Wiring and Via Configuration> FIG. 13 is a cross-sectional view showing an example of a semiconductor structure in a semiconductor device to which the present disclosure is applied. In the semiconductor structure of FIG. 13, among the conductive films 23, a two-dimensional conductive film 61 is used for a thin film that covers the side surface and the bottom surface of the conductive film 23A. The conductive film 23A is in contact with an etch stop layer 51 in the horizontal direction. As shown in FIGS. 14 and 15, the two-dimensional conductive film 61 can be applied to at least one of a wiring and a via.

[0047] FIG. 14 is a diagram showing an example where the structure of the present disclosure is applied when wiring is formed using dual damascene. When dual damascene is used, after a wiring trench and a via hole (a wiring trench connecting an upper-layer wiring and a lower-layer wiring) are formed on an insulating film, a wiring metal material is deposited to fill both at the same time, and polishing is performed to leave the wiring metal in the trench, thereby forming the wiring. Therefore, as shown in FIG. 14, the conductive film 23A is composed of a wiring 71 and a via 72, and the two-dimensional conductive film 61 is used for a thin film covering the side walls and bottom surfaces of the wiring 71 and the via 72. The via 72 is a connecting conductor that connects the upper-layer wiring and the lower-layer wiring. The etch stop layer 51 is in contact with the conductive film 23A composed of the wiring 71 and the via 72 in the horizontal direction.

[0048] Figure 15 shows an example of applying the structure of the present disclosure when forming wiring using single damascene. When using single damascene, wiring grooves are formed on an insulating film, then wiring metal is deposited and polished to leave the wiring metal in the grooves and form the wiring, but the wiring grooves and via holes are formed separately. Therefore, as shown in Figure 15, the conductive film 23A consists of wiring 73 or vias 74, and a two-dimensional conductive film 61 is used as a thin film covering the side walls and bottom surfaces of the wiring 73 or vias 74. The etch stop layer 51 is in contact with the conductive film 23A consisting of wiring 73 or vias 74 in the horizontal direction.

[0049] <Front-end / Back-end wiring and vias> The structures of the present disclosure can be applied to at least one of the wiring and vias formed in the front-end (substrate process) or back-end (wiring process).

[0050] Figure 16 shows an example of a semiconductor structure in which the structure of the present disclosure is applied to global wiring. Global wiring is a long-distance wiring used to transmit power and signals, and is arranged in a predetermined direction such as the horizontal direction. In Figure 16, a two-dimensional conductive film 61 is used as a thin film covering the wiring and the side walls and bottom surfaces of vias that constitute the global wiring 81. The global wiring 81 is in contact with the etch stop layer 51 in the horizontal direction.

[0051] Figure 17 shows an example of a semiconductor structure in which the structure of the present disclosure is applied to semi-global wiring. Semi-global wiring is a long-distance wiring used to transmit power and signals, and is shorter in distance than global wiring. In Figure 17, a two-dimensional conductive film 61 is used as a thin film covering the wiring and the side walls and bottom surfaces of vias that constitute the semi-global wiring 82. The semi-global wiring 82 is in contact with the etch stop layer 51 in the horizontal direction.

[0052] Figures 18 and 19 show examples of semiconductor structures in which the structure of the present disclosure is applied to intermediate wiring. Intermediate wiring is wiring (interlayer wiring) for electrically connecting elements formed in semiconductor layers, etc. In Figure 18, a two-dimensional conductive film 61 is used as a thin film covering the wiring and the sidewall and bottom surface of the via that constitutes the intermediate wiring 83. In Figure 19, a two-dimensional conductive film 61 is used as a thin film covering the wiring and the sidewall and bottom surface of the via that constitutes the intermediate wiring 84. In Figures 18 and 19, the etch stop layer 51 is in contact with the intermediate wiring 83 and intermediate wiring 84 in the horizontal direction.

[0053] Figure 20 shows an example of a semiconductor structure in which the structure of the present disclosure is applied to local wiring. Local wiring is short-distance wiring used to transmit power and signals, and is arranged in a predetermined direction such as the horizontal direction. In Figure 20, a two-dimensional conductive film 61 is used as a thin film covering the side walls and bottom surfaces of the wiring constituting the local wiring 85. The local wiring 85 is in contact with the etch stop layer 51 in the horizontal direction.

[0054] Figure 21 shows an example of a semiconductor structure in which the structure of the present disclosure is applied to contact wiring. Contact wiring is wiring used to connect, for example, conductive layers, gate electrodes, upper layer wiring, etc. In Figure 21, a two-dimensional conductive film 61 is used as a thin film covering the side walls and bottom surfaces of the wiring constituting the contact wiring 86. The contact wiring 86 is in contact with the etch stop layer 51 in the horizontal direction.

[0055] Thus, the two-dimensional conductive film 61 can be used on at least one of any wiring and vias in at least one layer of wiring and vias formed in the front end or back end. In particular, in fine regions such as local wiring and contact wiring, it has been difficult to maintain hydrogen blocking properties with conventional thin-film embedding of metal films, but by applying the structure of the present disclosure and providing the two-dimensional conductive film 61, a hydrogen blocking structure can be realized.

[0056] <Two-Layer Stacked Wiring and Vias> The structure of the present disclosure can be applied to at least one of wiring and vias that connect different semiconductor surfaces (junction surfaces). Figures 22 to 24 show the semiconductor structure corresponding to the semiconductor device 1B shown in Figure 10, that is, the semiconductor structure of a semiconductor device configured as a semiconductor chip with two semiconductor substrates stacked.

[0057] Figure 22 shows an example of a semiconductor structure in which two semiconductor substrates are stacked and the structure of the present disclosure is applied to the lower layer. In Figure 22, the structure consists of a lower semiconductor substrate 11 and an upper semiconductor substrate 12, which are joined by hybrid bonding. The conductive film 23 of the semiconductor substrate 11 and the conductive film 33 of the semiconductor substrate 12 are electrically connected at the semiconductor surface (bonding surface). In the multilayer wiring layer 22 of the semiconductor substrate 11, a two-dimensional conductive film 61 is used as a thin film covering the side walls and bottom surface of the conductive film 23A that is connected to the conductive film 33 of the semiconductor substrate 12. The conductive film 23A is composed of wiring and vias. In the multilayer wiring layer 22 of the semiconductor substrate 11, the conductive film 23A using the two-dimensional conductive film 61 is in contact with the etch stop layer 51 in the horizontal direction.

[0058] Figure 23 shows an example of a semiconductor structure in which two semiconductor substrates are stacked and the structure of the present disclosure is applied to the upper layer. In Figure 23, in the semiconductor substrates 11 and 12 joined by hybrid bonding, the conductive film 23 and the conductive film 33 are electrically connected on the semiconductor surface. In the multilayer wiring layer 32 of the upper semiconductor substrate 12, a two-dimensional conductive film 61 is used as a thin film covering the side walls and bottom surface of the conductive film 33A that is connected to the conductive film 23 of the lower semiconductor substrate 11. The conductive film 33A is composed of wiring and vias. In the multilayer wiring layer 32 of the semiconductor substrate 12, the conductive film 33A using the two-dimensional conductive film 61 is in contact with the etch stop layer 51 in the horizontal direction.

[0059] Figure 24 shows an example of a semiconductor structure in which two semiconductor substrates are stacked and the structure of the present disclosure is applied to the upper and lower layers. In Figure 24, in the semiconductor substrates 11 and 12 joined by hybrid bonding, the conductive film 23A and the conductive film 33A are electrically connected on the semiconductor surface. In the multilayer wiring layer 22 of the lower semiconductor substrate 11, a two-dimensional conductive film 61-1 is used as a thin film covering the side walls and bottom surface of the conductive film 23A that is connected to the conductive film 33A of the semiconductor substrate 12. The conductive film 23A on which the two-dimensional conductive film 61-1 is used is in contact with the etch stop layer 51-1 in the horizontal direction. On the other hand, in the multilayer wiring layer 32 of the upper semiconductor substrate 12, a two-dimensional conductive film 61-2 is used as a thin film covering the side walls and bottom surface of the conductive film 33A that is connected to the conductive film 23A of the semiconductor substrate 11. The conductive film 33A, which uses the two-dimensional conductive film 61-2, is in contact with the etch stop layer 51-2 in the horizontal direction.

[0060] <Wiring and Vias in Multi-Chip Stacking> Figures 25 to 27 show the semiconductor structure corresponding to the semiconductor device 1C shown in Figure 11, that is, the semiconductor structure of a semiconductor device composed of multiple semiconductor chips stacked on top of each other. Note that in Figures 25 to 27, for the sake of explanation, symbols with "-1" and "-2" added are used, but the components indicated by these symbols are the same components as those indicated by symbols without "-1" and "-2".

[0061] Figure 25 shows an example of a semiconductor structure in which multiple semiconductor chips are stacked and the structure of the present disclosure is applied to the upper layer. In Figure 25, the structure consists of lower semiconductor chips 11-1 and 11-2 stacked with an upper semiconductor chip 12A, and semiconductor chips 11-1 and 11-2 and semiconductor chip 12A are joined by hybrid bonding. The conductive film 33A-1 of semiconductor chip 12A is electrically connected to the conductive film 23-1 of semiconductor chip 11-1 on the semiconductor surface. In addition, the conductive film 33A-2 of semiconductor chip 12A is electrically connected to the conductive film 23-2 of semiconductor chip 11-2 on the semiconductor surface.

[0062] In the semiconductor chip 12A shown in Figure 25, a two-dimensional conductive film 61-1 is used as a thin film covering the side walls and bottom surface of the conductive film 33A-1, which is connected to the conductive film 23-1 of semiconductor chip 11-1. In addition, in semiconductor chip 12A, a two-dimensional conductive film 61-2 is used as a thin film covering the side walls and bottom surface of the conductive film 33A-2, which is connected to the conductive film 23-2 of semiconductor chip 11-2. In semiconductor chip 12A, the conductive film 33A-1 using the two-dimensional conductive film 61-1 and the conductive film 33A-2 using the two-dimensional conductive film 61-2 are in contact with the etch stop layer 51 in the horizontal direction.

[0063] Figure 26 shows an example of a semiconductor structure in which multiple semiconductor chips are stacked and the structure of the present disclosure is applied to the lower layer. In Figure 26, the conductive films 23A-1 and 23A-2 and the conductive films 33-1 and 33-2 are electrically connected on the semiconductor surface between semiconductor chips 11-1 and 11-2, which are joined by hybrid bonding, and semiconductor chip 12A.

[0064] In semiconductor chip 11-1 shown in Figure 26, a two-dimensional conductive film 61-1 is used as a thin film covering the sidewalls and bottom surface of the conductive film 23A-1 connected to the conductive film 33-1 of semiconductor chip 12A. In semiconductor chip 11-1, the conductive film 23A-1 using the two-dimensional conductive film 61-1 is in contact with the etch stop layer 51-1 in the horizontal direction. In semiconductor chip 11-2, a two-dimensional conductive film 61-2 is used as a thin film covering the sidewalls and bottom surface of the conductive film 23A-2 connected to the conductive film 33-2 of semiconductor chip 12A. In semiconductor chip 11-2, the conductive film 23A-2 using the two-dimensional conductive film 61-2 is in contact with the etch stop layer 51-2 in the horizontal direction.

[0065] Figure 27 shows an example of a semiconductor structure in which multiple semiconductor chips are stacked and the structure of the present disclosure is applied to a part of the lower layer. In Figure 27, the conductive films 23A and 23-2, and conductive films 33-1 and 33-2 are electrically connected on the semiconductor surface between semiconductor chips 11-1 and 11-2, which are joined by hybrid bonding, and semiconductor chip 12A.

[0066] In the semiconductor chip 11-1 shown in Figure 27, a two-dimensional conductive film 61 is used as a thin film covering the sidewall and bottom surface within the conductive film 23A that is connected to the conductive film 33-1 of the semiconductor chip 12A. In the semiconductor chip 11-1, the conductive film 23A using the two-dimensional conductive film 61 is in contact with the etch stop layer 51 in the horizontal direction. Note that the structures shown in Figures 25 to 27 are examples, and when multiple semiconductor chips are stacked, it is possible to apply the structure of this disclosure to all of the wiring and vias of the hybrid bonding, or to only a part of the wiring and vias (for example, wiring and vias placed at any position, or any number of wiring and vias).

[0067] <Multilayer Wiring and Vias> Figures 28 to 32 show the semiconductor structure corresponding to the semiconductor device 1D shown in Figure 12, that is, the semiconductor structure of a semiconductor device configured as a semiconductor chip with three layers stacked. In Figures 28 to 32, the semiconductor substrate 13 is denoted by reference numerals corresponding to the semiconductor substrate 11 and the semiconductor substrate 12. Specifically, the semiconductor substrate 13 has a semiconductor layer 41 and a multilayer wiring layer 42. Conductive films 43 such as wiring and vias and interlayer films 44 are formed on the multilayer wiring layer 42. A MOS transistor 45, which is an N-channel or P-channel MOSFET, is provided on the semiconductor layer 41.

[0068] Figure 28 shows an example of a semiconductor structure in which three semiconductor substrates are stacked and the structure of the present disclosure is applied to the middle layer. In Figure 28, the structure consists of a bottom semiconductor substrate 11, a middle semiconductor substrate 12, and an upper semiconductor substrate 13, which are stacked together. The semiconductor substrates 11 and 12, and the semiconductor substrates 12 and 13 are joined by hybrid bonding. The conductive film 23 of semiconductor substrate 11 and the conductive film 33 of semiconductor substrate 12 are electrically connected on the semiconductor surface. The conductive film 33A of semiconductor substrate 12 and the conductive film 43 of semiconductor substrate 13 are electrically connected on the semiconductor surface.

[0069] In the semiconductor substrate 12 shown in Figure 28, a two-dimensional conductive film 61 is used as a thin film covering the side walls and bottom surface of the conductive film 33A that is connected to the conductive film 43 of the semiconductor substrate 13. Furthermore, in the semiconductor substrate 12, the conductive film 33A on which the two-dimensional conductive film 61 is used is in contact with the etch stop layer 51 in the horizontal direction.

[0070] Figure 29 shows an example of a semiconductor structure in which three semiconductor substrates are stacked and the structure of the present disclosure is applied to the lower layer. In Figure 29, in semiconductor substrates 11 and 12 joined by hybrid bonding, the conductive film 23A and the conductive film 33 are electrically connected on the semiconductor surface. In addition, in semiconductor substrates 12 and 13 joined by hybrid bonding, the conductive film 33 and the conductive film 43 are electrically connected on the semiconductor surface.

[0071] In the semiconductor substrate 11 shown in Figure 29, a two-dimensional conductive film 61 is used as a thin film covering the side walls and bottom surface of the conductive film 23A that is connected to the conductive film 33 of the semiconductor substrate 12. Furthermore, in the semiconductor substrate 11, the conductive film 23A on which the two-dimensional conductive film 61 is used is in contact with the etch stop layer 51 in the horizontal direction.

[0072] Figure 30 shows an example of a semiconductor structure in which three semiconductor substrates are stacked and the structure of the present disclosure is applied to the middle and bottom layers. In Figure 30, in semiconductor substrates 11 and 12 joined by hybrid bonding, the conductive film 23A and the conductive film 33 are electrically connected on the semiconductor surface. In addition, in semiconductor substrates 12 and 13 joined by hybrid bonding, the conductive film 33A and the conductive film 43 are electrically connected on the semiconductor surface.

[0073] In the semiconductor substrate 11 of Figure 30, a two-dimensional conductive film 61-1 is used as a thin film covering the side walls and bottom surface of the conductive film 23A connected to the conductive film 33 of the semiconductor substrate 12. Furthermore, in the semiconductor substrate 11, the conductive film 23A using the two-dimensional conductive film 61-1 is in contact with the etch stop layer 51-1 in the horizontal direction. In the semiconductor substrate 12 of Figure 30, a two-dimensional conductive film 61-2 is used as a thin film covering the side walls and bottom surface of the conductive film 33A connected to the conductive film 43 of the semiconductor substrate 13. Furthermore, in the semiconductor substrate 12, the conductive film 33A using the two-dimensional conductive film 61-2 is in contact with the etch stop layer 51-2 in the horizontal direction.

[0074] Figure 31 shows an example of a semiconductor structure in which three semiconductor substrates are stacked and the structure of the present disclosure is applied to through silicon vias (TSVs). In Figure 31, in semiconductor substrates 11 and 12 joined by hybrid bonding, the conductive film 23 and the conductive film 33 are electrically connected on the semiconductor surface. In addition, in semiconductor substrates 12 and 13 joined by hybrid bonding, the conductive film 33 and the conductive film 43 are electrically connected on the semiconductor surface.

[0075] In the semiconductor substrate 12 shown in Figure 31, the conductive film 33 is composed of a conductive film 33A that penetrates the interior of the silicon semiconductor layer 31 as an electrode. That is, in the semiconductor substrate 12, the conductive film 33 is composed of silicon through-vias 91. In the semiconductor substrate 12 shown in Figure 31, a two-dimensional conductive film 61 is used as a thin film covering the side walls and bottom surface of the conductive film 33A which is composed of silicon through-vias 91. Furthermore, in the semiconductor substrate 12, the conductive film 33A using the two-dimensional conductive film 61 is in contact with the etch stop layer 51 in the horizontal direction.

[0076] Figure 32 shows an example of a semiconductor structure in which three semiconductor substrates are stacked and the structure of the present disclosure is applied to the back wiring. In Figure 32, similar to Figure 31, the semiconductor substrate 12, semiconductor substrate 11, and semiconductor substrate 13 are joined by hybrid bonding and electrically connected on the semiconductor surface. In the semiconductor substrate 12 of Figure 32, the conductive film 33 is composed of back wiring 92. The back wiring 92 is wiring that is arranged on the opposite side (back side) when a MOS transistor 35 is provided on the upper side (front side) of the semiconductor layer 31 made of silicon. In the semiconductor substrate 12 of Figure 32, a two-dimensional conductive film 61 is used as a thin film covering the side wall and bottom surface of the conductive film 33A which is composed of back wiring 92. In addition, in the semiconductor substrate 12, the conductive film 33A using the two-dimensional conductive film 61 is in contact with the etch stop layer 51 in the horizontal direction.

[0077] Thus, the two-dimensional conductive film 61 can be used on at least one of the wirings and vias in at least one or more arbitrary wirings and vias in a semiconductor stack in which semiconductor structures are stacked. The structure of the present disclosure can be applied to any layer of the semiconductor stack in which semiconductor structures are stacked, or it can be applied to all layers.

[0078] <Whether or not it can be applied within the same planar wiring layer> In the semiconductor structure of semiconductor device 1, there may be a mixture of application areas using the structure of the present disclosure and non-application areas not using the structure of the present disclosure within the same planar wiring layer.

[0079] Figure 33 shows a first example of a semiconductor structure in which application areas and non-application areas are mixed within the same planar wiring layer. In the semiconductor structure of Figure 33, application areas using the structure of the present disclosure and non-application areas not using the structure of the present disclosure are mixed in the wiring and vias formed on the same plane at the back end.

[0080] In the semiconductor structure of Figure 33, conductive films 23A, 23B, and 23C are formed at the same horizontal position and are located on the same planar wiring layer. In this case, a two-dimensional conductive film 61 is used as a thin film covering the side and bottom surfaces within conductive film 23A. On the other hand, the two-dimensional conductive film 61 is not used for conductive films 23B and 23C. Furthermore, in the semiconductor structure of Figure 33, conductive films 23A, 23B, and 23C are in contact with the etch stop layer 51 in the horizontal direction.

[0081] Thus, in the semiconductor structure of Figure 33, among the conductive films formed on the same planar wiring layer, conductive film 23A is an applicable area, while conductive films 23B and 23C are not. For example, in the semiconductor structure of Figure 33, if we focus on the region below the etch stop layer 51, in conductive film 23A, which is an applicable area, hydrogen diffusion is suppressed, thereby reducing the amount of hydrogen near the MOS transistor 25-1. On the other hand, in conductive films 23B and 23C, which are not applicable areas, hydrogen can pass from the top to the bottom of the etch stop layer 51, thus increasing the amount of hydrogen near the MOS transistor 25-2.

[0082] Figure 34 shows an example of the configuration of a semiconductor device having the semiconductor structure shown in Figure 33. For example, consider a case where the semiconductor device in Figure 34 is composed of circuit 11E-1 and circuit 11E-2, and the conductive film formed on circuit 11E-1 and the conductive film formed on circuit 11E-2 are formed on the same planar wiring layer. In this case, the conductive film formed on circuit 11E-1 is made in a non-applicable area, as shown by conductive film 23B and conductive film 23C in Figure 33, and the conductive film formed on circuit 11E-2 is made in an applicable area, as shown by conductive film 23A in Figure 33. This makes it possible to form regions with increased hydrogen content and regions with decreased hydrogen content within a single-layer semiconductor chip. Thus, it becomes possible to optimize the characteristics for each circuit region.

[0083] Figure 35 shows a second example of a semiconductor structure in which application areas and non-application areas are mixed within the same planar wiring layer. In the semiconductor structure of Figure 35, in the semiconductor substrates 11 and 12 joined by hybrid bonding, application areas using the structure of the present disclosure and non-application areas not using the structure of the present disclosure are mixed in the wiring and vias formed on the same plane.

[0084] In Figure 35, the conductive films 23A-1 and 23A-2 on the semiconductor substrate 11 and the conductive films 33-1 and 33-2 on the semiconductor substrate 12 are electrically connected at the semiconductor surface (junction surface). In the semiconductor substrate 11 of Figure 35, the conductive films 23A-1 and 23A-2 are formed at the same position in the horizontal direction and are formed on the same planar wiring layer. In this case, a two-dimensional conductive film 61 is used as a thin film covering the side and bottom surfaces within the conductive film 23A-1. On the other hand, the two-dimensional conductive film 61 is not used in the conductive film 23A-2. Also, in the semiconductor substrate 11, the conductive films 23A-1 and 23A-2 are in contact with the etch stop layer 51 in the horizontal direction.

[0085] Thus, in the semiconductor structure of Figure 35, among the conductive films formed on the same planar wiring layer, conductive film 23A-1 is an applicable area, while conductive film 23A-2 is not. For example, in the semiconductor structure of Figure 35, if we focus on the region below the etch stop layer 51, in conductive film 23A-1, which is an applicable area, hydrogen diffusion is suppressed, thus reducing the amount of hydrogen near MOS transistor 25-1. Also, in conductive film 23A-2, which is not an applicable area, hydrogen can pass from the top to the bottom of the etch stop layer 51, thus increasing the amount of hydrogen near MOS transistor 25-2. Furthermore, if we focus on the region above the etch stop layer 51, the amount of hydrogen near MOS transistors 35-1 and 35-2 can be increased.

[0086] <Application in layers not in contact with ESL> In the semiconductor structure of semiconductor device 1, the structure of the present disclosure may be used in the conductive film of any layer that is not in contact with the etch stop layer.

[0087] Figure 36 shows an example of a semiconductor structure in which the structure of the circuit body and the seal ring of this disclosure are applied. The seal ring structure is provided along the outer circumference of the circuit body and is used for purposes such as noise shielding, such as reducing digital noise coupling, and preventing moisture intrusion. The seal ring is also called a guard ring. In the semiconductor structure of Figure 36, the cross-sectional structure of the circuit body 101 and the seal ring 102 provided around the circuit body 101 in a plan view is shown.

[0088] In the semiconductor structure shown in Figure 36, conductive films 23-1 and 23-2 are formed in the region corresponding to the circuit body 101. Of conductive film 23-1, a two-dimensional conductive film 61 is used as a thin film covering the side and bottom surfaces of conductive film 23A-1. Similarly, of conductive film 23-2, a two-dimensional conductive film 61 is used as a thin film covering the side and bottom surfaces of conductive film 23A-2. Conductive films 23A-1 and 23A-2 are in contact with the etch stop layer 51 in the horizontal direction.

[0089] Furthermore, in the semiconductor structure of Figure 36, conductive films 23-3 and 23-4 are formed in the region corresponding to the seal ring 102. Of the conductive films 23-3, a two-dimensional conductive film 61 is used as a thin film covering the side and bottom surfaces within conductive film 23A-3. Similarly, of the conductive films 23-4, a two-dimensional conductive film 61 is used as a thin film covering the side and bottom surfaces within conductive film 23A-4. Conductive films 23A-3 and 23A-4 are in contact with the etch stop layer 51 in the horizontal direction.

[0090] In conductive film 23-3, the two-dimensional conductive film 61 is used not only in conductive film 23A-3, which is in contact with the etch stop layer 51, but also in conductive films of other layers such as conductive film 23B-3, as a thin film covering the sides and bottom. Similarly, in conductive film 23-4, the two-dimensional conductive film 61 is used not only in conductive film 23A-4, which is in contact with the etch stop layer 51, but also in conductive films of other layers such as conductive film 23B-4, as a thin film covering the sides and bottom.

[0091] In other words, in the semiconductor structure of Figure 36, the conductive films 23-3 and 23-4 formed on the seal ring 102 are not limited to conductive films 23A-3 and 23A-4 that are in contact with the etch stop layer 51, but the two-dimensional conductive film 61 is also used for conductive films of any layer that are not in contact with the etch stop layer 51, such as conductive films 23B-3 and 23B-4. In conductive films 23-3 and 23-4, the presence or absence of contact with the etch stop layer 51 at each layer is arbitrary.

[0092] In addition, in the conductive films 23-1 and 23-2 formed on the circuit body 101, the conductive films of the other layers (conductive films 23B-1, 23B-2, etc.), excluding conductive films 23A-1 and 23A-2 which are in contact with the etch stop layer 51, do not use the two-dimensional conductive film 61. In the semiconductor layer 21, MOS transistors 25-1 and 25-2 are provided corresponding to conductive films 23-1 and 23-2, and semiconductor regions 26-1 and 26-2 are provided corresponding to conductive films 23-3 and 23-4.

[0093] Furthermore, for example, in a single-layer semiconductor chip or a semiconductor structure in which multiple semiconductor chips are stacked, the structure of the present disclosure can be used in the conductive film of any layer that is not in contact with the etch stop layer.

[0094] Figure 37 shows an example of a semiconductor structure in which the structure of the present disclosure is applied to a single-layer semiconductor chip. In the semiconductor structure of Figure 37, the two-dimensional conductive film 61 is used in any conductive film 23 of the layer in contact with the etch stop layer 51. In addition, in the semiconductor structure of Figure 37, the two-dimensional conductive film 61 is used in any conductive film 23 of the layer not in contact with the etch stop layer 51. By using the structure of the present disclosure in the conductive film of any layer not in contact with the etch stop layer 51 in this way, hydrogen diffusion in the horizontal direction (in-plane direction) can be suppressed by the two-dimensional conductive film 61 used in the conductive film of any layer, as shown by the bent arrow in the figure.

[0095] Figure 38 shows an example of a semiconductor structure in which the structure of the present disclosure is used in a structure in which multiple semiconductor chips are stacked. In Figure 38, semiconductor chips 11-1 and 11-2, which are lower layers, and semiconductor chip 12A, which is an upper layer, are stacked and joined by hybrid bonding. In the semiconductor structure of Figure 38, a two-dimensional conductive film 61 is used for the conductive film 23 of the layer in contact with the etch stop layer 51 of the lower layer. In addition, in the semiconductor structure of Figure 38, the two-dimensional conductive film 61 is used for the conductive film of any layer among the conductive films 23 of the layers that are not in contact with the etch stop layer 51. In this way, by using the structure of the present disclosure for the conductive film of any layer that is not in contact with the etch stop layer, horizontal hydrogen diffusion can be suppressed by the two-dimensional conductive film 61 used for the conductive film of any layer, as shown by the bent arrow in the figure.

[0096] In the above explanation, a structure was shown in which a two-dimensional conductive film is used as a thin film covering the side walls and bottom surface within the conductive film. However, a two-dimensional conductive film may also be used as a cap material covering the top surface. Figure 39 shows an example of a structure in which a two-dimensional conductive film is used as a cap material. In Figure 39, when conductive films 23A-1 and 23A-2 consist of wiring 71 and via 72, a two-dimensional conductive film 61 is used as a thin film covering the side walls and bottom surface of wiring 71 and via 72. The two-dimensional conductive film 61 is also used as a cap material covering the top surface of wiring 71. In this way, a structure can be adopted in which a two-dimensional conductive film covers not only the side walls and bottom surface but also the top surface within the conductive film. When this structure is used, for example, in a sealing ring structure, functions such as noise shielding and moisture intrusion suppression can be improved.

[0097] Furthermore, in Figure 36, when the structure of the present disclosure is applied to the circuit body 101 and the seal ring 102, the conductive films 23-1 and 23-2 formed on the circuit body 101 show a structure in which the two-dimensional conductive film 61 is not used in the lower conductive films other than the upper conductive films 23A-1 and 23A-2 that are in contact with the etch stop layer 51. However, the two-dimensional conductive film 61 may be used in the lower conductive films.

[0098] Figure 40 shows another example of a semiconductor structure in which the structure of the circuit body and seal ring is applied to the structure of the present disclosure. In the semiconductor structure of Figure 40, the conductive films 23-1 and 23-2 formed on the circuit body 101 are not limited to conductive films 23A-1 and 23A-2 that are in contact with the etch stop layer 51, but the two-dimensional conductive film 61 is also used for conductive films of any layer that is not in contact with the etch stop layer 51, such as conductive films 23B-1 and 23B-2, compared to the semiconductor structure of Figure 36.

[0099] Thus, in the semiconductor structure of Figure 40, the two-dimensional conductive film 61 is used not only in the upper conductive film that contacts the etch stop layer 51, but also in the lower conductive film that does not contact the etch stop layer 51, similar to the seal ring 102 in the circuit body 101. This eliminates the need for separate manufacturing processes depending on whether the two-dimensional conductive film 61 is present or absent during production. Therefore, when adopting the semiconductor structure of Figure 40, it can be manufactured at a lower cost compared to adopting the semiconductor structure of Figure 36. Although adopting the semiconductor structure of Figure 36 increases the number of processes due to an increase in masks, etc., compared to adopting the semiconductor structure of Figure 40, the two-dimensional conductive film is not used in the lower conductive film, resulting in better diffusion of gas within the plane. This makes it a more useful structure when it is desired to uniformly increase the hydrogen supply amount according to the characteristic target.

[0100] <Structure with partially removed ESL> In the semiconductor structure of semiconductor device 1, the etch stop layer provided on the conductive film on which the two-dimensional conductive film is provided may be partially removed.

[0101] Figure 41 shows an example of a semiconductor structure in which the structure of the circuit body, seal ring, and partition of this disclosure is applied. The partition structure is a structure provided to separate the circuit body (for example, to separate the analog region and the logic region). In Figure 41, a partition 103 is provided to separate the main circuit 101A and the main circuit 101B, which are surrounded by a seal ring 102 in a plan view. A planar configuration corresponding to the cross-sectional structure of Figure 41 is shown in Figure 43, which will be described later.

[0102] In the semiconductor structure shown in Figure 41, conductive films 23-1 and 23-2 are formed in the region corresponding to the main circuit 101A. The upper conductive film in contact with the etch-stop layer 51 and the lower conductive film not in contact with the etch-stop layer 51 utilize the two-dimensional conductive film 61. In the region corresponding to the main circuit 101B, conductive films 23-3 and 23-4 are formed, and the two-dimensional conductive film 61 is used in the conductive films of each layer.

[0103] Furthermore, in the semiconductor structure of Figure 41, conductive films 23-5 and 23-6 are formed in the region corresponding to the seal ring 102, and a two-dimensional conductive film 61 is used for the upper conductive film that is in contact with the etch stop layer 51 and for the lower conductive film that is not in contact with the etch stop layer 51. In the region corresponding to the partition 103, a conductive film 23-7 is formed, and a two-dimensional conductive film 61 is used for the upper conductive film that is in contact with the etch stop layer 51 and for the lower conductive film that is not in contact with the etch stop layer 51.

[0104] In the semiconductor structure of Figure 41, among the regions corresponding to the main circuit 101A, main circuit 101B, seal ring 102, and partition 103, the etch stop layer 51 is removed in the region corresponding to the main circuit 101B, as shown by the dashed line in the figure, and conductive films 23-3 and 23-4 are not in contact with the etch stop layer 51. In the region corresponding to the main circuit 101B, the etch stop layer 51 is not provided, and a hydrogen diffusion path is secured, so the amount of hydrogen near MOS transistors 25-3 and 25-4 can be increased, as shown by the arrows in the figure. On the other hand, in the region corresponding to the main circuit 101A, the etch stop layer 51 is provided, and hydrogen diffusion is suppressed, so the amount of hydrogen near MOS transistors 25-1 and 25-2 can be reduced, as shown by the bent arrows in the figure. In the semiconductor layer 21, semiconductor regions 27-1 to 27-3 are provided corresponding to conductive films 23-5 to 23-7.

[0105] Thus, in the semiconductor structure of Figure 41, even in regions where the etch stop layer 51 is partially removed, a two-dimensional conductive film 61 is provided on the conductive film of each layer. Therefore, during manufacturing, a separate process for manufacturing based on the presence or absence of the two-dimensional conductive film 61 is unnecessary. Consequently, when adopting the semiconductor structure of Figure 41, it is possible to manufacture regions with increased hydrogen content and regions with decreased hydrogen content at a lower cost compared to adopting the semiconductor structure of Figure 36. Although the semiconductor structure of Figure 41 requires a separate manufacturing process based on the presence or absence of the etch stop layer 51, the number of masks and processes are smaller compared to the separate manufacturing process based on the presence or absence of the two-dimensional conductive film 61, resulting in lower costs.

[0106] <Protection from various gas molecules> In the above explanation, hydrogen was used as an example of a gas molecule that suppresses diffusion. However, the structure of this disclosure can be applied not only to hydrogen, but also to protect semiconductor devices such as MOSFETs and wiring from other substances such as water and oxygen.

[0107] Figure 42 illustrates a structure of the present disclosure that protects semiconductor devices and wiring from various gas molecules. In the semiconductor structure of Figure 42, conductive films 23-1 and 23-2 are formed in the region corresponding to the circuit body 101, and a two-dimensional conductive film 61 is used for the conductive film of each layer. Conductive films 23-3 and 23-4 are formed in the region corresponding to the seal ring 102, and a two-dimensional conductive film 61 is used for the conductive film of each layer. In the semiconductor structure of Figure 42, the upper conductive films 23-1 to 23-4 are in contact with the etch stop layer 51 in the horizontal direction.

[0108] In the semiconductor structure shown in Figure 42, the etch-stop layer 51 and the two-dimensional conductive film 61 used in each layer of conductive films 23-1 to 23-4 suppress the diffusion of various gas molecules such as moisture and oxygen. As shown by the bent arrows in the figure, semiconductor devices such as MOS transistors 25-1 and 25-2, and wiring such as at least a portion of conductive films 23-1, 23-2, and conductive films 23-3 and 23-4 can be protected. The etch-stop layer 51 and the two-dimensional conductive film 61 can, for example, block moisture, thereby suppressing the deterioration of the reliability of the wiring elements. Furthermore, by blocking oxygen, oxidation of the wiring and an increase in resistivity can be suppressed. Here, the etch-stop layer 51 and the two-dimensional conductive film 61 can have blocking performance against gas molecules in general that are larger in size than hydrogen.

[0109] <Shape of seal ring / partition> In the semiconductor structure of semiconductor device 1, various shapes can be adopted for the seal ring and partition. For example, the seal ring and partition can be any closed shape within the semiconductor chip. In addition, the partition can be selectively applied to locations in adjacent circuit blocks where it is desired to suppress the diffusion of gas molecules such as hydrogen. As shown in Figure 41, the amount of gas exposed to the circuit block can be controlled depending on the presence or absence of an etch stop layer in the vertical direction.

[0110] Examples of the shapes of the seal ring and partition are shown in Figures 43 to 45. Figures 43 to 45 show the planar configuration of the semiconductor device 1 as viewed from a bird's-eye perspective. Note that, for the sake of simplicity, only the semiconductor substrate and the seal ring and partition, on which a conductive film using a two-dimensional conductive film is formed, are shown in Figures 43 to 45.

[0111] Figure 43 is a plan view showing a first example of the shape of the seal ring and partition. In Figure 43, a seal ring 102 is provided around the main circuit 101A and the main circuit 101B, and a partition 103 is provided to divide the main circuit 101A and the main circuit 101B into left and right regions. For example, the A-A' section in Figure 43 corresponds to the cross-sectional structure shown in Figure 41.

[0112] Figure 44 is a plan view showing a second example of the shape of the seal ring and partition. In Figure 44, a seal ring 102 is provided around the main circuit 101A and the main circuit 101B, and a partition 103 is provided to divide the main circuit 101A and the main circuit 101B into a lower left region and the rest of the region.

[0113] Figure 45 is a plan view showing a third example of the shape of the seal ring and partition. In Figure 45, a seal ring 102 is provided around the main circuit 101A, main circuit 101B, and main circuit 101C, and a partition 103 is provided to divide the main circuit 101A, main circuit 101B, and main circuit 101C into a lower left region and the rest of the region. In Figure 45, main circuit 101B and main circuit 101C are provided in the region excluding the lower left region, and main circuit 101B and main circuit 101C are separated by a vertical dashed line. The reason why a partition 103 is not provided in the region 104 corresponding to the dashed line is that gas separation is not intended between main circuit 101B and main circuit 101C.

[0114] <Types of Interlayer Insulating Films> The interlayer insulating films constituting the semiconductor structure of semiconductor device 1 may include insulating films (interlayer insulating films) containing any gas. For example, insulating films with adjusted hydrogen content can be used as a means of supplying hydrogen to each layer separated by a two-dimensional conductive film. In this case, hydrogen can be diffused by applying heat treatment to the semiconductor structure in which the insulating film containing hydrogen has been formed.

[0115] Figures 46 and 47 show the process of hydrogen diffusion by heat treatment of a hydrogen-containing insulating film. Figure 46 shows the semiconductor structure before heat treatment, and Figure 47 shows the semiconductor structure after heat treatment. In Figures 46 and 47, in the semiconductor substrates 11 and 12 joined by hybrid bonding, conductive films 23A-1 and 33-1, and conductive films 23A-2 and 33-2 are electrically connected on the semiconductor surface. In semiconductor substrate 11, a two-dimensional conductive film 61-1 is used as a thin film covering the sidewalls and bottom surface within conductive film 23A-1, and a two-dimensional conductive film 61-2 is used as a thin film covering the sidewalls and bottom surface within conductive film 23A-2. Conductive films 23A-1 and 23A-2 are in contact with the etch stop layer 51 in the horizontal direction.

[0116] As shown in Figure 46, the semiconductor structure before heat treatment, an insulating film 111 containing hydrogen is formed on the semiconductor substrate 12, relative to the interlayer film 34 which serves as an interlayer insulating film. When heat treatment is applied, as shown in Figure 47, the semiconductor structure after heat treatment, hydrogen is diffused and supplied from the insulating film 111. However, in the semiconductor substrate 11, hydrogen diffusion is suppressed by the etch stop layer 51 and the two-dimensional conductive film 61. Therefore, in the semiconductor substrate 11, the amount of hydrogen near the MOS transistors 25-1 and 25-2 provided on the semiconductor layer 21 can be reduced. On the other hand, in the semiconductor substrate 12, as indicated by the arrows in the figure, hydrogen can move and increase the amount of hydrogen near the MOS transistors 35-1 and 35-2 provided on the semiconductor layer 31.

[0117] Furthermore, the gas contained in the insulating film 111 is not limited to hydrogen; other gases may also be used, and the type and amount of gas are arbitrary. Also, while Figures 46 and 47 illustrate semiconductor structures using the insulating film 111 as the interlayer insulating film, the film type is not limited, and other film types may be used.

[0118] As described above, the semiconductor device 1 to which the present disclosure is applied has a semiconductor structure including at least one conductive film (for example, conductive film 23A), and at least one layer of the thin film covering the side walls and bottom surface within the conductive film is a two-dimensional conductive film 61, and the conductive film is in contact with a gas-sealing etch-stop layer 51. As a result, the etch-stop layer 51 and the two-dimensional conductive film 61 make it possible to suppress the diffusion of gas molecules such as hydrogen (for example, enabling a wiring structure with hydrogen barrier properties), thereby improving the characteristics (reliability, etc.) of semiconductor devices and wiring.

[0119] The embodiments described herein are not limited to those described above, and various modifications are possible without departing from the spirit of this disclosure. For example, the embodiments described above may be implemented individually or in combination with other embodiments. Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also occur.

[0120] Furthermore, this disclosure can take the following form.

[0121] (1) A semiconductor device having a semiconductor structure including at least one conductive film, wherein at least one of the thin films covering the side walls and bottom surface within the conductive film is a two-dimensional conductive film, and the conductive film is in contact with an etch stop layer that separates the semiconductor structure in the first direction in a second direction perpendicular to a first direction which is the thickness direction of the semiconductor structure. (2) The semiconductor device according to (1), wherein the etch stop layer is in direct physical contact with the two-dimensional conductive film, or includes a thin film of at least one of a conductive film and an insulating film between itself and the two-dimensional conductive film. (3) The semiconductor device according to (1) or (2), wherein the two-dimensional conductive film is used in at least one of wiring and vias formed at the front end or back end, or in at least one of wiring and vias in a semiconductor laminate formed by stacking the semiconductor structures. (4) The semiconductor device according to any one of (1) to (3), wherein the semiconductor structure is a mixture of at least one conductive film, in which at least one of the thin films covering the side walls and bottom surface within the conductive film within the same plane is an application area in which the two-dimensional conductive film is used, and a thin film covering the side walls and bottom surface within the conductive film is not used in the application area. (5) The semiconductor device according to any one of (1) to (4), wherein the two-dimensional conductive film is used in the conductive film of any layer not in contact with the etch stop layer. (6) The semiconductor device according to (5), wherein the two-dimensional conductive film is used as a cap material covering the upper surface of the conductive film. (7) The semiconductor device according to (5), wherein the etch stop layer is partially removed in the second direction. (8) The semiconductor device according to any one of (1) to (7), wherein the semiconductor structure is composed of one semiconductor substrate or semiconductor chip, or composed of a plurality of semiconductor substrates or semiconductor chips stacked together. (9) The semiconductor device according to (8), wherein the semiconductor structure is configured by stacking a pixel circuit having a plurality of pixels including a photoelectric conversion unit and a logic circuit that processes signals from the pixel circuit. (10) The semiconductor device according to any one of (1) to (9), wherein the interlayer insulating film constituting the semiconductor structure includes an insulating film containing an arbitrary gas.(11) The semiconductor device according to any one of (1) to (10), wherein the two-dimensional conductive film is graphene, graphene oxide, or a transition metal dichalcogenide. (12) The semiconductor device according to any one of (1) to (11), wherein the etch stop layer is a compound that combines at least one of oxides, nitrides, and carbides.

[0122] 1, 1A-1D Semiconductor device, 11 Semiconductor substrate, 11A-1 Analog circuit, 11A-2 Logic circuit, 11B Logic circuit, 11C-1 Logic circuit, 11C-2 External chip, 11D Logic circuit, 12 Semiconductor substrate, 12B Pixel circuit, 12C Pixel circuit, 12D Analog circuit, 13 Semiconductor substrate, 13D Pixel circuit, 21 Semiconductor layer, 22 Multilayer wiring layer, 23 Conductive film, 23A Conductive film, 24 Interlayer film, 25 MOS transistor, 31 Semiconductor layer, 32 Multilayer wiring layer, 33 Conductive film, 33A Conductive film, 34 Interlayer film, 35 MOS transistor, 41 Semiconductor layer, 42 Multilayer wiring layer, 43 Conductive film, 44 Interlayer film, 45 MOS transistor, 51 Etch stop layer, 61 Two-dimensional conductive film, 62 Barrier metal, 63 Two-dimensional material seed layer, 64 Wiring seed layer, 65 Bulk wiring layer, 66 Thin film layer, 71 Wiring, 72 Via, 73 Wiring, 74 Via, 81 Global wiring, 82 Semi-global wiring, 83 Intermediate wiring, 84 Intermediate wiring, 85 Local wiring, 86 Contact wiring, 91 Through-silicon via, 92 Backside wiring, 101 Main circuit, 101A Main circuit, 101B Main circuit, 101C Main circuit, 102 Seal ring, 103 Partition, 111 Insulating film

Claims

1. A semiconductor device having a semiconductor structure comprising at least one conductive film, wherein at least one of the thin films covering the side walls and bottom surface within the conductive film is a two-dimensional conductive film, and the conductive film is in contact with an etch stop layer that separates the semiconductor structure in the first direction in a second direction perpendicular to a first direction which is the thickness direction of the semiconductor structure.

2. The semiconductor device according to claim 1, wherein the etch stop layer is in direct physical contact with the two-dimensional conductive film, or includes a thin film of at least one of the conductive film and the insulating film between itself and the two-dimensional conductive film.

3. The semiconductor device according to claim 1, wherein the two-dimensional conductive film is used in at least one of the wiring and vias formed at the front end or back end, or in at least one of the wiring and vias in a semiconductor laminate in which the semiconductor structures are stacked.

4. The semiconductor device according to claim 1, wherein the semiconductor structure comprises at least one conductive film, and within the same plane, at least one of the thin films covering the side walls and bottom surface of the conductive film is mixed with application areas where the two-dimensional conductive film is used and non-application areas where the thin film covering the side walls and bottom surface of the conductive film is not used.

5. The semiconductor device according to claim 1, wherein the two-dimensional conductive film is used as a conductive film in any layer that is not in contact with the etch stop layer.

6. The semiconductor device according to claim 5, wherein the two-dimensional conductive film is used as a cap material covering the upper surface of the conductive film.

7. The semiconductor device according to claim 5, wherein the etch stop layer is partially removed in the second direction.

8. The semiconductor device according to claim 1, wherein the semiconductor structure is composed of one semiconductor substrate or semiconductor chip, or is composed of a plurality of semiconductor substrates or semiconductor chips stacked together.

9. The semiconductor device according to claim 8, wherein the semiconductor structure is configured by stacking a pixel circuit having a plurality of pixels including a photoelectric conversion unit and a logic circuit that processes signals from the pixel circuit.

10. The semiconductor device according to claim 1, wherein the interlayer insulating film constituting the semiconductor structure includes an insulating film containing an arbitrary gas.

11. The semiconductor device according to claim 1, wherein the two-dimensional conductive film is graphene, graphene oxide, or a transition metal dichalcogenide.

12. The semiconductor device according to claim 1, wherein the etch stop layer is a compound comprising at least one of an oxide, a nitride, and a carbide.

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