Storage device, storage system, and storage method

Abstract

A storage device according to an embodiment of the present invention comprises: a data cell that has a variable resistance value; a reference cell that has a variable resistance value; a read control unit that reads data by comparing the resistance value of the data cell and the resistance value of the reference cell; an error processing unit that determines whether an error exists in the data; and a log storage unit that stores log information including an error history of the reference cell that is based on the determination results relating to the data.

Description

Memory device, memory system and memory method

[0001] The present disclosure relates to a memory device, a memory system, and a memory method.

[0002] For example, in a memory device using MTJ (Magnetic Tunnel Junction) elements as data cells and reference cells, data stored in the MTJ element may be unintentionally flipped due to some factor (e.g., Read disturb). For example, the same current path is used for write operations and read operations, and even if the minute current applied during a read operation is equal to or lower than the write threshold, there is a probability that data may be rewritten. This is a phenomenon that cannot be ignored in reference cells that are accessed every time a read operation is performed. For example, if an unintended logic inversion occurs in a reference cell, erroneous reading of data from the memory device may occur, resulting in reduced reliability.

[0003] In order to cope with such data errors, there is a technique for recovering soft errors using an error correction code (ECC) (see, for example, Patent Document 1). Note that a soft error is not a hard error caused by physical damage, that is, a hard error in which a data cell or a reference cell does not operate normally due to physical damage; instead, it is an error in which, for example, a data cell or a reference cell does not operate normally due to a temporary malfunction, but operates normally when used again.

[0004] International Publication No. 2008 / 133087

[0005] However, for an error detected by ECC, it is unclear whether the error is in the data cell or the reference cell. For this reason, simply correcting the data cell may not be able to recover soft errors, resulting in reduced reliability.

[0006] Therefore, the present disclosure provides a technique capable of improving reliability.

[0007] The storage device according to the embodiment includes a data cell with a variable resistance value, a reference cell with a variable resistance value, a read control unit that reads data by comparing the resistance value of the data cell with the resistance value of the reference cell, an error processing unit that determines whether or not there is an error in the data, and a log storage unit that stores log information including the error history of the reference cell based on the determination result of the data.

[0008] The storage system according to the embodiment comprises a storage device and a main device communicatively connected to the storage device, wherein the storage device includes a data cell with a variable resistance value, a reference cell with a variable resistance value, and a read control unit that reads data by comparing the resistance value of the data cell with the resistance value of the reference cell, and the storage device or the main device includes an error processing unit that determines whether or not there is an error in the data, and a log storage unit that stores log information including the error history of the reference cell based on the determination result of the data.

[0009] The storage method according to the embodiment includes a storage device that reads data by comparing the resistance value of a data cell whose resistance value is variable with the resistance value of a reference cell whose resistance value is variable, determines whether or not there is an error in the data, and stores log information including the error history of the reference cell based on the determination result of the data.

[0010] This figure shows an example configuration of the storage system according to the first embodiment. This figure shows an example configuration of log information according to the first embodiment. This figure shows an example configuration of log information according to the first embodiment. This figure illustrates an example of generating a reference potential according to the first embodiment. This figure shows a flowchart of a processing example of a read operation according to the first embodiment. This figure illustrates an example of correcting a reference cell according to the first embodiment. This figure illustrates an example of correcting a reference cell according to the first embodiment. This figure shows an example configuration of the storage system according to the second embodiment. This figure shows an example configuration of the storage system according to the third embodiment. This figure shows a flowchart of a processing example of a read operation according to the third embodiment. This figure illustrates an example of correcting a data cell according to the third embodiment. This figure illustrates an example of correcting a data cell according to the third embodiment. This figure illustrates an example of correcting a data cell according to the third embodiment. This figure shows a flowchart of a processing example of another read operation according to the third embodiment. This figure illustrates an example of correcting a data cell according to the third embodiment. This figure illustrates an example of correcting a data cell according to the third embodiment. This figure illustrates an example of correcting a data cell according to the third embodiment. This figure illustrates variations in the installation of the error processing unit, log processing unit, and log storage unit according to each of the above embodiments. This figure illustrates variations in the installation of the error processing unit, log processing unit, and log storage unit according to each of the above embodiments. This figure illustrates the installation variations of the error processing unit, log processing unit, and log storage unit according to each of the embodiments described above. This figure shows application examples of the storage system according to each of the embodiments described above. This figure shows an example of the configuration of the imaging device according to the application example. This figure shows an example of the configuration of the distance measuring device according to the application example.

[0011] Embodiments of this disclosure will be described in detail below with reference to the drawings. Embodiments include examples and modifications. However, the technology relating to this disclosure is not limited by the embodiments. In addition, in the following embodiments, the same reference numerals are used for essentially the same parts to omit redundant explanations.

[0012] This disclosure will be described in the following order of items: 1. First Embodiment 1-1. Example of Memory System Configuration 1-2. Example of Log Information Configuration 1-3. Example of Reference Potential Generation 1-4. Example of Read Operation Processing 2. Second Embodiment 2-1. Example of Memory System Configuration 3. Third Embodiment 3-1. Example of Memory System Configuration 3-2. Example of Read Operation Processing 3-3. Other Read Operation Processing Examples 4. Installation Variations 5. Operation and Effects of Each Embodiment 6. Other Embodiments 7. Application Examples 7-1. Various Devices 7-2. Imaging Device 7-3. Distancing Device 8. Notes

[0013] <1. First Embodiment> <1-1. Example of Memory System Configuration> An example of the configuration of the memory system 100 according to the first embodiment will be described with reference to Figure 1. Figure 1 is a diagram showing an example of the configuration of the memory system 100 according to the first embodiment.

[0014] As shown in Figure 1, the storage system 100 according to the first embodiment comprises a semiconductor storage device 110 and a main device 120. The semiconductor storage device 110 is an example of a storage device for storing data.

[0015] The semiconductor memory device 110 includes a data memory array 10, a reference memory array 20, a row selection unit 30, a column selection unit 40, a write control unit 50, a read control unit 60, and a control unit 70.

[0016] The data memory array 10 includes a plurality of data cells 11. Each data cell 11 is arranged, for example, in a two-dimensional matrix. Each of these data cells 11 stores data. Word lines (WL) and bit lines (BL) are connected to each data cell 11, respectively, to transmit signals such as control signals.

[0017] The reference memory array 20 includes a plurality of reference cells 21. Each reference cell 21 is arranged, for example, in a two-dimensional matrix. Each of these reference cells 21 stores data (reference data). Word lines (WL) and bit lines (BL) that transmit signals such as control signals are connected to each of the reference cells 21.

[0018] Multiple word lines are provided in both the data memory array 10 and the reference memory array 20 so as to extend in the row direction. Similarly, multiple bit lines are provided in both the data memory array 10 and the reference memory array 20 so as to extend in the column direction. The planar sizes (e.g., number of cells) of the data memory array 10 and the reference memory array 20 may be the same or different. For example, the planar size of the reference memory array 20 may be smaller than that of the data memory array 10.

[0019] Each data cell 11 and reference cell 21 is connected to a word line and a pair of bit lines. A single word line is commonly connected to a data cell 11 or a reference cell 21 in the same row. A pair of bit lines is commonly connected to a data cell 11 or a reference cell 21 in the same column. One of the bit lines is also called the source line (SL) or sense line.

[0020] Each data cell 11 and each reference cell 21 has, for example, a selection element and a memory element. The selection element is connected to one end of the memory element and controls the application of voltage, current, etc., to the memory element. Various transistors can be used as the selection element. As the memory element, for example, a resistive random-access memory element with a variable resistance can be used. Examples of resistive random-access memory elements include magnetoresistive elements (magnetoresistive effect elements) such as MTJ (Magnetic Tunnel Junction) elements.

[0021] A magnetoresistive element has two magnetic layers and a non-magnetic layer (e.g., an insulating layer) between them. The magnetoresistive element is an element whose resistance value changes depending on the magnetization direction (direction of magnetization) of the two magnetic layers. The magnetoresistive element is in a high-resistance state where the resistance value is high when the magnetization directions of each magnetic layer are different, and in a low-resistance state where the resistance value is low when the magnetization directions are the same. The magnetization direction changes, for example, when a writing voltage or writing current is applied to the magnetoresistive element. For example, the values ​​"0" and "1" are associated with the low-resistance state and high-resistance state of the magnetoresistive element, respectively, and data is stored.

[0022] The row selection unit 30 selects an arbitrary word line based on the row address and row selection command specified by the control unit 70. Each word line is connected to the row selection unit 30.

[0023] The column selection unit 40 selects an arbitrary bit line based on the column address and column selection command specified by the control unit 70. Each bit line is connected to the column selection unit 40.

[0024] The write control unit 50 controls the writing of data to the data memory array 10 and the reference memory array 20, respectively, based on the write command specified by the control unit 70.

[0025] The read control unit 60 controls the reading of data from the data memory array 10 and the reference memory array 20, respectively, based on the read command specified by the control unit 70.

[0026] The control unit 70 includes an address control unit 71, a command control unit 72, an error processing unit 73, a log processing unit 74, and a log storage unit 75.

[0027] The address control unit 71 outputs addresses corresponding to commands to the row selection unit 30, column selection unit 40, and log processing unit 74, based on addresses (for example, row addresses and column addresses) input from the main device 120 and commands input from the command control unit 72.

[0028] The command control unit 72 outputs various commands corresponding to the commands input from the main device 120 to the row selection unit 30, column selection unit 40, write control unit 50, and read control unit 60.

[0029] The error processing unit 73 performs various processes such as error correction coding (ECC) conversion, decoding, and error detection, and outputs the determination result to the log processing unit 74. The determination result includes, for example, determination information indicating whether or not there is an error in the read data.

[0030] The log processing unit 74 reads log information for the reference cell 21 corresponding to the read address (address information) input from the address control unit 71 from the log storage unit 75 (log reading), and based on the read log information, it determines whether or not to rewrite to the reference cell 21 and updates the log information in the log storage unit 75 (log updating). The log information is, for example, error history information including the error history for each reference cell 21.

[0031] For example, if the log processing unit 74 determines, based on the log information, that a reference cell 21 has an error history, it outputs the write address (reference cell address information) for that reference cell 21 to the command control unit 72. The log processing unit 74 also outputs a reference cell error notification signal to the main device 120 to notify that there is an error in the reference cell 21. When a series of read operations are completed, the log processing unit 74 outputs a read completion notification signal to the main device 120 to notify that the read operation has finished (read operation completion).

[0032] The log storage unit 75 is a memory area that stores log information. For example, a flip-flop or SRAM (Static Random Access Memory) can be used as the log storage unit 75. In addition to flip-flops and SRAM, the log storage unit 75 may also be an empty area of ​​the data memory array 10 or the reference memory array 20, for example.

[0033] The main unit 120 includes an address control unit 121, a command control unit 122, and a data control unit 123. For example, the main unit 120 could be a memory controller, a CPU (Central Processing Unit), or the like.

[0034] The address control unit 121 outputs addresses input from an external source to the address control unit 71 of the semiconductor memory device 110. The command control unit 122 outputs commands input from an external source to the command control unit 72 of the semiconductor memory device 110. The data control unit 123 outputs data input from an external source to the error processing unit 73 of the semiconductor memory device 110.

[0035] <1-2. Example of Log Information Configuration> An example of the log information configuration according to the first embodiment will be described with reference to Figures 2 and 3. Figures 2 and 3 are diagrams showing example configurations of log information (for example, log information A1, A2, and A3) according to the first embodiment.

[0036] As shown in Figure 2, log information A1 is error history information that includes error information for each reference cell 21 (for example, address information of the reference cell 21). Error information is, for example, information indicating whether or not an error occurred. Address information is, for example, information indicating the position of the reference cell 21 by the individual numbers of the row address and column address.

[0037] In log information A1, for example, there is no error in reference cell 21 with row address 0 and column address 0, there is an error in reference cell 21 with row address 0 and column address 1, there is an error in reference cell 21 with row address 0 and column address 2, and so on. Error information is generated for each reference cell 21.

[0038] In the example shown in Figure 2, log information A1 contains individual error information for all reference cells 21, each corresponding to all data cells 11. In this case, log information A1 is highly accurate, but the storage capacity of the log storage unit 75 becomes large.

[0039] Therefore, as shown in Figure 2, in log information A2, the error information for each reference cell 21 is compressed in the row-arrangement direction (row address direction: up and down in Figure 2). In the example in Figure 2, five rows are compressed into one row. For example, if there is an error in any of the five data cells 11 corresponding to the five reference cells 21 compressed in the row-arrangement direction, then there will be an error in the one reference cell 21 compressed in the row-arrangement direction. On the other hand, if there are no errors in any of the five data cells 11 corresponding to the five reference cells 21 compressed in the row-arrangement direction, then there will be no errors in the one reference cell 21 compressed in the row-arrangement direction. In this case, one reference cell 21 will correspond to five data cells 11 arranged in the row-arrangement direction.

[0040] Furthermore, as shown in Figure 3, in log information A3, the error information for each reference cell 21 is compressed in the direction of the column arrangement (column address direction: left to right in Figure 3). In the example in Figure 3, five columns are compressed into one column. For example, if there is an error in any of the five data cells 11 corresponding to the five reference cells 21 compressed in the direction of the column arrangement, then there will be an error in the one reference cell 21 compressed in the direction of the column arrangement. On the other hand, if there are no errors in any of the five data cells 11 corresponding to the five reference cells 21 compressed in the direction of the column arrangement, then there will be no errors in the one reference cell 21 compressed in the direction of the column arrangement. In this case, one reference cell 21 will correspond to five data cells 11 arranged in the direction of the column arrangement.

[0041] In this way, in each log information A2 and A3, the error information for each reference cell 21 is compressed in either the row-order direction or the column-order direction. This reduces the storage capacity of the log storage unit 75.

[0042] In the examples in Figures 2 and 3, the error information for each reference cell 21 is compressed in either the row-order direction or the column-order direction, but this is not limited to this, and it may be compressed in both the row-order direction and the column-order direction.

[0043] <1-3. Example of Reference Potential Generation> An example of reference potential generation (reference sharing method) according to the first embodiment will be described with reference to FIG. 4. FIG. 4 is a diagram for explaining an example of reference potential generation according to the first embodiment.

[0044] As shown in FIG. 4, a plurality of sense amplifiers 51 are provided. These sense amplifiers 51 are provided, for example, in a read control unit 60 (see FIG. 1). A data cell 11 and a reference cell 21 are electrically connected to each of the sense amplifiers 51. The data cell 11 includes an MTJ element 12 and a transistor 13. The reference cell 21 includes an MTJ element 22 and a transistor 23. Each of the MTJ elements 12 and 22 is an example of the aforementioned memory element, and each of the transistors 13 and 23 is an example of the aforementioned selection element.

[0045] The sense amplifier 51 compares the potential (for example, resistance value: data resistance) of the data cell 11 with a reference potential (for example, reference resistance value: reference resistance), and reads data from the data cell 11. Specifically, when reading data from the data cell 11, the sense amplifier 51 compares the potential output from the data cell 11 through a bit line with the reference potential generated by the reference cell 21, and outputs data indicating that the potential is lower (L) or higher (H) than the reference potential. The reference potential is a potential for determining whether the data in the data cell 11 is at a low potential or a high potential. Determining whether the data is at a low potential or a high potential means determining whether the data cell 11 is in a low resistance state or a high resistance state.

[0046] As a method of generating a reference potential (e.g., a reference resistance value), for example, an intermediate resistance value that is an intermediate value between a high resistance value (RH) and a low resistance value (RL) is used. In this case, a wider read margin can be obtained. The intermediate resistance value is obtained by connecting reference cells 21 having a high resistance value (RH) and reference cells 21 having a low resistance value (RL) in series and in parallel. Therefore, an intermediate resistance value for one data cell 11 is obtained by connecting a predetermined number of reference cells 21. The correspondence between one data cell 11 and the predetermined number of reference cells 21 is included, for example, in log information. Therefore, it can be identified which reference cell 21 in the reference memory array 20 is used for generating a reference potential for one data cell 11. Note that short-circuiting a plurality of reference cells 21 can also suppress variations in reference potential.

[0047] <1-4. Processing Example of Read Operation> A processing example of the read operation according to the first embodiment will be described with reference to FIGS. 5 to 7. FIG. 5 is a flowchart showing a processing example of the read operation according to the first embodiment. Each of FIGS. 6 and 7 is a diagram for explaining an example of correction of the reference cell 21 according to the first embodiment.

[0048] As shown in FIG. 5, an error processing unit 73 determines whether there is an error in read data (for example, either the data cell 11 or the reference cell 21) (step S11). If the error processing unit 73 determines that there is no error (step S11: No), the process ends. On the other hand, if the error processing unit 73 determines that there is an error (step S11: Yes), a log processing unit 74 reads log information from a log storage unit 75 (step S12), and determines whether an error history exists in the read log information (step S13).

[0049] If the log processing unit 74 determines that there is no error history (step S13: No), the log processing unit 74 updates the log information (step S14), and ends the process. On the other hand, if the log processing unit 74 determines that there is an error history (step S13: Yes), the log processing unit 74 instructs writing to the target reference cell 21 (step S15), updates the log information (step S14), and also outputs a reference cell error notification signal (step S16), and ends the process.

[0050] In step S15, the log processing unit 74, for example, outputs the address information of the target reference cell 21, thereby instructing the write control unit 50 to write to the reference cell 21 via the command control unit 72. Furthermore, when instructing to write to the data cell 11, the log processing unit 74 outputs the address information of the target data cell 11, thereby instructing the write control unit 50 to write to the data cell 11 via the command control unit 72.

[0051] (Correction Example) As shown in Figure 6, an error (data inversion) occurs in a reference cell 21, but as shown in Figure 7, the error is corrected. The process flow from the occurrence of this error to its correction will be explained using the presence or absence of an error in the target reference cell 21 and the presence or absence of error history in the log status (log information).

[0052] As shown in Figure 6, under normal conditions, the target reference cell 21 is "○" and the log status is "No history". "○" indicates that there are no errors in the target reference cell 21. "No history" indicates that there is no error history for the target reference cell 21 in the log information.

[0053] In step S11, it is determined that there is an error (Yes). The error occurred unintentionally due to some factor (Error present). At this time, the target reference cell 21 is "×" and the log status is "No history". "×" indicates that there is an error in the target reference cell 21.

[0054] In step S12, the log information of the target reference cell 21 is read. At this time, the target reference cell 21 is "×" and the log status is "No history".

[0055] In step S13, it is determined that there is no error history (No), and in step S14, the log information of the target reference cell 21 is updated. At this time, reference cell 21 is "×", and the log status is "history exists".

[0056] Next, as shown in Figure 7, the target reference cell 21 is in an abnormal state (error present). In this case, the target reference cell 21 is marked with "×", and the log status is "history present".

[0057] In step S12, the log information of the target reference cell 21 is read. At this time, the target reference cell 21 is "×" and the log status is "history exists".

[0058] In step S13, it is determined that there is an error history (Yes), and in step S15, writing to the target reference cell 21 is performed. As a result, the target reference cell 21 changes from an abnormal state to a normal state. At this time, the reference cell 21 is "〇" and the log status is "History exists".

[0059] In step S14, the log information of the target reference cell 21 is updated. At this time, reference cell 21 is "〇" and the log status is "No history". Reference cell 21 returns to a normal state.

[0060] According to the first embodiment, the log processing unit 74 stores log information, including the error history of the reference cell 21, in the log storage unit 75. Subsequently, the log processing unit 74 reads the log information from the log storage unit 75 and determines whether or not the reference cell 21 has an error history based on the read log information. Depending on the result of this determination, it becomes possible to correct the error in the reference cell 21, thereby improving reliability.

[0061] <2. Second Embodiment> <2-1. Example of Memory System Configuration> An example of the configuration of the memory system 100 according to the second embodiment will be described with reference to Figure 8. Figure 8 is a diagram showing an example of the configuration of the memory system 100 according to the second embodiment.

[0062] As shown in Figure 8, in the second embodiment, the main device 120 includes a memory control unit 124, an error processing unit 73, a log processing unit 74, and a log storage unit 75. In other words, the memory control unit 124, the error processing unit 73, the log processing unit 74, and the log storage unit 75 are located within the main device 120. This is the only difference from the first embodiment; otherwise, it is the same as the first embodiment. The second embodiment can achieve the same effects as the first embodiment. The memory control unit 124 outputs addresses input from the outside to the address control unit 71 and outputs commands input from the outside to the command control unit 72.

[0063] <3. Third Embodiment> <3-1. Example of Memory System Configuration> An example of the configuration of the memory system 100 according to the third embodiment will be described with reference to Figure 9. Figure 9 is a diagram showing an example of the configuration of the memory system 100 according to the third embodiment.

[0064] As shown in Figure 9, in the third embodiment, if the log processing unit 74 determines, based on the log information, that there is no error history for the target reference cell 21, it outputs the write address (data cell address information) to the target data cell 11 to the command control unit 72. This is the difference from the first embodiment, although the configuration itself is the same as in the first embodiment. Note that the target reference cell 21 and the target data cell 11 are cells to be read.

[0065] <3-2. Example of Read Operation Processing> An example of read operation processing according to the third embodiment will be described with reference to Figures 10 to 13. Figure 10 is a flowchart of the read operation processing example according to the third embodiment. Figures 11 to 13 are diagrams illustrating examples of correction of data cell 11 according to the third embodiment.

[0066] As shown in Figure 10, the error processing unit 73 determines whether or not there is an error in the read data (for example, either data cell 11 or reference cell 21) (step S11). If the error processing unit 73 determines that there is no error (step S11: No), it terminates the process. On the other hand, if the error processing unit 73 determines that there is an error (step S11: Yes), the log processing unit 74 reads log information from the log storage unit 75 (step S12) and determines whether or not there is an error history in the read log information (step S13).

[0067] If the log processing unit 74 determines that there is no error history (step S13: No), it instructs the system to write to the target data cell 11 (step S21), updates the log information (step S14), and terminates the process. On the other hand, if the log processing unit 74 determines that there is an error history (step S13: Yes), it instructs the system to write to the target reference cell 21 (step S15), updates the log information (step S14), outputs a reference cell error notification signal (step S16), and terminates the process.

[0068] (Correction Example 1) As shown in Figure 11, an error (data inversion) occurs in a data cell 11, but this error is corrected. The process flow from the occurrence of this error to its correction will be explained using the presence or absence of errors in the target data cell 11 and the presence or absence of error history in the log status (log information).

[0069] As shown in Figure 11, under normal conditions, the target data cell 11 is marked "○" and the log status is "No history". "○" indicates that there are no errors in the target data cell 11. "No history" indicates that there is no error history in the log information for the reference cell 21 corresponding to the target data cell 11. The reference cell 21 corresponding to the target data cell 11 is the reference cell 21 used for the reference potential of the data cell 11.

[0070] In step S11, it is determined that there is an error (Yes). An error has occurred unintentionally due to some factor (Error present). At this time, the target data cell 11 is marked with "×", and the log status is "No history". "×" indicates that there is an error in the target data cell 11.

[0071] In step S12, the log information of the reference cell 21 corresponding to the target data cell 11 is read. At this time, the target data cell 11 is "×" and the log status is "No history".

[0072] In step S13, it is determined that there is no error history (No), and in step S21, writing to data cell 11 is instructed and executed. At this time, the target data cell 11 is "〇" and the log status is "No history".

[0073] In step S14, the log information of the target reference cell 21 corresponding to the target data cell 11 is updated. At this time, data cell 11 is "〇" and the log status is "history exists". Data cell 11 returns to a normal state.

[0074] (Correction Example 2) Correction Example 2 is a modified version of Correction Example 1 described above. In Correction Example 2, the position of writing to data cell 11 (step S21) is different from that of Correction Example 1. That is, step S21 is located between step S11 and step S12.

[0075] As shown in Figure 12, if an error is determined in step S11 (Yes), then writing to data cell 11 is performed in step S21. At this time, the target data cell 11 is "○" and the log status is "No history". Thus, the timing of writing to data cell 11 is different from that in Correction Example 1.

[0076] (Correction Example 3) Correction Example 3 is a modified version of Correction Example 1 described above. In Correction Example 3, the position of writing to data cell 11 (step S21) differs from that of Correction Example 1 and Correction Example 2. That is, step S21 is located after step S14.

[0077] As shown in Figure 13, in step S14, the log information of the target reference cell 21 corresponding to the target data cell 11 is updated, and in step S21, writing to the data cell 11 is performed. At this time, the target data cell 11 is "○" and the log status is "history exists". Thus, the timing of writing to the data cell 11 differs from that of correction example 1 and correction example 2.

[0078] <3-3. Examples of other read operations> Examples of other read operations according to the third embodiment will be described with reference to Figures 14 to 16. Figure 14 is a flowchart showing an example of another read operation according to the third embodiment. Figures 15 and 16 are diagrams illustrating examples of corrections to the data cell 11 according to the third embodiment.

[0079] As shown in Figure 14, the error processing unit 73 determines whether or not there is an error in the read data (for example, either data cell 11 or reference cell 21) (step S11). If the error processing unit 73 determines that there is no error (step S11: No), it terminates the process. On the other hand, if the error processing unit 73 determines that there is an error (step S11: Yes), the log processing unit 74 reads log information from the log storage unit 75 (step S12) and determines whether or not there is an error history in the read log information (step S13).

[0080] If the log processing unit 74 determines that there is no error history (step S13: No), it instructs the system to write to the target data cell 11 (step S21), updates the log information (step S14), and terminates the process. On the other hand, if the log processing unit 74 determines that there is an error history (step S13: Yes), it instructs the system to write to the target data cell 11 and the target reference cell 21 (step S31), updates the log information (step S14), outputs a reference cell error notification signal (step S16), and terminates the process.

[0081] (Correction Example 1) As shown in Figure 15, an error (data inversion) occurs in a data cell 11, but this error is corrected. The process flow from the occurrence of this error to its correction will be explained using the presence or absence of errors in the target data cell 11 and the presence or absence of error history in the log status (log information).

[0082] As shown in Figure 15, under normal conditions, the target data cell 11 is "○" and the log status is "No history".

[0083] In step S11, it is determined that an error exists (Yes). The error occurred unintentionally due to some factor (Error present). At this time, the target data cell 11 is "×" and the log status is "No history".

[0084] In step S12, the log information of the reference cell 21 corresponding to the target data cell 11 is read. At this time, the target data cell 11 is "×" and the log status is "No history".

[0085] In step S13, it is determined that there is no error history (No), and in step S21, writing to data cell 11 is performed. At this time, the target data cell 11 is "〇" and the log status is "No history".

[0086] In step S14, the log information of the target reference cell 21 corresponding to the target data cell 11 is updated. At this time, data cell 11 is "〇" and the log status is "history exists". Data cell 11 returns to a normal state.

[0087] (Correction Example 2) Unlike the aforementioned Correction Example 1, in Correction Example 2, the log status is "history exists" at the initial stage. The process in this case will be explained below.

[0088] As shown in Figure 16, in step S11, it is determined that an error has occurred (Yes). The error occurred unintentionally due to some factor (Error present). At this time, the target data cell 11 is marked "×", and the log status is "History present".

[0089] In step S12, log information for the reference cell 21 corresponding to the target data cell 11 is read. At this time, the target data cell 11 is "×" and the log status is "history exists".

[0090] In step S13, it is determined that there is an error history (Yes), and in step S31, writing to data cell 11 and reference cell 21 is performed. At this time, the target data cell 11 is "○" and the log status is "history exists".

[0091] In step S14, the log information of the reference cell 21 corresponding to the target data cell 11 is updated. At this time, data cell 11 is "〇" and the log status is "No history". Data cell 11 returns to a normal state. Reference cell 21 also returns to a normal state.

[0092] According to the third embodiment, in addition to the same effects as the first embodiment, it becomes possible to correct errors in the data cell 11, thereby further improving reliability.

[0093] <4. Installation Variations> Installation variations of the error processing unit 73, log processing unit 74, and log storage unit 75 according to each embodiment will be described with reference to Figures 17 to 19. Each of Figures 17 to 19 is a diagram illustrating the installation variations of the error processing unit 73, log processing unit 74, and log storage unit 75 according to each embodiment described above.

[0094] As shown in Figure 17, the storage system 100 is composed of a semiconductor storage device 110 and a main device 120. The semiconductor storage device 110 includes an error processing unit 73, a log processing unit 74, and a log storage unit 75 (see Figure 1 of the first embodiment or Figure 9 of the third embodiment). In other words, the error processing unit 73, the log processing unit 74, and the log storage unit 75 are located within the semiconductor storage device 110.

[0095] As shown in Figure 18, the storage system 100, like in Figure 17, is composed of a semiconductor memory device 110 and a main device 120. The main device 120 includes an error processing unit 73, a log processing unit 74, and a log storage unit 75 (see Figure 8 of the second embodiment). In other words, the error processing unit 73, the log processing unit 74, and the log storage unit 75 are located within the main device 120.

[0096] As shown in Figure 19, unlike Figures 17 and 18, the memory system 100 is composed of a semiconductor memory device 110, a main device 120, and a memory device 130. The main device 120 includes an error processing unit 73 and a log processing unit 74. In other words, the error processing unit 73 and the log processing unit 74 are located within the main device 120. The memory device 130 includes a log storage unit 75. In other words, the log storage unit 75 is located within the memory device 130.

[0097] The main device 120 is communicatively connected to the semiconductor memory device 110 and the memory device 130. The memory device 130 is provided separately from the semiconductor memory device 110, for example. An SRAM or the like can be used as the memory device 130. The semiconductor memory device 110 is an example of a first memory device, and the memory device 130 is an example of a second memory device.

[0098] While various installation variations like these are possible, the system is not limited to these, and other installation variations may also be used.

[0099] <5. Operation and Effects of Each Embodiment> As described above, the storage system 100 according to each embodiment includes a data cell 11 with a variable resistance value, a reference cell 21 with a variable resistance value, a read control unit 60 that reads data by comparing the resistance values ​​of the data cell 11 and the reference cell 21, an error processing unit 73 that determines whether or not there are errors in the data, and a log storage unit 75 that stores log information including the error history of the reference cell 21 based on the data determination result (see Figure 1, etc.). As a result, log information including the error history of the reference cell 21 can be stored in the log storage unit 75, and it is possible to determine whether or not there are errors in the reference cell 21 based on the log information. Therefore, it becomes possible to correct errors in the reference cell 21, thereby improving reliability.

[0100] Furthermore, the storage system 100 may also include a log processing unit 74 that determines whether or not to write to the reference cell 21 based on the determination result and log information (see Figures 1, 5 to 7). This can reliably improve reliability.

[0101] Furthermore, the storage system 100 further includes a write control unit 50 that controls writing to the data cell 11 and the reference cell 21, and the log processing unit 74 may instruct the write control unit 50 to write to the reference cell 21 if there is an error in the data and there is an error history in the log information (see Figures 1, 5 to 7). This ensures improved reliability.

[0102] Furthermore, if there is an error in the data, the log processing unit 74 may instruct the write control unit 50 to write to the data cell 11 (see Figures 10 to 16). This can reliably improve reliability.

[0103] Furthermore, the log processing unit 74 may instruct the write control unit 50 to write to the data cell 11 before reading the log information from the log storage unit 75 (see Figure 12). This can reliably improve reliability.

[0104] Furthermore, the log processing unit 74 may instruct the write control unit 50 to write the log information to the data cell 11 after reading it from the log storage unit 75 (see Figure 13). This ensures a significant improvement in reliability.

[0105] Furthermore, the log processing unit 74 may update the log information if there are errors in the data (see Figures 5 to 7 and 10 to 16). This can reliably improve reliability.

[0106] Furthermore, the log processing unit 74 may output information (for example, a read completion notification signal) that notifies the completion of the data and reference data read operation (see Figure 1, etc.). This can reliably improve reliability.

[0107] Furthermore, the log processing unit 74 may output information (for example, a reference cell error notification signal) that indicates an error in the reference cell 21 (see Figures 1 and 5, etc.). This can reliably improve reliability.

[0108] Furthermore, multiple data cells 11 are arranged in a matrix, and multiple reference cells 21 are also arranged in a matrix. The log information may include error information for each address, indicating whether or not there is an error for each address of the reference cell 21 (see Figure 2). This can reliably improve reliability.

[0109] Furthermore, the error information for each reference cell 21 may be compressed in the row-arrangement direction (row address direction) (see Figure 3). This reduces the planar size of the reference memory array 20 and the storage capacity of the log storage unit 75.

[0110] Furthermore, the error information for each reference cell 21 may be compressed in the direction of the column arrangement (column address direction) (see Figure 2). This reduces the planar size of the reference memory array 20 and the storage capacity of the log storage unit 75.

[0111] Furthermore, the error information for each reference cell 21 may be compressed in the row-direction (row address direction) and the column-direction (column address direction) (see Figures 2 and 3). This reduces the storage capacity of the log storage unit 75.

[0112] Furthermore, the log storage unit 75 may include a flip-flop or SRAM (see Figure 1, etc.). This simplifies the configuration of the log storage unit 75.

[0113] Furthermore, the log storage unit 75 may include free space in a memory (for example, a data memory array 10 or a reference memory array 20) having multiple data cells 11 or reference cells 21 (see Figure 1, etc.). This simplifies the configuration of the log storage unit 75.

[0114] Furthermore, each of the data cell 11 and the reference cell 21 may include a magnetoresistive element (see Figure 1, etc.). Reliability can also be improved with such a configuration.

[0115] <6. Other Embodiments> The configurations and processes described in the above-described embodiments (including examples and modifications) may be implemented in various other forms besides those described above. For example, the configurations and processes may be in various forms, not limited to the examples described above. Also, for example, the configurations, processing procedures, specific names, and information including various data and parameters shown in the above document and drawings may be changed at will unless otherwise specified.

[0116] Furthermore, the configurations and processes described in the above-mentioned embodiments (including examples and modifications) do not necessarily have to be physically configured as shown in the figures. In other words, the specific forms of distribution and integration of each configuration and process are not limited to those shown in the figures, and all or part of them may be functionally or physically distributed and integrated in any unit depending on various loads and usage conditions.

[0117] Furthermore, the various configurations and processes described in the above-mentioned embodiments (including examples and modifications) may be combined as appropriate. For example, at least a part of one embodiment may be combined with at least a part of another embodiment as appropriate. Also, the effects described in the embodiments are merely illustrative and not limiting, and other effects may also occur.

[0118] <7. Application Examples> <7-1. Various Devices> Application examples of the memory system 100 according to each embodiment (including examples and modified versions) described above will be explained with reference to Figure 20. Figure 20 is a diagram showing application examples of the memory system 100 according to each embodiment described above. The memory system 100 may be applied to various cases, i.e., various devices (an example of electronic equipment), as follows.

[0119] As shown in Figure 20, the memory system 100 is used in, for example, "devices that capture images for viewing purposes, such as digital cameras and portable devices with camera functions," "devices used for traffic purposes, such as in-vehicle sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles," "devices used in home appliances such as TVs, refrigerators, and air conditioners to capture user gestures and operate the device according to those gestures," "devices used for medical and healthcare purposes, such as endoscopes and devices that perform angiography by receiving infrared light," "devices used for security purposes, such as surveillance cameras for crime prevention and cameras for person recognition," "devices used for beauty purposes, such as skin measuring devices that capture images of the skin and microscopes that capture images of the scalp," "devices used for sports purposes, such as action cameras and wearable cameras for sports use," and "devices used for agriculture, such as cameras for monitoring the condition of fields and crops."

[0120] Furthermore, the technology disclosed herein can be applied to a variety of products. For example, the technology disclosed herein may be implemented as electronic equipment mounted on any type of mobile device, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, robots, construction machinery, or agricultural machinery (tractors). Alternatively, the technology disclosed herein may be implemented as electronic equipment mounted on, for example, an endoscopic surgical system or a microsurgical system.

[0121] <7-2. Imaging Device> The imaging device 1000 according to the application example will be described with reference to Figure 21. Figure 21 is a diagram showing an example configuration of the imaging device 1000 according to the application example. This imaging device 1000 is an example of an electronic device to which the memory system 100 according to any of the embodiments described above is applied. Examples of the imaging device 1000 include digital still cameras, video cameras, smartphones and mobile phones with imaging functions, and other electronic devices.

[0122] As shown in Figure 21, the imaging device 1000 includes an optical system 1001, a shutter device 1002, an image sensor (solid-state imager) 1003, a control circuit (drive circuit) 1004, a signal processing circuit 1005, a monitor 1006, and a memory 1007. This imaging device 1000 is capable of capturing both still and moving images.

[0123] The optical system 1001 has one or more lenses. This optical system 1001 guides light from the subject (incident light) to the image sensor 1003 and forms an image on the light-receiving surface of the image sensor 1003.

[0124] The shutter device 1002 is positioned between the optical system 1001 and the image sensor 1003. The shutter device 1002 controls the light illumination period and the light shielding period for the image sensor 1003 according to the control of the control circuit 1004.

[0125] The image sensor 1003 accumulates signal charge for a certain period of time in response to light formed on the light-receiving surface via the optical system 1001 and shutter device 1002. The signal charge accumulated in the image sensor 1003 is transferred according to a drive signal (timing signal) supplied from the control circuit 1004. As the image sensor 1003, a solid-state imaging device such as an image sensor is used, for example.

[0126] The control circuit 1004 drives the image sensor 1003 and the shutter device 1002 by outputting drive signals that control the transfer operation of the image sensor 1003 and the shutter operation of the shutter device 1002. As the control circuit 1004, for example, the main device 120 according to any of the embodiments described above is used.

[0127] The signal processing circuit 1005 performs various signal processing operations on the signal charge output from the image sensor 1003. The image (image data) obtained by the signal processing circuit 1005 is supplied to the monitor 1006 and also to the memory 1007.

[0128] The monitor 1006 displays a video or still image captured by the image sensor 1003 based on image data supplied from the signal processing circuit 1005. For example, the monitor 1006 may be a panel-type display device such as a liquid crystal panel or an organic EL (Electro-Luminescence) panel.

[0129] The memory 1007 stores image data supplied from the signal processing circuit 1005, that is, image data of moving or still images captured by the image sensor 1003. As the memory 1007, for example, a semiconductor memory device 110 according to any of the embodiments described above is used.

[0130] Even in the imaging device 1000 configured in this way, the same effects as in any of the above embodiments can be obtained by applying the storage system 100 according to any of the above embodiments.

[0131] <7-3. Distance Measuring Device> The distance measuring device 2000 according to the application example will be described with reference to Figure 22. Figure 22 is a diagram showing an example configuration of the distance measuring device 2000 according to the application example. This distance measuring device 2000 is an example of an electronic device to which the storage system 100 according to any of the embodiments described above is applied.

[0132] As shown in Figure 22, the distance measuring device (distance image sensor) 2000 comprises a light source unit 2001, an optical system 2002, an image sensor (solid-state imager) 2003, a control circuit (drive circuit) 2004, a signal processing circuit 2005, a monitor 2006, and a memory 2007. This distance measuring device 2000 projects light from the light source unit 2001 toward the subject and receives the light (modulated light or pulsed light) reflected from the surface of the subject, thereby acquiring a distance image corresponding to the distance to the subject.

[0133] The light source unit 2001 projects light toward the subject. Examples of light sources used for the light source unit 2001 include a vertical cavity surface-emitting laser (VCSEL) array that emits laser light as a surface light source, and a laser diode array in which laser diodes are arranged in a line. The laser diode array is supported by a predetermined drive unit (not shown) and scanned in a direction perpendicular to the arrangement of the laser diodes.

[0134] The optical system 2002 has one or more lenses. This optical system 2002 guides light from the subject (incident light) to the image sensor 2003 and forms an image on the light-receiving surface (sensor part) of the image sensor 2003.

[0135] The image sensor 2003 accumulates signal charge in response to light formed on the light-receiving surface via the optical system 2002. A distance signal indicating the distance, determined from the light-receiving signal (APD OUT) output from the image sensor 2003, is supplied to the signal processing circuit 2005. As the image sensor 2003, a solid-state imaging device such as an image sensor is used, for example.

[0136] The control circuit 2004 outputs drive signals (control signals) that control the operation of the light source unit 2001 and the image sensor 2003, and drives the light source unit 2001 and the image sensor 2003. As the control circuit 2004, for example, the main device 120 according to any of the embodiments described above is used.

[0137] The signal processing circuit 2005 performs various signal processing operations on the distance signal supplied from the image sensor 2003. For example, the signal processing circuit 2005 performs image processing (e.g., histogram processing and peak detection processing) to construct a distance image based on the distance signal. The image (image data) obtained by the signal processing circuit 2005 is supplied to the monitor 2006 and also to the memory 2007.

[0138] The monitor 2006 displays the distance image captured by the image sensor 2003 based on the image data supplied from the signal processing circuit 2005. For example, a panel-type display device such as a liquid crystal panel or an organic EL panel can be used as the monitor 2006.

[0139] The memory 2007 stores image data supplied from the signal processing circuit 2005, that is, image data of the distance image captured by the image sensor 2003. As the memory 2007, for example, a semiconductor memory device 110 according to any of the embodiments described above is used.

[0140] Even with the distance measuring device 2000 configured in this way, the same effects as in any of the above embodiments can be obtained by applying the storage system 100 according to any of the above embodiments.

[0141] As described above, the storage system 100 according to each embodiment described above can be implemented in various electronic devices. For example, the storage system 100 according to any of the embodiments described above may be installed in various electronic devices other than imaging devices 1000 and distance measuring devices 2000, such as HDDs (hard disk drives), notebook PCs (personal computers), mobile devices (e.g., smartphones and tablet PCs), PDAs (personal digital assistants), wearable devices, game devices, and music players. For example, the storage system 100 may be installed as various types of memory, such as storage.

[0142] <8. Addendum> The technology can also be configured as follows: (1) A storage device comprising: a data cell with a variable resistance value; a reference cell with a variable resistance value; a read control unit that reads data by comparing the resistance value of the data cell and the resistance value of the reference cell; an error processing unit that determines whether or not there is an error in the data; and a log storage unit that stores log information including the error history of the reference cell based on the determination result of the data. (2) The storage device according to (1), further comprising a log processing unit that determines whether or not to perform a write to the reference cell based on the determination result and the log information. (3) The storage device according to (2), further comprising a write control unit that controls writing to the data cell and the reference cell, wherein the log processing unit instructs the write control unit to write to the reference cell if there is an error in the data and there is an error history in the log information. (4) The storage device according to (3), wherein the log processing unit instructs the write control unit to write to the data cell if there is an error in the data. (5) The storage device according to (4), wherein the log processing unit instructs the write control unit to write to the data cell before reading the log information from the log storage unit. (6) The storage device according to (4), wherein the log processing unit instructs the write control unit to write to the data cell after reading the log information from the log storage unit. (7) The storage device according to any one of (2) to (6), wherein the log processing unit updates the log information if there is an error in the data. (8) The storage device according to any one of (2) to (7), wherein the log processing unit outputs information notifying the completion of the data reading operation. (9) The storage device according to any one of (2) to (8), wherein the log processing unit outputs information notifying that there is an error in the reference cell. (10) A storage device according to any one of (1) to (9), wherein the data cells are arranged in a matrix, the reference cells are arranged in a matrix, and the log information includes error information for each address information indicating whether or not the error is present for each address information of the reference cell.(11) The storage device according to (10), wherein the error information for each reference cell is compressed in the row-by-row direction. (12) The storage device according to (10), wherein the error information for each reference cell is compressed in the column-by-column direction. (13) The storage device according to (10), wherein the error information for each reference cell is compressed in both the row-by-row direction and the column-by-column direction. (14) The storage device according to any one of (1) to (13), wherein the log storage unit includes a flip-flop or SRAM (Static Random Access Memory). (15) The storage device according to any one of (1) to (13), wherein the log storage unit includes an empty memory area having a plurality of data cells or reference cells. (16) The storage device according to any one of (1) to (15), wherein each of the data cells and reference cells includes a magnetoresistive element. (17) A storage system comprising: a storage device; and a main device communicatively connected to the storage device, wherein the storage device includes: a data cell with a variable resistance value; a reference cell with a variable resistance value; and a read control unit that reads data by comparing the resistance value of the data cell with the resistance value of the reference cell, and the storage device or the main device includes: an error processing unit that determines whether or not there is an error in the data; and a log storage unit that stores log information including the error history of the reference cell based on the determination result of the data. (18) The storage system according to (17), wherein the main device includes the error processing unit and the log storage unit. (19) The storage system according to (17), comprising: a first storage device and a second storage device, wherein the first storage device includes the data cell, the reference cell and the read control unit; the main device includes the error processing unit; and the second storage device includes the log storage unit.(20) A storage method comprising: reading data by comparing the resistance value of a data cell whose resistance value is variable with the resistance value of a reference cell whose resistance value is variable; determining whether or not there is an error in the data; and storing log information including the error history of the reference cell based on the determination result of the data. (21) A storage system comprising the storage device described in any one of (1) to (16). (22) A storage method that performs storage using the storage device described in any one of (1) to (16).

[0143] 10 Data memory array 11 Data cell 12 MTJ element 13 Transistor 20 Reference memory array 21 Reference cell 22 MTJ element 23 Transistor 30 Row selection unit 40 Column selection unit 50 Write control unit 51 Sense amplifier 60 Read control unit 70 Control unit 71 Address control unit 72 Command control unit 73 Error processing unit 74 Log processing unit 75 Log storage unit 100 Storage system 110 Semiconductor storage device 120 Main unit 121 Address control unit 122 Command control unit 123 Data control unit 130 Storage device A1 Log information A2 Log information A3 Log information

Claims

1. A storage device comprising: a data cell with a variable resistance value; a reference cell with a variable resistance value; a read control unit that reads data by comparing the resistance value of the data cell with the resistance value of the reference cell; an error processing unit that determines whether or not there is an error in the data; and a log storage unit that stores log information including the error history of the reference cell based on the determination result of the data.

2. The storage device according to claim 1, further comprising a log processing unit that determines whether or not to perform writing to the reference cell based on the determination result and the log information.

3. The storage device according to claim 2, further comprising a write control unit that controls writing to the data cell and the reference cell, wherein the log processing unit instructs the write control unit to write to the reference cell if there is an error in the data and there is an error history in the log information.

4. The storage device according to claim 3, wherein the log processing unit instructs the write control unit to write to the data cell if there is an error in the data.

5. The storage device according to claim 4, wherein the log processing unit instructs the write control unit to write to the data cell before reading the log information from the log storage unit.

6. The storage device according to claim 4, wherein the log processing unit reads the log information from the log storage unit and then instructs the write control unit to write it to the data cell.

7. The storage device according to claim 2, wherein the log processing unit updates the log information if there is an error in the data.

8. The storage device according to claim 2, wherein the log processing unit outputs information indicating the completion of the data reading operation.

9. The storage device according to claim 2, wherein the log processing unit outputs information indicating that there is an error in the reference cell.

10. The storage device according to claim 1, wherein the data cells are arranged in a matrix, the reference cells are arranged in a matrix, and the log information includes error information for each address, indicating whether or not the error is present for each address of the reference cell.

11. The storage device according to claim 10, wherein the error information for each reference cell is compressed in the row-by-row direction.

12. The storage device according to claim 10, wherein the error information for each reference cell is compressed in the direction of the columns.

13. The storage device according to claim 10, wherein the error information for each reference cell is compressed in the row-by-row direction and the column-by-column direction.

14. The storage device according to claim 1, wherein the log storage unit includes a flip-flop or SRAM (Static Random Access Memory).

15. The storage device according to claim 1, wherein the log storage unit includes a free area of ​​memory having a plurality of data cells or reference cells.

16. The storage device according to claim 1, wherein each of the data cell and the reference cell includes a magnetoresistive element.

17. A storage system comprising: a storage device; and a main device communicatively connected to the storage device, wherein the storage device includes: a data cell with a variable resistance value; a reference cell with a variable resistance value; and a read control unit that reads data by comparing the resistance value of the data cell with the resistance value of the reference cell, and the storage device or the main device includes: an error processing unit that determines whether or not there is an error in the data; and a log storage unit that stores log information including the error history of the reference cell based on the determination result of the data.

18. The storage system according to claim 17, wherein the main device includes the error processing unit and the log storage unit.

19. The storage system according to claim 17, wherein the storage device comprises a first storage device and a second storage device, the first storage device includes the data cell, the reference cell and the read control unit, the main device includes the error processing unit, and the second storage device includes the log storage unit.

20. A storage method comprising: reading data by comparing the resistance value of a data cell whose resistance value is variable with the resistance value of a reference cell whose resistance value is variable; determining whether or not there is an error in the data; and storing log information including the error history of the reference cell based on the determination result of the data.

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