Photodetector and electronic device

Abstract

A photodetector according to an embodiment of the present disclosure comprises: a first semiconductor layer which has a first surface and a second surface opposite to each other and in which a sensor pixel for performing photoelectric conversion is formed; and a second semiconductor layer which is laminated on the first surface side of the first semiconductor layer and has a third surface facing the first surface and a fourth surface opposite to the third surface and in which a plurality of pixel transistors constituting a readout circuit for outputting a pixel signal based on a charge output from the sensor pixel are formed. One or more contact wirings are connected to each of the plurality of pixel transistors from one or both of the third surface side and the fourth surface side.

Description

Photodetector and electronic device

[0001] The present disclosure relates to a photodetector and an electronic device in which a plurality of semiconductor layers are stacked.

[0002] For example, Non-Patent Document 1 discloses an imaging device in which a first substrate including a first semiconductor substrate and having sensor pixels that perform photoelectric conversion, and a second substrate including a second semiconductor substrate and having a readout circuit that outputs pixel signals based on charges output from the sensor pixels are electrically connected to each other through a through-wiring penetrating the second semiconductor substrate.

[0003] International Publication No. 2019 / 130702

[0004] Incidentally, in a photodetector in which a plurality of semiconductor layers are stacked, improvement of the area efficiency of the semiconductor layer provided with a readout circuit is required.

[0005] It is desirable to provide a photodetector and an electronic device capable of improving the area efficiency of a semiconductor layer provided with a readout circuit in a configuration in which a plurality of semiconductor layers are stacked.

[0006] A photodetector according to an embodiment of the present disclosure includes: a first semiconductor layer having opposing first and second surfaces and having sensor pixels that perform photoelectric conversion formed thereon; and a second semiconductor layer stacked on the first surface side of the first semiconductor layer, having a third surface opposing the first surface and a fourth surface opposite to the third surface, and having a plurality of pixel transistors that configure a readout circuit outputting pixel signals based on charges output from the sensor pixels formed thereon, wherein one or more contact wirings are connected to each of the plurality of pixel transistors from one or both of the third surface side and the fourth surface side.

[0007] An electronic device according to an embodiment of the present disclosure includes the photodetector according to the above-described embodiment as a photodetector.

[0008] In a photodetector and an electronic device according to one embodiment of the present disclosure, in a second semiconductor layer stacked on a first semiconductor layer on which sensor pixels for photoelectric conversion are formed, one or more contact wires are connected to a plurality of pixel transistors constituting a readout circuit formed on the second semiconductor layer from one or both of the front (fourth surface) and back (third surface) of the second semiconductor layer. This eliminates the need for through-wiring that penetrates the second semiconductor layer.

[0009] Figure 1 is a diagram showing an example of the schematic configuration of a photodetector according to an embodiment of the present disclosure. Figure 2 is a diagram showing an example of the sensor pixel and readout circuit shown in Figure 1. Figure 3 is a schematic diagram of an example of the cross-sectional configuration of the photodetector shown in Figure 1. Figure 4 is a diagram showing another example of the sensor pixel and readout circuit shown in Figure 1. Figure 5 is a schematic plan view showing an example of the layout of a plurality of pixel transistors constituting the readout circuit shown in Figure 4. Figure 6 is a schematic diagram of the cross-sectional configuration of a second substrate corresponding to the I-I' line shown in Figure 5. Figure 7 is a perspective view showing an example of the configuration of the pixel transistors shown in Figure 6, etc. A schematic cross-sectional diagram illustrating an example of a method for manufacturing the photodetector shown in Figure 1. Figure 8B is a schematic cross-sectional diagram showing the process following Figure 8A. Figure 8C is a schematic cross-sectional diagram showing the process following Figure 8B. Figure 8D is a schematic cross-sectional diagram showing the process following Figure 8C. Figure 9A is a schematic cross-sectional diagram showing the process following Figure 8D. Figure 9B is a schematic cross-sectional diagram showing the process following Figure 9A. Figure 10A is a schematic cross-sectional diagram showing the process following Figure 9B. Figure 10B is a schematic cross-sectional diagram showing the process following Figure 10A. Figure 10C is a schematic cross-sectional diagram showing the process following Figure 10B. Figure 10D is a schematic cross-sectional diagram showing the process following Figure 10C. Figure 11A is a schematic cross-sectional diagram showing the process following Figure 10D. Figure 11B is a schematic cross-sectional diagram showing the process following Figure 11A. Figure 11C is a schematic cross-sectional diagram showing the process following Figure 11B. Figure 12 is a schematic cross-sectional diagram showing the process following Figure 11C. Figure 13 schematically shows an example of the cross-sectional configuration of a photodetector according to a second embodiment of the present disclosure. Figure 14 is a schematic diagram showing the planar configuration of the pixel transistor shown in Figure 13. Figure 15A is a schematic cross-sectional diagram of a pixel transistor corresponding to the II-II' line shown in Figure 14. Figure 15B is a schematic cross-sectional diagram of a pixel transistor corresponding to the III-III' line shown in Figure 14. Figure 15C is a schematic cross-sectional diagram of a pixel transistor corresponding to the IV-IV' line shown in Figure 14. Figure 14 is a schematic cross-sectional diagram illustrating an example of a manufacturing method for the pixel transistor and contact wiring shown in Figure 14. Figure 16B is a schematic cross-sectional diagram showing the process following Figure 16A. Figure 16C is a schematic cross-sectional diagram showing the process following Figure 16B. Figure 16D is a schematic cross-sectional diagram showing the process following Figure 16C.Figure 16E is a schematic cross-sectional diagram showing the process following Figure 16D. Figure 16F is a schematic cross-sectional diagram showing the process following Figure 16E. Figure 16G is a schematic cross-sectional diagram showing the process following Figure 16F. Figure 16H is a schematic cross-sectional diagram showing the process following Figure 16G. Figure 16I is a schematic cross-sectional diagram showing the process following Figure 16H. Figure 16J is a schematic cross-sectional diagram showing the process following Figure 16I. Figure 16K is a schematic cross-sectional diagram showing the process following Figure 16J. Figure 16L is a schematic cross-sectional diagram showing the process following Figure 16K. Figure 17 schematically shows an example of the cross-sectional configuration of a photodetector according to the third embodiment of this disclosure. Figure 18 schematically shows another example of the cross-sectional configuration of a photodetector according to the third embodiment of this disclosure. This is a schematic cross-sectional diagram illustrating an example of a method for manufacturing the pixel transistor and contact wiring shown in Figure 17. Figure 19B is a schematic cross-sectional diagram showing the process following Figure 19A. Figure 19C is a schematic cross-sectional diagram showing the process following Figure 19B. Figure 19D is a schematic cross-sectional diagram showing the process following Figure 19C. Figure 19E is a schematic cross-sectional diagram showing the process following Figure 19D. Figure 19F is a schematic cross-sectional diagram showing the process following Figure 19E. Figure 19G is a schematic cross-sectional diagram showing the process following Figure 19F. Figure 19H is a schematic cross-sectional diagram showing the process following Figure 19G. Figure 19I is a schematic cross-sectional diagram showing the process following Figure 19H. Figure 19J is a schematic cross-sectional diagram showing the process following Figure 19I. Figure 19K is a schematic cross-sectional diagram showing the process following Figure 19J. Figure 19L is a schematic cross-sectional diagram showing the process following Figure 19K. Figure 19M is a schematic cross-sectional diagram showing the process following Figure 19L. Figure 19N is a schematic cross-sectional diagram showing the process following Figure 19M. Figure 20 schematically shows an example of a cross-sectional configuration of a photodetector, which is a modified example of the third embodiment of the present disclosure. Figure 21 schematically shows an example of a cross-sectional configuration of a photodetector according to a fourth embodiment of the present disclosure. Figure 22 is a schematic diagram showing the planar configuration of the pixel transistor shown in Figure 21. Figure 23A is a schematic cross-sectional diagram of a pixel transistor corresponding to the V-V' line shown in Figure 22. Figure 23B is a schematic cross-sectional diagram of a pixel transistor corresponding to the VI-VI' line shown in Figure 22. Figure 23C is a schematic cross-sectional diagram of a pixel transistor corresponding to the VII-VII' line shown in Figure 22.Figure 21 is a schematic plan and cross-sectional diagram illustrating an example of a method for manufacturing a pixel transistor shown in Figure 21. Figure 24B is a schematic plan and cross-sectional diagram showing the process following Figure 24A. Figure 24C is a schematic plan and cross-sectional diagram showing the process following Figure 24B. Figure 24D is a schematic plan and cross-sectional diagram showing the process following Figure 24C. Figure 24E is a schematic plan and cross-sectional diagram showing the process following Figure 24D. Figure 24F is a schematic plan and cross-sectional diagram showing the process following Figure 24E. Figure 24G is a schematic plan and cross-sectional diagram showing the process following Figure 24F. Figure 24H is a schematic plan and cross-sectional diagram showing the process following Figure 24G. Figure 25 is a block diagram showing an example of the configuration of an electronic device having a photodetector shown in Figure 1. Figure 26A is a schematic diagram showing an example of the overall configuration of a photodetector system using the photodetector shown in Figure 1, etc. Figure 26B is a diagram showing an example of the circuit configuration of the photodetector system shown in Figure 26A. Figure 27 is a diagram showing an example of a schematic configuration of an endoscopic surgical system. Figure 28 is a block diagram showing an example of the functional configuration of a camera head and a CCU. Figure 29 is a block diagram showing an example of a schematic configuration of a vehicle control system. Figure 30 is an explanatory diagram showing an example of the installation positions of an external information detection unit and an imaging unit. Figure 31 is a schematic representation of an example of the cross-sectional configuration of a light detection device according to the fifth embodiment of this disclosure. Figure 31 is a schematic plan and cross-sectional diagram illustrating an example of a method for manufacturing a pixel transistor. Figure 32B is a schematic plan and cross-sectional diagram showing the process following Figure 32A. Figure 32C is a schematic plan and cross-sectional diagram showing the process following Figure 32B. Figure 32D is a schematic plan and cross-sectional diagram showing the process following Figure 32C. Figure 32E is a schematic plan and cross-sectional diagram showing the process following Figure 32D. Figure 32F is a schematic plan and cross-sectional diagram showing the process following Figure 32E. Figure 32G is a schematic plan and cross-sectional diagram showing the process following Figure 32F. Figure 32H is a schematic plan and cross-sectional diagram showing the process following Figure 32G. Figure 32I is a schematic plan and cross-sectional view showing the process following Figure 32H. Figure 32J is a schematic plan and cross-sectional view showing the process following Figure 32I. Figure 32K is a schematic plan and cross-sectional view showing the process following Figure 32J. Figure 32L is a schematic plan and cross-sectional view showing the process following Figure 32K. Figure 32M is a schematic plan and cross-sectional view showing the process following Figure 32L.Figure 32N is a schematic plan and cross-sectional view showing the process following Figure 32M. Figure 32O is a schematic plan and cross-sectional view showing the process following Figure 32N.

[0010] The embodiments of this disclosure will be described in detail below with reference to the drawings. The following description is one specific example of this disclosure, and this disclosure is not limited to the following embodiments. Furthermore, this disclosure is not limited to the arrangement, dimensions, dimensional ratios, etc. of each component shown in each figure. The order of description is as follows: 1. First Embodiment (Example of a photodetector in which one or more contact wirings are connected to a pixel transistor provided on a second substrate from one or both of the front and back surfaces) 2. Second Embodiment (Example of a photodetector in which the contact wiring connected from the back side of the pixel transistor is formed in a self-aligned manner) 3. Third Embodiment (Example of a photodetector in which the gate electrode of the pixel transistor and the contact wiring connected from the back side are formed from the same material) 4. Modification (Another example of the structure of a pixel transistor) 5. Fourth Embodiment (Example of a photodetector in which the pixel transistor provided on the second substrate has a gate-all-around (GAA) structure) 6. Fifth Embodiment (Example of a photodetector in which the fin height differs between the channel region and the source / drain region of a pixel transistor) 7. Application Examples 8. Application Examples

[0011] <1. First Embodiment> Figure 1 shows an example of the schematic configuration of a light detection device 1 according to the first embodiment of this disclosure. The light detection device 1 is used, for example, as a CMOS (Complementary Metal Oxide Semiconductor) image sensor used in electronic devices such as digital still cameras and video cameras.

[0012] The photodetector 1 of this embodiment, as shown in Figure 3 for example, has multiple semiconductor substrates (semiconductor substrate 11 and semiconductor substrate 21) stacked on top of each other. The semiconductor substrate 11 has opposing front surface 11S1 and back surface 11S2, and has sensor pixels 12 that perform photoelectric conversion formed on it. The semiconductor substrate 21 has a front surface 21S1 and a back surface 21S2, and has multiple pixel transistors 210 that constitute a readout circuit 22 that outputs a pixel signal based on the charge output from the sensor pixels 12. The semiconductor substrates 11 and 21 are stacked so that their respective front surfaces 11S1 and back surfaces 21S2 face each other. In the photodetector 1, one or more contact lines (contact lines 53, 57) are connected to the multiple pixel transistors 210 from either the front surface 21S1 side or the back surface 21S2 side or both.

[0013] Here, the semiconductor substrate 11 corresponds to a specific example of the "first semiconductor layer" as one embodiment of the present disclosure. The semiconductor substrate 21 corresponds to a specific example of the "second semiconductor layer" as one embodiment of the present disclosure. The sensor pixel 12 corresponds to a specific example of the "sensor pixel" as one embodiment of the present disclosure. The readout circuit 22 corresponds to a specific example of the "readout circuit" as one embodiment of the present disclosure, and the plurality of pixel transistors 210 correspond to a specific example of the "plural of pixel transistors" as one embodiment of the present disclosure. The contact wiring 53, 57 corresponds to a specific example of the "one or more contact wiring" as one embodiment of the present disclosure. The surface 11S1 corresponds to a specific example of the "first surface" as one embodiment of the present disclosure, and the back surface 11S2 corresponds to a specific example of the "second surface" as one embodiment of the present disclosure. The surface 21S1 corresponds to a specific example of the "fourth surface" as one embodiment of the present disclosure, and the back surface 21S2 corresponds to a specific example of the "third surface" as one embodiment of the present disclosure.

[0014] [Outline Configuration of the Photodetector] The photodetector 1 is a three-dimensional imaging device comprising a first substrate 10, a second substrate 20, and a third substrate 30, as shown in Figure 1, for example, and is constructed by bonding these three substrates together. The first substrate 10, the second substrate 20, and the third substrate 30 are stacked in this order.

[0015] The first substrate 10 includes a semiconductor substrate 11 having a plurality of sensor pixels 12 that perform photoelectric conversion. The plurality of sensor pixels 12 are arranged in a matrix within the pixel region 13 of the first substrate 10.

[0016] The second substrate 20 includes a semiconductor substrate 21 having a readout circuit 22 that outputs a pixel signal based on the charge from the sensor pixels 12. The readout circuit 22 is provided, for example, one for every four sensor pixels 12, and is a readout circuit that sequentially reads the charge converted photoelectrically from the four sensor pixels 12. The second substrate 20 also includes a plurality of pixel drive lines 23 extending in the row direction and a plurality of vertical signal lines 24 extending in the column direction.

[0017] The third substrate 30 includes a semiconductor substrate 31 having a logic circuit 32 for processing pixel signals. The logic circuit 32 also includes, for example, a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36. The logic circuit 32 can output an output voltage Vout for each sensor pixel 12 to the outside via the horizontal drive circuit 35.

[0018] The vertical drive circuit 33, for example, sequentially selects a plurality of sensor pixels 12 row by row. The column signal processing circuit 34, for example, applies correlated double sampling (CDS) to the pixel signals output from each sensor pixel 12 in the row selected by the vertical drive circuit 33. For example, by applying CDS processing, the column signal processing circuit 34 can extract the signal level of the pixel signals and retain pixel data corresponding to the amount of light received by each sensor pixel 12. The horizontal drive circuit 35, for example, sequentially outputs the pixel data held by the column signal processing circuit 34 to the outside. The system control circuit 36, for example, controls the driving of each component in the logic circuit 32. As a result, the logic circuit 32 can output pixel data to the outside based on the amount of light received by each sensor pixel 12.

[0019] [Readout Circuit Configuration] Figure 2 shows an example of a sensor pixel 12 and a readout circuit 22. Below, we will describe the case where four sensor pixels 12 share one readout circuit 22, as shown in Figure 2. Here, "sharing" means that the outputs of the four sensor pixels 12 are input to a common readout circuit 22.

[0020] Each sensor pixel 12 has components that are common to all of them. In the following, when the components of each sensor pixel 12 are distinguishable from each other, an identification number (1, 2, 3, 4) is added to the end of the component's code. On the other hand, when the components of each sensor pixel 12 are not distinguishable from each other, the addition of an identification number to the end of the component's code is omitted.

[0021] The sensor pixel 12 includes, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD that temporarily holds the charge output from the photodiode PD via the transfer transistor TR. The photodiode PD corresponds to one specific example of a "photoelectric conversion element" as one embodiment of the present disclosure. The transfer transistor TR corresponds to one specific example of a "transfer transistor" as one embodiment of the present disclosure. The floating diffusion FD corresponds to one specific example of a "charge holding unit" as one embodiment of the present disclosure. The photodiode PD is a photoelectric conversion element that generates a charge corresponding to the amount of light received by performing photoelectric conversion. The transfer transistor TR is, for example, a MOS (Metal Oxide Semiconductor) transistor.

[0022] The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to the reference potential line. The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to the pixel drive line 23.

[0023] Each floating diffusion FD of the sensor pixels 12 that share the readout circuit 22 is electrically connected to each other and is also electrically connected to the input terminal of the common readout circuit 22. The readout circuit 22 includes, for example, a reset transistor RST, a selection transistor SEL, and an amplification transistor AMP. Furthermore, the readout circuit 22 may optionally have a selection transistor SEL.

[0024] The source of the reset transistor RST (i.e., the input terminal of the readout circuit 22) is electrically connected to the floating diffusion FD, the drain of the reset transistor RST is electrically connected to the power line VDD and the drain of the amplification transistor AMP, and the gate of the reset transistor RST is electrically connected to the pixel drive line 23. The source of the amplification transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. The source of the selection transistor SEL (i.e., the output terminal of the readout circuit 22) is electrically connected to the vertical signal line 24, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 23.

[0025] When the transfer transistor TR is turned ON, it transfers the charge converted photoelectrically by the photodiode PD to the floating diffusion FD. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned ON, it resets the potential of the floating diffusion FD to the potential of the power line VDD. The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 22.

[0026] The amplification transistor AMP generates a pixel signal with a voltage corresponding to the level of charge held in the floating diffusion FD. The amplification transistor AMP constitutes a so-called source follower type amplifier and outputs a pixel signal with a voltage corresponding to the level of charge generated by the photodiode PD. When the selection transistor SEL is turned ON, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the amplified potential to the column signal processing circuit 34 via the vertical signal line 24. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, MOS transistors.

[0027] The selection transistor SEL may be provided between the power line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 23. The source of the amplification transistor AMP (i.e., the output terminal of the readout circuit 22) is electrically connected to the vertical signal line 24, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST.

[0028] Furthermore, an FD conversion gain switching transistor FDG may be provided between the source of the reset transistor RST and the gate of the amplification transistor AMP.

[0029] Since the charge Q is expressed as the product of capacitance C and voltage V, if the capacitance C of the floating diffusion FD is large, the voltage V after conversion by the amplification transistor AMP will be low. On the other hand, if the charge Q of the pixel signal is large, if the capacitance C of the floating diffusion FD is not large enough, the floating diffusion FD will not be able to hold the charge Q from the photodiode PD. It is also important that the capacitance C of the floating diffusion FD is appropriately large so that the voltage V converted by the amplification transistor AMP does not become excessively high. Therefore, the FD conversion gain switching transistor FDG is provided to switch the charge-voltage conversion efficiency in the readout circuit 22.

[0030] When the FD conversion gain switching transistor FDG is in the ON state, the capacitance C of the floating diffusion FD can be increased by the gate capacitance of the FD conversion gain switching transistor FDG compared to the OFF state. Therefore, by switching the ON or OFF state of the FD conversion gain switching transistor FDG to vary the capacitance C of the floating diffusion FD, the charge-voltage conversion efficiency in the readout circuit 22 can be switched.

[0031] Furthermore, the configuration of the readout circuit 22 is not limited to this. For example, as shown in Figure 4 later, the readout circuit 22A may be further provided with a capacitor FC having a MIM (Metal-Insulator-Metal) structure, a capacitive connection transistor FCG connecting the floating diffusion FD and the capacitor FC, a subFD capacitor SFD, etc.

[0032] [Cross-sectional configuration of the light detection device] Figure 3 shows an example of the vertical cross-sectional configuration of the light detection device 1. The light detection device 1 is constructed by stacking a first substrate 10, a second substrate 20, and a third substrate 30 in this order. Furthermore, the light incident side (also called the back side) of the first substrate 10 is equipped with a color filter 92, a light receiving lens 94, etc. In other words, the light detection device 1 is a back-illuminated imaging device.

[0033] The first substrate 10 is constructed by stacking wiring layers 44 on a semiconductor substrate 11. The semiconductor substrate 11 is made of, for example, a silicon substrate. The semiconductor substrate 11 has, for example, a p-well layer 412 made of p-type semiconductor regions in a part of the surface 11S1 and its vicinity, and an n-type semiconductor region 411 with a different conductivity type than the p-well layer 412 in the remaining region (a region deeper than the p-well layer 412). The photodiode PD is, for example, constructed as a pn-junction type photodiode 41 by this n-type semiconductor region 411 and the p-well layer 412. Inside the p-well layer 412, the semiconductor substrate 11 has an n-type semiconductor region 413 as a floating diffusion FD and a p-type semiconductor region 414 with a higher concentration of p-type impurities than the p-well layer 412. The p-type semiconductor region 414 is a well contact region WC and is connected to, for example, ground potential or a fixed potential (see Figure 6). This supplies a reference potential to the semiconductor substrate 11.

[0034] The first substrate 10 has a photodiode PD, a transfer transistor TR, a floating diffusion FD, and a well contact region WC for each sensor pixel 12. The first substrate 10 has the transfer transistor TR, floating diffusion FD, and well contact region WC on the side opposite to the light incident surface of the semiconductor substrate 11 (i.e., the surface 11S1 side).

[0035] The first substrate 10 further has a pixel isolation section 42 that separates each of the sensor pixels 12. The pixel isolation section 42 is formed by extending in the direction normal to the main surface of the semiconductor substrate 11 (a direction perpendicular to the surface 11S1 of the semiconductor substrate 11), and electrically isolates each of the adjacent sensor pixels 12. The pixel isolation section 42 has, for example, an FTI (Full Trench Isolation) structure and penetrates the semiconductor layer 100S. The pixel isolation section 42 is composed of, for example, a light-shielding film 42A that penetrates the semiconductor substrate 11 and an insulating film 42B provided between the semiconductor substrate 11 and the light-shielding film 42A. For example, tungsten (W) can be used for the light-shielding film 43A. For example, silicon oxide (SiO) can be used for the insulating film 43B. Although not shown, the pixel isolation section 42 is not limited to an FTI structure that penetrates the semiconductor layer 100S. The pixel separation section 42 may, for example, be a DTI (Deep Trench Isolation) structure that does not penetrate the semiconductor layer 100S.

[0036] The first substrate 10 further has a pinning region 415 in contact with the side surface of the pixel separation portion 42. The pinning region 415 is composed of a p-type semiconductor region, similar to the p-well layer 412. The first substrate 10 further has a fixed charge film 43 in contact with the back surface 11S2 of the semiconductor substrate 11. The fixed charge film 43 is composed of an insulating film having a negative fixed charge in order to suppress the generation of dark current caused by the interface level on the light incident surface side of the semiconductor substrate 11. Examples of materials for the fixed charge film 43 include hafnium oxide (HfO), zircon oxide (ZrO), aluminum oxide (AlO), titanium oxide (TiO), or tantalum oxide (TaO). By inducing an electric field, the fixed charge film 43 can form a hole accumulation layer at the interface on the light incident surface side of the semiconductor substrate 11, suppressing the generation of electrons from the interface.

[0037] The wiring layer 44 corresponds to a specific example of the "first wiring layer" as an embodiment of the present disclosure. The wiring layer 44 has, for example, an interlayer insulating layer 45, a plurality of pad portions 46, a gate electrode 47, and a plurality of wirings (for example, wiring layers M11, M12) provided inside the interlayer insulating layer 45. The wiring layer 44 further has a plurality of pad electrodes 48 inside the interlayer insulating layer 45. Each of the pad electrodes 48 is formed of a metal such as copper (Cu). Each of the pad electrodes 48 is exposed on the surface of the wiring layer 44 and is used for bonding the first substrate 10 and the second substrate 20, and for electrical connection between the first substrate 10 and the second substrate 20.

[0038] On the light incident side (also called the back side) of the first substrate 10, for example, a protective layer 91, a color filter 92, a partition wall 93, and a light-receiving lens 94 are provided. The protective layer 91 protects the back surface 11S2 of the semiconductor substrate 11, and for example, silicon oxide (SiO) or silicon nitride (SiN) is used. The color filter 92 includes, for example, a red filter 92R that transmits red light, a green filter 92G that transmits green light, and a blue filter 92B that transmits blue light, and the red filter 23R, green filter 23G, and color filter 23B are arranged according to a Bayer array. The partition wall 93 is provided at the boundary of each adjacent sensor pixel 12. The color filter 92 (red filter 23R, green filter 23G, and color filter 23B) and the light-receiving lens 94 are each provided, for example, one for every four sensor pixels 12 arranged in a 2x2 pixel unit.

[0039] The second substrate 20 is constructed by laminating a wiring layer 55 on the front surface 21S1 side of the semiconductor substrate 21 and a wiring layer 51 on the back surface 21S2 side of the semiconductor substrate 21. The semiconductor substrate 21 is made of, for example, a silicon substrate and has, for example, one readout circuit 22 for every four sensor pixels 12. The second substrate 20 is bonded to the first substrate 10 with the back surface 21S2 of the semiconductor substrate 21 facing the front surface 11S1 side of the semiconductor substrate 11. In other words, the second substrate 20 is bonded to the first substrate 10 face to back.

[0040] As will be described in detail later, each of the multiple pixel transistors 210 constituting the readout circuit 22 has a three-dimensional structure. For example, each of the multiple pixel transistors 210 has a Fin-FET structure, and the semiconductor substrate 21 is divided into fin-shaped sections extending in the Y-axis direction for each pixel transistor 210, as shown in Figure 5, for example. An element isolation layer 28 is embedded between the fin-shaped sections of the semiconductor substrate 21, electrically isolating them from one another.

[0041] The wiring layer 51 corresponds to a specific example of the "second wiring layer" as an embodiment of the present disclosure. The wiring layer 51 includes, for example, an interlayer insulating layer 52, one or more contact wirings 53, and a plurality of wirings (for example, wiring layers M21, M22) provided inside the interlayer insulating layer 52. The one or more contact wirings 53 correspond to a specific example of the "first contact wiring" as an embodiment of the present disclosure and extend in the direction normal to the main surface of the semiconductor substrate 21 (a direction perpendicular to the back surface 21S2 of the semiconductor substrate 21). The one or more contact wirings 53 are connected from the back surface 21S2 side of the semiconductor substrate 21 to one of the gate electrodes 26, source region 21S, and drain region 21D of each of the plurality of pixel transistors 210.

[0042] The wiring layer 51 further has a plurality of pad electrodes 54 inside the interlayer insulating layer 52. Each of the pad electrodes 54 is made of a metal such as copper (Cu). Each of the pad electrodes 54 is exposed on the surface of the wiring layer 51 and is used for bonding the first substrate 10 and the second substrate 20, and for electrical connection between the first substrate 10 and the second substrate 20. In other words, the first substrate 10 and the second substrate 20 are electrically connected to each other by the bonding of the pad electrodes 48 and 54.

[0043] The wiring layer 55 corresponds to a specific example of the "third wiring layer" as an embodiment of the present disclosure. The wiring layer 55 includes, for example, an interlayer insulating layer 56, one or more contact wirings 57, and a plurality of wirings (e.g., wiring layers M23, M24) provided inside the interlayer insulating layer 56. The one or more contact wirings 57 correspond to a specific example of the "second contact wiring" as an embodiment of the present disclosure and extend in the direction normal to the main surface of the semiconductor substrate 21 (a direction perpendicular to the surface 21S1 of the semiconductor substrate 21). The one or more contact wirings 57 are connected from the surface 21S1 side of the semiconductor substrate 21 to one of the gate electrodes 26, source region 21S, and drain region 21D of each of the plurality of pixel transistors 210. Pixel drive lines 23 and vertical signal lines 24 are provided, for example, on the plurality of wirings (e.g., wiring layers M23, M24).

[0044] The wiring layer 55 further includes a plurality of pad electrodes 58 inside the interlayer insulating layer 56. Each pad electrode 58 is formed of, for example, a metal such as copper (Cu). Each pad electrode 58 is exposed on the surface of the wiring layer 55, and is used for bonding the second substrate 20 and the third substrate 30, and for electrical connection between the second substrate 20 and the third substrate 30. For example, one of the plurality of pad electrodes 58 is provided for each of the pixel drive lines 23 and the vertical signal lines 24.

[0045] The third substrate 30 is configured, for example, by laminating a wiring layer 61 on a semiconductor substrate 31. The semiconductor substrate 31 is formed of, for example, a silicon substrate, and includes a logic circuit 32. The third substrate 30 is bonded to the second substrate 20 such that the surface 31S1 of the semiconductor substrate 31 faces the surface 21S1 side of the semiconductor substrate 21. In other words, the third substrate 30 is bonded face-to-face with the second substrate 20.

[0046] The wiring layer 61 corresponds to a specific example of "the fourth wiring layer" according to one embodiment of the present disclosure. The wiring layer 61 includes, for example, an interlayer insulating layer 62, a plurality of wirings provided inside the interlayer insulating layer 62 (e.g., wiring layers M31, M32, M33, M34), and a plurality of pad electrodes 63 electrically connected to the logic circuit 32 via the plurality of wirings. Each pad electrode 63 is formed of, for example, a metal such as copper (Cu). The pad electrode 63 is exposed on the surface of the wiring layer 61, and is used for bonding the second substrate 20 and the third substrate 30, and for electrical connection between the second substrate 20 and the third substrate 30. The second substrate 20 and the third substrate 30 are electrically connected to each other by bonding the pad electrodes 58 and 63 to each other.

[0047] [Configuration and Connection Mode of Pixel Transistors] Figure 4 illustrates another example of a sensor pixel 12 and a readout circuit (readout circuit 22A). Figure 5 schematically shows an example of the layout of a plurality of pixel transistors 210 constituting the readout circuit 22A shown in Figure 4. Figure 6 schematically shows a cross-sectional configuration of the second substrate 20 corresponding to the line I-I' shown in Figure 5. Note that in Figure 6, some of the components shown in Figure 3 are omitted to simplify the drawing.

[0048] The readout circuit 22A is provided, for example, one for each sensor pixel 12. Each of the plurality of pixel transistors 210 constituting the readout circuit 22A has a three-dimensional structure as described above. One or more contact wirings (contact wirings 53, 57) are connected to each of the plurality of pixel transistors 210 constituting the readout circuit 22A from one or both of the front surface 21S1 side and the back surface 21S2 side of the semiconductor substrate 21.

[0049] Each of the plurality of pixel transistors 210 has a Fin-FET structure as shown in FIG. 7, and is composed of a fin 21X formed of the semiconductor substrate 21, a gate insulating film 25, and a gate electrode 26.

[0050] The fin 21X has, for example, a flat plate shape that stands upright in the Z-axis direction and extends in the Y-axis direction. The top surface (front surface 21S1) and side surfaces of the fin 21X are covered with the gate insulating film 25. The gate electrode 26 is provided so as to straddle the fin 21X in the X-axis direction intersecting the extending direction (Y-axis direction) of the fin 21X, and extends to the top surface (front surface 21S1) and side surfaces of the fin 21X. In the fin 21X, a channel region 21C is formed at a position facing the gate electrode 26, and a source region 21S and a drain region 21D are formed at both ends sandwiching the channel region 21C.

[0051] The gate insulating film 25 can be formed from a high dielectric constant material (High-K material) such as silicon oxide (SiO), hafnium oxide (HfO), hafnium silicate (HfSiO), nitrogen-doped hafnium silicate (HfSiON), zirconium oxide (ZrO), zirconium silicate (ZrSiON), tantalum oxide (TaO), and tantalum oxynitride (TaON). ​​The gate electrode 26 can be formed from, for example, titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), aluminum (Al), and polysilicon (Poly-Si).

[0052] A channel protection film 27 is provided on the lower surface (back surface 21S2) of the fin 21X, which electrically isolates the channel region 21C from the contact wiring 53. The channel protection film 27 corresponds to a specific example of an "insulating film" as an embodiment of the present disclosure. The channel protection film 27 is formed, for example, from a single layer of silicon nitride (SiN), silicon oxide (SiO), or undoped polysilicon (Poly-Si), or from a laminated film consisting of two or more of these.

[0053] The pixel transistor 210 and the contact wirings 53 and 57 are connected as follows. For example, the contact wiring 53 connected from the back surface 21S2 side of the semiconductor substrate 21 to the gate electrode 26 of the pixel transistor 210 has a diameter larger than the width of the fin 21X, as shown in Figure 6, for example, and is connected to the gate electrode 26 so as to straddle the channel protection film 27 provided on the lower surface (back surface 21S2) of the fin 21X. For example, the contact wiring 53 connected from the back surface 21S2 side of the semiconductor substrate 21 to the source region 21S or drain region 21D of the pixel transistor 210 has a diameter larger than the width of the fin 21X, and the portion that protrudes outside the fin 21X is extended to the side surface of the fin 21X, thereby connecting to the source region 21S or drain region 21D from the side surface of the fin 21X. For example, the contact wiring 57 connecting the gate electrode 26 of the pixel transistor 210, the source region 21S, or the drain region 21D of the semiconductor substrate 21 from the surface 21S1 side is connected from the upper surface (surface 21S1) side of the fin 21X with a diameter less than or equal to the width of the fin 21X, as shown in Figure 6. Alternatively, the contact wiring 57 connecting the source region 21S or the drain region 21D from the surface 21S1 side of the semiconductor substrate 21 may have a diameter greater than the width of the fin 21X, similar to the contact wiring 53 connecting the source region 21S or the drain region 21D from the back surface 21S2 side of the semiconductor substrate 21. The portion extending beyond the fin 21X may be extended to the side of the fin 21X, thereby connecting to the source region 21S or the drain region 21D from both the upper and side surfaces of the fin 21X.

[0054] [Manufacturing Method for Light Detection Device] Figures 8A to 8D, 9A, 9B, 10A to 10D, 11A to 11C, and 12 show an example of a manufacturing method for the light detection device 1.

[0055] First, as shown in Figure 8A, a support substrate 71 is prepared in which the base layer 72 and the sacrificial layer 73 are laminated in that order. Next, as shown in Figure 8B, a semiconductor substrate 21, which has a channel protective film 27 and an interlayer insulating layer 52 laminated on the back surface 21S2 side, is bonded to the sacrificial layer 73 with the interlayer insulating layers 52 facing each other. Then, the semiconductor substrate 21 is thinned to a predetermined thickness by chemical mechanical polishing (CMP).

[0056] Next, as shown in Figure 8C, the semiconductor substrate 21 and channel protective film 27 are processed into a fin shape by photolithography and etching (for example, dry etching), and then the gate electrodes 26 are formed in a predetermined pattern. Then, as shown in Figure 8C, an element isolation layer 28 and an interlayer insulating layer 56 are formed to fill the gaps between adjacent fin-shaped semiconductor substrates 21 and gate electrodes 26, and then contact wiring 57 are formed to connect to a plurality of pixel transistors 210 from the surface 21S1 side.

[0057] Next, as shown in Figure 8D, after sequentially depositing wiring layers M23 and M24 using the BEOL process, a plurality of pad electrodes 58 are formed and exposed on the surface of the interlayer insulating layer 56. This forms the wiring layer 55 on the surface 21S1 side of the semiconductor substrate 21.

[0058] Next, as shown in Figure 9A, a logic circuit 32 is prepared, which includes an interlayer insulating layer 62 containing the logic circuit 32 and wiring layers M31, M32, M33, and M34 within the layer. Subsequently, as shown in Figure 9B, a plurality of pad electrodes 63 are formed and exposed on the surface of the interlayer insulating layer 62. This forms a wiring layer 61 on the semiconductor substrate 31.

[0059] Next, as shown in Figure 10A, the wiring layer 55 and the wiring layer 61 are placed facing each other, and the multiple pad electrodes 58 and 63 exposed on the respective surfaces of the wiring layer 55 and the wiring layer 61 are bonded together. This electrically connects the second substrate 20 and the third substrate 30.

[0060] Next, as shown in Figure 10B, the support substrate 71 is removed and the interlayer insulating layer 52 is thinned to a predetermined thickness using CMP. Then, as shown in Figure 10C, contact wiring 53 is formed to connect to the multiple pixel transistors 210 from the back surface 21S2 side.

[0061] Next, as shown in Figure 10D, after sequentially depositing wiring layers M21 and M22 using the BEOL process, a plurality of pad electrodes 54 are formed and exposed on the surface of the interlayer insulating layer 52. As a result, the wiring layer 51 is formed on the back surface 21S2 side of the semiconductor substrate 21.

[0062] Next, as shown in Figure 11A, a semiconductor substrate 11 is prepared, and as shown in Figure 11B, a pixel separation portion 42 is formed from the surface 11S1 side of the semiconductor substrate 11, and a transfer transistor TR, a floating diffusion FD, and a well contact region WC are formed for each sensor pixel 12. Subsequently, as shown in Figure 11B, wiring layers M11, M12, etc. are formed inside the interlayer insulating layer 45 by the BEOL process. Next, as shown in Figure 11C, a plurality of pad electrodes 48 are formed and exposed on the surface of the interlayer insulating layer 45. As a result, a wiring layer 44 is formed on the semiconductor substrate 11.

[0063] Next, as shown in Figure 12, the wiring layer 44 and the wiring layer 51 are placed facing each other, and the multiple pad electrodes 48 and 54 exposed on the respective surfaces of the wiring layer 44 and the wiring layer 51 are bonded together. This electrically connects the first substrate 10 and the second substrate 20. After that, the semiconductor substrate 11 is thinned to a predetermined thickness by CMP, and then a photodiode PD and the like are formed for each sensor pixel 12. Finally, a protective layer 91, a partition wall 93, a color filter 92, and a light-receiving lens 94 are sequentially formed on the back surface 11S2 side of the semiconductor substrate 11. With these steps, the light detection device 1 shown in Figure 3 is completed.

[0064] [Function and Effects] In the photodetector 1 of this embodiment, a semiconductor substrate 11 on which a sensor pixel 12 that performs photoelectric conversion is formed and a semiconductor substrate 21 on which a plurality of pixel transistors 210 that constitute a readout circuit 22 that outputs a pixel signal based on the charge output from the sensor pixel 12 are formed are stacked. One or more contact lines (contact lines 53, 57) are connected to the plurality of pixel transistors 210 from one or both of the front surface 21S1 side and the back surface 21S2 side of the semiconductor substrate 21. This will be explained below.

[0065] Traditionally, miniaturization of the area per pixel in two-dimensional imaging devices has been achieved through the introduction of microprocessing and improvements in mounting density. In recent years, three-dimensional imaging devices have been developed to achieve further miniaturization and miniaturization of the area per pixel.

[0066] In a three-dimensional imaging device, as described above, for example, a first substrate having a first semiconductor substrate and sensor pixels that perform photoelectric conversion, and a second substrate having a second semiconductor substrate and a readout circuit that outputs a pixel signal based on the charge output from the sensor pixels are stacked on top of each other, and the first and second substrates are electrically connected to each other via through-wiring that penetrates the second semiconductor substrate. This makes it possible to increase the integration density of sensor pixels or increase the size of the readout circuit while maintaining the same chip size as before.

[0067] However, in imaging devices with a three-dimensional structure as described above, the layout of the multiple pixel transistors constituting the readout circuit is restricted by through-wiring that electrically connects the first substrate and the second substrate, and it is difficult to effectively utilize the area of ​​the second semiconductor substrate.

[0068] In contrast, in this embodiment, as described above, one or more contact lines (contact lines 53, 57) are connected to the multiple pixel transistors 210 formed on the semiconductor substrate 21 from either the front surface 21S1 side and the back surface 21S2 side or both of the semiconductor substrate 21. As a result, the through-wiring described above is unnecessary, and the semiconductor substrate 21 on which the readout circuit 22 is provided can be effectively utilized.

[0069] As described above, the optical detection device 1 of this embodiment makes it possible to improve the area efficiency of the semiconductor substrate 21 on which the readout circuit 22 is provided.

[0070] Furthermore, in the light detection device 1 of this embodiment, the through-wiring described above is unnecessary, so the number of transistors and the area of ​​the transistors provided on the second substrate 20 can be increased. This makes it possible to provide a more advanced light detection device.

[0071] Next, the second to fifth embodiments and modifications of the present disclosure, as well as examples of applications and uses, will be described. In the following modifications, components common to the first embodiment will be denoted by the same reference numerals.

[0072] <2. Second Embodiment> Figure 13 shows an example of a vertical cross-sectional configuration of the light detection device 2 according to the second embodiment of the present disclosure. The light detection device 2 is used, for example, as a CMOS image sensor used in electronic devices such as digital still cameras and video cameras.

[0073] [Outline Configuration of the Photodetector] The photodetector 2, like the photodetector 1 of the first embodiment described above, comprises a first substrate 10, a second substrate 20, and a third substrate 30, and is a three-dimensional imaging device constructed by bonding these three substrates together. The first substrate 10, the second substrate 20, and the third substrate 30 are stacked in this order.

[0074] The first substrate 10 includes a semiconductor substrate 11 having a plurality of sensor pixels 12 that perform photoelectric conversion. The plurality of sensor pixels 12 are arranged in a matrix within the pixel region 13 of the first substrate 10.

[0075] The second substrate 20 includes a semiconductor substrate 21 having a readout circuit (for example, a readout circuit 22A) that outputs a pixel signal based on the charge from the sensor pixels 12. For example, one readout circuit 22A is provided for each sensor pixel 12. The second substrate 20 also includes a plurality of pixel drive lines 23 extending in the row direction and a plurality of vertical signal lines 24 extending in the column direction.

[0076] The third substrate 30 includes a semiconductor substrate 31 having a logic circuit 32 for processing pixel signals. The logic circuit 32 also includes, for example, a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36. The logic circuit 32 can output an output voltage Vout for each sensor pixel 12 to the outside via the horizontal drive circuit 35.

[0077] [Cross-sectional configuration of the light detection device] As described above, the light detection device 2 has a first substrate 10, a second substrate 20, and a third substrate 30 stacked in this order. Furthermore, the light incident side (also called the back side) of the first substrate 10 is equipped with a color filter 92, a light receiving lens 94, etc. In other words, the light detection device 2 is a back-illuminated imaging device.

[0078] The first substrate 10 is constructed by laminating wiring layers 44 on a semiconductor substrate 11. The second substrate 20 is constructed by laminating wiring layers 55 on the front surface 21S1 side of the semiconductor substrate 21 facing the third substrate 30, and wiring layers 51 on the back surface 21S2 side of the semiconductor substrate 21 facing the first substrate 10. The third substrate 30 is constructed, for example, by laminating wiring layers 61 on a semiconductor substrate 31. In other words, the first substrate 10 and the second substrate 20 are bonded face to back. The second substrate 20 and the third substrate 30 are bonded face to face.

[0079] [Configuration and Connection of Pixel Transistors] Figure 14 schematically shows the planar configuration of the pixel transistor 210A shown in Figure 13. Figure 15A schematically shows the cross-sectional configuration of the pixel transistor 210A corresponding to the II-II' line shown in Figure 14. Figure 15B schematically shows the cross-sectional configuration of the pixel transistor 210A corresponding to the III-III' line shown in Figure 14. Figure 15C schematically shows the cross-sectional configuration of the pixel transistor 210A corresponding to the IV-IV' line shown in Figure 14.

[0080] Each of the multiple pixel transistors 210A constituting the readout circuit 22A has a three-dimensional structure. One or more contact lines (contact lines 53, 57) are connected to each of the multiple pixel transistors 210A constituting the readout circuit 22A from either the front surface 21S1 side or the back surface 21S2 side or both of the semiconductor substrate 21.

[0081] Each of the multiple pixel transistors 210A has a Fin-FET structure, similar to the pixel transistor 210 in the first embodiment described above, and is composed of a fin 21X made of a semiconductor substrate 21, a gate insulating film 25, and a gate electrode 26.

[0082] The fin 21X has a flat plate shape, for example, that is erected in the Z-axis direction and extends in the Y-axis direction. The upper surface (surface 21S1) and side surfaces of the fin 21X are covered with a gate insulating film 25. The gate electrode 26 is provided so as to straddle the fin 21X in the X-axis direction, which intersects with the extension direction (Y-axis direction) of the fin 21X, and extends to the upper surface (surface 21S1) and side surfaces of the fin 21X. A channel region 21C is formed on the fin 21X at a position opposite to the gate electrode 26, and a source region 21S and a drain region 21D are formed at both ends of this channel region 71C.

[0083] The gate insulating film 25 can be formed from a high dielectric constant material (High-K material) such as silicon oxide (SiO), hafnium oxide (HfO), hafnium silicate (HfSiO), nitrogen-doped hafnium silicate (HfSiON), zirconium oxide (ZrO), zirconium silicate (ZrSiON), tantalum oxide (TaO), and tantalum oxynitride (TaON). ​​The gate electrode 26 can be formed from, for example, titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), aluminum (Al), and polysilicon (Poly-Si).

[0084] A channel protection film 27 is provided on the lower surface (back surface 21S2) of the fin 21X to electrically isolate the channel region 21C from the contact wiring 53. The channel protection film 27 is formed of, for example, a single layer of silicon nitride (SiN), silicon oxide (SiO), or undoped polysilicon (Poly-Si), or a laminated film consisting of two or more of these.

[0085] The pixel transistor 210A and the contact wirings 53 and 57 are connected as follows. For example, the contact wiring 53 connected to the gate electrode 26 of the pixel transistor 210A from the back surface 21S2 side of the semiconductor substrate 21 has approximately the same width as the fin 21X, as shown in Figure 15A, and is formed below the fin 21X. The gate electrode 26 extends from the upper surface (front surface 21S1) of the fin 21X to the side surface via the gate insulating film 25, and further protrudes toward the first substrate 10 side from the lower surface (back surface 21S2) of the fin 21X so as to follow the side surface of the contact wiring 53. In other words, the contact wiring 53 connected to the gate electrode 26 is connected to the gate electrode 26 via the side surface. For example, the contact wiring 53 connecting the source region 21S or drain region 21D of the pixel transistor 210A from the back surface 21S2 side of the semiconductor substrate 21 has a diameter larger than the width of the fin 21X, and the portion that protrudes outside the fin 21X extends to the side surface of the fin 21X, thereby connecting to the source region 21S or drain region 21D from the side surface of the fin 21X. For example, the contact wiring 57 connecting the gate electrode 26, source region 21S or drain region 21D of the pixel transistor 210A from the front surface 21S1 side of the semiconductor substrate 21 has a diameter less than or equal to the width of the fin 21X, as shown in Figure 13, for example, and is connected from the top surface (front surface 21S1) side of the fin 21X. Furthermore, the contact wiring 57 connecting the source region 21S or drain region 21D to the semiconductor substrate 21 from the surface 21S1 side may have a diameter larger than the width of the fin 21X, similar to the contact wiring 53 connecting the source region 21S or drain region 21D to the back surface 21S2 side of the semiconductor substrate 21. The portion that protrudes outside the fin 21X may extend to the side surface of the fin 21X, thereby connecting to the source region 21S or drain region 21D from the top surface and side surface of the fin 21X.

[0086] [Manufacturing Method for Light Detection Device] Figures 16A to 16L show an example of a manufacturing method for the pixel transistor 210A and the contact wiring 53.

[0087] First, as shown in Figure 16A, a silicon substrate 74 is prepared in which the channel protection film 27 and the semiconductor substrate 21 are stacked in that order. Next, as shown in Figure 16B, the semiconductor substrate 21, the channel protection film 27, and a portion of the silicon substrate 74 are processed into a fin shape by photolithography and etching (for example, dry etching).

[0088] Next, as shown in Figure 16C, an interlayer insulating layer 52 is formed to fill the space between adjacent fin-shaped semiconductor substrates 21. Then, as shown in Figure 16D, a gate insulating film 25 is formed on the surface of the semiconductor substrate 21 exposed from the interlayer insulating layer 52, for example, by thermal oxidation.

[0089] Next, as shown in Figure 16E, after forming the gate electrode 26 in a predetermined pattern, an insulating film 521 is deposited to cover the fin-shaped semiconductor substrate 21. Then, as shown in Figure 16F, after depositing an interlayer insulating layer 56 to fill the gaps between adjacent fin-shaped semiconductor substrates 21, contact wiring 57 is formed to connect to a plurality of pixel transistors 210A from the surface 21S1 side.

[0090] Next, as shown in Figure 16G, wiring layers M23 and M24 (not shown) are sequentially deposited using the BEOL process, after which multiple pad electrodes 58 are formed and exposed on the surface of the interlayer insulating layer 56. As a result, a wiring layer 55 is formed on the surface 21S1 side of the semiconductor substrate 21.

[0091] Next, as shown in Figure 16H, the wiring layer 55 and the wiring layer 61 of the separately prepared third substrate 30 are placed facing each other, and the multiple pad electrodes 58 and 63 exposed on the respective surfaces of the wiring layer 55 and wiring layer 61 are bonded together. This electrically connects the second substrate 20 and the third substrate 30.

[0092] Next, as shown in Figure 16I, the silicon substrate 74 is removed by, for example, CMP, and the interlayer insulating layer 52 is thinned to a predetermined thickness. Then, as shown in Figure 16J, the silicon substrate 74 embedded in the interlayer insulating layer 52 is removed to form an opening H1, and then, as shown in Figure 16K, the gate insulating film 25 remaining on the side surface of the opening H1 is removed.

[0093] Next, as shown in Figure 16L, contact wiring 53 is formed within the opening H1. This ensures that the contact wiring 53, which connects the gate electrode 26 of the pixel transistor 210A to the back surface 21S2 side of the semiconductor substrate 21, is self-aligned.

[0094] [Function and Effects] In the photodetector 2 of this embodiment, one or more contact lines (contact lines 53, 57) are connected to a plurality of pixel transistors 210 formed on the semiconductor substrate 21 from one or both of the front surface 21S1 and the back surface 21S2 of the semiconductor substrate 21. As a result, the above-mentioned through-wiring is unnecessary, and the semiconductor substrate 21 on which the readout circuit 22 is provided can be effectively utilized.

[0095] As described above, the light detection device 2 of this embodiment can obtain the same effects as the first embodiment.

[0096] Furthermore, in the photodetector 2 of this embodiment, the gate electrode 26 of the pixel transistor 210A and the contact wiring 53 connected from the back surface 21S2 side of the semiconductor substrate 21 are formed in a self-aligned manner, thereby preventing a decrease in reliability due to misalignment between the gate electrode 26 and the contact wiring 53.

[0097] Furthermore, in the light detection device 2 of this embodiment, compared to the first embodiment described above, the diameter of the contact wiring 53 connected from the back surface 21S2 side of the semiconductor substrate 21 to the gate electrode 26 of the pixel transistor 210A is reduced, making it possible to effectively utilize the contact area with the gate electrode 26.

[0098] <2. Third Embodiment> Figure 17 shows an example of the vertical cross-sectional configuration of the light detection device 3 according to the third embodiment of the present disclosure. Figure 18 shows another example of the vertical cross-sectional configuration of the light detection device 3 according to the third embodiment of the present disclosure. The light detection device 3 is used, for example, as a CMOS image sensor used in electronic devices such as digital still cameras and video cameras.

[0099] [Outline Configuration of the Photodetector] The photodetector 3, like the photodetector 1 of the first embodiment described above, comprises a first substrate 10, a second substrate 20, and a third substrate 30, and is a three-dimensional imaging device constructed by bonding these three substrates together. The first substrate 10, the second substrate 20, and the third substrate 30 are stacked in this order.

[0100] The first substrate 10 includes a semiconductor substrate 11 having a plurality of sensor pixels 12 that perform photoelectric conversion. The plurality of sensor pixels 12 are arranged in a matrix within the pixel region 13 of the first substrate 10.

[0101] The second substrate 20 includes a semiconductor substrate 21 having a readout circuit (for example, a readout circuit 22A) that outputs a pixel signal based on the charge from the sensor pixels 12. For example, one readout circuit 22A is provided for each sensor pixel 12. The second substrate 20 also includes a plurality of pixel drive lines 23 extending in the row direction and a plurality of vertical signal lines 24 extending in the column direction.

[0102] The third substrate 30 includes a semiconductor substrate 31 having a logic circuit 32 for processing pixel signals. The logic circuit 32 also includes, for example, a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36. The logic circuit 32 can output an output voltage Vout for each sensor pixel 12 to the outside via the horizontal drive circuit 35.

[0103] [Cross-sectional configuration of the light detection device] As described above, the light detection device 3 has a first substrate 10, a second substrate 20, and a third substrate 30 stacked in this order. Furthermore, the light incident side (also called the back side) of the first substrate 10 is equipped with a color filter 92, a light receiving lens 94, etc. In other words, the light detection device 3 is a back-illuminated imaging device.

[0104] The first substrate 10 is constructed by laminating wiring layers 44 on a semiconductor substrate 11. The second substrate 20 is constructed by laminating wiring layers 55 on the front surface 21S1 side of the semiconductor substrate 21 facing the third substrate 30, and wiring layers 51 on the back surface 21S2 side of the semiconductor substrate 21 facing the first substrate 10. The third substrate 30 is constructed, for example, by laminating wiring layers 61 on a semiconductor substrate 31. In other words, the first substrate 10 and the second substrate 20 are bonded face to back. The second substrate 20 and the third substrate 30 are bonded face to face.

[0105] [Configuration and Connection of Pixel Transistors] Each of the multiple pixel transistors 210B constituting the readout circuit 22A has a three-dimensional structure. One or more contact lines (contact lines 53, 57) are connected to each of the multiple pixel transistors 210B constituting the readout circuit 22A from either the front surface 21S1 side or the back surface 21S2 side or both of the semiconductor substrate 21.

[0106] Each of the multiple pixel transistors 210B has a Fin-FET structure, similar to the pixel transistor 210 in the first embodiment described above, and is composed of a fin 21X made of a semiconductor substrate 21, a gate insulating film 25, and a gate electrode 26.

[0107] The fin 21X has a flat plate shape, for example, that is erected in the Z-axis direction and extends in the Y-axis direction. The upper surface (surface 21S1) and side surfaces of the fin 21X are covered with a gate insulating film 25. The gate electrode 26 is provided so as to straddle the fin 21X in the X-axis direction, which intersects with the extension direction (Y-axis direction) of the fin 21X, and extends to the upper surface (surface 21S1) and side surfaces of the fin 21X. A channel region 21C is formed on the fin 21X at a position opposite to the gate electrode 26, and a source region 21S and a drain region 21D are formed at both ends of this channel region 71C.

[0108] The gate insulating film 25 can be formed from a high dielectric constant material (High-K material) such as silicon oxide (SiO), hafnium oxide (HfO), hafnium silicate (HfSiO), nitrogen-doped hafnium silicate (HfSiON), zirconium oxide (ZrO), zirconium silicate (ZrSiON), tantalum oxide (TaO), and tantalum oxynitride (TaON). ​​The gate electrode 26 can be formed from a metallic material such as one of titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), and aluminum (Al).

[0109] A channel protection film 27 is provided on the lower surface (back surface 21S2) of the fin 21X to electrically isolate the channel region 21C from the contact wiring 53. The channel protection film 27 is formed of, for example, a single layer of silicon nitride (SiN), silicon oxide (SiO), or undoped polysilicon (Poly-Si), or a laminated film consisting of two or more of these.

[0110] The pixel transistor 210B and the contact wirings 53 and 57 are connected as follows. For example, the contact wiring 53 connected to the gate electrode 26 of the pixel transistor 210B from the back surface 21S2 side of the semiconductor substrate 21 is formed together with the gate electrode 26, as will be described in detail later, and is made of the same material as the gate electrode 26. This contact wiring 53 formed together with the gate electrode 26 is formed as a part of the gate electrode 26 (contact portion 26X), and unlike other contact wirings 53, it has a shape in which the diameter gradually decreases from the semiconductor substrate 21 side toward the first substrate 10. Alternatively, the contact portion 26X may be formed below a widened portion 26Y, which is a part of the gate electrode 26 that extends in the in-plane direction (XY direction) of the semiconductor substrate 21, as shown in Figure 18. The widened portion 26Y corresponds to one specific example of the "widened portion" as one embodiment of this disclosure. For example, the contact wiring 53 connecting the source region 21S or drain region 21D of the pixel transistor 210B from the back surface 21S2 side of the semiconductor substrate 21 has a diameter larger than the width of the fin 21X, and the portion that protrudes outside the fin 21X extends to the side surface of the fin 21X, thereby connecting to the source region 21S or drain region 21D from the side surface of the fin 21X. For example, the contact wiring 57 connecting the gate electrode 26, source region 21S or drain region 21D of the pixel transistor 210B from the front surface 21S1 side of the semiconductor substrate 21 has a diameter less than or equal to the width of the fin 21X, as shown in Figure 13, for example, and is connected from the top surface side of the fin 21X. Furthermore, the contact wiring 57 connecting the source region 21S or drain region 21D to the semiconductor substrate 21 from the surface 21S1 side may be made with a diameter larger than the width of the fin 21X, similar to the contact wiring 53 connecting the source region 21S or drain region 21D to the back surface 21S2 side of the semiconductor substrate 21, and the portion that protrudes outside the fin 21X may be extended to the side surface of the fin 21X so that it is connected to the source region 21S or drain region 21D from the top surface (surface 21S1) and side surface of the fin 21X.

[0111] [Manufacturing Method for Light Detection Device] Figures 19A to 19N show an example of a manufacturing method for the pixel transistor 210B and contact wiring 53.

[0112] First, as shown in Figure 19A, a support substrate 75 is prepared in which an interlayer insulating layer 52, a channel protective film 27, and a semiconductor substrate 21 are stacked in that order. Next, as shown in Figure 19B, the semiconductor substrate 21 and the channel protective film 27 are processed into a fin shape by photolithography and etching (for example, dry etching).

[0113] Next, as shown in Figure 19C, an opening H2 is formed in the interlayer insulating layer 52 by photolithography and etching (for example, dry etching). Then, as shown in Figure 19D, a silicon oxide film is formed as the temporary gate insulating film 76, and a polysilicon film is formed as the temporary gate film 77 in sequence. After that, as shown in Figure 19E, the temporary gate film 77 is processed into a predetermined pattern by photolithography and etching. The temporary gate insulating film 76 can be formed by chemical vapor deposition (CVD) or thermal oxidation.

[0114] Next, as shown in Figure 19F, an element isolation layer 28 is formed to fill the space between adjacent fin-shaped semiconductor substrates 21. Then, as shown in Figure 19G, the element isolation layer 28 is thinned, for example by CMP, and a temporary gate film 77 is exposed on the surface of the element isolation layer 28.

[0115] Next, as shown in Figure 19H, the temporary gate film 77 and temporary gate insulating film 76 are removed by etching (for example, wet etching) to form an opening H3. Then, as shown in Figure 19I, a gate insulating film 25 is formed on the surface of the semiconductor substrate 21 by, for example, CVD or thermal oxidation, and then a metal film that will become the gate electrode 26 and contact portion 26X is deposited in the opening H3 by, for example, CVD or atomic layer deposition (ALD).

[0116] Next, as shown in Figure 19J, the metal film deposited on the element isolation layer 28 is removed, for example by CMP. Then, as shown in Figure 19K, wiring layers M23 and M24 (not shown) are sequentially deposited by the BEOL process, after which a plurality of pad electrodes 58 are formed and exposed on the surface of the interlayer insulating layer 56. As a result, the wiring layer 55 is formed on the surface 21S1 side of the semiconductor substrate 21.

[0117] Next, as shown in Figure 19L, the wiring layer 55 and the wiring layer 61 of the separately prepared third substrate 30 are placed facing each other, and the multiple pad electrodes 58 and 63 exposed on the respective surfaces of the wiring layer 55 and wiring layer 61 are bonded together. This electrically connects the second substrate 20 and the third substrate 30. Then, as shown in Figure 19M, the silicon substrate 74 is removed, for example, by CMP.

[0118] Next, as shown in Figure 19N, after sequentially depositing wiring layers M21 and M22 (not shown) using the BEOL process, a plurality of pad electrodes 54 are formed and exposed on the surface of the interlayer insulating layer 52. This forms a wiring layer 51 on the back surface 21S2 side of the semiconductor substrate 21. Subsequently, the wiring layer 44 and wiring layer 51 of the separately formed first substrate 10 are placed facing each other, and the plurality of pad electrodes 48 and 54 exposed on the respective surfaces of the wiring layer 44 and wiring layer 51 are bonded together. This electrically connects the first substrate 10 and the second substrate 20. With the above steps, the photodetector 3 shown in Figure 17 is completed.

[0119] [Function and Effects] In the photodetector 3 of this embodiment, one or more contact lines (contact lines 53, 57) are connected to a plurality of pixel transistors 210 formed on the semiconductor substrate 21 from one or both of the front surface 21S1 and back surface 21S2 sides of the semiconductor substrate 21. As a result, the above-mentioned through-wiring is unnecessary, and the semiconductor substrate 21 on which the readout circuit 22 is provided can be effectively utilized.

[0120] As described above, the light detection device 3 of this embodiment can obtain the same effects as the first embodiment.

[0121] Furthermore, in the photodetector 3 of this embodiment, the gate electrode 26 of the pixel transistor 210B and the contact wiring 53 connected from the back surface 21S2 side of the semiconductor substrate 21 are formed from the same material, so that the contact resistance is reduced compared to the first embodiment. Therefore, it is possible to improve the device characteristics.

[0122] Furthermore, in the photodetector 3 of this embodiment, the gate electrode 26 of the pixel transistor 210B and the contact wiring 53 connected from the back surface 21S2 side of the semiconductor substrate 21 are formed before joining with the third substrate 30. This prevents a decrease in reliability due to misalignment between the gate electrode 26 and the contact wiring 53 caused by bonding strain.

[0123] <3. Modification> Figure 20 shows an example of a vertical cross-sectional configuration of the photodetector 3A, which is a modification of the third embodiment of the present disclosure.

[0124] In the third embodiment described above, the present technology was explained using a pixel transistor 210B having a three-dimensional structure as an example, but it is not limited thereto. In this modified example, the photodetector 3A applies the present technology to a planar transistor 210C, and the contact wiring connecting the gate electrode 26A formed on the surface 21S1 side of the semiconductor substrate 21 and the wiring (for example, a pad electrode 54) provided inside the wiring layer 61 is formed of the same material as the gate electrode 26A. Except for this point, the photodetector 3A has substantially the same configuration as the photodetector 3 of the third embodiment described above.

[0125] Even with this configuration, the modified photodetector 3A can achieve the same effects as the photodetector 3 of the third embodiment described above.

[0126] <5. Fourth Embodiment> Figure 21 shows an example of a vertical cross-sectional configuration of the light detection device 4 according to the fourth embodiment of the present disclosure. The light detection device 4 is used, for example, as a CMOS image sensor used in electronic devices such as digital still cameras and video cameras.

[0127] [Outline Configuration of the Photodetector] The photodetector 4, like the photodetector 1 of the first embodiment described above, comprises a first substrate 10, a second substrate 20, and a third substrate 30, and is a three-dimensional imaging device constructed by bonding these three substrates together. The first substrate 10, the second substrate 20, and the third substrate 30 are stacked in this order.

[0128] The first substrate 10 includes a semiconductor substrate 11 having a plurality of sensor pixels 12 that perform photoelectric conversion. The plurality of sensor pixels 12 are arranged in a matrix within the pixel region 13 of the first substrate 10.

[0129] The second substrate 20 includes a semiconductor substrate 21 having a readout circuit (for example, a readout circuit 22A) that outputs a pixel signal based on the charge from the sensor pixels 12. For example, one readout circuit 22A is provided for each sensor pixel 12. The second substrate 20 also includes a plurality of pixel drive lines 23 extending in the row direction and a plurality of vertical signal lines 24 extending in the column direction.

[0130] The third substrate 30 includes a semiconductor substrate 31 having a logic circuit 32 for processing pixel signals. The logic circuit 32 also includes, for example, a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36. The logic circuit 32 can output an output voltage Vout for each sensor pixel 12 to the outside via the horizontal drive circuit 35.

[0131] [Cross-sectional configuration of the light detection device] As described above, the light detection device 4 has a first substrate 10, a second substrate 20, and a third substrate 30 stacked in this order. Furthermore, the light incident side (also called the back side) of the first substrate 10 is equipped with a color filter 92, a light receiving lens 94, etc. In other words, the light detection device 4 is a back-illuminated imaging device.

[0132] The first substrate 10 is constructed by laminating wiring layers 44 on a semiconductor substrate 11. The second substrate 20 is constructed by laminating wiring layers 55 on the front surface 21S1 side of the semiconductor substrate 21 facing the third substrate 30, and wiring layers 51 on the back surface 21S2 side of the semiconductor substrate 21 facing the first substrate 10. The third substrate 30 is constructed, for example, by laminating wiring layers 61 on a semiconductor substrate 31. In other words, the first substrate 10 and the second substrate 20 are bonded face to back. The second substrate 20 and the third substrate 30 are bonded face to face.

[0133] [Configuration and Connection of Pixel Transistors] Figure 22 schematically shows the planar configuration of the pixel transistor 210D shown in Figure 21. Figure 23A schematically shows the cross-sectional configuration of the pixel transistor 210D corresponding to the V-V' line shown in Figure 22. Figure 23B schematically shows the cross-sectional configuration of the pixel transistor 210D corresponding to the VI-VI' line shown in Figure 22. Figure 23C schematically shows the cross-sectional configuration of the pixel transistor 210D corresponding to the VII-VII' line shown in Figure 22.

[0134] Each of the multiple pixel transistors 210D constituting the readout circuit 22A has a three-dimensional structure. One or more contact lines (contact lines 53, 57) are connected to each of the multiple pixel transistors 210D constituting the readout circuit 22A from either the front surface 21S1 side or the back surface 21S2 side or both of the semiconductor substrate 21.

[0135] Each of the multiple pixel transistors 210D has a gate-all-around (GAA) structure and is composed of a fin 21X made of a semiconductor substrate 21, a gate insulating film 25, and a gate electrode 26.

[0136] The fin 21X has a flat plate shape, for example, that is erect in the Z-axis direction and extends in the Y-axis direction. The upper surface (front surface 21S1), lower surface (back surface 21S2), and side surfaces of the fin 21X are covered with a gate insulating film 25. The gate electrode 26 straddles the fin 21X in the X-axis direction, which intersects with the extension direction (Y-axis direction) of the fin 21X, and extends along the upper surface (front surface 21S1), lower surface (back surface 21S2), and side surfaces of the fin 21X so as to surround the fin 21X. A channel region 21C is formed on the fin 21X at a position opposite to the gate electrode 26, and a source region 21S and a drain region 21D are formed at both ends of this channel region 71C.

[0137] The gate insulating film 25 can be formed from a high dielectric constant material (High-K material) such as silicon oxide (SiO), hafnium oxide (HfO), hafnium silicate (HfSiO), nitrogen-doped hafnium silicate (HfSiON), zirconium oxide (ZrO), zirconium silicate (ZrSiON), tantalum oxide (TaO), and tantalum oxynitride (TaON). ​​The gate electrode 26 can be formed from, for example, titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), aluminum (Al), and polysilicon (Poly-Si).

[0138] A channel protection film 27 is provided on the lower surface (back surface 21S2) of the fin 21X to electrically isolate the channel region 21C from the contact wiring 53. The channel protection film 27 is formed of, for example, a single layer of silicon nitride (SiN), silicon oxide (SiO), or undoped polysilicon (Poly-Si), or a laminated film consisting of two or more of these.

[0139] The pixel transistor 210D and the contact wirings 53 and 57 are connected as follows. For example, the contact wiring 53 connected from the back surface 21S2 side of the semiconductor substrate 21 to the gate electrode 26 of the pixel transistor 210D is directly connected to the gate electrode 26 that extends to the lower surface (back surface 21S2) of the fin 21X, as shown in Figures 23A and 23C. For example, the contact wiring 53 connected from the back surface 21S2 side of the semiconductor substrate 21 to the source region 21S or drain region 21D of the pixel transistor 210D is connected from the lower surface (back surface 21S2) of the fin 21X to the source region 21S or drain region 21D with a diameter approximately the same as the width of the fin 21X, as shown in Figure 21. For example, the contact wiring 57 connecting the gate electrode 26, source region 21S, or drain region 21D of the pixel transistor 210D to the surface 21S1 side of the semiconductor substrate 210D is connected from the upper surface (surface 21S1) side of the fin 21X with a diameter approximately the same as the width of the fin 21X, as shown in Figures 21 and 22.

[0140] [Manufacturing Method for Photodetector] Figures 24A to 24H show an example of a manufacturing method for the pixel transistor 210D. In Figures 24A to 24H, (A) shows the planar configuration of the pixel transistor 210D, (B) shows the cross-sectional configuration of the pixel transistor 210D corresponding to the V-V' line shown in (A), (C) shows the cross-sectional configuration of the pixel transistor 210D corresponding to the VI-VI' line shown in (A), and (D) shows the cross-sectional configuration of the pixel transistor 210D corresponding to the VII-VII' line shown in (A).

[0141] First, as shown in Figure 24A, a semiconductor substrate 21 is prepared in which an interlayer insulating layer 52 is laminated on the back surface 21S2. Next, as shown in Figure 24B, a mask 81 is patterned on the front surface 21S1 of the semiconductor substrate 21, and then, as shown in Figure 24C, a portion of the semiconductor substrate 21 and the interlayer insulating layer 52 are processed into a fin shape by photolithography and etching (for example, dry etching).

[0142] Next, as shown in Figure 24D, a mask 82 having an opening 82H at the position where the channel region 21C is formed is patterned across the semiconductor substrate 21 and the interlayer insulating layer 52. Subsequently, as shown in Figure 24E, the interlayer insulating layer 52 exposed from the mask 82 is processed by etching (for example, wet etching). As a result, a groove 52G is formed in the interlayer insulating layer 52 below the semiconductor substrate 21 where the channel region 21C is formed.

[0143] Next, as shown in Figure 24F, a gate insulating film 25 is formed on the surface of the semiconductor substrate 21 by, for example, thermal oxidation, and then the gate electrode 26 is deposited. Subsequently, as shown in Figure 24G, a mask 83 is patterned on the gate electrode 26 at the position where the channel region 21C is formed. At this time, the mask 83 is formed to be larger than the groove 52G so as to cover the entire groove 52G in a plan view.

[0144] Next, as shown in Figure 24H, the gate electrode 26 exposed from the mask 83 is removed by etching (for example, dry etching). As a result, as shown in Figure 23C, for example, a gate electrode 26 is formed in which the gate width between the source region 21S and the drain region 21D is different on the front surface 21S1 side and the back surface 21S2 side of the semiconductor substrate 21. Specifically, a gate electrode 26 is formed in which the gate width W1 on the front surface 21S1 side of the semiconductor substrate 21 is larger than the gate width W2 on the back surface 21S2 side of the semiconductor substrate 21 (W1 > W2).

[0145] [Function and Effects] In the photodetector 4 of this embodiment, one or more contact lines (contact lines 53, 57) are connected to a plurality of pixel transistors 210 formed on the semiconductor substrate 21 from either the front surface 21S1 side and the back surface 21S2 side or both of the semiconductor substrate 21

[0146] As described above, the light detection device 4 of this embodiment can obtain the same effects as the first embodiment.

[0147] Furthermore, in the photodetector 4 of this embodiment, the pixel transistor 210D has a GAA structure, which allows the entire upper surface of the contact wiring 53 to be directly connected to the gate electrode 26 that extends to the lower surface (back surface 21S2) of the fin 21X. Therefore, compared to the first embodiment and the like, the connection between the gate electrode 26 and the contact wiring 53 becomes easier. Also, it becomes easier to secure the connection area between the gate electrode 26 and the contact wiring 53, which is advantageous for reducing the size of the gate electrode 26 and the channel region 21C.

[0148] Furthermore, in the photodetector 4 of this embodiment, the pixel transistor 210D has a GAA structure, so the gate width can be secured compared to the first embodiment and others where the pixel transistor (for example, the pixel transistor 210) has a Fin-FET structure. Therefore, it is possible to improve the transconductance (gm) of the transistor.

[0149] <6. Fifth Embodiment> Figure 31 shows an example of a vertical cross-sectional configuration of the light detection device 5 according to the fifth embodiment of the present disclosure. The light detection device 5 is used, for example, as a CMOS image sensor used in electronic devices such as digital still cameras and video cameras.

[0150] [Outline Configuration of the Photodetector] The photodetector 5, like the photodetector 1 of the first embodiment described above, comprises a first substrate 10, a second substrate 20, and a third substrate 30, and is a three-dimensional imaging device constructed by bonding these three substrates together. The first substrate 10, the second substrate 20, and the third substrate 30 are stacked in this order.

[0151] The first substrate 10 includes a semiconductor substrate 11 having a plurality of sensor pixels 12 that perform photoelectric conversion. The plurality of sensor pixels 12 are arranged in a matrix within the pixel region 13 of the first substrate 10.

[0152] The second substrate 20 includes a semiconductor substrate 21 having a readout circuit (for example, a readout circuit 22A) that outputs a pixel signal based on the charge from the sensor pixels 12. For example, one readout circuit 22A is provided for each sensor pixel 12. The second substrate 20 also includes a plurality of pixel drive lines 23 extending in the row direction and a plurality of vertical signal lines 24 extending in the column direction.

[0153] The third substrate 30 includes a semiconductor substrate 31 having a logic circuit 32 for processing pixel signals. The logic circuit 32 also includes, for example, a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36. The logic circuit 32 can output an output voltage Vout for each sensor pixel 12 to the outside via the horizontal drive circuit 35.

[0154] [Cross-sectional configuration of the light detection device] As described above, the light detection device 5 has a first substrate 10, a second substrate 20, and a third substrate 30 stacked in this order. Furthermore, the light incident side (also called the back side) of the first substrate 10 is equipped with a color filter 92, a light receiving lens 94, etc. In other words, the light detection device 5 is a back-illuminated imaging device.

[0155] The first substrate 10 is constructed by laminating wiring layers 44 on a semiconductor substrate 11. The second substrate 20 is constructed by laminating wiring layers 55 on the front surface 21S1 side of the semiconductor substrate 21 facing the third substrate 30, and wiring layers 51 on the back surface 21S2 side of the semiconductor substrate 21 facing the first substrate 10. The third substrate 30 is constructed, for example, by laminating wiring layers 61 on a semiconductor substrate 31. In other words, the first substrate 10 and the second substrate 20 are bonded face to back. The second substrate 20 and the third substrate 30 are bonded face to face.

[0156] [Configuration and Connection of Pixel Transistors] Each of the multiple pixel transistors 210E constituting the readout circuit 22A has a three-dimensional structure. One or more contact lines (contact lines 53, 57) are connected to each of the multiple pixel transistors 210E constituting the readout circuit 22A from either the front surface 21S1 side and the back surface 21S2 side or both of the semiconductor substrate 21.

[0157] Each of the multiple pixel transistors 210E has a Fin-FET structure, similar to the pixel transistor 210 in the first embodiment described above, and is composed of a fin 21X made of a semiconductor substrate 21, a gate insulating film 25, and a gate electrode 26.

[0158] The fin 21X has a flat plate shape, for example, that is erected in the Z-axis direction and extends in the Y-axis direction. The upper surface (surface 21S1) and side surfaces of the fin 21X are covered with a gate insulating film 25. The gate electrode 26 is provided so as to straddle the fin 21X in the X-axis direction, which intersects with the extension direction (Y-axis direction) of the fin 21X, and extends to the upper surface (surface 21S1) and side surfaces of the fin 21X. A channel region 21C is formed on the fin 21X at a position opposite to the gate electrode 26, and a source region 21S and a drain region 21D are formed at both ends of this channel region 71C.

[0159] In this embodiment, the fin 21X has different heights in the channel region 21C and in the source region 21S and drain region 21D. As will be described in detail later, the channel region 21C is etched more deeply than the source region 21S and drain region 21D, and the lower surface (back surface 21S2-2) of the fin 21X in the channel region 21C is formed closer to the upper surface (front surface 21S1) of the fin 21X than the lower surface (back surface 21S2-1) of the fin 21X in the source region 21S and drain region 21D. In other words, the height h1 of the fin 21X in the source region 21S and drain region 21D is configured to be higher than the height h2 of the fin 21X in the channel region 21C (h1 > h2).

[0160] The gate insulating film 25 can be formed from a high dielectric constant material (High-K material) such as silicon oxide (SiO), hafnium oxide (HfO), hafnium silicate (HfSiO), nitrogen-doped hafnium silicate (HfSiON), zirconium oxide (ZrO), zirconium silicate (ZrSiON), tantalum oxide (TaO), and tantalum oxynitride (TaON). ​​The gate electrode 26 can be formed from a metallic material such as one of titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), and aluminum (Al).

[0161] Insulating films 52B and 59 are provided on the lower surface (back surface 21S2-2) of the fin 21X in the channel region 21C, serving as channel protective films to electrically isolate the channel region 21C from the contact wiring 53. The insulating films 52B and 59 are formed from insulating materials such as silicon nitride (SiN) or silicon oxide (SiO). The contact wiring 53 is directly connected to the lower surface (back surface 21S2-1) of the fin 21X in the source region 21S and the drain region 21D.

[0162] The pixel transistor 210E and the contact wirings 53 and 57 are connected as follows. The contact wiring 53, which is connected from the back surface 21S2 side of the semiconductor substrate 21 to the gate electrode 26 of the pixel transistor 210E, has a diameter larger than the width of the fin 21X, as shown in Figure 31, for example, and is connected to the gate electrode 26 so as to straddle the channel protective film (insulating film 52B, 59) provided on the lower surface (back surface 21S2-2) of the fin 21X in the channel region 21C. The contact wiring 53, which is connected from the back surface 21S2 side of the semiconductor substrate 21 to the source region 21S or drain region 21D of the pixel transistor 210E, is directly connected to the lower surface (back surface 21S2-1) of the fin 21X, as described above. The contact wiring 53 has a diameter larger than the width of the fin 21X in the source region 21S and drain region 21D, as shown in Figure 31, for example. The contact wiring 57 connecting the gate electrode 26 of the pixel transistor 210E, the source region 21S, or the drain region 21D to the semiconductor substrate 21 from the surface 21S1 side is connected from the upper surface (surface 21S1) side of the fin 21X, for example, with a diameter less than or equal to the width of the fin 21X, similar to the first embodiment described above. Alternatively, the contact wiring 57 connecting the source region 21S or the drain region 21D to the semiconductor substrate 21 from the surface 21S1 side may have a diameter greater than the width of the fin 21X, similar to the contact wiring 53 connecting the source region 21S or the drain region 21D to the back surface 21S2 side of the semiconductor substrate 21. The portion extending beyond the fin 21X may extend to the side surface of the fin 21X, thereby connecting to the source region 21S or the drain region 21D from both the upper and side surfaces of the fin 21X.

[0163] [Manufacturing Method for Light Detection Device] Figures 32A to 32O show an example of a manufacturing method for the pixel transistor 210E and contact wiring 53.

[0164] First, as shown in Figure 32A, a hard mask 84 is deposited on the surface 21S1 of a bulk silicon substrate (semiconductor substrate 21). Next, as shown in Figure 32B, after processing the hard mask 84 into a predetermined pattern, the semiconductor substrate 21 is processed into a fin shape by photolithography and etching (for example, dry etching). Subsequently, as shown in Figure 32C, a silicon oxide film, for example, is deposited as an element isolation layer 28 to fill the gaps between adjacent fins 21X.

[0165] Next, as shown in Figure 32D, boron (B) is implanted to a predetermined height on each fin 21X by, for example, ion implantation, to form an etching stopper film 29. At this time, the height to which the boron (B) is implanted differs between the channel region 21C and the source region 21S and drain region 21D of each fin 21X. Specifically, boron (B) is implanted to a deeper position in the source region 21S and drain region 21D of each fin 21X than in the channel region 21C. Subsequently, as shown in Figure 32E, the element isolation layer 28 is etched back to a predetermined thickness. Next, as shown in Figure 32F, a gate insulating film 25 is formed on the surface of each fin 21X exposed from the element isolation layer 28 by, for example, thermal oxidation, and then a gate electrode 26 is formed in a predetermined pattern.

[0166] Next, as shown in Figure 32G, a silicon oxide film is formed as part of the element isolation layer 28 and the interlayer insulating layer 56, covering each fin 21X, and then contact wiring 57 is formed to connect to the pixel transistor 210E from the surface 21S1 side. Then, as shown in Figure 32H, wiring layers M23 and M24 (not shown) are sequentially formed by the BEOL process, and then a plurality of pad electrodes 58 are formed and exposed on the surface of the interlayer insulating layer 56. As a result, a wiring layer 55 is formed on the surface 21S1 side of the semiconductor substrate 21.

[0167] Next, as shown in Figure 32I, the wiring layer 55 and the wiring layer 61 of the separately prepared third substrate 30 are placed facing each other, and the multiple pad electrodes 58 and 63 exposed on the respective surfaces of the wiring layer 55 and wiring layer 61 are bonded together. This electrically connects the second substrate 20 and the third substrate 30.

[0168] Next, as shown in Figure 32J, the semiconductor substrate 21 is thinned, for example by CMP, until the element isolation layer 28 is exposed, thereby separating each fin 21X. Subsequently, as shown in Figure 32K, the semiconductor substrate 21 constituting each fin 21X is etched down to the etching stopper film 29 to form an opening H4. That is, the semiconductor substrate 21 that becomes the channel region 21C of the fin 21X is etched deeper than the semiconductor substrate 21 that becomes the source region 21S and the drain region 21D. As a result, the lower surface (back surface 21S2-2) of the fin 21X that becomes the channel region 21C is formed at a deeper position than the lower surface (back surface 21S2-1) of the fin 21X that becomes the source region 21S and the drain region 21D. Next, as shown in Figure 32L, an insulating film 59, for example, a silicon nitride film, is deposited on the side and bottom surfaces of the opening H4 and on the element isolation layer 28, and then an insulating film 52B, for example, a silicon oxide film, is deposited on the insulating film 59 so as to fill the opening H4.

[0169] Next, as shown in Figure 32M, an opening H5 is formed in the insulating film 52B by photolithography and etching (for example, dry etching). Then, as shown in Figure 32N, the insulating film 59 and the element isolation layer 28 are further etched by photolithography and etching (for example, dry etching) to expose the bottom surface of the opening H5, which will be the gate electrode 26 or the bottom surface (back surface 21S2-2) of the fin 21X that will become the source region 21S and drain region 21D. Subsequently, as shown in Figure 32O, contact wiring 53 is formed to connect to the pixel transistor 210E from the back surface 21S2 side.

[0170] Next, in the same manner as in the first embodiment described above, the wiring layers M21 and M22 are sequentially formed by the BEOL process, and then a plurality of pad electrodes 54 are formed and exposed on the surface of the interlayer insulating layer 52. This forms the wiring layer 51 on the back surface 21S2 side of the semiconductor substrate 21. After that, the wiring layer 44 and wiring layer 51 of the separately formed first substrate 10 are placed facing each other, and the plurality of pad electrodes 48 and 54 exposed on the respective surfaces of the wiring layer 44 and wiring layer 51 are bonded together. This electrically connects the first substrate 10 and the second substrate 20. With the above steps completed, the photodetector 5 shown in Figure 31 is completed.

[0171] [Function and Effects] In the photodetector 5 of this embodiment, the height of the fins 21X is made different in the channel region 21C and the source region 21S and drain region 21D. The height h1 of the fins 21X in the source region 21S and drain region 21D is higher than the height h2 of the fins 21X in the channel region 21C (h1 > h2). Specifically, the lower surface (back surface 21S2-2) of the fins 21X in the channel region 21C is formed closer to the upper surface (front surface 21S1) of the fins 21X in the source region 21S and drain region 21D than the lower surface (back surface 21S2-1) of the fins 21X in the source region 21S and drain region 21D. This prevents short circuits between the contact wiring 53 and the channel region 21C, compared to, for example, the case in the first embodiment where the contact wiring 53 is extended to the side surface of the fins 21X to connect the contact wiring 53 to the source region 21S or drain region 21D from the side surface of the fins 21X.

[0172] As described above, the light detection device 5 of this embodiment can improve reliability in addition to the effects of the first embodiment.

[0173] Furthermore, in the optical detection device 5 of this embodiment, the manufacturing process eliminates the need for steps such as preparing the support substrate 71 and thinning the substrate after bonding the support substrate 71 to the semiconductor substrate 21, as shown in Figures 8A and 8B, thus reducing manufacturing costs.

[0174] <7. Application Examples> (Application Example 1) The above-mentioned light detection device 1 can be applied to any type of electronic device equipped with an imaging function, such as camera systems like digital still cameras and video cameras, and mobile phones with imaging capabilities. Figure 25 shows a schematic configuration of the electronic device 1000.

[0175] The electronic device 1000 includes, for example, a lens group 1001, a light detection device 1, a DSP (Digital Signal Processor) circuit 1002, a frame memory 1003, a display unit 1004, a recording unit 1005, an operation unit 1006, and a power supply unit 1007, all of which are interconnected via a bus line 1008.

[0176] The lens group 1001 captures incident light (image light) from the subject and forms an image on the imaging surface of the light detection device 1. The light detection device 1 converts the amount of incident light formed on the imaging surface by the lens group 1001 into an electrical signal on a pixel-by-pixel basis and supplies it as a pixel signal to the DSP circuit 1002.

[0177] The DSP circuit 1002 is a signal processing circuit that processes signals supplied from the light detection device 1. The DSP circuit 1002 outputs image data obtained by processing the signals from the light detection device 1. The frame memory 1003 temporarily holds the image data processed by the DSP circuit 1002 in frame units.

[0178] The display unit 1004 consists of a panel-type display device such as a liquid crystal panel or an organic EL (Electroluminescence) panel, and records the video or still image data captured by the light detection device 1 onto a recording medium such as a semiconductor memory or a hard disk.

[0179] The operation unit 1006 outputs operation signals for various functions possessed by the electronic device 1000 in accordance with user operations. The power supply unit 1007 appropriately supplies various power sources to the DSP circuit 1002, frame memory 1003, display unit 1004, recording unit 1005, and operation unit 1006.

[0180] (Application Example 2) Figure 26A schematically shows an example of the overall configuration of a photodetection system 2000 equipped with a photodetector 1. Figure 26B shows an example of the circuit configuration of the photodetection system 2000. The photodetection system 2000 includes a light-emitting device 2001 as a light source that emits infrared light L2, and a photodetector 2002 as a light-receiving unit having a photoelectric conversion element. The photodetector 1 described above can be used as the photodetector 2002. The photodetection system 2000 may further include a system control unit 2003, a light source drive unit 2004, a sensor control unit 2005, a light source side optical system 2006, and a camera side optical system 2007.

[0181] The photodetector 2002 can detect light L1 and light L2. Light L1 is light reflected from ambient light from the outside by the subject (object to be measured) 2100 (Figure 26A). Light L2 is light that has been emitted by the light-emitting device 2001 and then reflected by the subject 2100. Light L1 is, for example, visible light, and light L2 is, for example, infrared light. Light L1 is detectable in the photoelectric conversion unit of the photodetector 2002, and light L2 is detectable in the photoelectric conversion region of the photodetector 2002. Image information of the subject 2100 can be obtained from light L1, and distance information between the subject 2100 and the photodetector system 2000 can be obtained from light L2. The photodetector system 2000 can be mounted on, for example, electronic devices such as smartphones or mobile devices such as cars. The light-emitting device 2001 can be, for example, a semiconductor laser, a surface-emitting semiconductor laser, or a vertical-cavity surface-emitting laser (VCSEL). As a detection method for the light L2 emitted from the light-emitting device 2001 by the photodetector 2002, for example, the iTOF method can be used, but is not limited to this. In the iTOF method, the photoelectric conversion unit can measure the distance to the subject 2100 by, for example, the time-of-flight (TOF) of light. As a detection method for the light L2 emitted from the light-emitting device 2001 by the photodetector 2002, for example, the structured light method or the stereo vision method can also be used. For example, in the structured light method, the distance between the photodetector 2000 and the subject 2100 can be measured by projecting a predetermined pattern of light onto the subject 2100 and analyzing the degree of distortion of the pattern. In the stereo vision method, for example, the distance between the photodetector 2000 and the subject can be measured by using two or more cameras to acquire two or more images of the subject 2100 from two or more different viewpoints. Furthermore, the light-emitting device 2001 and the light-detecting device 2002 can be synchronously controlled by the system control unit 2003.

[0182] <8. Application Examples> (Application to Endoscopic Surgical Systems) The technology disclosed herein (this technology) can be applied to various products. For example, the technology disclosed herein may be applied to an endoscopic surgical system.

[0183] Figure 27 is a diagram showing an example of a schematic configuration of an endoscopic surgical system to which the technology described herein (the technology) may be applied.

[0184] Figure 27 illustrates a surgeon (physician) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgical system 11000. As shown in the figure, the endoscopic surgical system 11000 consists of an endoscope 11100, other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy treatment device 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 equipped with various devices for endoscopic surgery.

[0185] The endoscope 11100 consists of a barrel 11101, the tip of which is inserted into the body cavity of the patient 11132 for a predetermined length, and a camera head 11102 connected to the base end of the barrel 11101. In the illustrated example, the endoscope 11100 is shown as a so-called rigid endoscope having a rigid barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible endoscope having a flexible barrel.

[0186] An opening into which an objective lens is fitted is provided at the tip of the microscope tube 11101. A light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the tip of the microscope tube by a light guide extending inside the microscope tube 11101, and is irradiated through the objective lens towards the object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a straight-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0187] The camera head 11102 contains an optical system and an image sensor. Reflected light from the object being observed (observation light) is focused onto the image sensor by the optical system. The image sensor converts the observation light into electrical signals, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0188] The CCU 11201 is composed of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and other components, and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various image processing operations on that image signal, such as development processing (demosaic processing), to display an image based on that image signal.

[0189] The display device 11202 displays an image based on an image signal that has been processed by the CCU 11201, under control from the CCU 11201.

[0190] The light source device 11203 is composed of a light source such as an LED (light-emitting diode) and supplies illumination light to the endoscope 11100 when photographing the surgical area, etc.

[0191] The input device 11204 is an input interface for the endoscopic surgical system 11000. The user can input various types of information and instructions to the endoscopic surgical system 11000 via the input device 11204. For example, the user can input instructions to change the imaging conditions (type of light, magnification, focal length, etc.) of the endoscope 11100.

[0192] The treatment instrument control device 11205 controls the drive of the energy treatment instrument 11112 for purposes such as tissue cauterization, incision, or blood vessel sealing. The insufflation device 11206 injects gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity for the purpose of securing a field of view by the endoscope 11100 and securing the operator's workspace. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, images, or graphs.

[0193] The light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical area can be configured as a white light source consisting of, for example, an LED, a laser light source, or a combination thereof. When the white light source is configured as a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to capture images corresponding to each of the RGB colors in time-division by irradiating the observation target with laser light from each of the RGB laser light sources in time-division and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter on the image sensor.

[0194] Furthermore, the light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the drive of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity, images can be acquired in time-division order, and these images can be combined to generate high dynamic range images without so-called black crushing and white clipping.

[0195] Furthermore, the light source device 11203 may be configured to supply light in a predetermined wavelength range corresponding to special light observation. In special light observation, for example, so-called narrow-band imaging is performed, in which a predetermined tissue such as blood vessels on the surface of the mucosa is imaged with high contrast by irradiating with narrow-band light compared to the irradiation light used in normal observation (i.e., white light), utilizing the wavelength dependence of light absorption in body tissue. Alternatively, fluorescence observation may be performed in special light observation, in which an image is obtained from fluorescence generated by irradiation with excitation light. In fluorescence observation, fluorescence can be obtained by irradiating body tissue with excitation light and observing the fluorescence from the body tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into body tissue and irradiating the body tissue with excitation light corresponding to the fluorescence wavelength of the reagent to obtain a fluorescence image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0196] Figure 28 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in Figure 27.

[0197] The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0198] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and then incident on the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses, including a zoom lens and a focus lens.

[0199] The imaging unit 11402 may consist of one image sensor (a so-called single-chip type) or multiple image sensors (a so-called multi-chip type). If the imaging unit 11402 is configured as a multi-chip type, for example, each image sensor may generate image signals corresponding to RGB, and these may be combined to obtain a color image. Alternatively, the imaging unit 11402 may be configured to have a pair of image sensors for acquiring image signals for the right eye and left eye, respectively, corresponding to 3D (dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical area. In addition, if the imaging unit 11402 is configured as a multi-chip type, multiple lens units 11401 may be provided corresponding to each image sensor.

[0200] Furthermore, the imaging unit 11402 does not necessarily have to be located on the camera head 11102. For example, the imaging unit 11402 may be located inside the lens barrel 11101, directly behind the objective lens.

[0201] The drive unit 11403 is composed of actuators and, under control from the camera head control unit 11405, moves the zoom lens and focus lens of the lens unit 11401 along the optical axis by a predetermined distance. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted as appropriate.

[0202] The communication unit 11404 is composed of communication devices for sending and receiving various types of information with the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0203] Furthermore, the communication unit 11404 receives a control signal from the CCU 11201 to control the drive of the camera head 11102 and supplies it to the camera head control unit 11405. The control signal includes information about imaging conditions, such as information to specify the frame rate of the captured image, information to specify the exposure value at the time of imaging, and / or information to specify the magnification and focus of the captured image.

[0204] The imaging conditions such as frame rate, exposure value, magnification, and focus may be specified by the user as appropriate, or they may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with so-called AE (Auto Exposure), AF (Auto Focus), and AWB (Auto White Balance) functions.

[0205] The camera head control unit 11405 controls the drive of the camera head 11102 based on the control signal received from the CCU 11201 via the communication unit 11404.

[0206] The communication unit 11411 is comprised of a communication device for sending and receiving various types of information with the camera head 11102. The communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400.

[0207] Furthermore, the communication unit 11411 transmits control signals to the camera head 11102 to control the driving of the camera head 11102. Image signals and control signals can be transmitted by telecommunications, optical communications, etc.

[0208] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102.

[0209] The control unit 11413 performs various controls related to imaging the surgical area, etc., by the endoscope 11100, and the display of the images obtained from imaging the surgical area, etc. For example, the control unit 11413 generates a control signal to control the driving of the camera head 11102.

[0210] Furthermore, the control unit 11413 displays the captured image showing the surgical area, etc., on the display device 11202 based on the image signal processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical instruments such as forceps, specific biological sites, bleeding, mist when using the energy treatment device 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When the control unit 11413 displays the captured image on the display device 11202, it may use the recognition results to superimpose various surgical support information onto the image of the surgical area. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can proceed with the surgery reliably.

[0211] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable thereof.

[0212] In the illustrated example, communication was performed via a wired connection using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.

[0213] The above describes an example of an endoscopic surgical system to which the technology described herein may be applied. The technology described herein can be applied to the imaging unit 11402 of the configuration described above. By applying the technology described herein to the imaging unit 11402, the detection accuracy is improved.

[0214] While an endoscopic surgical system has been described here as an example, the technology described herein may also be applied to other systems, such as microsurgical systems.

[0215] (Examples of application to mobile devices) The technology disclosed herein can be applied to a variety of products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile device, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, robots, construction machinery, or agricultural machinery (tractors).

[0216] Figure 29 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0217] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 29, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0218] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0219] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0220] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0221] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0222] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0223] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including vehicle collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0224] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0225] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0226] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 29, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0227] Figure 30 shows an example of the installation position of the imaging unit 12031.

[0228] In Figure 30, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0229] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0230] Figure 30 shows an example of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0231] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0232] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, etc., that drives autonomously without driver operation, can be performed.

[0233] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0234] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0235] The above describes an example of a mobile object control system to which the technology of this disclosure may be applied. The technology of this disclosure can be applied to the imaging unit 12031 of the configuration described above. Specifically, the light detection device according to the above embodiment and its modified example 1 can be applied to the imaging unit 12031. By applying the technology of this disclosure to the imaging unit 12031, high-resolution images with low noise can be obtained, so that high-precision control using the captured images can be performed in the mobile object control system.

[0236] The present disclosure has been described above with reference to the first to fifth embodiments and modifications, as well as application examples and examples of applications. However, the present disclosure is not limited to the above embodiments, and various modifications are possible. The effects described herein are merely illustrative. The effects of the present disclosure are not limited to those described herein. The present disclosure may have effects other than those described herein.

[0237] Furthermore, for example, the present disclosure can take the following configuration. In a photodetector having the following configuration, in a second semiconductor layer laminated on a first semiconductor layer on which sensor pixels that perform photoelectric conversion are formed, one or more contact wirings are connected to a plurality of pixel transistors constituting a readout circuit formed on the second semiconductor layer from one or both of the front (fourth surface) and back (third surface) of the second semiconductor layer, so that through wiring penetrating the second semiconductor layer is unnecessary. Therefore, it is possible to improve the area efficiency of the second semiconductor layer. (1) A photodetector comprising: a first semiconductor layer having opposing first and second surfaces and on which sensor pixels that perform photoelectric conversion are formed; and a second semiconductor layer laminated on the first surface side of the first semiconductor layer and having a third surface facing the first surface and a fourth surface opposite to the third surface, and on which a plurality of pixel transistors constituting a readout circuit that outputs a pixel signal based on the charge output from the sensor pixels are formed, wherein one or more contact wirings are connected to each of the plurality of pixel transistors from one or both of the third surface side and the fourth surface side. (2) The photodetector according to (1), wherein the plurality of pixel transistors have a three-dimensional structure. (3) The photodetector according to (1) or (2), wherein the one or more contact lines are connected to any of the gate electrodes, source regions, and drain regions of the plurality of pixel transistors. (4) The photodetector according to any one of (1) to (3), wherein the one or more contact lines have a first contact line connected to the plurality of pixel transistors from the third surface side of the second semiconductor layer and a second contact line connected to the second semiconductor layer from the fourth surface side. (5) The photodetector according to (4), wherein the plurality of pixel transistors have a fin structure, and the plurality of pixel transistors have an insulating film between the channel region and the first contact line that electrically separates the channel region and the first contact line. (6) The photodetector according to (5), wherein the insulating film is provided on the third surface of the second semiconductor layer.(7) The photodetector according to (5) or (6), wherein the insulating film comprises silicon nitride, silicon oxide, or undoped polysilicon. (8) The photodetector according to any one of (5) to (7), wherein the second semiconductor layer is divided for each of the plurality of pixel transistors, and the first contact wiring is formed self-aligned below the second semiconductor layer including the channel region. (9) The photodetector according to any one of (5) to (8), wherein the gate electrodes of the plurality of pixel transistors extend from the fourth side of the second semiconductor layer through the gate insulating film along the side between the third and fourth surfaces and protrude toward the first semiconductor layer side beyond the third surface. (10) The photodetector according to (8) or (9), wherein the first contact wiring connected to the gate electrodes of the plurality of pixel transistors is electrically connected via the side of the gate electrodes. (11) The photodetector according to any one of (5) to (10), wherein the first contact wiring is formed of the same material as the gate electrodes of the plurality of pixel transistors. (12) The photodetector according to (11), wherein the first contact wiring and the gate electrodes of the plurality of pixel transistors are formed using a metallic material comprising titanium, tantalum, tungsten, molybdenum, and aluminum. (13) The photodetector according to (11) or (12), wherein the diameter of the first contact wiring gradually decreases from the second semiconductor layer toward the first semiconductor layer. (14) The photodetector according to any one of (11) to (13), wherein the gate electrode has a widened portion that extends from the fourth surface side of the second semiconductor layer through a gate insulating film along the side surface between the third and fourth surfaces and extends in the in-plane direction of the second semiconductor layer. (15) The photodetector according to (14), wherein the first contact wiring is connected to the widened portion. (16) The photodetector according to any one of (1) to (15), wherein the plurality of pixel transistors have a gate all-around structure.(17) The photodetector according to any one of (4) to (16), wherein the gate electrodes of the plurality of pixel transistors extend to the third surface, the fourth surface and the side surface between the third surface and the fourth surface of the second semiconductor layer via a gate insulating film, and the first contact wiring is electrically connected to the gate electrodes extending to the third surface side of the second semiconductor layer. (18) The photodetector according to any one of (4) to (17), wherein the first contact wiring connected to either the source region or the drain region of the plurality of pixel transistors is electrically connected to the third surface of the second semiconductor layer, each. (19) The photodetector according to any one of (16) to (18), wherein the length of the gate electrodes between the source region and the drain region of the plurality of pixel transistors surrounding the second semiconductor layer in the thickness direction differs on the third surface side and the fourth surface side of the second semiconductor layer. (20) The photodetector according to any one of (16) to (19), wherein the length of the gate electrode between the source region and the drain region of the plurality of pixel transistors surrounding the second semiconductor layer in the thickness direction is longer on the fourth side of the second semiconductor layer than on the third side. (21) The photodetector according to any one of (1) to (20), wherein the sensor pixel comprises a photoelectric conversion element, a transfer transistor electrically connected to the photoelectric conversion element, and a charge holding unit that temporarily holds the charge output from the photoelectric conversion element via the transfer transistor. (22) The photodetector according to (21), wherein the readout circuit comprises, as the plurality of pixel transistors, a reset transistor that resets the potential of the charge holding unit to a predetermined potential, an amplifying transistor that generates a signal of voltage corresponding to the level of charge held in the charge holding unit as the pixel signal, and a selection transistor that controls the output timing of the pixel signal from the amplifying transistor. (23) The photodetector according to any one of (1) to (22), further comprising a third semiconductor layer having a control circuit for controlling the drive of the readout circuit, wherein the first semiconductor layer, the second semiconductor layer and the third semiconductor layer are stacked in this order.(24) The photodetector according to (23), further comprising a first wiring layer provided on the first surface side of the first semiconductor layer and a second wiring layer provided on the third surface side of the second semiconductor layer, wherein the first wiring layer and the second wiring layer each have pad electrodes on their respective surfaces, and the first semiconductor layer and the second semiconductor layer are electrically connected to each other by bonding of the pad electrodes. (25) The photodetector according to (23) or (24), further comprising a third wiring layer provided on the fourth surface side of the second semiconductor layer and a fourth wiring layer provided on the surface side of the third semiconductor layer facing the second semiconductor layer, wherein the third wiring layer and the fourth wiring layer each have pad electrodes on their respective surfaces, and the second semiconductor layer and the third semiconductor layer are electrically connected to each other by bonding of the pad electrodes. (26) The photodetector according to any one of (1) to (25), wherein the plurality of pixel transistors have a fin structure, and the height of the fins of each of the plurality of pixel transistors differs between the channel region and the source region and the drain region. (27) The photodetector according to (26), wherein the height of the fins in the source region and the drain region is higher than the height of the fins in the channel region. (28) An electronic device comprising a photodetector, the photodetector comprising: a first semiconductor layer having opposing first and second surfaces and on which sensor pixels that perform photoelectric conversion are formed; and a second semiconductor layer stacked on the first surface side of the first semiconductor layer and having a third surface facing the first surface and a fourth surface opposite to the third surface, on which a plurality of pixel transistors constituting a readout circuit that outputs a pixel signal based on the charge output from the sensor pixels are formed, and each of the plurality of pixel transistors is connected to contact wiring from either the third surface side and the fourth surface side or both.

[0238] This application claims priority based on Japanese Patent Application No. 2025-051879, filed with the Japan Patent Office on 26 March 2025, and all contents of that application are incorporated herein by reference.

[0239] Those skilled in the art will understand that various modifications, combinations, subcombinations, and changes can be conceived depending on design requirements and other factors, and that these fall within the scope of the attached claims and their equivalents.

Claims

1. A photodetector comprising: a first semiconductor layer having opposing first and second surfaces and on which sensor pixels for photoelectric conversion are formed; and a second semiconductor layer stacked on the first surface side of the first semiconductor layer and having a third surface facing the first surface and a fourth surface opposite to the third surface, on which a plurality of pixel transistors constituting a readout circuit that outputs a pixel signal based on the charge output from the sensor pixels are formed, wherein one or more contact wirings are connected to each of the plurality of pixel transistors from either the third surface side and the fourth surface side or both.

2. The photodetector according to claim 1, wherein the plurality of pixel transistors have a three-dimensional structure.

3. The photodetector according to claim 1, wherein the one or more contact connections are connected to any of the gate electrodes, source regions, and drain regions of the plurality of pixel transistors.

4. The photodetector according to claim 1, wherein the one or more contact wirings have a first contact wiring connected to the plurality of pixel transistors from the third side of the second semiconductor layer and a second contact wiring connected from the fourth side of the second semiconductor layer.

5. The photodetector according to claim 4, wherein the plurality of pixel transistors have a fin structure, and the plurality of pixel transistors have an insulating film between the channel region and the first contact wiring that electrically isolates the channel region and the first contact wiring.

6. The photodetector according to claim 5, wherein the insulating film is provided on the third surface of the second semiconductor layer.

7. The photodetector according to claim 5, wherein the insulating film comprises silicon nitride, silicon oxide, or undoped polysilicon.

8. The photodetector according to claim 5, wherein the second semiconductor layer is divided for each of the plurality of pixel transistors, and the first contact wiring is formed self-aligned below the second semiconductor layer including the channel region.

9. The photodetector according to claim 5, wherein the gate electrodes of the plurality of pixel transistors extend from the fourth surface side of the second semiconductor layer through a gate insulating film along the side between the third and fourth surfaces, and protrude from the third surface toward the first semiconductor layer.

10. The photodetector according to claim 8, wherein the first contact wiring connected to the gate electrodes of the plurality of pixel transistors is electrically connected via the side surface of the gate electrodes.

11. The photodetector according to claim 5, wherein the first contact wiring is formed of the same material as the gate electrodes of the plurality of pixel transistors.

12. The photodetector according to claim 11, wherein the first contact wiring and the gate electrodes of the plurality of pixel transistors are formed using a metallic material comprising titanium, tantalum, tungsten, molybdenum, and aluminum.

13. The photodetector according to claim 11, wherein the diameter of the first contact wiring gradually decreases from the second semiconductor layer toward the first semiconductor layer.

14. The photodetector according to claim 11, wherein the gate electrode has a widened portion that extends from the fourth surface side of the second semiconductor layer through a gate insulating film along the side surface between the third surface and the fourth surface, and extends in the in-plane direction of the second semiconductor layer.

15. The light detection device according to claim 14, wherein the first contact wiring is connected to the widened portion.

16. The photodetector according to claim 1, wherein the plurality of pixel transistors have a gate-all-around structure.

17. The photodetector according to claim 4, wherein the gate electrodes of the plurality of pixel transistors extend to the third surface, the fourth surface and the side surface between the third surface and the fourth surface of the second semiconductor layer via a gate insulating film, and the first contact wiring is electrically connected to the gate electrodes extending to the third surface side of the second semiconductor layer.

18. The photodetector according to claim 4, wherein the first contact wiring connected to either the source region or the drain region of the plurality of pixel transistors is electrically connected to the third surface of the second semiconductor layer.

19. The photodetector according to claim 16, wherein the length of the gate electrode between the source region and the drain region of the plurality of pixel transistors surrounding the second semiconductor layer in the thickness direction is different on the third side and the fourth side of the second semiconductor layer.

20. The photodetector according to claim 16, wherein the length of the gate electrode between the source region and the drain region of the plurality of pixel transistors surrounding the second semiconductor layer in the thickness direction is longer on the fourth surface side of the second semiconductor layer than on the third surface side.

21. The light detection device according to claim 1, wherein the sensor pixel comprises a photoelectric conversion element, a transfer transistor electrically connected to the photoelectric conversion element, and a charge holding unit that temporarily holds the charge output from the photoelectric conversion element via the transfer transistor.

22. The photodetector according to claim 21, wherein the readout circuit comprises, as the plurality of pixel transistors, a reset transistor for resetting the potential of the charge holding portion to a predetermined potential, an amplification transistor for generating a signal of voltage corresponding to the level of charge held in the charge holding portion as the pixel signal, and a selection transistor for controlling the output timing of the pixel signal from the amplification transistor.

23. The photodetector according to claim 1, further comprising a third semiconductor layer having a control circuit for controlling the drive of the readout circuit, wherein the first semiconductor layer, the second semiconductor layer and the third semiconductor layer are stacked in this order.

24. The photodetector according to claim 23, further comprising a first wiring layer provided on the first surface side of the first semiconductor layer and a second wiring layer provided on the third surface side of the second semiconductor layer, wherein the first wiring layer and the second wiring layer each have pad electrodes on their respective surfaces, and the first semiconductor layer and the second semiconductor layer are electrically connected to each other by bonding of the pad electrodes.

25. The photodetector according to claim 23, further comprising a third wiring layer provided on the fourth surface side of the second semiconductor layer, and a fourth wiring layer provided on the surface side of the third semiconductor layer facing the second semiconductor layer, wherein the third wiring layer and the fourth wiring layer each have pad electrodes on their respective surfaces, and the second semiconductor layer and the third semiconductor layer are electrically connected to each other by bonding of the pad electrodes.

26. The photodetector according to claim 1, wherein the plurality of pixel transistors have a fin structure, and the height of the fin of each of the plurality of pixel transistors differs in the channel region, the source region and the drain region.

27. The photodetector according to claim 26, wherein the height of the fins in the source region and the drain region is greater than the height of the fins in the channel region.

28. An electronic device comprising a light detection device, the light detection device having a first semiconductor layer having opposing first and second surfaces and on which sensor pixels that perform photoelectric conversion are formed, and a second semiconductor layer stacked on the first surface side of the first semiconductor layer and having a third surface facing the first surface and a fourth surface opposite to the third surface, on which a plurality of pixel transistors constituting a readout circuit that outputs a pixel signal based on the charge output from the sensor pixels are formed, and each of the plurality of pixel transistors is connected by contact wiring from either the third surface side and the fourth surface side or both.

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