Photodetection device, semiconductor device, and electronic apparatus

Abstract

A photodetection device according to an embodiment of the present disclosure comprises: a first layer that includes a first semiconductor layer having a first surface and a second surface on the opposite side from the first surface; a second layer that includes a second semiconductor layer having a third surface and a fourth surface on the opposite side from the third surface and is stacked on the first layer such that the first surface and the fourth surface face each other; a photoelectric conversion element that is provided in the first semiconductor layer; a readout circuit that has a first transistor provided on the third surface side of the second semiconductor layer and is capable of outputting a first signal based on electric charge converted by the photoelectric conversion element; a first contact that is provided on the third surface side of the second semiconductor layer; and a second contact that is provided on the fourth surface side of the second semiconductor layer.

Description

Photodetector, semiconductor device, and electronic device

[0001] The present disclosure relates to a photodetector, a semiconductor device, and an electronic device.

[0002] An imaging device configured by bonding a first substrate having sensor pixels, a second substrate having a readout circuit, and a third substrate having a logic circuit has been proposed (Patent Document 1).

[0003] Japanese Unexamined Patent Publication No. 2020-88380

[0004] In an apparatus that detects light, it is desirable to be compatible with miniaturization.

[0005] It is desirable to provide a photodetector suitable for miniaturization.

[0006] A photodetector according to one embodiment of the present disclosure comprises a first layer including a first semiconductor layer having a first surface and a second surface opposite to the first surface, a second layer including a second semiconductor layer having a third surface and a fourth surface opposite to the third surface, and stacked on the first layer such that the first surface and the fourth surface face each other, a photoelectric conversion element provided on the first semiconductor layer, a readout circuit having a first transistor provided on the third surface side of the second semiconductor layer and capable of outputting a first signal based on the charge converted by the photoelectric conversion element, a first contact provided on the third surface side of the second semiconductor layer, and a second contact provided on the fourth surface side of the second semiconductor layer. An electronic device according to one embodiment of the present disclosure comprises an optical system and a photodetector that receives light transmitted through the optical system. The photodetector includes a first layer comprising a first semiconductor layer having a first surface and a second surface opposite to the first surface, a second layer comprising a second semiconductor layer having a third surface and a fourth surface opposite to the third surface, and stacked on the first layer such that the first surface and the fourth surface face each other, a photoelectric conversion element provided on the first semiconductor layer, a readout circuit having a first transistor provided on the third surface side of the second semiconductor layer and capable of outputting a first signal based on the charge converted by the photoelectric conversion element, a first contact provided on the third surface side of the second semiconductor layer, and a second contact provided on the fourth surface side of the second semiconductor layer. A semiconductor device according to one embodiment of the present disclosure includes a first layer comprising a first semiconductor layer having a first surface and a second surface opposite to the first surface, a second layer comprising a second semiconductor layer having a third surface and a fourth surface opposite to the third surface, and stacked on the first layer such that the first surface and the fourth surface face each other, a first active element provided on the first semiconductor layer, a circuit having a first transistor provided on the third surface side of the second semiconductor layer and electrically connectable to the first active element, a first contact provided on the third surface side of the second semiconductor layer, and a second contact provided on the fourth surface side of the second semiconductor layer. The second contact is electrically connected to the first gate electrode of the first transistor. An electronic device according to one embodiment of the present disclosure comprises a semiconductor device.The semiconductor device includes a first layer containing a first semiconductor layer having a first surface and a second surface opposite to the first surface, a second layer containing a second semiconductor layer having a third surface and a fourth surface opposite to the third surface, and stacked on the first layer such that the first surface and the fourth surface face each other, a first active element provided on the first semiconductor layer, a circuit having a first transistor provided on the third surface side of the second semiconductor layer and electrically connectable to the first active element, a first contact provided on the third surface side of the second semiconductor layer, and a second contact provided on the fourth surface side of the second semiconductor layer. The second contact is electrically connected to the first gate electrode of the first transistor.

[0007] Figure 1 is a block diagram showing an example of the schematic configuration of an imaging device, which is an example of a photodetector according to the first embodiment of this disclosure. Figure 2 is a diagram showing an example of a pixel array of an imaging device according to the first embodiment of this disclosure. Figure 3 is a diagram showing an example of the circuit configuration of a pixel in an imaging device according to the first embodiment of this disclosure. Figure 4 is a diagram showing another example of the circuit configuration of a pixel in an imaging device according to the first embodiment of this disclosure. Figure 5 is a diagram showing an example of the cross-sectional configuration of an imaging device according to the first embodiment of this disclosure. Figure 6 is a diagram illustrating an example of the configuration of a pixel transistor in an imaging device according to the first embodiment of this disclosure. Figure 7 is a diagram illustrating an example of the configuration of a pixel transistor in an imaging device according to the first embodiment of this disclosure. Figure 8 is a diagram illustrating an example of the configuration of a pixel transistor in an imaging device according to the first embodiment of this disclosure. Figure 9A is a diagram showing an example of contact arrangement in an imaging device according to the first embodiment of this disclosure. Figure 9B is a diagram showing an example of contact arrangement in an imaging device according to the first embodiment of this disclosure. Figure 10 is a diagram illustrating an example of the configuration of an imaging device according to the first embodiment of this disclosure. Figure 11 is a diagram illustrating an example configuration of an imaging device according to the first embodiment of this disclosure. Figure 12 is a diagram illustrating an example configuration of an imaging device according to the first embodiment of this disclosure. Figure 13 is a diagram illustrating another example configuration of an imaging device according to the first embodiment of this disclosure. Figure 14A is a diagram illustrating another example configuration of an imaging device according to the first embodiment of this disclosure. Figure 14B is a diagram illustrating another example configuration of an imaging device according to the first embodiment of this disclosure. Figure 15A is a diagram illustrating another example configuration of an imaging device according to the first embodiment of this disclosure. Figure 15B is a diagram illustrating another example configuration of an imaging device according to the first embodiment of this disclosure. Figure 16 is a diagram illustrating another example configuration of an imaging device according to the first embodiment of this disclosure. Figure 17A is a diagram illustrating an example of contact arrangement in an imaging device according to the first embodiment of this disclosure. Figure 17B is a diagram illustrating an example of contact arrangement in an imaging device according to the first embodiment of this disclosure. Figure 18 is a diagram illustrating an example of contact configuration in an imaging device according to the first embodiment of this disclosure.Figure 19 is a diagram illustrating an example of the contact configuration in an imaging device according to the first embodiment of this disclosure. Figure 20 is a diagram illustrating an example of the contact configuration in an imaging device according to the first embodiment of this disclosure. Figure 21 is a diagram illustrating an example of the contact arrangement in an imaging device according to the first embodiment of this disclosure. Figure 22 is a diagram illustrating an example of the configuration of an imaging device according to the first embodiment of this disclosure. Figure 23A is a diagram showing an example of the contact arrangement in an imaging device according to the first embodiment of this disclosure. Figure 23B is a diagram showing an example of the contact arrangement in an imaging device according to the first embodiment of this disclosure. Figure 24A is a diagram showing an example of the contact arrangement in an imaging device according to the first embodiment of this disclosure. Figure 24B is a diagram showing an example of the contact arrangement in an imaging device according to the first embodiment of this disclosure. Figure 25A is a diagram showing an example of the contact arrangement in an imaging device according to the first embodiment of this disclosure. Figure 25B is a diagram showing an example of the contact arrangement in an imaging device according to the first embodiment of this disclosure. Figure 26 is a diagram showing an example of the pixel circuit configuration of an imaging device according to a modified example of this disclosure. Figure 27A is a diagram illustrating an example of contact arrangement in an imaging device according to a modified example of the present disclosure. Figure 27B is a diagram illustrating an example of contact arrangement in an imaging device according to a modified example of the present disclosure. Figure 28A is a diagram illustrating an example of contact arrangement in an imaging device according to a modified example of the present disclosure. Figure 28B is a diagram illustrating an example of contact arrangement in an imaging device according to a modified example of the present disclosure. Figure 28C is a diagram illustrating an example of contact arrangement in an imaging device according to a modified example of the present disclosure. Figure 29 is a diagram illustrating an example of contact arrangement in an imaging device according to a modified example of the present disclosure. Figure 30 is a block diagram showing an example of the configuration of an electronic device having an imaging device. Figure 31 is a block diagram showing an example of a schematic configuration of a vehicle control system. Figure 32 is an explanatory diagram showing an example of the installation position of an external information detection unit and an imaging unit. Figure 33 is a diagram showing an example of a schematic configuration of an endoscopic surgery system. Figure 34 is a block diagram showing an example of the functional configuration of a camera head and a CCU.

[0008] The embodiments of this disclosure will be described in detail below with reference to the drawings. The description will be in the following order: 1. First Embodiment 2. Modification 3. Second Embodiment 4. Modification 5. Application Example 6. Application Example

[0009] <1. First Embodiment> Figure 1 is a block diagram showing an example of the schematic configuration of an imaging device, which is an example of a photodetector according to the first embodiment of the present disclosure. Figure 2 is a diagram showing an example of a pixel array of an imaging device according to the first embodiment. A photodetector is a device capable of detecting incident light. An imaging device 1, which is an example of a photodetector, has a plurality of pixels P including a photoelectric conversion unit, and is configured to generate a signal by photoelectric conversion of incident light.

[0010] The imaging device 1 is constructed using a substrate (for example, a semiconductor substrate such as a Si (silicon) substrate or an SOI (Silicon On Insulator) substrate) on which each pixel P is provided with a photoelectric conversion unit. The imaging device 1 has a structure (i.e., a laminated structure) formed by stacking multiple substrates (or semiconductor layers). The imaging device 1 receives light transmitted through an optical system (not shown) and generates a signal.

[0011] The imaging device 1 has a region (pixel array 100) where multiple pixels P are provided, as shown in the example in Figure 1 or Figure 2. The imaging device 1 has, for example, a pixel array 100 in which multiple pixels P are arranged in a matrix in two dimensions as the imaging area. The pixel array 100 is a pixel section where multiple pixels P are arranged, and can also be called a light-receiving region.

[0012] The photoelectric conversion unit of pixel P is, for example, a photodiode (PD) and is configured to convert light into photoelectric energy. Each photoelectric conversion unit of pixel P is a photoelectric conversion element and can also be called a photoelectric conversion region. The imaging device 1 captures incident light (image light) from the subject to be measured via an optical system that includes, for example, an optical lens and an aperture (diaphragm).

[0013] The imaging device 1 is configured to capture an image of a subject formed by an optical system, for example. The imaging device 1 generates a pixel signal by photoelectric conversion of received light (visible light, infrared light, etc.). The imaging device 1, being a light detection device, is a device that can receive light and generate a signal, and can also be called a light receiving device.

[0014] The imaging device 1 (light detection device) is configured as an image sensor, for example. For instance, the imaging device 1 may be a CMOS (Complementary Metal Oxide Semiconductor) image sensor, a CCD (Charge Coupled Device) image sensor, etc. The imaging device 1 can be used in various electronic devices such as digital still cameras, video cameras, and mobile phones.

[0015] As shown in Figure 2, the direction of incidence of light from the subject being measured is defined as the Z-axis direction, the left-right direction perpendicular to the Z-axis direction is defined as the X-axis direction, and the up-down direction perpendicular to both the Z-axis and X-axis directions is defined as the Y-axis direction. In subsequent figures, directions may also be indicated based on the direction of the arrows in Figure 2.

[0016] [Outline Configuration of the Imaging Device] The imaging device 1, as shown in the example in Figure 1, includes a pixel array 100, a pixel control unit 110, a signal processing unit 112, a control unit 113, and a processing unit 114. The imaging device 1 also includes, for example, a plurality of control lines Lc and a plurality of signal lines VSL. The number and arrangement of pixels P provided in the pixel array 100 (i.e., the pixel section) can be changed as appropriate.

[0017] A control line Lc is a signal line capable of transmitting signals to control a pixel P, and is connected to the pixel control unit 110 and the pixels P of the pixel array 100. The control line Lc is configured to transmit, for example, a control signal for reading signals from the pixels P. In the example shown in Figure 1, multiple control lines Lc are wired to each pixel row of the pixel array 100, which consists of multiple pixels P arranged horizontally (in the row direction).

[0018] The multiple control lines Lc for each pixel row of the imaging device 1 include, for example, wiring that transmits signals to control the transfer transistor, wiring that transmits signals to control the selection transistor, wiring that transmits signals to control the reset transistor, wiring that transmits signals to control the switching transistor, etc. The control lines Lc can also be called drive lines (or pixel drive lines) that transmit signals to drive the pixels P.

[0019] The signal line VSL is a signal line capable of transmitting signals from pixels P, and is connected to the pixels P of the pixel array 100 and the signal processing unit 112. The signal line VSL is electrically connected to the pixels P and is configured to transmit signals output from the pixels P. For example, the signal line VSL is wired to each pixel row of the pixel array 100, which is composed of multiple pixels P arranged vertically (in the column direction).

[0020] In the pixel array 100 of the imaging device 1, multiple signal lines VSL may be provided for a single pixel row. For example, the imaging device 1 has multiple signal lines VSL for each pixel row containing multiple pixels P. The number and arrangement of control lines Lc and signal lines VSL provided in the imaging device 1 are not limited to the illustrated example and can be changed as appropriate.

[0021] The pixel control unit 110 is configured to control each pixel P. The pixel control unit 110 is a control circuit (pixel control circuit) and is composed of multiple circuits, such as a buffer, a shift register, and an address decoder. The pixel control unit 110 generates a signal for controlling the pixels P and outputs it to each pixel P of the pixel array 100 via a control line Lc. The pixel control unit 110 is controlled, for example, by the control unit 113, and controls each pixel P of the pixel array 100.

[0022] The pixel control unit 110 generates signals for controlling pixels P (signals to control the transfer transistor of pixel P, signals to control the selection transistor, signals to control the reset transistor, signals to control the switching transistor, etc.) and supplies them to each pixel P via a control line Lc. The pixel control unit 110 can perform control to read out pixel signals from each pixel P. The pixel control unit 110 can also be described as a pixel drive unit (pixel drive circuit) configured to drive each pixel P.

[0023] The signal processing unit 112 is configured to perform signal processing on the input pixel signal. The signal processing unit 112 is a signal processing circuit and includes, for example, a load circuit, an AD (Analog Digital) conversion circuit, a horizontal selection switch, etc. The load circuit is, for example, composed of a current source capable of supplying current to the amplification transistor of the pixel P, and together with the amplification transistor of the pixel P, it forms a source follower circuit.

[0024] The load circuit and AD conversion circuit of the signal processing unit 112 are provided, for example, for each of the multiple signal lines VSL. The signal processing unit 112 may also have an amplification circuit configured to amplify the signal read from the pixel P via the signal line VSL. As an example, a load circuit, an amplification circuit, and an AD conversion circuit are provided for each pixel row of the pixel array 100.

[0025] The signals output from each pixel P selected and scanned by the pixel control unit 110 are input to the signal processing unit 112 via the signal line VSL. The signal processing unit 112 performs signal processing such as AD conversion and CDS (Correlated Double Sampling) of the pixel P signals. The signals from each pixel P transmitted via each signal line VSL are processed by the signal processing unit 112 and output to the processing unit 114.

[0026] The processing unit 114 is configured to acquire signals from each pixel P and perform signal processing. The processing unit 114 is a processing circuit and is composed of, for example, circuits that perform various signal processing on the input pixel signals. The processing unit 114 (processing circuit) is composed of, for example, an arithmetic circuit, a memory circuit, an I / F (interface) circuit, etc.

[0027] The processing unit 114 is configured to perform various signal processing operations, such as noise reduction, interpolation, and gradation correction. For example, the processing unit 114 can perform signal processing on the pixel signal input from the signal processing unit 112 and output the processed pixel signal. The processing unit 114 may also include a processor and memory.

[0028] The control unit 113 is configured to control each part of the imaging device 1. The control unit 113 is a control circuit and includes, for example, a PLL (Phase Locked Loop), a timing generator, a DAC (Digital to Analog Converter), etc. As an example, the control unit 113 can receive a clock and data commanding the operating mode from an external source, and can also output data such as internal information of the imaging device 1.

[0029] The control unit 113 includes, for example, a timing generator configured to generate various timing signals. Based on the various timing signals (pulse signals, clock signals, etc.) generated by the timing generator, the control unit 113 performs drive control for the pixel control unit 110 and the signal processing unit 112, etc. Note that the control unit 113 and the processing unit 114 may be configured as an integrated unit.

[0030] The pixel control unit 110, signal processing unit 112, control unit 113, processing unit 114, etc., described above may be provided on a single substrate or on multiple substrates. The pixel control unit 110, signal processing unit 112, control unit 113, processing unit 114, etc., of the imaging device 1 may be provided, for example, as peripheral circuits in the peripheral area of ​​the pixel array 100. Note that some or all of the signal processing unit 112, control unit 113, and processing unit 114 may be configured as a single unit.

[0031] [Pixel Configuration] Figure 3 shows an example of the circuit configuration of a pixel in an imaging device according to the first embodiment. A pixel P includes, for example, a photoelectric conversion unit 11, a transistor TG, a floating diffusion FD, and a circuit 15 (also referred to as a readout circuit 15). The photoelectric conversion unit 11 (photoelectric conversion element) is configured to receive light and generate a signal.

[0032] The circuit 15 (readout circuit 15) is configured to output a signal based on the photoelectrically converted charge. The readout circuit 15 has, for example, multiple transistors (referred to as pixel transistors) and is provided for each pixel P or for multiple pixels P. The readout circuit 15 can also be called a pixel circuit or a pixel readout circuit.

[0033] The photoelectric conversion unit 11 is configured to generate electric charge through photoelectric conversion. In the example shown in Figure 3, the photoelectric conversion unit 11 is a photodiode (PD) that converts incident light into electric charge. The photoelectric conversion unit 11 performs photoelectric conversion to generate an electric charge corresponding to the amount of light received. The photoelectric conversion unit 11 is a photoelectric conversion element and can also be called a light receiving element.

[0034] The transistor TG is configured to transfer the charge photoelectrically converted in the photoelectric conversion unit 11 to the floating diffusion FD. The transistor TG is a transfer transistor. The transistor TG is controlled by the signal STG to electrically connect or disconnect the photoelectric conversion unit 11 and the floating diffusion FD. The transistor TG (i.e., the transfer transistor) can transfer the charge converted and stored in the photoelectric conversion unit 11 to the floating diffusion FD.

[0035] The floating diffusion FD is a storage unit and is configured to store the transferred charge. The floating diffusion FD can store the charge photoelectrically converted by the photoelectric conversion unit 11. The floating diffusion FD stores the transferred charge and converts it into a voltage corresponding to the capacitance of the floating diffusion FD. The floating diffusion FD can also be described as a storage unit capable of holding charge.

[0036] The readout circuit 15 is configured to read out pixel signals based on the charge photoelectrically converted by the photoelectric conversion unit 11. The readout circuit 15 includes, as an example, a transistor AMP, a transistor SEL, and a transistor RST. The readout circuit 15 may also include a floating diffusion FD. The readout circuit 15 may also include a transistor TG.

[0037] The transistor AMP is configured to generate and output a signal based on the charge stored in the floating diffusion FD. The transistor AMP is an amplifying transistor. The transistor AMP (i.e., the amplifying transistor) can generate and output a signal based on the charge converted by the photoelectric conversion unit 11.

[0038] The gate of the transistor AMP is electrically connected to the floating diffusion diode (FD), and the voltage converted by the floating diffusion diode is input to it. The drain of the transistor AMP is connected to a power line that supplies, for example, the power supply voltage (the power supply voltage VDD in the example shown in Figure 3).

[0039] The source of the transistor AMP is connected to the signal line VSL, for example, via the transistor SEL. The transistor AMP is configured to generate a signal based on the charge stored in the floating diffusion FD, i.e., a signal based on the voltage of the floating diffusion FD, and output it to the signal line VSL.

[0040] The transistor SEL is configured to control the output of the pixel signal. The transistor SEL is a selection transistor. The transistor SEL is electrically connected in series with the transistor AMP, as shown in the example in Figure 3. The transistor SEL is controlled by the signal SSEL and is configured to output the signal from the transistor AMP to the signal line VSL. The transistor SEL (i.e., the selection transistor) can control the output timing of the pixel signal.

[0041] The transistor SEL is configured to output a signal based on the charge converted by the photoelectric conversion unit 11. The transistor SEL can output the pixel signal of pixel P to the signal line VSL. The transistor SEL may also be electrically connected in series between the power line to which the power supply voltage (power supply voltage VDD in Figure 3) is supplied and the transistor AMP. The transistor SEL may be omitted if necessary.

[0042] The transistor RST is configured to reset the voltage of the floating diffusion FD. The transistor RST is a reset transistor. The transistor RST (i.e., the reset transistor) is electrically connected to a power line to which a power supply voltage (power supply voltage VDD in the example shown in Figure 3) is supplied, and is configured to perform a reset of the charge of the pixel P.

[0043] The reset transistor RST is controlled by the signal SRST, can reset the charge accumulated in the floating diffusion FD and reset the voltage of the floating diffusion FD. The transistor RST electrically connects a power supply line to the floating diffusion FD, and discharges the charge accumulated in the floating diffusion FD. Note that the transistor RST can reset the charge accumulated in the photoelectric conversion unit 11 via the transistor TG.

[0044] The readout circuit 15 may be configured to be capable of changing the conversion gain (i.e., conversion efficiency) when converting charge to voltage. For example, the readout circuit 15 includes a transistor (switching transistor) used for setting the conversion gain. As one example, the switching transistor is electrically connected between the floating diffusion FD and the transistor RST.

[0045] In the readout circuit 15, when the switching transistor is turned on, the capacitance added to the floating diffusion FD of the pixel P increases, and the conversion gain for converting charge into voltage is switched. The switching transistor switches the capacitance connected to the gate of the transistor AMP, and can change the conversion gain (conversion efficiency). Note that the switching transistor may be electrically connected in series to the transistor RST, or may be electrically connected in parallel to the transistor RST.

[0046] The above-mentioned transistor TG (transfer transistor), transistor AMP (amplification transistor), transistor SEL (selection transistor), transistor RST (reset transistor), and switching transistor are each, for example, a MOS transistor (MOSFET) having gate, source, and drain terminals.

[0047] In the example shown in FIG. 3, the transistor TG, the transistor AMP, the transistor SEL, and the transistor RST are each configured by an NMOS transistor. Note that the transistors of the pixel P may be configured by PMOS transistors as needed.

[0048] A pixel control unit 110 (see FIG. 1) of the imaging apparatus 1 supplies a control signal to the gate of a transistor TG, a transistor SEL, a transistor RST, a switching transistor, or the like of each pixel P via the above-described control line Lc, to turn the transistor into an on state (conducting state) or an off state (non-conducting state).

[0049] As an example, the plurality of control lines Lc for each pixel row of the imaging apparatus 1 include a wiring for transmitting a signal STG that controls the transistor TG, a wiring for transmitting a signal SSEL that controls the transistor SEL, a wiring for transmitting a signal SRST that controls the transistor RST, a wiring for transmitting a signal that controls the switching transistor, and the like.

[0050] The transistor TG, the transistor SEL, the transistor RST, the switching transistor, and the like are on / off-controlled by the pixel control unit 110. The pixel control unit 110 causes a pixel signal from each pixel P to be output to the signal line VSL by controlling the readout circuit 15 of each pixel P. The pixel control unit 110 can perform control to read out the pixel signal of each pixel P to the signal line VSL.

[0051] FIG. 4 is a diagram showing another example of the circuit configuration of pixels of the imaging apparatus according to the first embodiment. The imaging apparatus 1 may have a configuration in which a plurality of pixels P share one readout circuit 15. The readout circuit 15 is provided for the plurality of pixels P. For example, in the imaging apparatus 1, the readout circuit 15 is arranged for each of the plurality of pixels P, and one readout circuit 15 is shared by the plurality of pixels P.

[0052] As an example, as shown in FIG. 4, the readout circuit 15 is arranged for every four pixels P (referred to as pixel Pa, pixel Pb, pixel Pc, and pixel Pd). The pixel Pa, the pixel Pb, the pixel Pc, and the pixel Pd share one readout circuit 15. For example, 2×2 pixels formed by adjacent pixels Pa to Pd share one readout circuit 15.

[0053] The imaging device 1 can read out the pixel signal of each 2x2 pixel by operating the readout circuit 15 in a time-division manner. The imaging device 1 can also read out a pixel signal which is the sum of the signals of each 2x2 pixel. For example, the imaging device 1 can read out a pixel signal corresponding to the sum of the charges obtained by photoelectric conversion in each of the 2x2 pixels.

[0054] The photoelectric conversion unit 11 (in the example shown in Figure 4, the photodiode PD of pixel Pa to the photodiode PD of pixel Pd) performs photoelectric conversion to generate charge according to the amount of light received. The transistors TG (in Figure 4, the transistor TG of pixel Pa to the transistor TG of pixel Pd) are configured to transfer the charge converted photoelectrically by the photoelectric conversion unit 11 to the floating diffusion FD.

[0055] In the example shown in Figure 4, the transistors TG of pixels Pa to Pd are controlled on and off by different signals. The transistor TG of pixel Pa is controlled by signal STG1, and the transistor TG of pixel Pb is controlled by signal STG2. The transistor TG of pixel Pc is controlled by signal STG3, and the transistor TG of pixel Pd is controlled by signal STG4.

[0056] The readout circuit 15 (i.e., the pixel readout circuit) may include switching transistors, capacitive elements, etc. The readout circuit 15 may include a floating diffusion FD and may include transistors TG from pixel Pa to pixel Pd.

[0057] The imaging device 1 may have a configuration in which five or more pixels P, for example eight pixels P, share one readout circuit 15. For example, in the imaging device 1, a readout circuit 15 is provided for every eight pixels P, and the eight pixels P share one readout circuit 15. Alternatively, 2x4 pixels may share one readout circuit 15.

[0058] [Configuration of the Imaging Device] Figure 5 is a diagram showing an example of the cross-sectional configuration of an imaging device according to the first embodiment. The imaging device 1 has, for example, a layer 201, a layer 202, and a layer 203, as shown in the example in Figure 5. The imaging device 1 has a configuration in which layer 201 as the first layer (first layer), layer 202 as the second layer (second layer), and layer 203 as the third layer (third layer) are stacked in the Z-axis direction.

[0059] In the example shown in Figure 5, layer 201 has a semiconductor layer 101 and a wiring layer 111. Layer 202 has a semiconductor layer 102, a wiring layer 121 and a wiring layer 122. Layer 203 has a semiconductor layer 103 and a wiring layer 131. From the side where light is incident, the semiconductor layer 101, wiring layer 111, wiring layer 122, semiconductor layer 102, wiring layer 121, wiring layer 131, and semiconductor layer 103 are provided.

[0060] The semiconductor layers 101, 102, and 103 are composed of semiconductor substrates such as Si substrates and SOI substrates. The semiconductor layers 101, 102, and 103 may also be composed of SiGe (silicon germanium) substrates, SiC (silicon carbide) substrates, or may be formed using other semiconductor materials.

[0061] The semiconductor layer 101 and the wiring layer 111 together can be referred to as the first substrate (or first circuit layer). The semiconductor layer 102, the wiring layer 121, and the wiring layer 122 together can be referred to as the second substrate (or second circuit layer). Furthermore, the semiconductor layer 103 and the wiring layer 131 together can be referred to as the third substrate (or third circuit layer).

[0062] As shown in Figure 5, the semiconductor layer 101 of layer 201 has opposing surfaces 11S1 and 11S2. Surface 11S2 is the surface opposite to surface 11S1. Surface 11S2 of the semiconductor layer 101 is, for example, a light-receiving surface (i.e., a light-incident surface). Surface 11S1 of the semiconductor layer 101 is an element-forming surface on which elements such as transistors and capacitive elements are formed. Surface 11S1 of the semiconductor layer 101 may be provided with a thermoplastic film, a gate insulating film (e.g., a gate oxide film), etc.

[0063] Each pixel P is provided in the semiconductor layer 101. The photoelectric conversion unit 11 is provided between surfaces 11S1 and 11S2 of the semiconductor layer 101. For example, multiple photoelectric conversion units 11 are embedded in the semiconductor layer 101. The photoelectric conversion unit 11 is a photoelectric conversion element, and can also be called a photoelectric conversion region.

[0064] The semiconductor layer 102 of layer 202 has opposing surfaces 12S1 and 12S2. Surface 12S2 is the surface opposite to surface 12S1. Similarly, the semiconductor layer 103 of layer 203 has opposing surfaces 13S1 and 13S2. Surface 13S2 is the surface opposite to surface 13S1. Surfaces 12S1 and 13S1 are, for example, element formation surfaces on which elements such as transistors are formed.

[0065] On the surface 12S1 of semiconductor layer 102 and the surface 13S1 of semiconductor layer 103 in the imaging device 1, a gate electrode, a gate insulating film, etc., are provided, respectively. The element formation surfaces of semiconductor layer 101, semiconductor layer 102, and semiconductor layer 103 are surfaces on which various circuit elements are provided, and can also be called circuit surfaces.

[0066] On the surface 11S1 side of the semiconductor layer 101, for example, the transistor TG and floating diffusion FD of the pixel P described above are provided. The floating diffusion FD is composed of, for example, an n-type semiconductor region. On the surface 12S1 side of the semiconductor layer 102, at least some of the transistors of the readout circuit 15 (pixel transistors such as transistor AMP, transistor SEL, or transistor RST) are provided.

[0067] A wiring layer 111 is provided on the surface 11S1 side of the semiconductor layer 101. A wiring layer 121 is provided on the surface 12S1 side of the semiconductor layer 102, and a wiring layer 122 is provided on the surface 12S2 side of the semiconductor layer 102. In addition, a wiring layer 131 is provided on the surface 13S1 side of the semiconductor layer 103. Each of the wiring layers 111, 121, 122, and 131 includes, for example, a conductive film and an insulating film, and has a plurality of wirings and a plurality of vias.

[0068] Each of the wiring layers 111, 121, 122, and 131 has an insulating film as an interlayer insulating film, multiple wirings, and vias, etc. As an example, each of the wiring layers 111, 121, and 131 is configured as a multilayer wiring layer having a structure in which multiple wirings are stacked, and includes two or more layers, or three or more layers of wiring. Note that the wiring layer 122 may also be configured to include two or more layers of wiring.

[0069] Each of the wirings in the wiring layers 111, 121, 122, and 131 may be formed using a metallic material such as aluminum (Al), copper (Cu), or tungsten (W), or may be constructed using polysilicon (Poly-Si) or other conductive materials. The interlayer insulating film may be formed using silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or other insulating materials.

[0070] In the example shown in Figure 5, the wiring layer 111 has multiple electrodes 91, and the wiring layer 122 has multiple electrodes 92. Furthermore, the wiring layer 121 has multiple electrodes 93, and the wiring layer 131 has multiple electrodes 94. Electrodes 91, 92, 93, and 94 are, for example, electrodes formed using copper (Cu).

[0071] Electrodes 91, 92, 93, and 94 are electrodes used for joining metal electrodes and are provided as joining electrodes. Note that electrodes 91, 92, 93, and 94, as joining electrodes, may be made of metal materials other than copper (Cu), such as nickel (Ni), cobalt (Co), gold (Au), tin (Sn), etc., or may be made of other materials.

[0072] As an example, layers 201 and 202 are bonded together by a bond between metal electrodes (electrodes 91 and 92) made of Cu, i.e., a Cu-Cu bond. In the imaging device 1, the circuit provided in layer 201 and the circuit provided in layer 202 are electrically connected via electrodes 91 and 92.

[0073] In the example shown in Figure 5, layers 201 and 202 are stacked so that surfaces 11S1 and 12S2 face each other by bonding between electrodes. That is, layers 201 and 202 are bonded so that the surface of semiconductor layer 101 and the back surface of semiconductor layer 102 face each other. Layers 201 and 202 are bonded face-to-back (FtoB).

[0074] Furthermore, for example, layers 202 and 203 are bonded together by a junction between electrodes 93 and 94, which are made of Cu, i.e., a Cu-Cu junction. In the imaging device 1, the circuit provided in layer 202 and the circuit provided in layer 203 are electrically connected via electrodes 93 and 94.

[0075] Layers 202 and 203 are stacked, for example, by bonding between electrodes, such that surfaces 12S1 and 13S1 face each other. That is, layers 202 and 203 are bonded so that the surface of semiconductor layer 102 and the surface of semiconductor layer 103 face each other. Layers 202 and 203 are bonded face-to-face (FtoF).

[0076] At least some of the above-mentioned pixel control unit 110, signal processing unit 112, control unit 113, and processing unit 114 (see Figure 1) are provided in the semiconductor layer 103 and the wiring layer 131. For example, the signal processing unit 112 (signal processing circuit) including an AD conversion circuit is provided in layer 203 which includes the semiconductor layer 103. At least one of the control unit 113 and processing unit 114 may be provided in layer 203. The pixel control unit 110 may also be provided in layer 201 or layer 202.

[0077] A lens 16 and a filter 17 are provided on the surface 11S2 side of the semiconductor layer 101. The lens 16 and filter 17 are stacked on the semiconductor layer 101 in the thickness direction (i.e., the Z-axis direction) perpendicular to the surface 11S2 of the semiconductor layer 101. The lens 16 and the filter 17 are provided on the side into which light from an optical system such as an imaging lens is incident, and the wiring layer 111 is provided on the side opposite to the side into which the light is incident.

[0078] The lens 16 is an optical component that focuses light and is also called an on-chip lens. The lens 16 (lens portion) is, for example, provided above the photoelectric conversion unit 11 for each pixel P or for each group of pixels P. The lens 16 is made of, for example, silicon oxide, silicon nitride, or silicon oxynitride. The lens 16 may also be formed using other light-transmitting materials.

[0079] Light from the subject being measured enters the lens 16, for example, through the optical system. The lens 16 guides the incident light towards the photoelectric conversion unit 11 of the pixel P. The photoelectric conversion unit 11 of the pixel P converts the incident light via the lens 16 and filter 17 into photoelectric energy. The photoelectric conversion unit 11 absorbs the incident light and generates an electric charge.

[0080] The filter 17 is configured to selectively transmit light in a specific wavelength range from the incident light. The filter 17 is, for example, a primary color system (RGB) color filter and is provided above the photoelectric conversion unit 11 for each pixel P or for each set of pixels P. As an example, the filter 17 is formed between the lens 16 and the semiconductor layer 101.

[0081] The filter 17 may be a complementary color filter (CMY), an infrared light-transmitting filter, or the like. The imaging device 1 may omit the filter 17 if necessary. The filter 17 may not be provided for some or all of the pixels P in the imaging device 1. For example, the filter 17 may not be provided for pixels P that receive white (W) light and perform photoelectric conversion.

[0082] Furthermore, the imaging device 1 has a separation region 18. The separation region 18 is a separation region provided between a plurality of adjacent pixels P (or photoelectric conversion unit 11). At least a portion of the separation region 18 is provided in the semiconductor layer 101 at the boundary between adjacent pixels P. The separation region 18 is constructed, for example, using a trench (groove) and is provided around the pixels P (or photoelectric conversion unit 11). The separation region 18 may also be provided so as to penetrate the semiconductor layer 101.

[0083] The isolation region 18 is formed, for example, in the semiconductor layer 101 between a plurality of adjacent pixels P, separating the pixels P (or photoelectric conversion units 11). As an example, the isolation region 18 is provided so as to surround all four sides of the photoelectric conversion unit 11 in a plan view (i.e., when viewed in the XY plane). The isolation region 18 may be formed in a grid pattern in the semiconductor layer 101 so as to surround each photoelectric conversion unit 11 of each pixel P.

[0084] The isolation region 18 (isolation part) may, for example, have an FTI (Full Trench Isolation) structure and be formed to extend to the surface 11S2 of the semiconductor layer 101. The isolation region 18 may also be provided from the surface 11S1 of the semiconductor layer 101 to the space between the surfaces 11S1 and 11S2 of the semiconductor layer 101. The isolation region 18 can also be called an inter-pixel isolation part or an inter-pixel isolation wall.

[0085] An insulating film, such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film, is provided in the trench of the separation region 18. The trench of the separation region 18 may also be filled with an insulating material, such as polysilicon, a metallic material, or another material.

[0086] The separation region 18 may be formed using a material having a low refractive index, such as silicon oxide or silicon oxynitride. A void (cavity) may be provided within the separation region 18. The separation region 18 may be composed of a semiconductor region (n-type or p-type semiconductor region) formed by ion implantation or solid-phase diffusion.

[0087] Each pixel P of the imaging device 1 has a plurality of transistors 30 (also referred to as pixel transistors 30). The transistors 30 (pixel transistors 30) are provided on the semiconductor layer 102 of layer 202, as shown in the example in Figure 5. The pixel transistor 30 has, for example, a gate electrode 31 and a gate insulating film 35 that are provided so as to sandwich a part (part P1) of the semiconductor layer 102.

[0088] The portion P1 of the semiconductor layer 102 is a channel-forming region (channel region). The pixel transistor 30 has a portion P1, which is part of the semiconductor layer 102, as the channel region of the pixel transistor 30. The pixel transistor 30 can be configured as a Fin-type transistor.

[0089] The pixel transistor 30 is, for example, the transistor of the readout circuit 15 described above using Figures 3 and 4. The pixel transistor 30 is used as an AMP (amplifying transistor), a SEL (selection transistor), a RST (reset transistor), or a switching transistor, etc.

[0090] Each of the gate electrode 31 and the gate insulating film 35 is provided, for example, up to the surface 12S2 side of the semiconductor layer 102. Each of the gate electrode 31 and the gate insulating film 35 is provided, for example, by carving into the semiconductor layer 102. A portion of each of the gate electrode 31 and the gate insulating film 35 is arranged, for example, to be embedded in the semiconductor layer 102.

[0091] The gate electrode 31 is constructed, for example, using polysilicon (Poly-Si). The gate electrode 31 may also be constructed using a metallic material or a metallic compound. The gate electrode 31 may be constructed from tungsten (W), tantalum nitride (TaN), titanium nitride (TiN), etc., or may be formed using other materials.

[0092] The gate insulating film 35 is composed of, for example, a single layer made of one of silicon oxide, silicon oxynitride, hafnium oxide (HfO), etc., or a multilayer film made of two or more of these. The gate insulating film 35 may also be formed using a high dielectric constant material having a dielectric constant higher than that of silicon oxide, such as a hafnium-based insulating film.

[0093] Figures 6 and 7 are diagrams illustrating an example of the configuration of pixel transistors in an imaging device according to the first embodiment. The example shown in Figures 6 and 7 shows an example of the configuration of two pixel transistors 30 (pixel transistor 30a, pixel transistor 30b). The pixel P readout circuit 15 has, for example, a plurality of pixel transistors 30, including pixel transistors 30a and 30b.

[0094] The pixel transistor 30a has a gate electrode 31 (referred to as gate electrode 31a), a gate insulating film 35 (referred to as gate insulating film 35a), a semiconductor region 41, and a semiconductor region 42. The pixel transistor 30a also has a portion P1 of the semiconductor layer 102 (the region shown by the dashed line in Figure 7, and referred to as portion P1a).

[0095] The pixel transistor 30b has a gate electrode 31 (referred to as gate electrode 31b), a gate insulating film 35 (referred to as gate insulating film 35b), a semiconductor region 42, and a semiconductor region 43. The pixel transistor 30b also has another portion P1 of the semiconductor layer 102 (the region shown by the dashed line in Figure 7, and referred to as portion P1b).

[0096] A portion P1a (shown by a dashed line in Figure 7), which is part of the semiconductor layer 102, and semiconductor region 41 (or semiconductor region 42) have different conductivity types. Furthermore, another portion P1b (shown by a dashed line in Figure 7), which is part of the semiconductor layer 102, and semiconductor region 42 (or semiconductor region 43) have different conductivity types.

[0097] Pixel transistor 30a has a portion P1a, which is part of the semiconductor layer 102, as its channel region. Similarly, pixel transistor 30b has a portion P1b, which is part of the semiconductor layer 102, as its channel region. Semiconductor region 41 and semiconductor region 42 are the source region and drain region of pixel transistor 30a.

[0098] One of the semiconductor regions 41 and 42 is the source region of the pixel transistor 30a. The other of the semiconductor regions 41 and 42 is the drain region of the pixel transistor 30a. In the example shown in Figure 6 or Figure 7, the semiconductor region 42 is also one of the source and drain regions of the pixel transistor 30b.

[0099] Semiconductor region 42 and semiconductor region 43 are the source region and drain region of the pixel transistor 30b. One of semiconductor region 42 and semiconductor region 43 is the source region of the pixel transistor 30b. The other of semiconductor region 42 and semiconductor region 43 is the drain region of the pixel transistor 30b.

[0100] The semiconductor regions 41, 42, and 43 are each regions formed using impurities, for example, n-type semiconductor regions. The semiconductor regions 41, 42, and 43 are formed, for example, by doping (adding) n-type impurities to the regions of the semiconductor layer 102. The semiconductor regions 41, 42, and 43 are each n-type diffusion regions, and can also be called n-type conductive regions.

[0101] At least one of the semiconductor regions 41 and 42, which serve as the source region and drain region, may be provided from surface 12S1 to surface 12S2 of the semiconductor layer 102. Also, at least one of the semiconductor regions 42 and 43, which serve as the source region and drain region, may be provided from surface 12S1 to surface 12S2 of the semiconductor layer 102.

[0102] The portion P1a and portion P1b of the semiconductor layer 102 are, for example, p-type semiconductor regions. Each of the portions P1a and P1b of the semiconductor layer 102 is provided, for example, as part of a well (for example, a p-type well (p-well)) formed in the semiconductor layer 102.

[0103] A gate electrode 31a and a gate insulating film 35a are provided around portion P1a of the semiconductor layer 102. Semiconductor regions 41 and 42 are arranged around the gate electrode 31a. A gate electrode 31b and a gate insulating film 35b are provided around portion P1b of the semiconductor layer 102. Semiconductor regions 42 and 43 are arranged around the gate electrode 31b.

[0104] The pixel transistor 30a has, for example, a gate electrode 31a and a gate insulating film 35a provided on the semiconductor layer 102 from the surface 12S1 side, sandwiching a part of the semiconductor layer 102 (i.e., portion P1a). The pixel transistor 30b has a gate electrode 31b and a gate insulating film 35b provided on the semiconductor layer 102 from the surface 12S1 side, sandwiching another part of the semiconductor layer 102 (i.e., portion P1b).

[0105] The gate electrode 31a of the pixel transistor 30a is provided, for example, to sandwich a portion P1a of the semiconductor layer 102, which is the channel region of the pixel transistor 30a, via a gate insulating film 35a. The pixel transistor 30a is configured, for example, as a Fin-type transistor. The portion P1a of the semiconductor layer 102 has a fin shape and can also be called a fin portion.

[0106] The gate insulating film 35a is, for example, a gate oxide film and is provided between the channel region P1a and the gate electrode 31a. The gate insulating film 35a is provided along the portion P1a of the semiconductor layer 102. The gate electrode 31a is, as an example, positioned to cover the portion P1a of the semiconductor layer 102 via the gate insulating film 35a.

[0107] The gate electrode 31b of the pixel transistor 30b is provided, for example, to sandwich a portion P1b of the semiconductor layer 102, which is the channel region of the pixel transistor 30b, via a gate insulating film 35b. The pixel transistor 30b is configured, for example, as a Fin-type transistor. The portion P1b of the semiconductor layer 102 has a fin shape and can also be called a fin portion.

[0108] The gate insulating film 35b is, for example, a gate oxide film and is provided between the channel region P1b and the gate electrode 31b. The gate insulating film 35b is provided along the portion P1b of the semiconductor layer 102. The gate electrode 31b may, as an example, be positioned to cover the portion P1b of the semiconductor layer 102 via the gate insulating film 35b.

[0109] The configuration of the pixel transistor 30 is not limited to the illustrated example and can be changed as appropriate. For example, the number and shape of the fins on the pixel transistor 30 can be changed as appropriate. The pixel transistor 30 may also be a gate-all-around (GAA) transistor having a structure in which the gate is provided so as to surround a part of the semiconductor layer 102 which serves as the channel region.

[0110] The imaging device 1 has contacts 51 and 52, as shown in the example in Figure 5. Contact 51 is provided on the surface 12S1 (i.e., front side) of the semiconductor layer 102 in layer 202. Contact 52 is provided on the surface 12S2 (i.e., back side) of the semiconductor layer 102 in layer 202.

[0111] The imaging device 1 is configured to have a plurality of contacts 51 and a plurality of contacts 52, for example, corresponding to the number of signals transmitted between layers 201 to 203. For example, in the pixel array 100, a plurality of contacts 51 and a plurality of contacts 52 are arranged for each pixel P or for a plurality of pixels P.

[0112] The contact 51 is provided on the wiring layer 121 on the surface 12S1 side (i.e., the surface side) of the semiconductor layer 102. The contact 51 is provided, for example, to a circuit element (transistor, capacitive element, or resistive element, etc.) provided on the semiconductor layer 102. As an example, the contact 51 is electrically connected to the terminals (e.g., gate, source, or drain) of a pixel transistor 30.

[0113] The contact 52 is provided on the wiring layer 122 on the surface 12S2 side (i.e., the back side) of the semiconductor layer 102. The contact 52 is electrically connected, for example, to a circuit element (such as a transistor) provided on the semiconductor layer 102 from the surface 12S2 side. As an example, the contact 52 is electrically connected to the terminal of a pixel transistor 30. The contact 52 is provided on the back side and can be called a backside contact.

[0114] Contacts 51 and 52 are each constructed using a conductive material. Each of contacts 51 and 52 is formed by, for example, embedding (filling) a conductive material such as tungsten (W) into a contact hole. Contacts 51 and 52 may be constructed from metallic materials such as copper (Cu) or aluminum (Al), or from other materials.

[0115] In the example shown in Figure 6 or Figure 7, a contact 51 (referred to as contact 51a) and a contact 52 (i.e., a backside contact) are provided for the pixel transistor 30a. In addition, two contacts 51 (referred to as contact 51b and contact 51c) are provided for the pixel transistor 30b.

[0116] The semiconductor region 41 (source region or drain region) of the pixel transistor 30a is connected to a contact 51a provided on the wiring layer 121 on the surface 12S1 side of the semiconductor layer 102. The semiconductor region 41 is electrically connected to the wiring and vias of the wiring layer 121 via the contact 51a.

[0117] The gate electrode 31a of the pixel transistor 30a is connected to a contact 52 (backside contact) provided on the wiring layer 122 on the surface 12S2 side of the semiconductor layer 102. In the example shown in Figure 6, the gate electrode 31a of the pixel transistor 30a is electrically connected to the electrode 92 (junction electrode) of the wiring layer 122 via the contact 52.

[0118] The gate electrode 31b of the pixel transistor 30b is connected to a contact 51b provided on the wiring layer 121 on the surface 12S1 side of the semiconductor layer 102. The gate electrode 31b of the pixel transistor 30b is electrically connected, for example, to the wiring and vias of the wiring layer 121 via the contact 51b.

[0119] The semiconductor region 43 (source region or drain region) of the pixel transistor 30b is connected to a contact 51c provided on the wiring layer 121 on the surface 12S1 side of the semiconductor layer 102. The semiconductor region 43 is electrically connected to the wiring and vias of the wiring layer 121 via the contact 51c.

[0120] As an example, the pixel transistor 30a is used as a transistor AMP in the readout circuit 15, as shown in Figure 8. The gate electrode 31a of the pixel transistor 30a configured as a transistor AMP is electrically connected to the floating diffusion FD provided in the semiconductor layer 101 via the contact 52.

[0121] The floating diffusion FD of the semiconductor layer 101 is electrically connected to the gate electrode 31a of the pixel transistor 30a, which is a transistor AMP, via electrodes 91, 92 and contact 52, for example. The semiconductor region 41 of the transistor AMP is electrically connected to a power line to which a power supply voltage (e.g., power supply voltage VDD) is supplied, via contact 51a, for example.

[0122] As an example, the pixel transistor 30b is used as the transistor SEL of the readout circuit 15, as shown in Figure 8. The gate electrode 31b of the pixel transistor 30b configured as the transistor SEL receives the signal SSEL described above via the wiring of the wiring layer 121 and the contact 51b. In addition, the semiconductor region 43 of the transistor SEL is electrically connected to the signal line VSL by the contact 51c.

[0123] In the imaging device 1, for example, the photoelectric conversion unit 11, transistor TG, and floating diffusion FD for each pixel P are provided in layer 201. The transistors (transistors AMP, SEL, RST, etc.) of the readout circuit 15 are provided in layer 202. The photoelectric conversion unit 11 and the transistors of the readout circuit 15 are arranged in separate layers. Therefore, the imaging device 1 can have a structure advantageous for pixel miniaturization.

[0124] In the imaging device 1, the floating diffusion FD of the semiconductor layer 101 is electrically connected to circuit elements provided on the semiconductor layer 102, such as transistors AMP and RST, by electrodes 91, 92 and contacts 52, etc. The readout circuit 15 is electrically connected to a circuit (for example, a signal processing unit 112) provided on the layer 203 by contacts 51 and electrodes 93, 94, etc.

[0125] The charge photoelectrically converted by the photoelectric conversion unit 11 of the semiconductor layer 101 is transferred via the transistor TG to the floating diffusion FD of the semiconductor layer 101 and the readout circuit 15 of the semiconductor layer 102. The readout circuit 15 can, for example, generate a pixel signal based on the charge converted by the photoelectric conversion unit 11 and output the pixel signal to the signal processing unit 112 of the semiconductor layer 103 via the signal line VSL.

[0126] Figures 9A and 9B show examples of contact arrangements in an imaging device according to the first embodiment. The imaging device 1 may have an insulating film 36, as shown in the example in Figure 9A or Figure 9B. The insulating film 36 (insulating member) is provided between a portion P1 (i.e., channel region) which is part of the semiconductor layer 102 and a contact 52 (i.e., backside contact).

[0127] The insulating film 36 is provided on the surface 12S2 side of the semiconductor layer 102 and is located between the portion P1 and the contact 52. The insulating film 36 is made of, for example, an insulating material and is provided so as to cover the bottom B1 (bottom surface) of the portion P1 (fin portion) which is a channel region. The insulating film 36 may be provided so as to be in contact with the portion P1, or so as to be in contact with the contact 52. The insulating film 36 can also be called a protective film.

[0128] The insulating film 36 is made of an insulating material such as silicon oxide (SiO) or silicon nitride (SiN). The insulating film 36 is provided between the portion P1 and the contact 52, electrically insulating the portion P1 and the contact 52. The insulating film 36 may be made of an insulating material such as silicon oxynitride (SiO) or aluminum oxide (AlO), or it may be made of other materials.

[0129] The insulating film 36 may be made of the same material as the surrounding insulating film, or it may be made of a different material from the surrounding insulating film. In the example shown in Figure 9A or Figure 9B, the insulating film 36 may be made of the same material as the insulating film 38 of the wiring layer 122 (e.g., silicon oxide film), or the same material as the insulating film 37 of the wiring layer 122 (e.g., silicon nitride film). The provision of the insulating film 36 allows for appropriate separation between portion P1 and contact 52.

[0130] As described above, the imaging device 1 according to this embodiment has a contact 51 provided on the surface 12S1 side of the semiconductor layer 102 and a contact 52 provided on the surface 12S2 side of the semiconductor layer 102. By utilizing contacts 51 and 52 (i.e., the upper and lower contacts), it becomes possible to eliminate the need for through electrodes for connecting the circuit elements of layer 201 and layer 202 in each pixel P.

[0131] In this embodiment, through-electrodes for connection that penetrate the semiconductor layer 102 can be eliminated in the pixel array 100. Therefore, the area of ​​the region in the semiconductor layer 102 where elements such as transistors and capacitive elements are arranged can be increased. This makes it possible to realize a photodetector (imaging device) suitable for miniaturization. Furthermore, it becomes possible to expand functionality (for example, by adding elements).

[0132] As shown in Figure 10, the imaging device 1 is configured such that, for example, the width of the first layer of wiring (wiring M1a) in the wiring layer 121 is smaller than the width of the first layer of wiring (wiring M1b) in the wiring layer 122. In the example shown in Figure 10, the width W1 in the X-axis direction of the first layer of wiring M1a in the wiring layer 121 is smaller than the width W2 in the X-axis direction of the first layer of wiring M1b in the wiring layer 122, for example, the electrode 92 which is a bonding electrode.

[0133] Thus, the imaging device 1 is configured such that the wiring width on the contact 51 side is smaller than the wiring width on the contact 52 (i.e., the back-side contact) side. Therefore, the circuits of layer 202 (e.g., the readout circuit 15) and the circuits of layer 203 (e.g., the signal processing unit 112) can be connected by fine wiring. The imaging device 1 can have a structure that is advantageous for miniaturization.

[0134] Furthermore, the imaging device 1 is configured such that the number of wires in the wiring layer 122 is less than the number of wires in the wiring layer 121. For example, as shown in the example in Figure 11, the total number of wires in the wiring layer 122 is less than the total number of wires in the wiring layer 121. This makes it possible to suppress the addition of unnecessary parasitic capacitance to the wiring, contacts, etc., of the wiring layers 122 and 111.

[0135] By configuring the imaging device 1 in this way, it is possible to prevent the addition of unnecessary parasitic capacitance to the wiring (i.e., floating diffusion wiring (FD wiring)) electrically connected between the floating diffusion FD of the semiconductor layer 101 and the pixel transistor 30 (e.g., transistor AMP) of the semiconductor layer 102. Parasitic capacitance can be reduced, and for example, it becomes possible to suppress the intrusion of noise into the pixel signal.

[0136] Figure 12 is a diagram illustrating an example of the configuration of an imaging device according to the first embodiment. The transistors AMP, SEL, and RST of the readout circuit 15 are configured as Fin-type transistors, for example, as shown in the example in Figure 12. Note that the transistors AMP, SEL, RST, etc. may be configured as GAA-type transistors.

[0137] The imaging device 1 may be configured such that an electrode 92, which serves as a bonding electrode, is positioned above the contact 52. In the example shown in Figure 12, electrodes 92 and 91, which are bonding electrodes (for example, electrodes made of Cu), are provided above the contact 52 connected to the gate electrode 31 of the transistor AMP. In the imaging device 1 according to this embodiment, through electrodes can be eliminated in each pixel P, making it possible to reduce the number of steps in the manufacturing process.

[0138] The imaging device 1 may have a shielding portion 70, as shown in the example in Figure 13. The shielding portion 70 is provided around bonding electrodes (for example, electrodes 91 and 92). The shielding portion 70 may be provided around at least one of electrodes 91 and 92. The shielding portion 70 (shielding member) is positioned between a plurality of adjacent electrodes 91 (or electrodes 92).

[0139] The shield portion 70 may be formed using a metallic material such as copper (Cu), aluminum (Al), or tungsten (W), or it may be constructed using other conductive materials. A predetermined potential (voltage) is supplied to the shield portion 70, for example, through wiring and vias in the wiring layer. The shield portion 70 can also be called a shield region or shield wiring.

[0140] The shield portion 70 may be provided so as to surround the electrode 92 (or electrode 91), as shown in the example in Figure 14A or Figure 14B. The shield portion 70 may be formed in a grid pattern so as to surround each electrode 92 (or electrode 91) provided for each or a plurality of pixels P in a plan view (i.e., when viewed in the XY plane).

[0141] As shown in the example in Figure 15A or Figure 15B, multiple shielding units 70 may be arranged to surround the electrode 92 (or electrode 91). In the imaging device 1, the provision of shielding units 70 can suppress the intrusion of noise into the signals transmitted by electrodes 91 and 92. The shape and arrangement of the shielding units 70 are not limited to the illustrated example and can be changed as appropriate.

[0142] Figure 16 is a diagram illustrating another configuration example of the imaging device according to the first embodiment. The contact 52 (backside contact) may be provided so as to be connected to the gate electrode of the pixel transistor 30, or it may be provided so as to be connected to the source region or drain region of the pixel transistor 30. In addition, a contact 52 connected to a capacitive element or a resistive element may be provided.

[0143] In the pixel array 100 of the imaging device 1, for example, each pixel P or each group of pixels P is provided with a group of contacts 52 (contacts 52a and 52b in Figure 16) and a group of pixel transistors 30 (pixel transistor 30a, pixel transistor 30b, etc.). The readout circuit 15 is configured to include the pixel transistors 30a and 30b as the transistors AMP, RST, etc. mentioned above.

[0144] Contact 52a is positioned corresponding to the pixel transistor 30a and is connected to the gate electrode 31 of the pixel transistor 30a. Contact 52b is positioned corresponding to the pixel transistor 30b and is connected to a portion P2 which is part of the semiconductor layer 102. The portion P2 of the semiconductor layer 102 is, for example, the source region or drain region of the pixel transistor 30.

[0145] The pixel transistor 30b has a portion P2, which is part of the semiconductor layer 102, as the source region or drain region of the pixel transistor 30b. The portion P2 of the semiconductor layer 102 is, for example, the semiconductor region 41, semiconductor region 42, or semiconductor region 43 described above. The contact 52b is formed to connect to the portion P2 of the semiconductor layer 102 (i.e., the semiconductor region 41, semiconductor region 42, or semiconductor region 43 of the semiconductor layer 102).

[0146] Pixel transistors 30a and 30b are, for example, used as different transistors in the readout circuit 15. Pixel transistor 30a may be provided as transistor AMP. Pixel transistor 30b may be provided as transistor RST, or as any other type of pixel transistor.

[0147] Figures 17A and 17B show examples of contact arrangement in an imaging device according to the first embodiment. Contact 52 may be connected to the side of the gate electrode 31 of the pixel transistor 30. Contact 52 has a side contact structure and is provided in contact with the side (side surface) of the gate electrode 31.

[0148] The contact 52 is provided so as to cover at least a portion of the side (side surface) of the gate electrode 31, for example, as shown in the example in Figure 17A. In the example shown in Figure 17A, the contact 52 is provided on the surface 12S2 side of the semiconductor layer 102 so as to sandwich a portion of the gate electrode 31 around the channel region P1.

[0149] The contact 52 may be connected to the side of portion P2 of the semiconductor layer 102, as shown in the example in Figure 17B. The contact 52 is provided in contact with, for example, the side (surface) of portion P2 which is the source region or drain region of the pixel transistor 30. The contact 52 may be provided so as to sandwich at least a part of portion P2.

[0150] Figures 18 to 20 illustrate examples of contact configurations in an imaging device according to the first embodiment. The shape and arrangement of the contacts 52 are not limited to the examples described above and can be changed as appropriate. The contacts 52 may have a rectangular shape in plan view (i.e., when viewed in the XY plane). The contacts 52 may have a circular, elliptical, or polygonal shape in plan view.

[0151] The placement position and number of contacts 52 can be arbitrarily set, as shown in the examples in Figure 19 or Figure 20. For example, taking into account misalignment, contacts 52 may be placed on a portion of the gate electrode 31 that extends in the X-axis direction (or Y-axis direction), as shown in the example in Figure 19. Multiple contacts 52 may be placed on a single gate electrode 31 or a single portion P2, as shown in the example in Figure 20.

[0152] Figure 21 is a diagram illustrating an example of contact arrangement in an imaging device according to the first embodiment. As shown in Figure 21, the semiconductor layer 102 has a well 48 and a semiconductor region 45. The well 48 is, for example, a p-type semiconductor region, and is a p-type well (p-well). The well 48 may be an n-type semiconductor region as an n-type well region if necessary.

[0153] The semiconductor regions 41, 42, and 43 described above are provided in, for example, the well 48. Semiconductor regions 41, 42, and 43 are, for example, n-type semiconductor regions. As an example, each of the semiconductor regions 41, 42, and 43 has an impurity concentration higher than the impurity concentration of the well 48 and is configured as an n+-type semiconductor region.

[0154] The semiconductor region 45 is a semiconductor region of the same conductivity type as the well 48. The semiconductor region 45 is provided relative to the well 48, for example, as a well contact region. As an example, the semiconductor region 45 has a higher impurity concentration than the well 48 and is configured as a p+ type semiconductor region. The semiconductor region 45 can also be called a p+ type diffusion region (diffusion layer) or a p+ type conductive region.

[0155] The imaging device 1 may have contacts 52 provided for the semiconductor region 45, as shown in the example in Figure 21. The semiconductor region 45 is electrically connected to a reference potential line, for example, via contacts 52 (backside contacts) of the wiring layer 122. The contacts 52 can also be called well contacts.

[0156] A voltage VSS (e.g., 0V) is applied to the semiconductor region 45 and well 48 via the contact 52 as a reference potential. This suppresses the accumulation of unwanted charge in the channel region (i.e., portion P1) of the transistor SEL (or transistor AMP). This suppresses noise from being mixed into the pixel signal and prevents a decrease in image quality.

[0157] Figure 22 is a diagram illustrating an example of the configuration of an imaging device according to the first embodiment. The imaging device 1 has a pixel array 100 and a region surrounding the pixel array 100 (referred to as the peripheral region 200), as shown in the example in Figure 22. The imaging device 1 also has a region where a plurality of pads 20 are provided (referred to as the pad region 210).

[0158] In the imaging device 1, for example, one or more pad areas 210 are provided around the pixel array 100. The imaging device 1 has, for example, pads 20, which are pads (terminals) used for transmitting signals to the outside. In addition, for example, power pads, GND (ground) pads, etc. are provided as pads 20.

[0159] The multiple pads 20 provided in the imaging device 1 include input / output pads to which signals are input and output, input pads to which signals are input from outside the imaging device 1, output pads to which signals are output to the outside of the imaging device 1, and so on. The number and arrangement of the pads 20 and pad areas 210 provided in the imaging device 1 are not limited to the illustrated example and can be set arbitrarily.

[0160] Contacts 51 and 52 described above are also provided in the area outside the pixel array 100, for example, in the peripheral area 200. In the imaging device 1, multiple contacts 51 and multiple contacts 52 are arranged in the peripheral area 200, and circuits (elements) provided in different layers are connected to each other. For example, in the peripheral area 200, multiple contacts 51 and multiple contacts 52 are arranged in a manner corresponding to the number of signals transmitted between layers 201 to 203.

[0161] Figures 23A and 23B show examples of contact arrangements in an imaging device according to the first embodiment. Figures 23A and 23B show examples of contact arrangements 51 and 52 in the peripheral region 200. For example, the circuit elements of layer 201 and the circuit elements of layer 203 are electrically connected to each other via the contacts 51 and 52 provided on layer 202.

[0162] Contact 51 and contact 52 (backside contact) are electrically connected to each other via a connection region 60 provided in the semiconductor layer 102, as shown in the example in Figure 23A or Figure 23B. Contact 51 and contact 52 are electrically connected to each other in the semiconductor layer 102. The connection region 60 (i.e., the connecting member) is formed using, for example, silicon (Si), polysilicon (Poly-Si), a metal material, etc.

[0163] The connection region 60 may be, for example, a semiconductor region or a conductive region containing impurities. The connection region 60 may, as an example, be made of polysilicon doped with impurities. The connection region 60 may also be made of other conductive materials. The shape of the connection region 60 is not limited to the illustrated example and can be changed as appropriate. Furthermore, multiple contacts 52 and contacts 51 may be connected to a single connection region 60.

[0164] As an example, as shown in Figure 24A, contact 52 is electrically connected to contact 51 via a connection region 60. As another example, as shown in Figure 24B, contact 52 is electrically connected to contact 51 via a connection region 60 which is configured as a gate electrode provided so as to sandwich a part of the semiconductor layer 102.

[0165] Contacts 51 and 52 may have a side contact structure, as shown in the example in Figure 25A. At least one of contacts 51 and 52 may be provided so as to be in contact with the side of the connection area 60. Contact 52 may be provided so as to be directly connected to contact 51. Contact 52 may be provided such that a part of contact 52 is in contact with contact 51, as shown in the example in Figure 25B.

[0166] [Function and Effects] The photodetector according to this embodiment includes a first layer (layer 201) which includes a first semiconductor layer (semiconductor layer 101) having a first surface (e.g., surface 11S1) and a second surface (surface 11S2) opposite to the first surface; a second semiconductor layer (semiconductor layer 102) which includes a third surface (e.g., surface 12S1) and a fourth surface (surface 12S2) opposite to the third surface, and is stacked on the first layer such that the first surface and the fourth surface face each other; a photoelectric conversion element (photoelectric conversion unit 11) provided on the first semiconductor layer; a readout circuit (readout circuit 15) which has a first transistor (pixel transistor 30) provided on the third surface side of the second semiconductor layer and is capable of outputting a first signal based on the charge converted by the photoelectric conversion element; a first contact (contact 51) provided on the third surface side of the second semiconductor layer; and a second contact (contact 52) ​​provided on the fourth surface side of the second semiconductor layer.

[0167] The photodetector (imaging device 1) according to this embodiment includes a layer 201 containing a semiconductor layer 101, a layer 202 containing a semiconductor layer 102 and laminated on layer 201, a contact 51 provided on the surface 12S1 side of the semiconductor layer 102, and a contact 52 (i.e., a backside contact) provided on the surface 12S2 side of the semiconductor layer 102. Therefore, it is possible to realize a photodetector suitable for miniaturization.

[0168] Next, modified examples of the present disclosure will be described. In the following, components similar to those in the above embodiments will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0169] <2. Modifications> (Modification 1) Figure 26 is a diagram showing an example of the circuit configuration of a pixel in an imaging device according to a modification of the present disclosure. The pixel P includes a photoelectric conversion unit 11, a transistor TG, a floating diffusion FD1, a transistor AMP, a transistor SEL, and a transistor RST. The floating diffusion FD1 in Figure 26 corresponds to the floating diffusion FD in Figure 3.

[0170] Furthermore, pixel P includes a transistor FDG, a floating diffusion FD2, a transistor FCG, and a floating diffusion FD3. Pixel P may also have a capacitive element C1 and a capacitive element C2, as shown in Figure 26. Note that pixel P may have only one of either capacitive element C1 or capacitive element C2.

[0171] The floating diffusion FD2 is a storage unit and is configured to store charge. The floating diffusion FD2 can store the charge photoelectrically converted by the photoelectric conversion unit 11. The floating diffusion FD2 stores the transferred charge and converts it into a voltage corresponding to the capacitance of the floating diffusion FD2. The floating diffusion FD2 can also be described as a storage unit (or charge storage unit) capable of holding charge.

[0172] The capacitive element C1 is configured to have a predetermined capacitance value and to hold charge. The capacitive element C1 is provided relative to the floating diffusion FD2 and stores the transferred charge. The capacitive element C1 is, for example, a MOS (Metal Oxide Semiconductor) capacitor, an MIM (Metal-Insulator-Metal) capacitor, etc.

[0173] One electrode of the capacitive element C1 is electrically connected to the floating diffusion FD2, and the other electrode of the capacitive element C1 is electrically connected to the potential line L11. The potential line L11 is a wire to which a predetermined voltage (potential) is supplied. The potential line L11 is, for example, a power line to which the power supply voltage is supplied, or a ground line (earthing line).

[0174] The floating diffusion FD3 is a storage unit and is configured to store charge. The floating diffusion FD3 can store the charge photoelectrically converted by the photoelectric conversion unit 11. The floating diffusion FD3 stores the transferred charge and converts it into a voltage corresponding to the capacitance of the floating diffusion FD3. The floating diffusion FD3 can also be described as a storage unit (or charge storage unit) capable of holding charge.

[0175] Capacitive element C2 is configured to have a predetermined capacitance value and to hold charge. Capacitive element C2 is provided with respect to the floating diffusion FD3 and stores the transferred charge. Capacitive element C2 is, for example, a MOS capacitor, an MIM capacitor, etc. Capacitive elements C1 and C2 may be other types of capacitive elements.

[0176] One electrode of the capacitive element C2 is electrically connected to the floating diffusion FD3, and the other electrode of the capacitive element C2 is electrically connected to the potential line L12. The potential line L12 is a wire to which a predetermined voltage is supplied. The potential line L12 is, for example, a power line to which the power supply voltage is supplied, or a ground line (earthing wire).

[0177] Transistors FDG and FCG are transistors used to set the conversion gain (i.e., conversion efficiency) when converting electric charge to voltage. Pixel P has transistors FDG and FCG, and is configured to allow changing the conversion gain. Transistors FDG and FCG are switching transistors, and can also be called gain switching transistors or capacitance switching transistors.

[0178] The transistor FDG is configured to electrically connect floating diffusion FD1 and floating diffusion FD2. The transistor FDG is controlled, for example, by the signal SFDG to electrically connect or disconnect floating diffusion FD1 and floating diffusion FD2.

[0179] In pixel P, when transistor FDG is turned on, floating diffusion FD1 and floating diffusion FD2 are electrically connected. The capacitance added to floating diffusion FD1 increases, and the conversion gain (conversion efficiency) when converting charge to voltage is switched.

[0180] The transistor FCG is configured to electrically connect floating diffusion FD2 and floating diffusion FD3. The transistor FCG is controlled, for example, by the signal SFCG to electrically connect or disconnect floating diffusion FD2 and floating diffusion FD3.

[0181] In the imaging device 1, the capacitance added to the floating diffusion FD1 can be changed and the conversion gain switched by controlling the on / off states of transistors FDG and FCG. By controlling transistors FDG and FCG, the capacitance that stores the photoelectrically converted charge can be switched in stages, making it possible to expand the dynamic range.

[0182] The transistor RST is configured to reset the voltages of floating diffusion FD1, floating diffusion FD2, and floating diffusion FD3. In the example shown in Figure 26, the transistor RST is electrically connected to a power line to which the power supply voltage VDD is supplied and is configured to perform a reset of the charge of pixel P.

[0183] The transistors TG, AMP, SEL, FDG (switching transistor), FCG (switching transistor), and RST mentioned above are, for example, MOS transistors (MOSFETs) having gate, source, and drain terminals.

[0184] In the example shown in Figure 26, transistors TG, AMP, SEL, FDG, FCG, and RST are each composed of NMOS transistors. The transistor for pixel P may be composed of a PMOS transistor if necessary.

[0185] The pixel control unit 110 (see Figure 1) supplies control signals to the gates of each pixel P, such as transistors TG, SEL, FDG, FCG, and RST, via the control line Lc described above, to turn the transistors on or off. The pixel control unit 110 can also control the reading of the pixel signals of each pixel P to the signal line VSL.

[0186] Figures 27A and 27B, and Figures 28A to 28C are diagrams illustrating examples of contact arrangement in an imaging device according to a modified example. The contact 52 (backside contact) may be provided to be connected to the capacitive element C, for example, as shown in the example in Figure 27A or Figure 27B. The capacitive element C is, for example, the capacitive element C1 or capacitive element C2 of the readout circuit 15 described above.

[0187] In the pixel array 100 of the imaging device 1, for example, a capacitive element C and a plurality of contacts 51 and contacts 52 are provided for each pixel P or for each group of pixels P. The capacitive element C is, for example, a MOS capacitor provided in the semiconductor layer 102, and is applied as the capacitive element C1 or capacitive element C2 described above.

[0188] Contact 52 is positioned relative to the capacitive element C and connected to the electrodes of the capacitive element C. For example, contact 52 is electrically connected to one of the electrodes 81 and 82 of the capacitive element C, for example, electrode 82. Contact 51 is electrically connected to the other electrode of the capacitive element C, for example, electrode 81.

[0189] Contact 52 may be electrically connected to electrode 81 of capacitive element C, and contact 51 may be electrically connected to electrode 82 of capacitive element C. The shapes of electrode 81 and electrode 82 of capacitive element C can be changed as appropriate, as shown in the examples in Figures 28A to 28C.

[0190] The capacitive element C may be configured as an MIM capacitor, as schematically shown in Figure 29. The contact 52 may have a side contact structure. The contact 52 may be provided so as to contact one side of the electrode 81 and electrode 82 of the capacitive element C. The imaging device 1 according to this modified example can also obtain the same effects as the embodiment described above.

[0191] <3. Second Embodiment> Next, a second embodiment of the present disclosure will be described. In the following, components similar to those in the embodiments described above will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0192] The technology disclosed herein is not limited to image sensors, but is also applicable to logic semiconductor devices including, for example, arithmetic circuits such as CPUs (Central Processing Units) and GPUs (Graphics Processing Units), or memory circuits such as SRAMs (Static Random Access Memory). The technology disclosed herein is applicable to various semiconductor devices.

[0193] The semiconductor device 2 according to this embodiment, for example, has a layer 201 including a semiconductor layer 101 and a layer 202 including a semiconductor layer 102, similar to the first embodiment. Layers 201 and 202 are stacked such that surfaces 11S1 and 12S2 face each other. For example, layer 201 may have a wiring layer 111, and layer 202 may have wiring layers 121 and 122. The semiconductor device 2 may also have a layer 203 including a semiconductor layer 103.

[0194] The semiconductor layer 101 of layer 201 is provided with active elements (transistors, diodes, etc.). The semiconductor device 2 has, for example, a plurality of active elements (MOSFETs, etc.) provided on the surface 11S1 side of the semiconductor layer 101. The active elements may be planar or fin type elements, or may have other structures. The semiconductor layer 102 of layer 202 is provided with a transistor 30.

[0195] The semiconductor device 2 has a circuit 15 that includes one or more transistors 30. The circuit 15 is configured to perform operations such as calculations and readouts. The semiconductor device 2 may be provided with multiple circuits 15, each having multiple transistors 30. The circuit 15 may be configured to include logic circuits (i.e., logic elements) such as AND circuits, NAND circuits, OR circuits, and NOR circuits. The circuit 15 may also have capacitive elements, resistive elements, etc.

[0196] The transistor 30, located in the semiconductor layer 102 of layer 202, can function, for example, as an n-type or p-type FET (Field Effect Transistor) that constitutes an arithmetic logic circuit. The circuit 15 has a transistor 30 provided on the surface 12S1 side of the semiconductor layer 102 and is configured to be electrically connectable to an active element provided in the semiconductor layer 101.

[0197] The transistor 30 has a gate electrode 31 and a gate insulating film 35 that are provided so as to sandwich a part (part P1) of the semiconductor layer 102 from the surface 12S1 side of the semiconductor layer 102, as in the example shown in Figures 5 to 8. The transistor 30 can be configured as a Fin transistor, a GAA transistor, etc.

[0198] The transistor 30 may be arranged in stack with the active element of the semiconductor layer 101. For example, the transistor 30 of the semiconductor layer 102 and the transistor as an active element of the semiconductor layer 101 may be arranged perpendicularly along the stacking direction of layers 201 and 202 (for example, the Z-axis direction).

[0199] The semiconductor device 2 has contacts 51 and 52. Contact 51 is provided on the side 12S1 of the semiconductor layer 102. Contact 52 is provided on the side 12S2 of the semiconductor layer 102. Each of contacts 51 and 52 (i.e., backside contacts) is arranged to correspond to, for example, a circuit element (transistor, capacitive element, or resistive element, etc.) of the semiconductor layer 102.

[0200] In the semiconductor device 2, for example, contact 51 is provided on the wiring layer 121 on the surface 12S1 (i.e., front) side of the semiconductor layer 102 and is electrically connected to the terminals (gate, source, or drain) of the transistor 30. Contact 52 is provided on the wiring layer 122 on the surface 12S2 (i.e., back) side of the semiconductor layer 102 and is electrically connected to the terminals (gate, source, or drain) of the transistor 30.

[0201] Contact 52 is electrically connected, for example, to the gate electrode 31 of transistor 30. Contact 52 may also be electrically connected to the source region or drain region of transistor 30 (for example, the semiconductor region 41, semiconductor region 42, or semiconductor region 43 described above). Contact 52 may also be electrically connected to the gate electrode of transistor 30 and to the source region or drain region of transistor 30.

[0202] The contact 51 may be electrically connected, for example, to the gate electrode 31 of the transistor 30. The contact 51 may also be electrically connected to the source region or drain region of the transistor 30. The contact 51 may be electrically connected to the gate electrode of the transistor 30 and to the source region or drain region of the transistor 30.

[0203] Contacts 51 and 52 are electrically connected to each other in the semiconductor layer 102, for example. Contact 52 may be provided so as to sandwich a part of the semiconductor layer 102. Contact 51 may also be provided so as to sandwich a part of the semiconductor layer 102. For example, contact 52 may be arranged so as to sandwich a part of the semiconductor layer 102 from the surface 12S2 side, and contact 51 may be arranged so as to sandwich a part of the semiconductor layer 102 from the surface 12S1 side.

[0204] The transistor 30 of the semiconductor layer 102 and the active element transistor of the semiconductor layer 101 have different conductivity types (for example, n-type and p-type), and can form a CFET (Complementary FET) structure stacked vertically. In this structure, the contact 52 (backside contact) may be electrically connected to a power line or reference potential wiring (power line to which voltage VDD is supplied or wiring to which voltage VSS is supplied) located on the surface 12S2 (backside) side of the semiconductor layer 102.

[0205] Specifically, a bias potential to keep transistor 30 in an "always on" or "always off" state, or a control signal to dynamically control the circuit's threshold voltage (Vth), can be supplied from the back side via contact 52. This dramatically reduces congestion in the wiring layer 121 on the front side, enables power supply to the gate electrode 31 via the shortest distance, suppresses voltage drop (IR-drop), and allows for high-speed operation.

[0206] Furthermore, contact 52 may be connected to signal lines such as clock signals and reset signals (i.e., global signal lines). Compared to the case where these signals are supplied via the multilayer wiring layer on the front side, directly inputting these signals from the wiring layer 122 on the back side to the gate electrode 31 via contact 52 reduces wiring delay (RC delay) and improves the overall power efficiency of the chip.

[0207] Contact 52 may be configured not only as a signal line, but also as a power supply contact that supplies power from the back side (i.e., the surface 12S2 side) of layer 202. This enables a sophisticated wiring separation structure in which signal lines are concentrated on the surface 12S1 side (front side) of the semiconductor layer 102, and the power supply network (Backside Power Delivery Network) is located on the surface 12S2 side (back side).

[0208] [Function and Effects] The semiconductor device according to this embodiment includes a first layer (layer 201) including a first semiconductor layer (semiconductor layer 101) having a first surface (e.g., surface 11S1) and a second surface (surface 11S2) opposite to the first surface; a second semiconductor layer (semiconductor layer 102) having a third surface (e.g., surface 12S1) and a fourth surface (surface 12S2) opposite to the third surface, and the second layer (layer 202) is stacked on the first layer such that the first surface and the fourth surface face each other; a first active element provided on the first semiconductor layer; a first transistor (transistor 30) provided on the third surface side of the second semiconductor layer and a circuit (circuit 15) electrically connectable to the first active element; a first contact (contact 51) provided on the third surface side of the second semiconductor layer; and a second contact (contact 52) ​​provided on the fourth surface side of the second semiconductor layer. The second contact is electrically connected to the first gate electrode of the first transistor.

[0209] The semiconductor device (semiconductor device 2) according to this embodiment includes a layer 201 containing a semiconductor layer 101, a layer 202 containing a semiconductor layer 102 and stacked on layer 201, an active element provided on the semiconductor layer 101, a circuit 15 having a transistor 30 and electrically connectable to the active element, a contact 51 provided on the surface 12S1 side of the semiconductor layer 102, and a contact 52 (i.e., a back-side contact) provided on the surface 12S2 side of the semiconductor layer 102. The contact 52 is electrically connected to the gate electrode 31 of the transistor 30. Therefore, it is possible to realize a semiconductor device that can improve performance.

[0210] Next, modified examples of the present disclosure will be described. In the following, components similar to those in the above embodiments will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0211] <4. Modification> (Modification 2) Microbumps may be used as conductive protrusions for interlayer bonding and electrical connection (for example, between layer 201 and layer 202). The microbumps are made of a conductive material such as solder, gold, copper, or an alloy thereof, and are interposed, for example, between a pad provided on the wiring layer 111 of layer 201 and a pad provided on the wiring layer 122 of layer 202. In this configuration, the contact 52 (backside contact) is electrically connected to the circuit elements on the layer 201 side (for example, active elements such as transistors or wiring networks) via the pads and microbumps of the wiring layer 122.

[0212] A stacked structure using microbumps makes it easier to ensure alignment margins between the chips being bonded, which is advantageous when stacking multiple chips (chiplets) manufactured at different process nodes. Even in this case, maintaining a structure that allows access to the gate electrode (e.g., gate electrode 31) via the contact 52 enables high-speed signal transmission between the stacked chips.

[0213] The bonding between layers (for example, between layer 201 and layer 202, or between layer 202 and layer 203) is not limited to Cu-Cu bonding via bonding electrodes (electrodes 91 to 94), but may also be achieved using hybrid bonding, which joins metal pads and insulating films on the same plane. In this case, for example, the surfaces of wiring layer 111 and wiring layer 122 are planarized, the insulating films are joined to each other by intermolecular forces through plasma activation, and the embedded copper pads are metallically bonded to each other by heat treatment. This makes it possible to laminate with an extremely fine pitch (for example, 0.5 μm or less) without being constrained by bumps or electrode irregularities.

[0214] Furthermore, each layer (layers 201 to 203) may be formed not only by bonding separate substrates, but also by monolithic 3D stacking technology (Sequential Integration), in which device layers are sequentially formed on a single semiconductor substrate using epitaxial growth or low-temperature processes. In this configuration, electrical connections between layers are made using conventional vias (Monolithic Inter-tier Vias: MIVs) without the need for bonding electrodes. This allows for high-precision placement of contacts from both the front and back surfaces to the gate electrode (e.g., gate electrode 31) without being limited by bonding accuracy (alignment error).

[0215] <5. Examples of Application> The above-described imaging device 1 can be applied to any type of electronic device equipped with an imaging function, such as camera systems like digital still cameras and video cameras, or mobile phones with imaging capabilities. Figure 30 shows a schematic configuration of the electronic device 1000.

[0216] The electronic device 1000 includes, for example, a lens group 1001, an imaging device 1, a DSP (Digital Signal Processor) circuit 1002, a frame memory 1003, a display unit 1004, a recording unit 1005, an operation unit 1006, and a power supply unit 1007, all of which are interconnected via a bus line 1008.

[0217] The lens group 1001 captures incident light (image light) from the subject and forms an image on the imaging surface of the imaging device 1. The imaging device 1 converts the amount of incident light formed on the imaging surface by the lens group 1001 into an electrical signal on a pixel-by-pixel basis and supplies it as a pixel signal to the DSP circuit 1002.

[0218] The DSP circuit 1002 is a signal processing circuit that processes signals supplied from the imaging device 1. The DSP circuit 1002 outputs image data obtained by processing the signals from the imaging device 1. The frame memory 1003 temporarily holds the image data processed by the DSP circuit 1002 in frame units.

[0219] The display unit 1004 consists of a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and records the video or still image data captured by the imaging device 1 onto a recording medium such as a semiconductor memory or a hard disk.

[0220] The operation unit 1006 outputs operation signals for various functions possessed by the electronic device 1000 in accordance with user operations. The power supply unit 1007 appropriately supplies various power sources to the DSP circuit 1002, frame memory 1003, display unit 1004, recording unit 1005, and operation unit 1006.

[0221] <6. Application Examples> (Application Examples to Mobile Devices) The technology relating to this disclosure (this technology) can be applied to various products. For example, the technology relating to this disclosure may be realized as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0222] Figure 31 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0223] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 31, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0224] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0225] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0226] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0227] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0228] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0229] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0230] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0231] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0232] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 31, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0233] Figure 32 shows an example of the installation position of the imaging unit 12031.

[0234] In Figure 32, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0235] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0236] Figure 32 shows an example of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0237] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0238] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0239] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0240] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0241] The above describes an example of a mobile control system to which the technology described herein can be applied. The technology described herein can be applied to, for example, the imaging unit 12031 of the configuration described above. Specifically, for example, the imaging device 1 can be applied to the imaging unit 12031. By applying the technology described herein to the imaging unit 12031, it becomes possible to obtain high-definition captured images. This makes it possible to perform high-precision control using captured images in the mobile control system.

[0242] (Examples of application to endoscopic surgical systems) The technology disclosed herein (this technology) can be applied to various products. For example, the technology disclosed herein may be applied to endoscopic surgical systems.

[0243] Figure 33 is a diagram showing an example of a schematic configuration of an endoscopic surgical system to which the technology described herein (the technology) may be applied.

[0244] Figure 33 illustrates a surgeon (physician) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgical system 11000. As shown in the figure, the endoscopic surgical system 11000 consists of an endoscope 11100, other surgical instruments 11110 such as an insufflation tube 11111 and an energy treatment device 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 equipped with various devices for endoscopic surgery.

[0245] The endoscope 11100 consists of a barrel 11101, the tip of which is inserted into the body cavity of the patient 11132 for a predetermined length, and a camera head 11102 connected to the base end of the barrel 11101. In the illustrated example, the endoscope 11100 is shown as a so-called rigid endoscope having a rigid barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible endoscope having a flexible barrel.

[0246] An opening into which an objective lens is fitted is provided at the tip of the microscope tube 11101. A light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the tip of the microscope tube by a light guide extending inside the microscope tube 11101, and is irradiated through the objective lens towards the object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a straight-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0247] The camera head 11102 contains an optical system and an image sensor. Reflected light from the object being observed (observation light) is focused onto the image sensor by the optical system. The image sensor converts the observation light into electrical signals, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0248] The CCU 11201 is composed of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and other components, and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various image processing operations on that image signal, such as development processing (demosaic processing), to display the image based on that image signal.

[0249] The display device 11202 displays an image based on an image signal that has been processed by the CCU 11201, under control from the CCU 11201.

[0250] The light source device 11203 consists of a light source such as an LED (Light Emitting Diode) and supplies illumination light to the endoscope 11100 when photographing the surgical area, etc.

[0251] The input device 11204 is an input interface for the endoscopic surgical system 11000. The user can input various types of information and instructions to the endoscopic surgical system 11000 via the input device 11204. For example, the user can input instructions to change the imaging conditions (type of light, magnification, focal length, etc.) of the endoscope 11100.

[0252] The treatment instrument control device 11205 controls the drive of the energy treatment instrument 11112 for purposes such as tissue cauterization, incision, or blood vessel sealing. The insufflation device 11206 injects gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity for the purpose of securing a field of view by the endoscope 11100 and securing the operator's workspace. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, images, or graphs.

[0253] The light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical area can be configured as a white light source consisting of, for example, an LED, a laser light source, or a combination thereof. When the white light source is configured as a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to capture images corresponding to each of the RGB colors in time-division by irradiating the observation target with laser light from each of the RGB laser light sources in time-division and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter on the image sensor.

[0254] Furthermore, the light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the drive of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity, images can be acquired in time-division order, and these images can be combined to generate high dynamic range images without so-called black crushing and white clipping.

[0255] Furthermore, the light source device 11203 may be configured to supply light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption in body tissue and irradiating with narrow-band light compared to the irradiation light used in normal observation (i.e., white light), so-called narrow-band imaging is performed to image predetermined tissues such as blood vessels on the surface of mucosa with high contrast. Alternatively, in special light observation, fluorescence observation may be performed to obtain an image from fluorescence generated by irradiation with excitation light. In fluorescence observation, excitation light is irradiated onto body tissue and fluorescence from the body tissue is observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) is injected into body tissue and excitation light corresponding to the fluorescence wavelength of the reagent is irradiated onto the body tissue to obtain a fluorescence image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0256] Figure 34 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in Figure 33.

[0257] The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0258] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and then incident on the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses, including a zoom lens and a focus lens.

[0259] The imaging unit 11402 is composed of image sensors. The imaging unit 11402 may consist of one image sensor (a so-called single-chip type) or multiple image sensors (a so-called multi-chip type). If the imaging unit 11402 is composed of multiple chips, for example, each image sensor may generate image signals corresponding to RGB, and these may be combined to obtain a color image. Alternatively, the imaging unit 11402 may be configured to have a pair of image sensors for acquiring image signals for the right eye and left eye, respectively, corresponding to 3D (Dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical area. In addition, if the imaging unit 11402 is composed of multiple chips, multiple lens units 11401 may also be provided corresponding to each image sensor.

[0260] Furthermore, the imaging unit 11402 does not necessarily have to be located on the camera head 11102. For example, the imaging unit 11402 may be located inside the lens barrel 11101, directly behind the objective lens.

[0261] The drive unit 11403 is composed of actuators and, under control from the camera head control unit 11405, moves the zoom lens and focus lens of the lens unit 11401 along the optical axis by a predetermined distance. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted as appropriate.

[0262] The communication unit 11404 is composed of communication devices for sending and receiving various types of information with the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0263] Furthermore, the communication unit 11404 receives a control signal from the CCU 11201 to control the drive of the camera head 11102 and supplies it to the camera head control unit 11405. The control signal includes information about imaging conditions, such as information to specify the frame rate of the captured image, information to specify the exposure value at the time of imaging, and / or information to specify the magnification and focus of the captured image.

[0264] The imaging conditions such as frame rate, exposure value, magnification, and focus may be specified by the user as appropriate, or they may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 will be equipped with so-called AE (Auto Exposure), AF (Auto Focus), and AWB (Auto White Balance) functions.

[0265] The camera head control unit 11405 controls the drive of the camera head 11102 based on the control signal received from the CCU 11201 via the communication unit 11404.

[0266] The communication unit 11411 is comprised of a communication device for sending and receiving various types of information with the camera head 11102. The communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400.

[0267] Furthermore, the communication unit 11411 transmits control signals to the camera head 11102 to control the driving of the camera head 11102. Image signals and control signals can be transmitted by telecommunications, optical communications, etc.

[0268] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102.

[0269] The control unit 11413 performs various controls related to imaging the surgical area, etc., by the endoscope 11100, and the display of the images obtained from imaging the surgical area, etc. For example, the control unit 11413 generates a control signal to control the driving of the camera head 11102.

[0270] Furthermore, the control unit 11413 displays the captured image showing the surgical area, etc., on the display device 11202 based on the image signal processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical instruments such as forceps, specific biological sites, bleeding, mist when using the energy treatment device 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When the control unit 11413 displays the captured image on the display device 11202, it may use the recognition results to superimpose various surgical support information onto the image of the surgical area. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can proceed with the surgery reliably.

[0271] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable thereof.

[0272] In the illustrated example, communication was performed via a wired connection using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.

[0273] The above describes an example of an endoscopic surgical system to which the technology described herein may be applied. The technology described herein can be suitably applied, for example, to the imaging unit 11402 provided on the camera head 11102 of the endoscope 11100. By applying the technology described herein to the imaging unit 11402, it becomes possible to provide a high-definition endoscope 11100.

[0274] Although the present disclosure has been described above with reference to embodiments, modifications, application examples, and application examples, the present technology is not limited to the above embodiments, and various modifications are possible. For example, although the above modifications were described as modifications of the above embodiments, the configurations of each modification can be combined as appropriate.

[0275] In the embodiments described above, an imaging device was used as an example; however, the light detection device of this disclosure may be any device that receives incident light and converts the light into an electric charge. The output signal may be an image information signal or a distance measurement information signal. The light detection device (imaging device) can be applied to an image sensor, a distance measurement sensor, etc. Furthermore, this disclosure is not limited to back-illuminated image sensors, but is also applicable to front-illuminated image sensors.

[0276] The light detection device relating to this disclosure can also be used as a distance measuring sensor capable of measuring distance using the Time of Flight (TOF) method. The light detection device (imaging device) can also be used as a sensor capable of detecting events, for example, an event-driven sensor (also known as an EVS (Event Vision Sensor), EDS (Event Driven Sensor), DVS (Dynamic Vision Sensor), etc.).

[0277] An optical detection device according to one embodiment of the present disclosure includes a first layer containing a first semiconductor layer having a first surface and a second surface opposite to the first surface, a second layer containing a second semiconductor layer having a third surface and a fourth surface opposite to the third surface, and stacked on the first layer such that the first surface and the fourth surface face each other, a photoelectric conversion element provided on the first semiconductor layer, a readout circuit having a first transistor provided on the third surface side of the second semiconductor layer and capable of outputting a first signal based on the charge converted by the photoelectric conversion element, a first contact provided on the third surface side of the second semiconductor layer, and a second contact provided on the fourth surface side of the second semiconductor layer.Therefore, it is possible to realize an optical detection device suitable for miniaturization.

[0278] A semiconductor device according to one embodiment of the present disclosure includes a first layer comprising a first semiconductor layer having a first surface and a second surface opposite to the first surface, a second layer comprising a second semiconductor layer having a third surface and a fourth surface opposite to the third surface, and stacked on the first layer such that the first surface and the fourth surface face each other, a first active element provided on the first semiconductor layer, a circuit having a first transistor provided on the third surface side of the second semiconductor layer and electrically connectable to the first active element, a first contact provided on the third surface side of the second semiconductor layer, and a second contact provided on the fourth surface side of the second semiconductor layer. Therefore, it is possible to realize a semiconductor device capable of improved performance.

[0279] Furthermore, the effects described herein are merely illustrative and not limited to those described herein, and other effects may also exist. In addition, this disclosure may also take the following configuration: (1) A photodetector comprising: a first layer including a first semiconductor layer having a first surface and a second surface opposite to the first surface; a second layer including a second semiconductor layer having a third surface and a fourth surface opposite to the third surface, and stacked on the first layer such that the first surface and the fourth surface face each other; a photoelectric conversion element provided on the first semiconductor layer; a readout circuit having a first transistor provided on the third surface side of the second semiconductor layer and capable of outputting a first signal based on the charge converted by the photoelectric conversion element; a first contact provided on the third surface side of the second semiconductor layer; and a second contact provided on the fourth surface side of the second semiconductor layer. (2) The photodetector according to (1), wherein the first layer includes a first wiring layer provided on the first side of the first semiconductor layer, and the second layer includes a second wiring layer provided on the third side of the second semiconductor layer and a third wiring layer provided on the fourth side of the second semiconductor layer, and the first layer and the second layer are laminated by bonding the electrodes of the first wiring layer and the electrodes of the third wiring layer. (3) The photodetector according to (1) or (2), wherein the second layer includes a second wiring layer provided on the third side of the second semiconductor layer and a third wiring layer provided on the fourth side of the second semiconductor layer, and the width of the first wiring in the second wiring layer is smaller than the width of the first wiring in the third wiring layer. (4) The photodetector according to (3), wherein the third wiring layer has the first wiring provided as a bonding electrode. (5) The photodetector according to any one of (1) to (4), wherein the second layer includes a second wiring layer provided on the third side of the second semiconductor layer and a third wiring layer provided on the fourth side of the second semiconductor layer, and the number of wirings in the third wiring layer is less than the number of wirings in the second wiring layer. (6) The photodetector according to any one of (1) to (5), wherein the second layer includes a third wiring layer provided on the fourth side of the second semiconductor layer, and the third wiring layer has a bonding electrode provided above the second contact.(7) The photodetector according to any one of (1) to (7), wherein the first transistor has a first gate insulating film and a first gate electrode provided on the third surface side of the second semiconductor layer so as to sandwich a part of the second semiconductor layer, and the second contact is electrically connected to the first gate electrode of the first transistor. (8) The photodetector according to (7), further comprising an insulating film provided between the part of the second semiconductor layer and the second contact. (9) The photodetector according to (7) or (8), wherein the first contact is electrically connected to the first gate electrode of the first transistor. (10) The photodetector according to any one of (7) to (9), further comprising a floating diffusion provided in the first semiconductor layer and capable of storing the charge converted by the photoelectric conversion element, and a junction electrode provided above the second contact, wherein the first gate electrode of the first transistor is electrically connected to the floating diffusion via the second contact and the junction electrode, and the first transistor is capable of generating the first signal based on the charge stored in the floating diffusion. (11) The photodetector according to (10), further comprising a shield portion provided around the junction electrode. (12) The photodetector according to any one of (1) to (11), wherein the first transistor has a source region and a drain region provided in the second semiconductor layer, and the second contact is electrically connected to the source region or the drain region of the first transistor. (13) The photodetector according to any one of (1) to (12), further comprising a well of a first conductivity type provided in the second semiconductor layer, wherein the first transistor has a source region and a drain region of a second conductivity type provided in the well, and the second contact is electrically connected to the well. (14) The photodetector according to any one of (1) to (13), wherein the readout circuit has a capacitive element provided in the second layer capable of storing charge, and the second contact is electrically connected to the capacitive element.(15) The photodetector according to any one of (1) to (14), wherein the first contact and the second contact are electrically connected to each other in the second semiconductor layer. (16) The photodetector according to any one of (1) to (15), wherein the second contact is provided so as to sandwich a part of the second semiconductor layer. (17) The photodetector according to any one of (1) to (16), further comprising: a pixel array including a plurality of pixels each having a photoelectric conversion element; a third contact provided on the third surface side of the second semiconductor layer outside the pixel array; and a fourth contact provided on the fourth surface side of the second semiconductor layer outside the pixel array, wherein the first contact and the second contact are electrically connected to each other in the second semiconductor layer. (18) The photodetector according to any one of (1) to (17), further comprising a third layer laminated with the second layer, wherein the third layer includes a third semiconductor layer having a fifth surface and a sixth surface opposite to the fifth surface, and is laminated on the second layer such that the third surface and the fifth surface face each other. (19) The photodetector according to (18), wherein the second layer and the third layer are laminated by a junction between electrodes, and the third layer has at least a portion of a signal processing circuit capable of performing signal processing of the first signal. (20) Electronic device comprising an optical system and a photodetector that receives light transmitted through the optical system, wherein the photodetector includes a first layer including a first semiconductor layer having a first surface and a second surface opposite to the first surface, a second layer including a second semiconductor layer having a third surface and a fourth surface opposite to the third surface, and stacked on the first layer such that the first surface and the fourth surface face each other, a photoelectric conversion element provided on the first semiconductor layer, a readout circuit having a first transistor provided on the third surface side of the second semiconductor layer and capable of outputting a first signal based on the charge converted by the photoelectric conversion element, a first contact provided on the third surface side of the second semiconductor layer, and a second contact provided on the fourth surface side of the second semiconductor layer.(21) A semiconductor device comprising: a first layer including a first semiconductor layer having a first surface and a second surface opposite to the first surface; a second layer including a second semiconductor layer having a third surface and a fourth surface opposite to the third surface, the second layer being stacked on the first layer such that the first surface and the fourth surface face each other; a first active element provided on the first semiconductor layer; a circuit having a first transistor provided on the third surface side of the second semiconductor layer and electrically connectable to the first active element; a first contact provided on the third surface side of the second semiconductor layer; and a second contact provided on the fourth surface side of the second semiconductor layer. (22) A semiconductor device comprising: a first layer including a first semiconductor layer having a first surface and a second surface opposite to the first surface; a second layer including a second semiconductor layer having a third surface and a fourth surface opposite to the third surface, the second layer being stacked on the first layer such that the first surface and the fourth surface face each other; a first active element provided on the first semiconductor layer; a circuit having a first transistor provided on the third surface side of the second semiconductor layer and electrically connectable to the first active element; a first contact provided on the third surface side of the second semiconductor layer; and a second contact provided on the fourth surface side of the second semiconductor layer, wherein the second contact is electrically connected to the first gate electrode of the first transistor. (23) The semiconductor device according to (21) or (22), wherein the first transistor has a first gate insulating film and a first gate electrode provided on the third surface side of the second semiconductor layer so as to sandwich a part of the second semiconductor layer, and the second contact is electrically connected to the first gate electrode of the first transistor. (24) The semiconductor device according to any one of (21) to (23), wherein the first contact is electrically connected to the first gate electrode of the first transistor. (25) The semiconductor device according to any one of (21) to (24), wherein the first transistor has a source region and a drain region provided in the second semiconductor layer, and the second contact is electrically connected to the source region or the drain region of the first transistor.(26) The semiconductor device according to any one of (21) to (25), wherein the first contact and the second contact are electrically connected to each other in the second semiconductor layer. (27) The semiconductor device according to any one of (21) to (26), wherein the second contact is provided so as to sandwich a part of the second semiconductor layer. (28) The semiconductor device according to any one of (21) to (27), wherein the second contact is electrically connected to a signal line or power line included in a wiring layer provided on the fourth side of the second semiconductor layer. (29) The semiconductor device according to any one of (21) to (28), wherein the first active element includes a second transistor, and the first transistor and the second transistor are arranged perpendicularly along the stacking direction of the first layer and the second layer. (30) Electronic device comprising a semiconductor device, the semiconductor device comprising: a first layer including a first semiconductor layer having a first surface and a second surface opposite to the first surface; a second layer including a second semiconductor layer having a third surface and a fourth surface opposite to the third surface, the second layer being stacked on the first layer such that the first surface and the fourth surface face each other; a first active element provided on the first semiconductor layer; a circuit having a first transistor provided on the third surface side of the second semiconductor layer and electrically connectable to the first active element; a first contact provided on the third surface side of the second semiconductor layer; and a second contact provided on the fourth surface side of the second semiconductor layer. (31) Electronic device comprising a semiconductor device, the semiconductor device comprising: a first layer including a first semiconductor layer having a first surface and a second surface opposite to the first surface; a second layer including a second semiconductor layer having a third surface and a fourth surface opposite to the third surface, the second layer being stacked on the first layer such that the first surface and the fourth surface face each other; a first active element provided on the first semiconductor layer; a circuit having a first transistor provided on the third surface side of the second semiconductor layer and electrically connectable to the first active element; a first contact provided on the third surface side of the second semiconductor layer; and a second contact provided on the fourth surface side of the second semiconductor layer, the second contact being electrically connected to the first gate electrode of the first transistor.

[0280] This application claims priority based on Japanese Patent Application No. 2025-051878, filed with the Japan Patent Office on 26 March 2025, and all contents of that application are incorporated herein by reference.

[0281] Those skilled in the art will understand that various modifications, combinations, subcombinations, and changes can be conceived depending on design requirements and other factors, and that these fall within the scope of the attached claims and their equivalents.

Claims

1. A photodetector comprising: a first layer including a first semiconductor layer having a first surface and a second surface opposite to the first surface; a second layer including a second semiconductor layer having a third surface and a fourth surface opposite to the third surface, and stacked on the first layer such that the first surface and the fourth surface face each other; a photoelectric conversion element provided on the first semiconductor layer; a readout circuit having a first transistor provided on the third surface side of the second semiconductor layer and capable of outputting a first signal based on the charge converted by the photoelectric conversion element; a first contact provided on the third surface side of the second semiconductor layer; and a second contact provided on the fourth surface side of the second semiconductor layer.

2. The photodetector according to claim 1, wherein the first layer includes a first wiring layer provided on the first surface side of the first semiconductor layer, the second layer includes a second wiring layer provided on the third surface side of the second semiconductor layer and a third wiring layer provided on the fourth surface side of the second semiconductor layer, and the first layer and the second layer are laminated by bonding the electrodes of the first wiring layer and the electrodes of the third wiring layer.

3. The photodetector according to claim 1, wherein the second layer includes a second wiring layer provided on the third side of the second semiconductor layer and a third wiring layer provided on the fourth side of the second semiconductor layer, and the width of the first wiring in the second wiring layer is smaller than the width of the first wiring in the third wiring layer.

4. The photodetector according to claim 3, wherein the third wiring layer has the first wiring layer provided as a bonding electrode.

5. The photodetector according to claim 1, wherein the second layer includes a second wiring layer provided on the third side of the second semiconductor layer and a third wiring layer provided on the fourth side of the second semiconductor layer, and the number of wirings in the third wiring layer is less than the number of wirings in the second wiring layer.

6. The photodetector according to claim 1, wherein the second layer includes a third wiring layer provided on the fourth surface side of the second semiconductor layer, and the third wiring layer has a bonding electrode provided above the second contact.

7. The photodetector according to claim 1, wherein the first transistor has a first gate insulating film and a first gate electrode provided on the third surface side of the second semiconductor layer so as to sandwich a part of the second semiconductor layer, and the second contact is electrically connected to the first gate electrode of the first transistor.

8. The photodetector according to claim 7, further comprising an insulating film provided between the portion of the second semiconductor layer and the second contact.

9. The photodetector according to claim 7, wherein the first contact is electrically connected to the first gate electrode of the first transistor.

10. The photodetector according to claim 7, further comprising a floating diffusion provided in the first semiconductor layer and capable of storing the charge converted by the photoelectric conversion element, and a junction electrode provided above the second contact, wherein the first gate electrode of the first transistor is electrically connected to the floating diffusion via the second contact and the junction electrode, and the first transistor is capable of generating the first signal based on the charge stored in the floating diffusion.

11. The photodetector according to claim 10, further comprising a shielding portion provided around the bonding electrode.

12. The photodetector according to claim 1, wherein the first transistor has a source region and a drain region provided in the second semiconductor layer, and the second contact is electrically connected to the source region or the drain region of the first transistor.

13. The photodetector according to claim 1, further comprising a well of a first conductivity type provided in the second semiconductor layer, wherein the first transistor has a source region and a drain region of a second conductivity type provided in the well, and the second contact is electrically connected to the well.

14. The photodetector according to claim 1, wherein the readout circuit has a capacitive element provided in the second layer and capable of storing charge, and the second contact is electrically connected to the capacitive element.

15. The photodetector according to claim 1, wherein the first contact and the second contact are electrically connected to each other in the second semiconductor layer.

16. The photodetector according to claim 1, wherein the second contact is provided so as to sandwich a part of the second semiconductor layer.

17. The photodetector according to claim 1, further comprising: a pixel array including a plurality of pixels each having a photoelectric conversion element; a third contact provided on the third surface side of the second semiconductor layer outside the pixel array; and a fourth contact provided on the fourth surface side of the second semiconductor layer outside the pixel array, wherein the first contact and the second contact are electrically connected to each other in the second semiconductor layer.

18. The photodetector according to claim 1, further comprising a third layer laminated with the second layer, wherein the third layer includes a third semiconductor layer having a fifth surface and a sixth surface opposite to the fifth surface, and is laminated with the second layer such that the third surface and the fifth surface face each other.

19. The photodetector according to claim 18, wherein the second layer and the third layer are stacked by a junction between electrodes, and the third layer has at least a portion of a signal processing circuit capable of performing signal processing on the first signal.

20. An electronic device comprising an optical system and a photodetector that receives light transmitted through the optical system, wherein the photodetector includes a first layer containing a first semiconductor layer having a first surface and a second surface opposite to the first surface, a second layer containing a second semiconductor layer having a third surface and a fourth surface opposite to the third surface, and stacked on the first layer such that the first surface and the fourth surface face each other, a photoelectric conversion element provided on the first semiconductor layer, a readout circuit having a first transistor provided on the third surface side of the second semiconductor layer and capable of outputting a first signal based on the charge converted by the photoelectric conversion element, a first contact provided on the third surface side of the second semiconductor layer, and a second contact provided on the fourth surface side of the second semiconductor layer.

21. A semiconductor device comprising: a first layer including a first semiconductor layer having a first surface and a second surface opposite to the first surface; a second layer including a second semiconductor layer having a third surface and a fourth surface opposite to the third surface, the second layer being stacked on the first layer such that the first surface and the fourth surface face each other; a first active element provided on the first semiconductor layer; a circuit having a first transistor provided on the third surface side of the second semiconductor layer and electrically connectable to the first active element; a first contact provided on the third surface side of the second semiconductor layer; and a second contact provided on the fourth surface side of the second semiconductor layer, wherein the second contact is electrically connected to the first gate electrode of the first transistor.

22. The semiconductor device according to claim 21, wherein the first transistor has a first gate insulating film and a first gate electrode provided on the third surface side of the second semiconductor layer so as to sandwich a part of the second semiconductor layer, and the second contact is electrically connected to the first gate electrode of the first transistor.

23. The semiconductor device according to claim 21, wherein the first contact is electrically connected to the first gate electrode of the first transistor.

24. The semiconductor device according to claim 21, wherein the first transistor has a source region and a drain region provided in the second semiconductor layer, and the second contact is electrically connected to the source region or the drain region of the first transistor.

25. The semiconductor device according to claim 21, wherein the first contact and the second contact are electrically connected to each other in the second semiconductor layer.

26. The semiconductor device according to claim 21, wherein the second contact is provided so as to sandwich a part of the second semiconductor layer.

27. The semiconductor device according to claim 21, wherein the second contact is electrically connected to a signal line or power line included in a wiring layer provided on the fourth surface side of the second semiconductor layer.

28. The semiconductor device according to claim 21, wherein the first active element includes a second transistor, and the first transistor and the second transistor are arranged perpendicularly along the stacking direction of the first and second layers.

29. Electronic device comprising a semiconductor device, the semiconductor device comprising: a first layer including a first semiconductor layer having a first surface and a second surface opposite to the first surface; a second layer including a second semiconductor layer having a third surface and a fourth surface opposite to the third surface, the second layer being stacked on the first layer such that the first surface and the fourth surface face each other; a first active element provided on the first semiconductor layer; a circuit having a first transistor provided on the third surface side of the second semiconductor layer and electrically connectable to the first active element; a first contact provided on the third surface side of the second semiconductor layer; and a second contact provided on the fourth surface side of the second semiconductor layer, the second contact being electrically connected to the first gate electrode of the first transistor.

Images