Memory element, memory device, memory system, and computation device

Abstract

In order to reduce the element area of a memory element, a memory element according to the present disclosure comprises a storage layer in which the magnetization direction is variable, a reference layer in which the magnetization direction is fixed, and a tunnel barrier layer that is arranged between the storage layer of the memory element and the reference layer of the memory element. The storage layer of the memory element is provided with a plurality of magnetization regions which are obtained by dividing the storage layer of the memory element in the surface direction, each of which has perpendicular magnetic anisotropy, and which are composed of an Mn-based alloy.

Description

Memory element, memory device, memory system, and arithmetic unit

[0001] This disclosure relates to memory elements, memory devices, memory systems, and arithmetic units.

[0002] In magnetoresistive random access memory (MRAM) using magnetoresistive elements, memory elements have been proposed that improve storage density by multi-leveling the recorded bits. For example, a memory element has been proposed that has a magnetized fixed layer, a non-magnetic layer provided on one surface of the magnetized fixed layer, a first region and a second region in which the magnetization is oriented in different directions, and a magnetic domain wall disposed between the first region and the second region (see, for example, Patent Document 1). In this memory element, the magnetic domain wall is moved by passing an electric current through the second region, and the ratio of the first region and the second region is changed to multi-leveling the recorded bits.

[0003] Japanese Patent Publication No. 2018-182291

[0004] However, the conventional technology described above requires a terminal for current to flow in the second region, resulting in a problem where the memory element becomes a three-terminal element, increasing the element area.

[0005] Therefore, this disclosure proposes a memory element capable of reducing element area, as well as a memory device, memory system, and arithmetic device using the memory element.

[0006] The memory element of this disclosure comprises a storage layer with a variable magnetization direction, a reference layer with a fixed magnetization direction, and a tunnel barrier layer disposed between the storage layer and the reference layer, wherein the storage layer comprises a plurality of magnetization regions, each of which is a region obtained by dividing the storage layer in the planar direction and has perpendicular magnetic anisotropy, and is made of a Mn-based alloy.

[0007] This figure shows an example configuration of a memory device according to the present disclosure. This figure shows an example configuration of a memory element according to the present disclosure. This figure shows an example configuration of a storage layer according to the present disclosure. This figure shows an example configuration of a storage layer according to the present disclosure. This figure shows an example of the characteristics of a memory element according to the present disclosure. This figure shows another example of the characteristics of a memory element according to the present disclosure. This figure shows another example of the characteristics of a memory element according to the present disclosure. This figure shows another example of the characteristics of a memory element according to the present disclosure. This figure shows another example of the configuration of a memory element according to the present disclosure. This figure shows another example of the configuration of a memory element according to the present disclosure. This figure shows an example of the configuration of a memory element according to the second embodiment of the present disclosure. This figure shows another This figure shows another example configuration of the memory element according to the second embodiment of this disclosure. This figure shows another example configuration of the memory element according to the second embodiment of this disclosure. This figure shows an example of the processing procedure for the write process according to the third embodiment of this disclosure. This figure shows an example of the processing procedure for the write process according to the third embodiment of this disclosure. This figure shows an example of the write process according to the third embodiment of this disclosure. This figure shows another example of the processing procedure for the write process according to the third embodiment of this disclosure. This figure shows an example of the write process according to the third embodiment of this disclosure. This figure shows another example of the processing procedure for the write process according to the third embodiment of this disclosure. This figure shows another example of the write process according to the third embodiment of this disclosure. This figure shows another example of the processing procedure for the write process according to the third embodiment of this disclosure. This figure shows another example of the write process according to the third embodiment of this disclosure.This figure shows another example of the processing procedure for the write process according to the third embodiment of this disclosure. This figure shows another example of the write process according to the third embodiment of this disclosure. This figure shows an example of the configuration of a memory system according to the fourth embodiment of this disclosure. This figure shows an example of the configuration of a memory system according to the fourth embodiment of this disclosure. This figure shows an example of the operation of a data conversion circuit according to the fourth embodiment of this disclosure. This figure shows an example of the operation of a data conversion circuit according to the fourth embodiment of this disclosure. This figure shows another example of the operation of a data conversion circuit according to the fourth embodiment of this disclosure. This figure shows another example of the operation of a data conversion circuit according to the fourth embodiment of this disclosure. This figure shows an example of the configuration of a memory system according to the fifth embodiment of this disclosure. This figure shows an example of the configuration of an error correction circuit according to the fifth embodiment of this disclosure. This figure shows another example of the configuration of an error correction circuit according to the fifth embodiment of this disclosure. This figure shows an example of the configuration of an arithmetic unit according to the sixth embodiment of this disclosure. This figure shows an example of the configuration of an arithmetic unit according to the sixth embodiment of this disclosure. This figure shows another example of the configuration of an arithmetic unit according to the sixth embodiment of this disclosure. This figure shows an example of the configuration of an AI function device according to the seventh embodiment of this disclosure. This figure shows an example of the configuration of an AI function device according to the seventh embodiment of this disclosure. This figure shows an example of the configuration of an error correction decoding device according to the seventh embodiment of this disclosure. This figure shows an example of the configuration of an error correction decoding device according to the seventh embodiment of this disclosure. This figure shows an example configuration of a computing system according to the eighth embodiment of this disclosure. This figure shows an example configuration of a memory computing device according to the eighth embodiment of this disclosure. This figure shows an example configuration of a computing system according to the eighth embodiment of this disclosure. This figure shows an example of the processing procedure for arithmetic processing in a computing system according to the eighth embodiment of this disclosure. This figure shows an example of arithmetic processing in a computing system according to the eighth embodiment of this disclosure. This figure shows another example configuration of a memory system according to the eighth embodiment of this disclosure. This figure shows another example configuration of a computing device according to the eighth embodiment of this disclosure. This figure shows another example of the processing procedure for arithmetic processing in a computing system according to the eighth embodiment of this disclosure.

[0008] Embodiments of the present disclosure will be described in detail below with reference to the drawings. The description will be in the following order. In each of the following embodiments, the same parts will be denoted by the same reference numerals, and redundant descriptions will be omitted. 1. First Embodiment 2. Second Embodiment 3. Third Embodiment 4. Fourth Embodiment 5. Fifth Embodiment 6. Sixth Embodiment 7. Seventh Embodiment 8. Eighth Embodiment

[0009] (1. First Embodiment) <Configuration of Memory Device> Figure 1 is a diagram showing an example configuration of a memory device according to the present disclosure. The same figure is a block diagram showing an example configuration of the memory device 1. The memory device 1 comprises a memory cell array 10, a word line control circuit 20, a bit line control circuit 30, a source line control circuit 40, a read circuit 50, a read voltage generation circuit 60, a write circuit 80, and a control unit 90.

[0010] The memory cell array 10 is configured in which memory cells 100 for storing data are arranged in a two-dimensional matrix. Each memory cell 100 includes a memory element 120 and a cell transistor 110.

[0011] The memory element 120 is a magnetoresistive element. This memory element 120 has a magnetic tunnel junction (MTJ) structure in which a tunnel barrier layer is sandwiched between two magnetic layers (a memory layer and a reference layer). The resistance value of the memory element 120 changes depending on the magnetization direction of these two magnetic layers. Specifically, the memory element 120 becomes a high-resistance state when the magnetization directions of these two ferromagnetic layers are different, and a low-resistance state when the magnetization directions are the same. The state in which the magnetization directions are the same is called a parallel state, and the state in which the magnetization directions are different is called an anti-parallel state. This magnetization direction can be changed by applying a write voltage to the MTJ element. As will be described later, the memory element is a multi-level memory element having a high-resistance state, a low-resistance state, and an intermediate resistance state which is an intermediate resistance between at least one high-resistance state and a low-resistance state.

[0012] The cell transistor 110 is connected to one end of the memory element 120 and controls the application of voltage to the memory element 120. For example, an n-channel MOS transistor can be used for this cell transistor 110.

[0013] The memory cell array 10 is equipped with word lines 11, bit lines 12, and source lines 13. The word lines 11 are composed of multiple word lines WL. The bit lines 12 are composed of multiple bit lines BL. The source lines 13 are composed of multiple source lines SL. The word lines WL and bit lines BL are wirings that transmit control signals to the memory cell 100. The source lines SL are wirings that transmit signals from the memory cell 100. Multiple word lines WL are wired in the row direction, and multiple bit lines BL and source lines SL are wired in the column direction.

[0014] The word line control circuit 20 outputs a control signal to the word line WL selected by the control unit 90.

[0015] The bit line control circuit 30 outputs a control signal to the bit line BL selected by the control unit 90.

[0016] The source line control circuit 40 transmits the signal of the source line SL selected by the control unit 90 to the readout circuit 50.

[0017] The read circuit 50 reads data by detecting the current flowing through the memory cell 100 during reading. The read data is output to the control unit 90.

[0018] The read voltage generation circuit 60 is a circuit that generates the voltage applied when reading from the memory cell 100.

[0019] <Memory Element Configuration> Figure 2 is a diagram showing an example configuration of a memory element according to the present disclosure. The same figure is a schematic cross-sectional view showing an example configuration of a memory element 120. The memory element 120 comprises an electrode 121, a reference layer 122, a tunnel barrier layer 130, a storage layer 140, and an electrode 128. Electrodes 121 and 128 are electrodes that apply a voltage to the magnetic layer of the memory element 120. Electrode 121 corresponds to a lower layer electrode and is an electrode that is positioned close to the substrate on which the memory element 120 is placed. Electrodes 121 and 128 can be made of conductive materials such as Al, Cr, Fe, Co, Cu, Rh, Ru, Ta, Pd, Ag, Ir, Pt, Au, Mo, W, and TiN.

[0020] The reference layer 122 is a layer having perpendicular magnetic anisotropy and a fixed (invariant) magnetization direction. This reference layer 122 can be made of, for example, Fe, Co, CoFe, CoFeB, NiFe, CoPt, and CoNi. Alternatively, the reference layer 122 can be a composite antiferromagnetic structure in which multiple ferromagnetic layers are stacked via a non-magnetic layer. As materials for the ferromagnetic layers constituting this composite antiferromagnetic magnetic reference layer, for example, Fe, Co, CoFe, CoNi, CoPt, and CoFeB can be used. As materials for the non-magnetic layers, for example, Cr, Cu, Mo, Ru, Re, Ir, W, and Os can be used. Furthermore, by utilizing magnetic pinning with an antiferromagnetic layer, the magnetization direction of the ferromagnetic layer can be fixed. Examples of materials for the antiferromagnetic layer include FeMn, PtMn, PtCrMn, NiMn, IrMn, NiO, and Fe ２ O ３ Examples of magnetic materials include the following. Furthermore, non-magnetic elements such as Ag, Cu, Au, Al, Si, Bi, Ta, B, C, O, N, Pd, Pt, Zr, Hf, Ir, W, Mo, and Nb can be added to these magnetic materials.

[0021] The tunnel barrier layer 130 is positioned between the reference layer 122 and the storage layer 140, separating the reference layer 122 and the storage layer 140. This tunnel barrier layer 130 can be composed of, for example, an oxide of at least one element selected from the group Mg, Al, Ti, Si, Zn, Zr, Hf, Ta, Bi, Cr, Ga, La, Gd, Sr, and Ba. Alternatively, the tunnel barrier layer 130 can be composed of, for example, a nitride of at least one element selected from the group Mg, Al, Ti, Si, Zn, Zr, Hf, Ta, Bi, Cr, Ga, La, Gd, Sr, and Ba. Furthermore, the tunnel barrier layer 130 can be composed of, for example, MgF ２ , CaF, SrTiO ２ , AllaO ３ It can also be constructed using insulators such as AlNO, dielectrics, and semiconductors. The tunnel barrier layer 130 is preferably configured to be 0.6 nm or larger.

[0022] The memory layer 140 is a layer that has magnetic anisotropy and a variable magnetization direction. The details of the configuration of the memory layer 140 will be explained using Figures 3A and 3B.

[0023] <Configuration of the Memory Layer> Figures 3A and 3B show examples of the configuration of a memory layer according to the present disclosure. Figures 3A and 3B show examples of the configuration of a memory layer 140. Figure 3A is a schematic diagram showing an example of the configuration of a memory element 120 including a memory layer 140. The memory layer 140 comprises a plurality of magnetized regions 149, which are regions divided in the planar direction of the memory layer 140. The regions separated by thin lines in the figure represent magnetized regions 149. The magnetized regions 149 are made of a Mn-based alloy. Furthermore, each of the plurality of magnetized regions 149 has perpendicular magnetic anisotropy, and the direction of magnetization can be changed individually.

[0024] Figure 3B is a cross-sectional view showing an example of the configuration of the memory layer 140. The tunnel barrier layer 130 and the reference layer 122 are further shown in the same figure. As described above, the magnetization direction of each magnetization region 149 can be changed individually. The white arrows in the figure represent the magnetization direction. When the magnetization direction of almost all magnetization regions 149 of the reference layer 122 is different from the magnetization direction of the reference layer 122, a complete antiparallel arrangement state is achieved, and the memory element 120 becomes a high-resistance state. When the magnetization direction of almost all magnetization regions 149 of the reference layer 122 is the same as the magnetization direction of the reference layer 122, a complete parallel arrangement state is achieved, and the memory element 120 becomes a low-resistance state.

[0025] On the other hand, if the magnetization direction of some of the magnetization regions 149 differs from the magnetization direction of the reference layer 122, and the magnetization direction of the remaining magnetization regions 149 is the same as that of the reference layer 122, the memory element 120 will be in an intermediate resistance state, taking a resistance value between the high resistance state and the low resistance state. In this case, the memory element 120 will have a resistance value based on the ratio of the magnetization regions 149 with the same magnetization direction as the reference layer 122 and the magnetization regions 149 with a different magnetization direction. In other words, the memory layer 140 of this disclosure can arbitrarily change the distribution of regions that are arranged parallel to the magnetization direction of the reference layer 122 and regions that are arranged antiparallel to the magnetization direction of the reference layer 122.

[0026] Each magnetized region 149 is crystalline, and grain boundaries (magnetic domain walls) exist between the magnetized regions 149. As described above, the memory layer 140 is composed of a Mn-based alloy. Specifically, the memory layer 140 can be composed of FeCoMn, MnGaGe, and Heusler alloys containing Mn.

[0027] As shown in Figure 3A, the memory element 120 can be configured in a cylindrical shape. The storage layer 140 can also be configured in a cylindrical shape. Assuming the shape of the magnetized region 149 is cylindrical, the magnetized region 149 can be configured with a diameter of approximately 1 / 50 of the diameter of the storage layer 140. Furthermore, the magnetized region 149 can be configured with a diameter of 2 to 20 nm. As will be described later, crystallization of the magnetized region 149 can be performed without using boron (B). Therefore, the B content of the storage layer 140 can be reduced to 10 at% or less. In addition, it is preferable for the storage layer 140 to be configured with a thickness of 10 nm or less.

[0028] The direction of magnetization in the magnetization region of the memory layer 140 can be reversed by applying current or voltage to the memory element 120, which includes the memory layer 140. The process of bringing the memory element 120 into a desired resistance state is called writing.

[0029] <Characteristics of the Memory Element> Figure 4 is a diagram showing an example of the characteristics of a memory element according to the embodiment of this disclosure. The diagram shows the change in resistance when a voltage is applied to the memory element 120. As shown in the upper part of the diagram, the change in resistance was measured when a voltage from a voltage source 400 was applied to the memory element 120. In the lower part of the diagram, the horizontal axis represents the applied voltage [V]. The vertical axis represents the resistance of the memory element 120. First, a voltage of -1V is applied to the memory element 120 for initialization. "A" in the diagram represents this state. At this time, almost all magnetization regions 149 of the storage layer 140 become antiparallel. As a result, the memory state of the memory element 120 is erased. When the application of voltage is stopped, the memory element 120 becomes a high-resistance state. "B" in the diagram represents this state.

[0030] Next, writing is performed. Writing can be done by applying a voltage with a different polarity than that used for initialization. When a voltage of 1V is applied, the state transitions to "C" in Figure 4, and almost all magnetized regions 149 of the memory layer 140 become parallel-aligned. After that, when the voltage application is stopped, the memory element 120 enters a low-resistance state. "D" in Figure 4 represents this state.

[0031] When writing, applying a voltage lower than 1V causes a portion of the magnetized regions 149 of the memory layer 140 to transition to a parallel alignment state. For example, applying 0.5V ("E" in Figure 4) causes a portion of the magnetized regions 149 of the memory layer 140 to transition to a parallel alignment state, while the remaining magnetized regions 149 remain in an antiparallel alignment state. When the voltage application is stopped, the memory element 120 takes on a resistance value intermediate between the high-resistance state and the low-resistance state ("F" in Figure 4). Furthermore, by changing the writing voltage, the resistance of the memory element 120 can be changed non-volatilely.

[0032] Figure 5 shows another example of the characteristics of a memory element according to the embodiment of this disclosure. This figure shows the change in resistance when a pulse voltage is applied to the memory element 120. As shown in the upper part of the figure, the change in resistance was measured when a pulse voltage from a pulse voltage source 401 was applied to the memory element 120. The lower part of the figure shows the change in resistance when the pulse width of the pulse voltage applied to the memory element 120 is changed. In the lower part of the figure, the horizontal axis represents the pulse width [ns]. As shown in the figure, a decrease in resistance is observed when the pulse width is around 3ns. In this way, the resistance of the memory element 120 can be changed by keeping the voltage constant and adjusting the pulse width.

[0033] Figure 6 shows another example of the characteristics of a memory element according to the embodiment of this disclosure. Similar to Figure 5, this figure shows the change in resistance when a pulse voltage is applied to the memory element 120. This figure shows the change in resistance when the number of pulses applied to the memory element 120 is changed. In the lower part of this figure, the horizontal axis represents the number of pulses. In this way, the resistance of the memory element 120 can be changed by keeping the voltage and pulse width constant and adjusting the number of pulses applied.

[0034] <Other Configurations of Memory Elements> Figure 7 is a diagram showing other configuration examples of memory elements according to the embodiments of this disclosure. This figure is a cross-sectional view showing an example configuration of the memory element 120, similar to Figure 3B. The memory element 120 in this figure differs from the memory element 120 in Figure 3B in that the reference layer 122, tunnel barrier layer 130, and storage layer 140 are arranged in reverse order.

[0035] FIG. 8 is a diagram illustrating another configuration example of a memory device according to an embodiment of the present disclosure. This figure is a cross-sectional view illustrating a configuration example of the memory device 120, similarly to FIG. 3B. The memory device 120 in this figure differs from the memory device 120 in FIG. 3B in that it includes a storage layer 141 instead of a storage layer 140. The storage layer 141 has a granular structure in which each magnetization region 149 is partitioned by a non-magnetic material 148. Note that the non-magnetic material 148 is an example of the "non-magnetic film" in the present disclosure.

[0036] As described above, the memory device 120 of the present disclosure includes the storage layer 140 having a plurality of magnetization regions 149, thereby enabling multi-level recording bits. This allows the memory device 120 to be a two-terminal device, and can reduce the device area.

[0037] (2. Second Embodiment) The memory device 120 according to the first embodiment described above includes the storage layer 140 having a plurality of magnetization regions 149. In the second embodiment of the present disclosure, variations of the memory device 120 will be described.

[0038] <Configuration of Memory Device> FIG. 9 is a diagram illustrating a configuration example of a memory device according to a second embodiment of the present disclosure. This figure is a schematic cross-sectional view illustrating a configuration example of the memory device 120, similarly to FIG. 3B. The memory device 120 in this figure differs from the memory device 120 in FIG. 3B in that a tunnel barrier layer 131 is disposed instead of the tunnel barrier layer 130.

[0039] The tunnel barrier layer 131 is made of a crystalline material and has a polycrystalline structure including a plurality of crystal grains. In addition, the tunnel barrier layer 131 has a crystal plane with a specific orientation formed on a surface adjacent to the storage layer 142. The tunnel barrier layer 131 is made of, for example, MgO, MgAlO, MgTiO, MgFeO, MgMnO, MgCrO and Al ２ O ３ and can be configured by. By aligning a specific crystal plane on the surface of the tunnel barrier layer 131 in contact with the storage layer 142, crystals in the magnetization regions 149 of the storage layer 142 can be grown.

[0040] FIG. 10 is a diagram illustrating a configuration example of a memory device according to the second embodiment of the present disclosure. This figure is a schematic cross-sectional view illustrating a configuration example of the memory device 120, similar to FIG. 9. The memory device 120 in this figure illustrates an example including a (001)-oriented polycrystalline tunnel barrier layer 132. The tunnel barrier layer 132 can be formed of a rock salt structure material such as MgO, MgAlO, MgTiO, MgFeO, MgMnO, and MgCrO.

[0041] The storage layer 143 in FIG. 10 can be formed of (001)-oriented tetragonal crystal. The storage layer 143 can be formed of, for example, FeCoMn and MnGaGe. Alternatively, the storage layer 143 can be formed of tetragonal Heusler alloys such as CoMnSi, NiMnGa, NiMnSb, NiMnAl, and PtMnSb.

[0042] Note that the reference layer 122, the tunnel barrier layer 132, and the storage layer 143 can be formed by sputter deposition.

[0043] Note that the memory device 120 on the right side of FIG. 10 illustrates an example in which the reference layer 122, the tunnel barrier layer 132, and the storage layer 143 are arranged in reverse order. The same applies to FIGS. 11 to 21 below.

[0044] FIG. 11 is a diagram illustrating another configuration example of a memory device according to the second embodiment of the present disclosure. This figure is a schematic cross-sectional view illustrating a configuration example of the memory device 120, similar to FIG. 10. The memory device 120 in this figure differs from the memory device 120 in FIG. 10 in that it further includes a magnetic layer 124.

[0045] The magnetic layer 124 can be formed using CoFe, CoFeB, Fe, FeB, etc. The magnetic layer 124 may also contain transition metals (Hf, Ta, W, Re, Ir, Pt, Au, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Ti, V, Cr, Mn, Ni, and Cu) and nitrides and oxides of these transition metals. Furthermore, the magnetic layer 124 may be formed using Ir and Os, which are materials that induce a nearby magnetic moment in the magnetic material. The magnetic layer 124 preferably has a thickness of 3.0 nm or less. For example, using a material with high perpendicular magnetic anisotropy, such as CoPt, CoPd, FePt, FePd, and NiCo, as the "magnetic layer" can improve data retention characteristics.

[0046] The magnetic layer 124 is positioned on a side of the memory layer 143 that is not adjacent to the tunnel barrier layer 132. That is, the magnetic layer 124 is positioned adjacent to the memory layer 143. The magnetic layer 124 has perpendicular magnetic anisotropy and can be constructed using a magnetic material such as the material mentioned above. The magnetic layer 124 can also be constructed of a (111) oriented tetragonal crystal, such as FeCoPt.

[0047] Figure 12 is a diagram showing another example configuration of a memory element according to the second embodiment of the present disclosure. This figure, like Figure 11, is a schematic cross-sectional view showing an example configuration of the memory element 120. The memory element 120 in this figure differs from the memory element 120 in Figure 11 in that it further comprises a spacer layer 125.

[0048] The spacer layer 125 is a non-magnetic layer placed between the memory layer 143 and the magnetic layer 124. The spacer layer 125 can be formed using materials such as Mg, Al, Ti, Si, Zn, Zr, Hf, Ta, Bi, Cr, Ga, La, Gd, Sr, Ba, W, Re, Ir, Pt, Au, Nb, Mo, Ru, Rh, Pd, Ag, V, Mn, Cu, and Os. Furthermore, by using high-melting-point materials such as W, Ta, and Mo as the spacer layer between the magnetic layer and the memory layer, it becomes easier to combine magnetic layers and memory layers with different crystal structures and crystal orientations. This improves the degree of freedom in device design for improving characteristics.

[0049] Furthermore, the magnetic layer 124 in Figure 12 has perpendicular magnetic anisotropy and can be made of a magnetic material such as the material described above. In addition, the magnetic layer 124 can also be made of a (111) oriented tetragonal crystal, such as FeCoPt.

[0050] Figure 13 is a diagram showing another example configuration of a memory element according to the second embodiment of the present disclosure. This figure, like Figure 10, is a schematic cross-sectional view showing an example configuration of the memory element 120. The memory element 120 in this figure differs from the memory element 120 in Figure 10 in that it further comprises an interface control layer 123.

[0051] The interface control layer 123 is positioned between the tunnel barrier layer 132 and the memory layer 143 to control the interface of the memory layer 143. The interface control layer 123 can be made of a magnetic alloy having a (001) oriented body-centered cubic (bcc) lattice structure, such as FeCo and FeAl. By using the "interface control layer," the perpendicular magnetic anisotropy and magnetoresistivity ratio of the "memory layer" can be improved.

[0052] Figure 14 is a diagram showing another example configuration of a memory element according to the second embodiment of the present disclosure. This figure, like Figure 10, is a schematic cross-sectional view showing an example configuration of the memory element 120. The memory element 120 in this figure differs from the memory element 120 in Figure 10 in that it further comprises a magnetic layer 124 and an interface control layer 123.

[0053] Furthermore, the magnetic layer 124 in Figure 14 has perpendicular magnetic anisotropy and can be made of a magnetic material such as the material mentioned above. In addition, the magnetic layer 124 can also be made of a (111) oriented tetragonal crystal, such as FeCoPt.

[0054] Figure 15 is a diagram showing another example configuration of a memory element according to the second embodiment of the present disclosure. This figure, like Figure 10, is a schematic cross-sectional view showing an example configuration of the memory element 120. The memory element 120 in this figure differs from the memory element 120 in Figure 10 in that it further comprises a magnetic layer 124, a spacer layer 125, and an interface control layer 123.

[0055] Note that the magnetic layer 124 in FIG. 15 has perpendicular magnetic anisotropy and can be formed of a magnetic material such as the above-mentioned materials. The magnetic layer 124 can also be formed of (111)-oriented tetragonal crystal, for example, FeCoPt or the like.

[0056] FIG. 16 is a diagram showing another configuration example of a memory element according to a second embodiment of the present disclosure. Similarly to FIG. 9, this figure is a schematic cross-sectional view illustrating a configuration example of the memory element 120. The memory element 120 in this figure illustrates an example including a (111)-oriented polycrystalline tunnel barrier layer 133. The tunnel barrier layer 133 can be formed of a rock salt structure material such as MgO, MgAlO, MgTiO, MgFeO, MgMnO, and MgCrO.

[0057] The storage layer 144 in FIG. 16 can be formed of (111)-oriented tetragonal crystal. The storage layer 144 can be formed of, for example, FeCoMn and MnGaGe. Further, the storage layer 144 can also be formed of tetragonal Heusler alloys such as CoMnSi, NiMnGa, NiMnSb, NiMnAl, and PtMnSb.

[0058] Further, the tunnel barrier layer 133 may be made of Al ２ O ３ or other corundum structure materials. For example, a (0001)-oriented polycrystalline tunnel barrier layer 133 having a corundum structure can also be used. In this case, the (111)-oriented tetragonal storage layer 144 can be formed on the (0001) plane of the tunnel barrier layer 133.

[0059] Note that the reference layer 122, the tunnel barrier layer 133, and the storage layer 144 can be formed by sputter deposition.

[0060] Furthermore, the memory element 120 in Figure 16 may also include a magnetic layer 124, similar to that in Figure 11. This magnetic layer 124 has perpendicular magnetic anisotropy and is positioned adjacent to the storage layer 144, and can be constructed using magnetic materials such as those mentioned above. The magnetic layer 124 may also be constructed of a (111) oriented tetragonal crystal, such as FeCoPt. Moreover, the memory element 120 in Figure 16 may also include a spacer layer 125, similar to that in Figure 12. The spacer layer 125 is a non-magnetic layer positioned between the storage layer 144 and the magnetic layer 124. The spacer layer can be formed using Mg, Al, Ti, Si, Zn, Zr, Hf, Ta, Bi, Cr, Ga, La, Gd, Sr, Ba, W, Re, Ir, Pt, Au, Nb, Mo, Ru, Rh, Pd, Ag, V, Mn, Ni, Cu, and Os, etc.

[0061] Figure 17 is a diagram showing another example configuration of a memory element according to the second embodiment of the present disclosure. This figure, like Figure 16, is a schematic cross-sectional view showing an example configuration of the memory element 120. The memory element 120 in this figure differs from the memory element 120 in Figure 16 in that it further comprises an interface control layer 129.

[0062] The interface control layer 129 is positioned between the tunnel barrier layer 133 and the memory layer 144 to control the interface of the memory layer 144. The interface control layer 129 can be made of a magnetic alloy having a (111)-oriented face-centered cubic (fcc) lattice structure, such as FeCo and FeNi.

[0063] Furthermore, the tunnel barrier layer 133 can be composed of rock salt structural materials such as MgO, MgAlO, MgTiO, MgFeO, MgMnO, and MgCrO. Also, the tunnel barrier layer 133 can be Al ２ O ３ It can also be constructed from corundum structural materials such as those mentioned above.

[0064] Furthermore, the memory element 120 in Figure 17 may also include a magnetic layer 124, similar to that in Figure 11. This magnetic layer 124 has perpendicular magnetic anisotropy and is positioned adjacent to the storage layer 144, and can be constructed using magnetic materials such as those mentioned above. The magnetic layer 124 may also be constructed of a (111) oriented tetragonal crystal, such as FeCoPt. Moreover, the memory element 120 in Figure 17 may also include a spacer layer 125, similar to that in Figure 12. The spacer layer 125 is a non-magnetic layer positioned between the storage layer 144 and the magnetic layer 124. The spacer layer can be formed using Mg, Al, Ti, Si, Zn, Zr, Hf, Ta, Bi, Cr, Ga, La, Gd, Sr, Ba, W, Re, Ir, Pt, Au, Nb, Mo, Ru, Rh, Pd, Ag, V, Mn, Cu, and Os, etc.

[0065] Figure 18 is a diagram showing another example configuration of a memory element according to the second embodiment of the present disclosure. This figure, like Figure 9, is a schematic cross-sectional view showing an example configuration of the memory element 120. The memory element 120 in this figure shows an example comprising a (0001) oriented polycrystalline tunnel barrier layer 134. The tunnel barrier layer 134 is Al ２ O ３ It can be constructed from corundum structural materials such as the above.

[0066] The memory layer 144 in Figure 18 can be constructed of a (0001) oriented hexagonal crystal. The memory layer 144 can be constructed of, for example, FeCoMn and MnGaGe. Alternatively, the memory layer 144 can be constructed of tetragonal Heusler alloys such as CoMnSi, NiMnGa, NiMnSb, NiMnAl, and PtMnSb.

[0067] Furthermore, the tunnel barrier layer 134 can also be made of rock salt structure materials such as MgO, MgAlO, MgTiO, MgFeO, MgMnO, and MgCrO. For example, a hexagonal memory layer 144 can be made on the (111) plane of a (111) oriented polycrystalline tunnel barrier layer 134 having a rock salt structure. In this case, the configuration can also include the interface control layer 129 shown in Figure 17.

[0068] The reference layer 122, tunnel barrier layer 134, and memory layer 144 can be formed by sputter deposition.

[0069] Figure 19 is a diagram showing another example configuration of a memory element according to the second embodiment of the present disclosure. This figure, like Figure 18, is a schematic cross-sectional view showing an example configuration of the memory element 120. The memory element 120 in this figure differs from the memory element 120 in Figure 18 in that it further comprises a magnetic layer 124.

[0070] The magnetic layer 124 has perpendicular magnetic anisotropy and is positioned adjacent to the memory layer 144, and can be constructed using a magnetic material such as the aforementioned material. The magnetic layer 124 can also be constructed of a (111) oriented tetragonal crystal, such as FeCoPt. Furthermore, the memory element 120 in Figure 19 may also further include a spacer layer 125, similar to Figure 12.

[0071] Figure 20 is a diagram showing another example configuration of a memory element according to the second embodiment of the present disclosure. This figure, like Figure 16, is a schematic cross-sectional view showing an example configuration of the memory element 120. The memory element 120 in this figure differs from the memory element 120 in Figure 18 in that it further comprises an interface control layer 129.

[0072] Figure 21 is a diagram showing another example configuration of a memory element according to the second embodiment of the present disclosure. This figure, like Figure 20, is a schematic cross-sectional view showing an example configuration of the memory element 120. The memory element 120 in this figure differs from the memory element 120 in that it further comprises a magnetic layer 124. The memory element 120 in this figure may also further comprise a spacer layer 125, similar to Figure 12.

[0073] The configuration of the memory element 120 other than that described above is the same as that of the memory element 120 in the first embodiment of this disclosure, so a description will be omitted.

[0074] Thus, the memory element 120 of the second embodiment of this disclosure can crystallize the Mn-based alloy memory layer by using a tunnel barrier layer 133, etc., made of a crystalline material.

[0075] (3. Third Embodiment) The part relating to writing to and reading from the memory element 120 in the memory device 1 described above will be explained.

[0076] Figure 22 is a diagram showing an example configuration of a memory device according to the third embodiment of this disclosure. The figure shows an extracted portion of the memory cell array 10 of the memory device 1.

[0077] The write circuit 80 is located for each bit line BL. The write circuit 80 generates a write voltage corresponding to the write data from the control unit 90 and applies it to the memory cell 100. The bit line control circuit 30 includes a plurality of switches 31. The switches 31 are located for each bit line BL and switch the connection destination of the bit line BL to either the write circuit 80, the read voltage generation circuit 60, or an isolated contact. The source line control circuit 40 includes a plurality of switches 41. The switches 41 are located for each source line SL and switch the connection destination of the source line SL to either the read circuit 50 or a common ground line. The read circuit 50 includes a plurality of analog-to-digital conversion circuits 51. Note that in Figure 22, "analog-to-digital conversion circuit" is written as "ADC". The analog-to-digital conversion circuit 51 is a current-input type analog-to-digital conversion circuit 51 that converts the current from the source line SL into a digital signal.

[0078] In Figure 22, a write circuit 80 is provided for each bit line BL, but a single write circuit 80 may control writing to multiple bit line BLs. In that case, a bit line BL selection circuit connected to the write circuit 80 is provided to sequentially select the desired bit line BLs and perform writing. Also, in Figure 22, an analog-to-digital conversion circuit 51 is provided for each source line SL, but a single analog-to-digital conversion circuit 51 may perform reading to multiple source lines SLs. In that case, a source line SL selection circuit connected to the analog-to-digital conversion circuit 51 is provided to sequentially select the desired source lines SLs and perform reading.

[0079] During writing, switch 31 connects the bit line BL to the writing circuit 80, and switch 41 connects the source line SL to the common ground line. Next, the writing circuit 80 generates a write voltage and applies it to the bit line BL. At this time, an ON signal is output to the word line WL connected to the desired memory cell 100. Here, the ON signal is a signal that causes the cell transistor 110 of the memory cell 100 to conduct. As a result, the write voltage is applied to the memory element 120 of the selected memory cell 100, and writing is performed.

[0080] During reading, switch 31 connects the bit line BL to the read voltage generation circuit 60, and switch 41 connects the source line SL to the read circuit 50. Next, the read voltage generation circuit 60 generates a read voltage and applies it to the bit line BL. At this time, an ON signal is output to the word line WL connected to the desired memory cell 100. As a result, the read voltage is applied to the memory element 120 of the selected memory cell 100, and a current corresponding to the resistance value of the memory element 120 flows through the source line SL. The analog-to-digital conversion circuit 51 converts the current in the source line SL into a digital signal and outputs it to the control unit 90 as read data.

[0081] <Writing Process> Figure 23 is a diagram showing an example of the processing procedure for the writing process according to the third embodiment of this disclosure. The figure is a flowchart showing the processing procedure for the writing process in the memory device 1.

[0082] First, initialization is performed (step S101). This can be done by arranging the memory elements 120 in an anti-parallel configuration. Next, the write voltage is set (step S102). This can be done by setting a voltage to make the memory elements 120 have a resistance value corresponding to the data to be written. Next, the write voltage is applied to the memory elements 120 (step S103). Note that the memory elements 120 can also be initialized to a parallel configuration by setting the voltage.

[0083] Figure 24 is a diagram showing an example of a write process according to the third embodiment of this disclosure. This figure is a timing diagram representing the write process in the memory device 1. In this figure, "write data" represents the value input to the write circuit 80. In the example shown in this figure, this value is represented by a 3-bit signed hexadecimal number. The bit width (3 bits) and signal values ​​(0x7, 0x0, 0x1, etc.) in this figure are examples only. Memory elements with many intermediate resistance states between the high-resistance state and the low-resistance state shown in Figures 4, 5, and 6 are represented with a larger bit width, and memory elements with fewer intermediate resistance states are represented with a smaller bit width. In the case of conventional magnetoresistive elements that do not have intermediate resistance states, i.e., only high-resistance and resistance states, they can be represented with a 1-bit width (1: high-resistance state, 0: low-resistance state). "Vb" represents the voltage of the bit line BL. "Vw" represents the voltage of the word line WL. "Rm" represents the resistance of the memory element 120.

[0084] During the period T1 to T2, the memory element 120 is initialized. The data "0x7" is input to the writing circuit 80. The writing circuit 80 generates a negative polarity initialization voltage and outputs it to the bit line BL. An ON signal is also input to the word line WL. As a result, the memory element 120 is initialized and enters a high-resistance state.

[0085] During the period T3 to T4, the write data (0x1) is input to the write circuit 80. The write circuit 80 generates a positive write voltage and outputs it to the bit line BL. An ON signal is also input to the word line WL. As a result, the write voltage is applied to the memory element 120, bringing it to the desired resistance state. The dashed line in Figure 24 represents the write voltage when the memory element 120 is in a low resistance state. The dashed line represents the write voltage when the memory element 120 is in an intermediate resistance state.

[0086] Figure 25 is a diagram showing another example of the processing procedure for a write operation according to the third embodiment of this disclosure. This figure is a flowchart showing the processing procedure for a write operation in the memory device 1, similar to Figure 23. The process in this figure differs from the process in Figure 23 in that it performs a read operation before writing.

[0087] First, data is read from the memory cell 100 (step S111). Next, it is determined whether the read value matches the data to be written (step S112). If they do not match (step S112, No), the write voltage is set (step S113), and the write voltage is applied to the memory element 120 (step S114). After that, the process is terminated. On the other hand, if the read value matches the data to be written in step S112 (step S112, Yes), the process is terminated.

[0088] Figure 26 is a diagram showing an example of a write process according to the third embodiment of this disclosure. The same figure is a timing diagram representing the write process in the memory device 1. The same figure is a timing diagram corresponding to the process in Figure 25.

[0089] During the period T5 to T6, the write data (0x1) is input to the write circuit 80. The write circuit 80 generates a positive write voltage and outputs it to the bit line BL. An ON signal is also input to the word line WL. As a result, the write voltage is applied to the memory element 120, bringing it to the desired resistance value state.

[0090] <Other Examples of Writing Processes> Figure 27 is a diagram showing another example of the writing process procedure according to the third embodiment of this disclosure. This figure, like Figure 23, is a flowchart showing the writing process procedure in the memory device 1. The process in this figure differs from the process in Figure 23 in that the writing circuit 80 generates the writing current. Also, as in Figure 25, it is possible to generate the writing current after reading before writing.

[0091] First, initialization is performed (step S121). Next, the write current is set (step S122). This can be done by setting a current to make the memory element 120 have a resistance value corresponding to the data to be written. Next, the write current is applied to the memory element 120 (step S123).

[0092] Figure 28 is a diagram showing another example of the write process according to the third embodiment of this disclosure. This figure is a timing diagram representing the write process in the memory device 1. This figure is a timing diagram corresponding to the process in Figure 27. In this figure, "Ib" represents the current of the bit line BL. Otherwise, the same notation as in Figure 24 is used.

[0093] During the period T1 to T2, the memory element 120 is initialized. The data "0x7" is input to the writing circuit 80. The writing circuit 80 generates a negative polarity initialization current and outputs it to the bit line BL. An ON signal is also input to the word line WL. As a result, the memory element 120 is initialized and enters a high-resistance state.

[0094] During the period T3 to T4, the write data (0x1) is input to the write circuit 80. The write circuit 80 generates a positive write current and outputs it to the bit line BL. An ON signal is also input to the word line WL. As a result, the write current flows through the memory element 120, bringing it to the desired resistance state. The dashed line in Figure 28 represents the write current when the memory element 120 is in a low resistance state. The dashed line represents the write current when the memory element 120 is in an intermediate resistance state.

[0095] Figure 29 is a diagram showing another example of the processing procedure for a write operation according to the third embodiment of this disclosure. This figure, like Figure 23, is a flowchart showing the processing procedure for a write operation in the memory device 1. The process in this figure differs from the process in Figure 23 in that the write circuit 80 generates the write pulse voltage. Also, as in Figure 25, it is possible to generate the pulse voltage after reading before writing.

[0096] First, initialization is performed (step S131). Next, the pulse width is set (step S132). This can be done by setting the pulse width to make the memory element 120 have a resistance value corresponding to the data to be written. Next, the write pulse voltage is applied to the memory element 120 (step S133).

[0097] Figure 30 is a diagram showing another example of the write process according to the third embodiment of this disclosure. This figure is a timing diagram representing the write process in the memory device 1. This figure is a timing diagram corresponding to the process in Figure 29.

[0098] During the period T1 to T2, the memory element 120 is initialized. The data "0x7" is input to the writing circuit 80. The writing circuit 80 generates a negative polarity initialization voltage and outputs it to the bit line BL. An ON signal is also input to the word line WL. As a result, the memory element 120 is initialized and enters a high-resistance state.

[0099] During the period T3 to T4, the write data (0x1) is input to the write circuit 80. The write circuit 80 generates a pulse voltage with a set pulse width and outputs it to the bit line BL. An ON signal is also input to the word line WL. As a result, a pulse voltage is applied to the memory element 120, bringing it to the desired resistance state. In Figure 30, the dashed line represents the pulse width when the memory element 120 is set to a low resistance state. The dashed line represents the pulse width when the memory element 120 is set to an intermediate resistance state.

[0100] Figure 31 is a diagram showing another example of the processing procedure for a write operation according to the third embodiment of the present disclosure. This figure, like Figure 29, is a flowchart showing the processing procedure for a write operation in the memory device 1. The process in this figure differs from the process in Figure 29 in that the write circuit 80 generates a write pulse voltage with a number of pulses corresponding to the data to be written. Also, as in Figure 25, it is possible to perform a read operation before writing and then generate a write pulse voltage with a number of pulses corresponding to the data to be written.

[0101] First, initialization is performed (step S141). Next, the number of pulses is set (step S142). This can be done by setting the number of pulses required to set the resistance value of the memory element 120 according to the data to be written. Next, the write pulse voltage is applied to the memory element 120 (step S143). Next, it is determined whether the set number of pulses is met (step S144). As a result, if the set number of pulses is met (step S144, Yes), the process ends; if the set number of pulses is not met (step S144, No), the process returns to step S143.

[0102] Figure 32 is a diagram showing another example of the write process according to the third embodiment of the present disclosure. This figure is a timing diagram representing the write process in the memory device 1. This figure is a timing diagram corresponding to the process in Figure 30.

[0103] During the period T1 to T2, the memory element 120 is initialized. The data "0x7" is input to the writing circuit 80. The writing circuit 80 generates a predetermined number of negative pulse voltages and outputs them to the bit line BL. An ON signal is also input to the word line WL. As a result, the memory element 120 is initialized and enters a high-resistance state.

[0104] During the period T3 to T4, the write data (0x1) is input to the write circuit 80. The write circuit 80 generates a pulse voltage with a set number of pulses and outputs it to the bit line BL. An ON signal is also input to the word line WL. As a result, a pulse voltage is applied to the memory element 120, bringing it to the desired resistance state. In Figure 32, the dashed line represents the number of pulses required to bring the memory element 120 to a low resistance state. The dashed line represents the number of pulses required to bring the memory element 120 to an intermediate resistance state.

[0105] Thus, the memory device 1 of the third embodiment of this disclosure can multi-level record bits of the memory element 120 of the memory cell 100 by using the write circuit 80 and the read circuit 50.

[0106] (4. Fourth Embodiment) An example of applying the above-described memory device 1 to a memory system will be described.

[0107] <Memory System Configuration> Figure 33 is a diagram showing an example configuration of a memory system according to the fourth embodiment of this disclosure. The same figure is a block diagram showing an example configuration of the memory system 2. The memory system 2 is obtained by adding an interface unit 3, a word line address decoder 71, a bit line address decoder 72, and data conversion circuits 73 and 74 to the memory device 1 of Figure 1. In this embodiment, an example having a memory interface connected to a host system is described, but the memory system 2 can be applied to other forms of memory systems. For example, the memory system 2 can also be applied to embedded memory, mixed memory, and mixed storage having I / O that connects to the internal bus or logic circuits of a SoC (System on a chip).

[0108] The interface unit 3 is responsible for communication with the host system and other devices that use the memory system 2.

[0109] The control unit 90 in Figure 33 further communicates with the host system, etc. The control unit 90 receives commands from the host system, etc., and controls data writing and reading based on the received commands. The control unit 90 outputs the write and read addresses to the word line address decoder 71 and the bit line address decoder 72.

[0110] The word line address decoder 71 selects the word line WL of the memory cell array 10 based on a control signal from the control unit 90.

[0111] The bit line address decoder 72 selects the bit line BL of the memory cell array 10 based on the control signal from the control unit 90.

[0112] The data conversion circuit 73 converts the written data to be compatible with the multi-level recording bits of the memory element 120. Note that the data conversion circuit 73 is an example of the "input data conversion circuit" described herein.

[0113] The data conversion circuit 74 converts the multi-level read data back into normal data. The data conversion circuit 74 is an example of the "read data conversion circuit" described herein.

[0114] Figure 34 is a diagram showing an example configuration of a memory system according to the fourth embodiment of this disclosure. The diagram shows an excerpt of the peripheral portion of the memory cell array 10 of the memory system 2. The memory system 2 in the diagram is equivalent to the memory device 1 in Figure 22 with the addition of a data conversion circuit 73 for converting written data and a data conversion circuit 74 for converting read data.

[0115] The read circuit 50 in Figure 34 includes multiple sense amplifiers 52. In Figure 34, "sense amplifier" is abbreviated as "SA". The sense amplifier 52 generates a signal based on the current of the source line SL. In Figure 34, a write circuit 80 is provided for each bit line BL, but a single write circuit 80 may control writing to multiple bit lines BL. In that case, a bit line BL selection circuit connected to the write circuit 80 is provided to sequentially select the desired bit lines BL and perform writing. Also, although a sense amplifier 52 is provided for each source line SL in Figure 34, reading to multiple source lines SL may be performed with a single sense amplifier 52. In that case, a source line SL selection circuit connected to the sense amplifier 52 is provided to sequentially select the desired SL and perform reading.

[0116] <Data Conversion> Figure 35 is a diagram illustrating an example of the operation of a data conversion circuit according to the fourth embodiment of this disclosure. This diagram illustrates the operation of the data conversion circuit 73. As described above, the data conversion circuit 73 converts the data to be written. This diagram shows an example where the memory element 120 is written to eight different resistance values. The data conversion circuit 73 divides the data to be written into predetermined number of bits (3 bits in this diagram) from the beginning, converts them, and distributes them to multiple writing circuits 80. In this diagram, the divided data is input directly to the writing circuits 80. The lower part of the diagram shows the relationship between the input to the writing circuit 80 and the corresponding output voltage. Note that the resistance values ​​and number of bits are not limited to the example shown in this diagram. For example, in the case of a memory element where 16 different resistance values ​​are written, it can be divided into 4-bit segments.

[0117] Figure 36 is a diagram illustrating an example of the operation of a data conversion circuit according to the fourth embodiment of this disclosure. This diagram illustrates the operation of the data conversion circuit 74. As described above, the data conversion circuit 74 converts the data read from the memory element 120. The sense amplifier 52 detects the resistance value based on the current of the source line SL. The data conversion circuit 74 converts this resistance value into 3-bit data, aggregates it, and outputs it as read data. The lower part of the figure shows the relationship between the detected resistance of the sense amplifier 52 and the corresponding output data.

[0118] <Other Examples of Data Conversion> Figure 37A shows another example of the operation of a data conversion circuit according to the fourth embodiment of this disclosure. This figure shows the relationship between the input of the writing circuit 80 and the corresponding output voltage, and the relationship between the detection resistor of the sense amplifier 52 and the corresponding output data. The target resistance value is different from that in Figures 35 and 36.

[0119] Figure 37B shows another example of the operation of a data conversion circuit according to the fourth embodiment of this disclosure. This figure shows the relationship between the input of the writing circuit 80 and the corresponding output voltage, and the relationship between the detection resistor of the sense amplifier 52 and the corresponding output data. The order of the input and output data is different from that of Figures 35 and 36. This order ensures that in adjacent data, the changing bit is always 1. This order minimizes the impact even if the resistance value shifts to the next cell.

[0120] Thus, the memory system 2 according to the fourth embodiment of this disclosure can improve recording density by using a multi-level memory element 120 with a multi-level recording bit count.

[0121] (5. Fifth Embodiment) A modified version of the fourth embodiment described above will now be explained.

[0122] <Memory System Configuration> Figure 38 is a diagram showing an example configuration of a memory system according to the fifth embodiment of this disclosure. This figure is a block diagram showing an example configuration of the memory system 2, similar to Figure 33. The memory system 2 in this figure differs from the memory system 2 in Figure 33 in that it further includes an error correction circuit 200.

[0123] The error correction circuit 200 detects and corrects errors in the stored data of the memory system 2.

[0124] <Configuration of Error Correction Circuit> Figure 39 is a diagram showing an example configuration of an error correction circuit according to the fifth embodiment of the present disclosure. The figure is a block diagram showing an example configuration of the error correction circuit 200. This error correction circuit 200 uses Reed-Solomon (RS) coding as the error correction code. The error correction circuit 200 comprises a bit-to-symbol conversion circuit 201, an encoding circuit 202, a symbol-to-bit conversion circuit 203, and a decoding circuit 204.

[0125] The bit-to-symbol conversion circuit 201 converts input data into symbols, which are the processing units of RS code. The number of bits in a symbol is preferably the same as the number of recording bits in the memory element 120, as this improves memory utilization efficiency. An example of input data conversion is shown at the bottom of Figure 39. Here, the input data is divided into 4-bit symbols.

[0126] The encoding circuit 202 encodes the input data, which has been divided into symbols. The encoded input data is input to the memory cell array 10 via the control unit 90.

[0127] The decoding circuit 204 decodes the encoded read data.

[0128] The symbol-to-bit conversion circuit 203 converts multiple symbols into read data. This conversion can be performed by aggregating multiple symbols.

[0129] <Other Configurations of Error Correction Circuits> Figure 40 is a diagram showing another example of an error correction circuit according to the fifth embodiment of the present disclosure. The figure is a block diagram representing another example of an error correction circuit 200. This error correction circuit 200 uses an error correction code other than RS code. The error correction circuit 200 in the figure comprises an error correction coding circuit 205, a bit-to-cell conversion circuit 206, an error correction decoding circuit 207, and a cell-to-bit conversion circuit 208.

[0130] The error correction coding circuit 205 performs error correction coding on the input data.

[0131] The bit-cell conversion circuit 206 converts the error-corrected encoded input data into data corresponding to the number of recording bits in the memory element 120. An example of input data conversion is shown at the bottom of Figure 40. Here, assuming that the number of recording bits in the memory element 120 is 3 bits, the conversion is performed by sequentially extracting 3 bits of data from the same digit of the three error-corrected encoded data from the beginning.

[0132] The cell-bit conversion circuit 208 converts multiple read data into error-corrected encoded data. This conversion can be performed by the reverse of the conversion process of the bit-cell conversion circuit 206 described above.

[0133] The error correction decoding circuit 207 decodes the encoded read data.

[0134] The configuration of the memory system 2 other than that described above is the same as the configuration of the memory system 2 in the fourth embodiment of this disclosure, so a description is omitted.

[0135] Thus, the memory system 2 of the fifth embodiment of this disclosure can correct errors in stored data using the error correction circuit 200.

[0136] (6. Sixth Embodiment) An example of applying the above-described memory device 1 to an arithmetic unit will be described.

[0137] <Configuration of the arithmetic unit> Figure 41 is a diagram showing an example configuration of an arithmetic unit according to the sixth embodiment of the present disclosure. The figure is a block diagram showing an example configuration of the arithmetic unit 4. This arithmetic unit 4 performs multiply-accumulate operations. The arithmetic unit 4 comprises a memory cell array 10, a word line control circuit 20, a bit line control circuit 30, a source line control circuit 40, a read circuit 50, an input circuit 75, a write circuit 80, and a control unit 90.

[0138] Figure 42 is a diagram showing an example of the configuration of a computing device according to the sixth embodiment of this disclosure. The figure shows an extracted portion of the memory cell array 10 of the computing device 4.

[0139] The writing circuit 80 in Figure 42 generates and outputs a writing voltage to set the memory element 120 of the memory cell 100 connected to the corresponding bit line BL to a desired resistance value. In addition to writing by set voltage (Figure 23), the writing circuit 80 can perform any of the following: writing by set current (Figure 27), writing by set pulse width (Figure 29), or writing by set number of pulses (Figure 31). Furthermore, as shown in Figure 25, the writing circuit 80 can also perform initial reading and writing with predetermined settings.

[0140] The input circuit 76 converts the input data into data that can be input to the memory cell 100. This input circuit 76 includes a plurality of digital-to-analog conversion circuits 77 arranged for each bit line BL. In Figure 42, the "digital-to-analog conversion circuit" is referred to as "DAC". The digital-to-analog conversion circuit 77 converts the input data into an analog signal.

[0141] The bit line control circuit 30 in Figure 42 includes a switch 32. This switch 32 switches the connection destination of the bit line BL to either the input circuit 76 or the writing circuit 80.

[0142] The arithmetic unit 4 uses each memory element 120 of the memory cell array 10 as a variable resistor element. That is, it pre-writes the memory elements 120 to a desired resistance value. Then, by applying a voltage (Vin in Figure 42) corresponding to the input data to the memory element 120 and detecting the current flowing through the memory element 120 (Iout in Figure 42), multiplication can be performed. That is, Iout = Vin × (1 / R). Here, R represents the resistance value of the memory element 120.

[0143] In this case, when a control signal is input to the word line WL to turn on the cell transistors 110 of multiple rows of memory cells 100, the current from the memory cells 100 connected to the same bit line BL flows simultaneously through the source line SL. When the memory cell array 10 is configured in i rows and j columns, the current from multiple memory cells 100 connected to the bit line BL(j) flows simultaneously through the source line SL(j). By detecting this current, the currents of each memory cell 100 can be added together. The current through the source line SL(j) can be expressed by the following formula. Here, the memory cell array 10 is configured with i rows and j columns, and the number of columns is M. Also, Iout(j) represents the current of the source line SL of the corresponding column. Vin(j) represents the input voltage of the corresponding column. Rij represents the resistance value of the corresponding memory cell 100. In this way, the arithmetic unit 4 can perform multiply-accumulate operations for each column.

[0144] The current in the source line SL is converted into a digital signal by the readout circuit 50. This signal is output to the control unit 90 as a calculation result.

[0145] <Other Configurations of the Arithmetic Processing Unit> Figure 43 is a diagram showing another example configuration of the arithmetic processing unit according to the sixth embodiment of this disclosure. This figure is a block diagram showing an example configuration of the arithmetic processing unit 4, similar to Figure 42.

[0146] The writing circuit 80 can perform writing by setting voltage (Figure 23), setting current (Figure 27), setting pulse width (Figure 29), or setting number of pulses (Figure 31). Furthermore, as shown in Figure 25, the writing circuit 80 can also perform initial reading and writing with predetermined settings.

[0147] When a control signal is input to the word line WL and the cell transistors 110 of multiple rows of memory cells 100 are turned ON, the current from the memory cells 100 connected to the same word line WL flows simultaneously through the source line SL. By detecting this current, the currents of each memory cell 100 can be added together. The current through the source line SL can be expressed by the following formula. Here, the memory cell array 10 is configured with i rows and j columns, with N rows (BLs) and M columns (WLs). Iout(j) represents the current of the source line SL of the corresponding column. Vin(i) represents the input voltage of the corresponding row. Rij represents the resistance value of the corresponding memory cell 100. In this way, the arithmetic unit 4 can perform multiply-accumulate operations for each column.

[0148] Thus, the arithmetic unit 4 according to the sixth embodiment of this disclosure can perform multiply-accumulate operations by using the memory element 120 as a variable resistor element that can be set to any resistance value.

[0149] (7. Seventh Embodiment) An example of the application of the memory system 2 and arithmetic unit 4 described above will be explained.

[0150] Figures 44A and 44B show an example configuration of an AI function device according to the seventh embodiment of this disclosure. Figures 44A and 44B are block diagrams showing an example configuration of the AI ​​function device 5.

[0151] The AI ​​function device 5 in Figure 44A is a device that performs AI calculations. This AI function device 5 comprises a control circuit 221, a temporary calculation value holding memory 223, and a multiply-accumulate circuit 224. The control circuit 221 controls the entire AI function device 5. The multiply-accumulate circuit 224 performs multiply-accumulate calculations used in AI calculations. The temporary calculation value holding memory 223 is a memory that temporarily holds the calculation results.

[0152] The AI ​​function device 5 in Figure 44B is a device that has a learning function in addition to AI calculation. This AI function device 5 comprises a control circuit 221, a temporary calculation value holding memory 223, a multiply-accumulate operation circuit 224, and a learning data holding memory 222. The learning data holding memory 222 is a memory that holds learning data.

[0153] The memory system 2 described in Figures 33 and 38 can be applied to the calculation value temporary holding memory 223 and the learning data holding memory 222. Furthermore, the arithmetic unit 4 described in Figures 42 and 43 can be applied to the multiply-accumulate circuit 224.

[0154] Figures 45A and 45B show an example configuration of an error correction decoding device according to the seventh embodiment of this disclosure. Figures 45A and 45B are block diagrams showing an example configuration of the error correction decoding device 6.

[0155] The error correction decoding device 6 shown in Figure 45A is a device that performs error correction decoding using the Belief Propagation method. This error correction decoding device 6 is used as an error correction decoding device in a communication line. The error correction decoding device 6 comprises a control circuit 231, a received LLR memory 232, an LLR memory 233, and a multiply-accumulate circuit 234. The control circuit 231 controls the entire error correction decoding device 6. The multiply-accumulate circuit 234 performs variable node calculations and check node calculations. The LLR memory 233 is a memory that holds demodulated signals and decoded signals. The received LLR memory 232 is a memory that holds received signals. Here, LLR represents the Log Likelihood Ratio.

[0156] The error correction decoding device 6 shown in Figure 45B comprises a control circuit 231, a receiving LLR memory 232, an LLR memory 233, a check node calculation circuit 235, and a variable node calculation circuit 236. The check node calculation circuit 235 and the variable node calculation circuit 236 each include a sum-of-accumulate calculation circuit.

[0157] The memory system 2 described in Figures 33 and 38 can be applied to the LLR memory 233 and the receiving LLR memory 232. Furthermore, the arithmetic unit 4 described in Figure 43 can be applied to the sum-of-accumulate circuits of the check node arithmetic circuit 235 and the variable node arithmetic circuit 236.

[0158] (8. Eighth Embodiment) The memory system 2 and arithmetic unit 4 described above transmitted digital signal data. In contrast, the memory system 2 and arithmetic unit 4 of the eighth embodiment of this disclosure differ from the above embodiment in that they transmit analog signal data.

[0159] <Configuration of the arithmetic system> Figure 46 is a diagram showing an example configuration of an arithmetic system according to the eighth embodiment of the present disclosure. The same figure is a block diagram showing an example configuration of the arithmetic system 7. The arithmetic system 7 comprises a memory system 2 and an arithmetic device 4.

[0160] <Memory System Configuration> Figure 47 is a diagram showing an example configuration of a memory system according to the eighth embodiment of the present disclosure. This figure is a block diagram showing an example configuration of the memory system 2, similar to Figure 33. The memory system 2 in this figure differs from the memory system 2 in Figure 33 in that the interface unit 3, data conversion circuits 73 and 74 and the writing circuit 80 are omitted, and an amplification circuit 78 and an initialization circuit 83 are added.

[0161] The amplification circuit 78 amplifies the input data of the analog signal. The initialization circuit 83 initializes the memory element 120 of the memory cell 100. The read circuit 50 in Figure 47 outputs an analog signal.

[0162] Figure 48 is a diagram showing an example configuration of a memory system according to the eighth embodiment of this disclosure. The figure shows an extracted portion of the memory cell array 10 of the memory system 2.

[0163] The amplification circuit 78 is placed for each bit line BL. The amplification circuit 78 amplifies the input data and applies it to the corresponding bit line BL.

[0164] The initialization circuit 83 generates a write voltage to reset the memory element 120 to its initial state and applies it to the bit line BL.

[0165] The switch 31 in Figure 48 switches the connection destination of the bit line BL to either the amplification circuit 78, the read voltage generation circuit 60, or the initialization circuit 83.

[0166] The readout circuit 50 in Figure 48 includes multiple charge storage circuits 53. The charge storage circuits 53 store the charge of the source line SL. The charge stored by the charge storage circuits 53 is output as output data.

[0167] Figure 49 shows an example configuration of the arithmetic unit 4 according to the eighth embodiment of the present disclosure. Similar to Figure 43, this figure shows only the peripheral portion of the memory cell array 10 within the arithmetic unit 4. The arithmetic unit 4 in this figure differs from the arithmetic unit 4 in Figure 43 in that an amplification circuit 79 is arranged instead of an input circuit 76. In addition, the read circuit 50 in this figure includes a charge storage circuit 54.

[0168] The amplification circuit 79 amplifies the input data. The amplified data is applied to the memory element 120 of the memory cell array 10.

[0169] The charge storage circuit 54 stores the charge on the source line SL. The stored charge is output as output data.

[0170] Figure 50 is a diagram showing an example configuration of an arithmetic system according to the eighth embodiment of the present disclosure. The diagram shows an example configuration of an arithmetic system 7. The arithmetic system 7 in the diagram comprises one arithmetic unit 4 and a plurality of memory systems 2. Note that the descriptions of the memory systems 2 and the arithmetic unit 4 are simplified in the diagram. Also, "memory cell array" is abbreviated as "MA". Each of the plurality of memory systems 2 holds data for calculation. Each memory system 2 inputs the held data to an amplification circuit 79 located in each row of the arithmetic unit 4. The arithmetic unit 4 also inputs the calculation results of each row to each of the plurality of memory systems 2. Note that the arithmetic system 7 in the diagram shows an example in which the same number of memory systems 2 as the number of rows of the arithmetic unit 4 are arranged.

[0171] In Figure 50, Li(i) represents the write current in memory system 2. Lo(i) represents the read current in memory system 2. Qi(j) represents the input value (charge) from the arithmetic unit to the memory. Qo(i) represents the output value (charge) from the memory to the arithmetic unit. Ii(i) represents the arithmetic input current. Io(j) represents the arithmetic output current.

[0172] <Calculation Processing> Figure 51 is a diagram showing an example of the processing procedure for calculation processing in the calculation system according to the eighth embodiment of the present disclosure. The same figure is a flowchart showing an example of the processing procedure for calculation processing in the calculation system 7.

[0173] First, a read current is applied to the memory cell 100 in the memory system 2 (step S151). Next, in the memory system 2, the charge storage circuit 53 stores the read charge from the memory cell 100 (step S152). Next, in the memory system 2, the charge storage circuit 53 discharges the stored charge (step S153). This charge is input to the amplification circuit 79 of the arithmetic unit 4. Next, in the arithmetic unit 4, the amplification circuit 79 amplifies the input calculation value (step S154) and inputs it to the memory cell 100 (step S155). Next, in parallel with the input of the calculation value to the arithmetic unit (steps S156 to S159 described later), the initialization circuit 83 in the memory system 2 applies an initialization current to the memory cell 100 (step S160).

[0174] Next, the arithmetic unit 4 outputs the calculation result from the memory cell 100 (step S156). Next, the charge storage circuit 54 in the arithmetic unit 4 stores the charge of the calculation result (step S157). Next, the charge storage circuit 54 in the arithmetic unit 4 discharges the charge of the calculation result (step S158). This charge is input to the amplification circuit 78 of the memory system 2. Next, the amplification circuit 78 in the memory system 2 amplifies the input calculation result (step S159). Next, a write current is applied to the memory cell 100 in the memory system 2 (step S161). Through the above process, calculations can be performed in the arithmetic system 7.

[0175] Figure 52 shows an example of arithmetic processing in an arithmetic system according to the eighth embodiment of the present disclosure. In this figure, Lo(i), Qo(i), Ii(i), Io(j), Qi(j), and Li(j) are the same as those described in Figure 50. Vg represents the signal of the word line WL in the arithmetic unit 4. T(j) represents the initialization current in the memory system 2. Rm(j) represents the resistance of the memory element 120 in the memory system 2.

[0176] In T11 to T12, a read current is output from the memory cell 100 of the memory system 2. This read current is stored by the charge storage circuit 53 and converted into the arithmetic input current Ii(i).

[0177] In T12 to T13, the output value Qo(i) from the memory system 2 is input to the arithmetic unit 4. This output value Qo(i) is amplified by the amplification circuit 79 to become the arithmetic input current Ii(i), which is applied to the memory cell 100. At this time, a signal is input to the word line WL of the arithmetic unit 4. As a result, the memory cell 100 outputs the arithmetic output current Io(j). In addition, an initialization current is applied to the memory cell 100 of the memory system 2, and the memory elements 120 of the memory cell 100 are initialized.

[0178] Between T13 and T14, the charge storage circuit 54 of the arithmetic unit 4 stores the calculation output current Io(j). After that, the signal input to the word line WL of the arithmetic unit 4 is stopped.

[0179] In steps T14 to T15, the output value from the arithmetic unit 4 is input to the memory system 2. A write current based on this input value Qi(j) is applied to the memory cell 100, and the writing operation is performed.

[0180] Subsequently, the same processing as T11 to T15 is repeated (T16 to T20) to perform a sum-of-products operation. The arithmetic system 7 can be applied to sum-of-products operations of inference and recognition circuits and Belief Propagation circuits.

[0181] The configuration of the arithmetic system 7 is not limited to this example. For example, more memory systems 2 than the number of rows in the arithmetic unit 4 may be arranged and selected for use. Alternatively, fewer memory systems 2 than the number of rows in the arithmetic unit 4 may be arranged, and multiple data can be read from each memory system 2.

[0182] <Other Configurations of the Memory System> Figure 53 is a diagram showing another example configuration of the memory system according to the eighth embodiment of the present disclosure. This figure is a block diagram showing an example configuration of the memory system 2, similar to Figure 48. The memory system 2 in this figure differs from the memory system 2 in Figure 48 in that an amplifier circuit 81 is placed in place of the amplifier circuit 78, and a current-voltage conversion circuit 55 is placed in place of the charge storage circuit 53 of the read circuit 50. In this figure, the "current-voltage conversion circuit" is denoted as "IV".

[0183] The amplification circuit 81 amplifies the input data, which is a voltage signal. The current-to-voltage conversion circuit 55 converts the current in the source line SL into a voltage. The voltage signal converted by the current-to-voltage conversion circuit 55 becomes the output data.

[0184] In the memory system 2 shown in Figure 53, input data and output data are assigned to each column of the memory cell array 10.

[0185] Figure 54 shows another example of the configuration of the arithmetic unit according to the eighth embodiment of the present disclosure. Similar to Figure 49, this figure shows an extracted portion of the memory cell array 10 of the arithmetic unit 4. The arithmetic unit 4 in this figure differs from the arithmetic unit 4 in Figure 49 in that an amplifier circuit 82 and a current-voltage conversion circuit 56 are arranged instead of the amplifier circuit 79 and the charge storage circuit 54.

[0186] The amplification circuit 82 amplifies the output data from the memory system 2, which is a voltage signal. The amplified output data is applied to the memory element 120 of the memory cell array 10.

[0187] The current-voltage conversion circuit 56 converts the current in the source line SL into a voltage signal. The converted signal is transmitted to the memory system 2 as input data.

[0188] In Figure 54, the arithmetic unit 4 assigns output data from the memory system 2 to each row of the memory cell array 10. The arithmetic unit 4 also assigns data from each column of the memory cell array 10 to the input data of the memory system 2.

[0189] <Calculation Processing> Figure 55 is a diagram showing another example of the processing procedure for calculation processing in the calculation system according to the eighth embodiment of the present disclosure. The same figure is a flowchart showing an example of the processing procedure for calculation processing in the calculation system 7.

[0190] First, data is read from the memory system 2 (step S171). This obtains multiple output data from the memory system 2. Next, the obtained output data is input to the arithmetic unit 4 (step S172). This applies a voltage to the memory element 120 corresponding to the output data from the memory system 2. Next, the arithmetic unit 4 performs a multiply-accumulate operation (step S173). Next, data corresponding to the calculation result is read from the arithmetic unit 4 (step S174). Next, the memory system 2 is initialized (step S175). This can be done by initializing the memory element 120 of the memory cell array 10 of the memory system 2. Next, data corresponding to the calculation result is written to the memory system 2 (step S176). Through the above process, the multiply-accumulate operation can be performed in the arithmetic system 7.

[0191] Thus, the arithmetic system 7 of the eighth embodiment of this disclosure exchanges analog signal data between the memory system 2 and the arithmetic unit 4. Since there is no need to convert the signals of the memory system 2 and the arithmetic unit 4 into digital signals, the processing time can be reduced.

[0192] Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also occur.

[0193] Furthermore, this technology can also take the following configurations: (1) A memory element comprising a memory layer with a variable magnetization direction, a reference layer with a fixed magnetization direction, and a tunnel barrier layer disposed between the memory layer and the reference layer, wherein the memory layer comprises a plurality of magnetization regions formed by dividing the memory layer in the planar direction, each having perpendicular magnetic anisotropy and composed of a Mn-based alloy. (2) The memory element according to (1), wherein the magnetization regions are composed of the crystallized Mn-based alloy. (3) The memory element according to (1) or (2), wherein the tunnel barrier layer is composed of a crystalline material and a crystal plane of a specific orientation is formed on the surface adjacent to the memory layer. (4) The memory element according to (3), wherein the tunnel barrier layer has a (001) plane formed on the surface in contact with the memory layer. (5) The memory element according to (4), wherein the memory layer is composed of a (001) oriented tetragonal crystal. (6) The memory element according to (5), further comprising a magnetic layer disposed on a side of the memory layer different from the side adjacent to the tunnel barrier layer. (7) The memory element according to (6), wherein the magnetic layer is composed of a (111) oriented tetragonal crystal. (8) The memory element according to (6), further comprising a spacer layer composed of a non-magnetic material disposed between the memory layer and the magnetic layer. (9) The memory element according to (5), further comprising a (001) oriented interface control layer disposed between the memory layer and the tunnel barrier layer. (10) The memory element according to (3), wherein the tunnel barrier layer has a (111) plane formed on the surface in contact with the memory layer. (11) The memory element according to (10), wherein the memory layer is composed of a (111) oriented tetragonal crystal. (12) The memory element according to (11), further comprising a (111) oriented interface control layer disposed between the memory layer and the tunnel barrier layer. (13) The memory element according to (10), wherein the memory layer is composed of a hexagonal crystal. (14) The memory element according to (13), further comprising an interface control layer having a (111) orientation disposed between the memory layer and the tunnel barrier layer. (15) The memory element according to (3), wherein the tunnel barrier layer has a (0001) plane formed on the surface in contact with the memory layer.(16) The memory element according to (15), wherein the memory layer is composed of a tetragonal crystal with a (111) orientation. (17) The memory element according to (15), wherein the memory layer is composed of a hexagonal crystal with a (0001) orientation. (18) The memory element according to (16), further comprising a (111) oriented interface control layer disposed between the memory layer and the tunnel barrier layer. (19) The memory element according to any one of (1) to (18), further comprising a non-magnetic film disposed at the boundary of a plurality of magnetization regions. (20) The memory element according to any one of (1) to (19), wherein the memory layer is configured in a substantially cylindrical shape, and the magnetization region is configured in a substantially cylindrical shape. (21) The memory element according to (20), wherein the magnetization region is configured to have a diameter of approximately 1 / 50 of the diameter of the memory layer. (22) The memory element according to (20), wherein the magnetization region has a diameter of 2 to 20 nm. (23) The memory element according to any one of (1) to (22), wherein the storage layer has a thickness of 10 nm or less. (24) The memory element according to any one of (1) to (23), wherein the storage layer has a boron (B) content of 10 at% or less. (25) A memory device comprising: a memory layer with a variable magnetization direction; a reference layer with a fixed magnetization direction; and a tunnel barrier layer disposed between the memory layer and the reference layer, wherein the memory layer comprises a plurality of magnetization regions formed by dividing the memory layer in the planar direction, each having perpendicular magnetic anisotropy and composed of a Mn-based alloy; a writing circuit for writing to the memory element into a high-resistance state, a low-resistance state, and an intermediate-resistance state which is a resistance between at least one of the high-resistance state and the low-resistance state; and a reading circuit for detecting the high-resistance state, the low-resistance state, and the at least one intermediate-resistance state of the memory element. (26) The memory device according to (25), wherein the writing circuit performs the writing by applying a writing voltage to the memory element corresponding to each of the high-resistance state, the low-resistance state, and the at least one intermediate-resistance state.(27) The memory device according to (25), wherein the writing circuit performs the writing by flowing a writing current to the memory element, the current corresponding to the high-resistance state, the low-resistance state, and the at least one intermediate-resistance state. (28) The memory device according to (25), wherein the writing circuit performs the writing by applying a writing voltage to the memory element, the pulse width corresponding to the high-resistance state, the low-resistance state, and the at least one intermediate-resistance state. (29) The memory device according to (25), wherein the writing circuit performs the writing by applying a writing voltage to the memory element, the number of pulses corresponding to the high-resistance state, the low-resistance state, and the at least one intermediate-resistance state. (30) A memory system comprising: a memory layer with a variable magnetization direction; a reference layer with a fixed magnetization direction; and a tunnel barrier layer disposed between the memory layer and the reference layer, wherein the memory layer comprises a plurality of magnetization regions formed by dividing the memory layer in the planar direction, each having perpendicular magnetic anisotropy and composed of a Mn-based alloy; a writing circuit that writes to the memory element to one of a high-resistance state, a low-resistance state, or an intermediate-resistance state having resistance between at least one of the high-resistance state and the low-resistance state; a reading circuit that detects the high-resistance state, the low-resistance state and the at least one intermediate-resistance state of the memory element; an input data conversion circuit that converts input write data according to the high-resistance state, the low-resistance state and the at least one intermediate-resistance state of the memory element and transmits it to the writing circuit; and a read data conversion circuit that converts the high-resistance state, the low-resistance state and the at least one intermediate-resistance state of the memory element detected by the reading circuit into read data.(31) A computing device comprising: a memory layer with a variable magnetization direction; a reference layer with a fixed magnetization direction; and a tunnel barrier layer disposed between the memory layer and the reference layer, wherein the memory layer comprises a plurality of magnetization regions formed by dividing the memory layer in the planar direction, each having perpendicular magnetic anisotropy and composed of a Mn-based alloy; a writing circuit for writing to the memory element to one of a high-resistance state, a low-resistance state, or an intermediate-resistance state which is a resistance between at least one of the high-resistance state and the low-resistance state; a reading circuit for detecting the high-resistance state, the low-resistance state, and the at least one intermediate-resistance state of the memory element; and an input circuit for converting input data into a voltage signal and applying it to the memory element.

[0194] 1 Memory device 2 Memory system 4 Arithmetic unit 10 Memory cell array 30 Bit line control circuit 40 Source line control circuit 50 Read circuit 60 Read voltage generation circuit 73, 74 Data conversion circuit 76 Input circuit 80 Write circuit 100 Memory cell 110 Cell transistor 120 Memory element 121, 128 Electrode 122 Reference layer 123, 129 Interface control layer 124 Magnetic layer 125 Spacer layer 130-134 Tunnel barrier layer 140-144 Storage layer 148 Non-magnetic material 149 Magnetization region

Claims

1. A memory element comprising a memory layer with a variable magnetization direction, a reference layer with a fixed magnetization direction, and a tunnel barrier layer disposed between the memory layer and the reference layer, wherein the memory layer comprises a plurality of magnetization regions, each of which is a region obtained by dividing the memory layer in the planar direction and has perpendicular magnetic anisotropy, and is made of a Mn-based alloy.

2. The memory element according to claim 1, wherein the magnetization region is composed of the crystallized Mn-based alloy.

3. The memory element according to claim 1, wherein the tunnel barrier layer is made of a crystalline material and a crystal plane of a specific orientation is formed on the surface adjacent to the memory layer.

4. The memory element according to claim 3, wherein the tunnel barrier layer has a (001) surface formed on the surface in contact with the memory layer.

5. The memory element according to claim 4, wherein the memory layer is composed of a (001) oriented tetragonal crystal.

6. The memory element according to claim 5, further comprising a magnetic layer disposed on a side of the memory layer different from the side adjacent to the tunnel barrier layer.

7. The memory element according to claim 6, wherein the magnetic layer is composed of a (111) oriented tetragonal crystal.

8. The memory element according to claim 6, further comprising a spacer layer made of a non-magnetic material disposed between the memory layer and the magnetic layer.

9. The memory element according to claim 5, further comprising an interface control layer having a (001) orientation disposed between the memory layer and the tunnel barrier layer.

10. The memory element according to claim 3, wherein the tunnel barrier layer has a (111) surface formed on the surface in contact with the memory layer.

11. The memory element according to claim 10, wherein the memory layer is composed of a (111) oriented tetragonal crystal.

12. The memory element according to claim 11, further comprising an interface control layer having a (111) orientation disposed between the memory layer and the tunnel barrier layer.

13. The memory element according to claim 10, wherein the memory layer is composed of a hexagonal crystal.

14. The memory element according to claim 13, further comprising an interface control layer having a (111) orientation disposed between the memory layer and the tunnel barrier layer.

15. The memory element according to claim 3, wherein the tunnel barrier layer has a (0001) surface formed on the surface in contact with the memory layer.

16. The memory element according to claim 15, wherein the memory layer is composed of a (111) oriented tetragonal crystal.

17. The memory element according to claim 15, wherein the memory layer is composed of a (0001) oriented hexagonal crystal.

18. The memory element according to claim 16, further comprising an interface control layer having a (111) orientation disposed between the memory layer and the tunnel barrier layer.

19. The memory element according to claim 1, further comprising a non-magnetic film disposed at the boundary of a plurality of magnetization regions.

20. The memory element according to claim 1, wherein the memory layer is configured in a substantially cylindrical shape, and the magnetization region is configured in a substantially cylindrical shape.

21. The memory element according to claim 20, wherein the magnetization region is configured to have a diameter approximately 1 / 50 of the diameter of the memory layer.

22. The memory element according to claim 20, wherein the magnetization region is configured to have a diameter of 2 to 20 nm.

23. The memory element according to claim 1, wherein the memory layer is configured to have a thickness of 10 nm or less.

24. The memory element according to claim 1, wherein the memory layer is configured to have a boron (B) content of 10 at% or less.

25. A memory device comprising: a memory layer with a variable magnetization direction; a reference layer with a fixed magnetization direction; and a tunnel barrier layer disposed between the memory layer and the reference layer, wherein the memory layer comprises a plurality of magnetization regions formed by dividing the memory layer in the planar direction, each having perpendicular magnetic anisotropy and composed of a Mn-based alloy; a writing circuit for writing to the memory element into a high-resistance state, a low-resistance state, and an intermediate-resistance state having a resistance between at least one of the high-resistance state and the low-resistance state; and a reading circuit for detecting the high-resistance state, the low-resistance state, and the at least one intermediate-resistance state of the memory element.

26. The memory device according to claim 25, wherein the writing circuit performs the writing by applying a writing voltage to the memory element, which is a voltage corresponding to the high-resistance state, the low-resistance state, and the at least one intermediate-resistance state.

27. The memory device according to claim 25, wherein the writing circuit performs the writing by flowing a writing current to the memory element, the current corresponding to the high-resistance state, the low-resistance state, and the at least one intermediate-resistance state.

28. The memory device according to claim 25, wherein the writing circuit performs the writing by applying a writing voltage to the memory element with a pulse width corresponding to each of the high-resistance state, the low-resistance state, and the at least one intermediate-resistance state.

29. The memory device according to claim 25, wherein the writing circuit performs the writing by applying a writing voltage with a number of pulses corresponding to each of the high-resistance state, the low-resistance state, and the at least one intermediate-resistance state to the memory element.

30. A memory system comprising: a memory layer with a variable magnetization direction; a reference layer with a fixed magnetization direction; and a tunnel barrier layer disposed between the memory layer and the reference layer, wherein the memory layer comprises a plurality of magnetization regions formed by dividing the memory layer in the planar direction, each having perpendicular magnetic anisotropy and composed of a Mn-based alloy; a writing circuit that writes to the memory element to one of a high-resistance state, a low-resistance state, or an intermediate-resistance state having resistance between at least one of the high-resistance state and the low-resistance state; a reading circuit that detects the high-resistance state, the low-resistance state and the at least one intermediate-resistance state of the memory element; an input data conversion circuit that converts input write data according to the high-resistance state, the low-resistance state and the at least one intermediate-resistance state of the memory element and transmits it to the writing circuit; and a read data conversion circuit that converts the high-resistance state, the low-resistance state and the at least one intermediate-resistance state of the memory element detected by the reading circuit into read data.

31. A computing device comprising: a memory layer with a variable magnetization direction; a reference layer with a fixed magnetization direction; and a tunnel barrier layer disposed between the memory layer and the reference layer, wherein the memory layer comprises a plurality of magnetization regions formed by dividing the memory layer in the planar direction, each having perpendicular magnetic anisotropy and composed of a Mn-based alloy; a writing circuit for writing to the memory element to one of a high-resistance state, a low-resistance state, or an intermediate-resistance state having a resistance between at least one of the high-resistance state and the low-resistance state; a reading circuit for detecting the high-resistance state, the low-resistance state, and the at least one intermediate-resistance state of the memory element; and an input circuit for converting input data into a voltage signal and applying it to the memory element.

Images