Memory device

Abstract

Provided is a memory device in which it is not necessary to store original data in a separate cell and imprinting can be recovered.　The memory device according to the present technology comprises: a memory cell; a bit line to which one end of the memory cell is connected; a plate line to which the other end of the memory cell is connected; and an equipotential circuit connected between the bit line and the plate line and capable of equalizing the potential of the bit line to the potential of the plate line and / or equalizing the potential of the plate line to the potential of the bit line. According to the memory device of the present technology, it is possible to provide a memory device in which it is not necessary to store original data in a separate cell, and imprinting can be recovered.

Description

Memory device

[0001] The technology according to the present disclosure (hereinafter also referred to as "the present technology") relates to a memory device.

[0002] Conventionally, memory devices including memory cells are known (see, for example, Patent Document 1).

[0003] For example, in the semiconductor memory device (memory device) disclosed in Patent Document 1, positive and negative attenuation pulses (cycling pulses) are applied to capacitors of memory cells in order to recover imprint.

[0004] Japanese Unexamined Patent Publication No. Hei 9-55547

[0005] However, for example, in the semiconductor memory device disclosed in Patent Document 1, original data is destroyed by application of cycling pulses, so it is necessary to store the original data in another cell.

[0006] Accordingly, a main object of the present technology is to provide a memory device that does not require storing original data in another cell and is capable of recovering imprint.

[0007] This technology provides a memory device comprising: a memory cell; a bit line to which one end of the memory cell is connected; a plate line to which the other end of the memory cell is connected; and an equipotentialization circuit connected between the bit line and the plate line, which is capable of making the potential of the bit line equal to the potential of the plate line, and / or making the potential of the plate line equal to the potential of the bit line. The equipotentialization circuit may have an input terminal on one of the bit line side and the plate line side, and an output terminal on the other. The memory device may further include at least a control circuit for controlling the equipotentialization circuit. The control circuit may drive the equipotentialization circuit at a predetermined timing to make the potential of the bit line equal to the potential of the plate line. The control circuit may drive the equipotentialization circuit at a predetermined timing to make the potential of the plate line equal to the potential of the bit line. The control circuit may drive the equipotentialization circuit at a first predetermined timing to equalize the potential of the bit line with the potential of the plate line, and drive the equipotentialization circuit at a second predetermined timing to equalize the potential of the plate line with the potential of the bit line. The equipotentialization circuit may include a switching element. The equipotentialization circuit may include a logic circuit. The memory device may further include a plate line potential keeping circuit connected to the plate line for keeping the potential of the plate line. The plate line potential keeping circuit may be driven at a predetermined timing by the control circuit. The plate line potential keeping circuit may include a latch circuit. The memory device may further include a sense amplifier connected to the bit line. The sense amplifier may be driven at a predetermined timing by the control circuit. The memory device may further include a plate line potential control circuit connected to the plate line for controlling the potential of the plate line. The plate line potential control circuit may be driven at a predetermined timing by the control circuit. The plate line potential control circuit may include a logic circuit. The memory device may further include a bit line potential control circuit connected to the bit line and controlling the potential of the bit line.The bit line potential control circuit may be driven at predetermined timings by the control circuit. The bit line potential control circuit may include logic circuits. The memory device may further include a plate line potential control circuit connected to the plate line and controlling the potential of the plate line, and a bit line potential control circuit connected to the bit line and controlling the potential of the bit line.

[0008] This is a conceptual diagram showing an example of operation of a memory device according to this technology. This is a conceptual diagram showing an example of the effect of a memory device according to this technology. This is a circuit diagram showing the configuration of a memory device according to Example 1 of the first embodiment of this technology. This is a block diagram showing the functions of a memory device according to Example 1 of the first embodiment of this technology. Figure 5A is a diagram showing an example of the configuration of the equipotentialization circuit 1 of a memory device according to Example 1 of the first embodiment of this technology. Figure 5B is a diagram showing an example of the configuration of the equipotentialization circuit 2 of a memory device according to Example 1 of the first embodiment of this technology. This is a diagram showing an example of the configuration of the equipotentialization circuit 3 of a memory device according to Example 1 of the first embodiment of this technology. This is a diagram showing an example of the configuration of the plate line potential keeping circuit and the energizing control unit of a memory device according to Example 1 of the first embodiment of this technology. This is a diagram showing an example of the configuration of the plate line potential control circuit and the energizing control unit of a memory device according to Example 1 of the first embodiment of this technology. This is a diagram showing an example of the configuration of the bit line potential control circuit and the energizing control unit of a memory device according to Example 1 of the first embodiment of this technology. This is a circuit diagram showing an example of the configuration of the memory cell array and equipotentialization circuit of a memory device according to Example 1 of the first embodiment of this technology. This is a timing diagram showing the read operation after data writing of a memory device according to Example 1 of the first embodiment of this technology. This is a circuit diagram showing the configuration of a comparative example memory device (1T1C type). This is a timing diagram showing the operation of a comparative example memory device (1T1C type). Figure 14A is a graph showing whether data can be read after it has been written in the memory device according to Embodiment 1 of this technology. Figure 14B is a graph showing whether different data can be written after it has been written in the memory device according to Embodiment 1 of this technology, while retaining the data. This is a circuit diagram showing an example configuration of the memory cell array and equipotentialization circuit of a memory device according to Embodiment 2 of the first embodiment of this technology. This is a timing diagram showing the read operation after data writing of the memory device according to Embodiment 2 of the first embodiment of this technology. This is a circuit diagram showing an example configuration of the memory cell array and power supply control unit of a memory device according to Embodiment 3 of the first embodiment of this technology. This is a timing diagram showing the write operation of the memory device according to Embodiment 3 of the first embodiment of this technology. This is a circuit diagram showing an example configuration of the memory cell array and power supply control unit of a memory device according to Embodiment 4 of the first embodiment of this technology.This is a timing diagram showing the writing operation of a memory device according to Embodiment 4 of the first embodiment of this technology. This is a diagram showing an example of a bias adjustment method by bias application time. This is a diagram showing an example of a bias adjustment method by bias application voltage. This is a circuit diagram showing an example configuration of a memory cell array and a power supply control unit of a memory device according to Embodiment 1 of the second embodiment of this technology. Figures 24A and 24B are diagrams for explaining the necessity of 2T2C type recovery. This is a circuit diagram showing an example configuration of a memory cell array and a power supply control unit of a memory device according to Embodiment 2 of the second embodiment of this technology. This is a diagram for explaining memory characteristic degradation due to imprint. Figure 27A is a graph showing whether the data held after writing data when imprint occurs can be read. Figure 27B is a graph showing whether the data can be held after writing data when imprint occurs and different data can be written. This is a diagram showing an example of the use of a memory device to which this technology is applied. This is a functional block diagram of an example of an electronic device equipped with a memory device to which this technology is applied. This is a block diagram showing an example of the schematic configuration of a vehicle control system. This is an explanatory diagram showing an example of the installation position of an external information detection unit and an imaging unit. This is a diagram showing an example of the schematic configuration of an endoscopic surgery system. This is a block diagram showing an example of the functional configuration of a camera head and a CCU.

[0009] Preferred embodiments of the present technology will be described in detail below with reference to the attached drawings. In this specification and the drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant explanations will be omitted. The embodiments described below represent typical embodiments of the present technology and should not be interpreted as narrowing the scope of the present technology. Even if this specification describes that a memory device relating to the present technology has multiple effects, it is sufficient for the memory device relating to the present technology to have at least one effect. The effects described in this specification are merely examples and are not limiting, and other effects may also exist.

[0010] Furthermore, the explanation will proceed in the following order: 0. Introduction 0.5. Concept of a memory device related to this technology 1. Memory device according to Example 1 of the first embodiment of this technology 2. Memory device according to Example 2 of the first embodiment of this technology 3. Memory device according to Example 3 of the first embodiment of this technology 4. Memory device according to Example 4 of the first embodiment of this technology 5. Memory device according to Example 1 of the second embodiment of this technology 6. Memory device according to Example 2 of the second embodiment of this technology 7. Example of use of a solid-state imaging device equipped with a memory device to which this technology is applied 8. Example of application to objects 9. Example of application to an endoscopic surgical system

[0011] <0. Introduction> In ferroelectric random access memory (FeRAM), after writing data, the data is retained, trapping charge at the interface between the electrode and the ferroelectric material. This reduces the proportion of external bias that can be applied to the ferroelectric material, causing imprinting (burn-in phenomenon). In this case, the hysteresis loop of the ferroelectric material changes from a normal state (see Figure 26 left) to an abnormal state (see Figure 26 right). That is, the memory characteristics deteriorate, negatively impacting reliability.

[0012] In particular, when driving memory cell arrays in which ferroelectric memory is arranged in an array, there is a concern that imprinting may cause read and write errors.

[0013] Figure 27A is a graph showing whether the data can be read after being written when an imprint occurs (SS). In Figure 27A, the horizontal axis represents time and the vertical axis represents voltage. In Figure 27A, due to the effect of imprint, the difference between the high-level bit line potential VBLH and the low-level bit line potential VBLL gradually decreases as the data retention time increases, so the concern about read errors is small. In other words, there is not much of a problem when retaining data and then reading that retained data. In Figures 27A and 27B, MW means Memory Window (MW = VBLH - VBLL) (the same applies hereafter).

[0014] Figure 27B is a graph showing whether data can be retained and different data written after data is written when imprint occurs (OS). In Figure 27B, the horizontal axis represents time and the vertical axis represents voltage. In Figure 27B, due to the effect of imprint, as the data retention time increases, the difference between the high-level VBLH and low-level VBLL bit line potentials decreases, raising concerns about write errors. In other words, problems may occur when writing different data after retaining the previous data.

[0015] To address the problems described above, conventional techniques have attempted to recover imprints by applying cycling pulses. However, this is difficult to implement in a series of sequences, and it destroys the original data, requiring the original data to be stored in a separate cell.

[0016] Therefore, after careful consideration, the inventors developed the memory device related to this technology, which does not require the original data to be stored in a separate cell and can recover the imprint.

[0017] <0.5. Concept of the Memory Device Related to This Technology> Figure 1 is a conceptual diagram showing an example of operation of the memory device related to this technology. Figure 2 is a conceptual diagram showing an example of the effect of the memory device related to this technology.

[0018] The memory device relating to this technology uses, for example, transistors, relay circuits, and logic circuits as switching elements, and as shown in Figure 1, during reading, for example, the BL potential is made equal to the PL potential at a first predetermined timing (potential copy), and the PL potential is made equal to the BL potential at a second predetermined timing (potential copy). This allows the imprint to be recovered within a series of sequences and enables write-back.

[0019] In the memory device relating to this technology, by performing the operation shown in Figure 1, as shown in the lower part of Figure 2 (the upper part of Figure 2 is the same as Figure 27B), the difference between the high-level VBLH bit line potential and the low-level VBLL bit line potential increases with increasing recovery pulse application time, thus eliminating concerns about write failures.

[0020] The memory device according to the first embodiment of this technology will be described in detail below with reference to several examples.

[0021] <1. Memory device according to Example 1 of the first embodiment of this technology>

[0022] <<Configuration of Memory Device>> Figure 3 is a circuit diagram showing the configuration of the memory device 10 according to Example 1 of the first embodiment of this technology. Figure 4 is a block diagram showing the functions of the memory device 10 according to Example 1 of the first embodiment of this technology.

[0023] The memory device 10 is, for example, a non-volatile memory, such as FeRAM (ferroelectric random access memory). In addition to the advantages of non-volatile memory, such as the ability to retain data even when the power is off (non-volatility) and low power consumption, FeRAM also possesses the advantages of volatile memory, such as a high number of data rewrite cycles and high-speed writing capabilities, despite being a non-volatile memory.

[0024] FeRAM is applied to or expected to be applied to product areas such as smartphones, IC cards, electronic tags, and image sensors.

[0025] (Overall configuration of the memory device) As an example, the memory device 10 includes a memory cell MC, a bit line BL0 to which one end of the memory cell MC is connected, a plate line PL0 to which the other end of the memory cell MC is connected, and an equipotential circuit 101 connected between the bit line BL0 and the plate line PL0. The memory device 10 further includes a sense amplifier SA connected to the bit line BL0. The bit line BL0 and the plate line PL0 are arranged parallel to each other. Multiple (for example, three) word lines WL (for example, WL0, WL1, WL2) are arranged orthogonally to the bit line BL0 and the plate line PL0 in an insulated state.

[0026] As an example, the memory device 10 includes, in addition to the equipotentialization circuit 101, a plate line potential keeping circuit 102, a plate line potential control circuit 103, a bit line potential control circuit 104, and a control circuit 100, as shown in Figure 4. The control circuit 100 controls the potential of each word line WL (WL potential), as well as the plate line potential keeping circuit 102, the plate line potential control circuit 103, the bit line potential control circuit 104, and the sense amplifier SA.

[0027] Returning to Figure 3, the memory device 10, as an example, has a memory cell array that includes a plurality (for example, three) of memory cells MC.

[0028] As an example, the three memory cell MCs include memory cell MC000 connected to word line WL0, bit line BL0, and plate line PL0; memory cell MC100 connected to word line WL1, bit line BL0, and plate line PL0; and memory cell MC200 connected to word line WL2, bit line BL0, and plate line PL0.

[0029] Each memory cell (MC) is a 1T1C type memory cell consisting of one transistor (Tr) and one variable capacitance capacitor (VC).

[0030] In each memory cell (MC), a MOSFET (metal-oxide-semiconductor field-effect transistor) as a transistor (Tr) and a ferroelectric capacitor as a variable capacitance capacitor (VC) are connected in series.

[0031] A ferroelectric capacitor has a three-layer structure in which a ferroelectric material is sandwiched between a pair of electrodes (conductors). The direction of polarization of the ferroelectric material corresponds to the "high" or "low" logical values. Examples of ferroelectric materials include barium titanate (BaTiO3), PZT (lead zirconate titanate: PbZrTiO3), SBT (strontium bismuth tantalate: SrBi2Ta2O9), and hafnium oxide (HfOx).

[0032] As an example, a transistor Tr (e.g., an nMOSFET) has its drain connected to the bit line BL0 and its source connected to one electrode of a variable capacitance capacitor VC. The other electrode of the variable capacitance capacitor VC is connected to the plate line PL0. Note that the transistor Tr may also be a pMOSFET.

[0033] Here, a word line WL is provided for each memory cell MC. The gate of the transistor Tr in each memory cell MC is connected to the corresponding word line WL (for example, one of word lines WL0, WL1, or WL2). That is, the gate of the transistor Tr in memory cell MC000 is connected to word line WL0, the gate of the transistor Tr in memory cell MC100 is connected to word line WL1, and the gate of the transistor Tr in memory cell MC200 is connected to word line WL2.

[0034] The equipotentialization circuit 101 can make the potential of the bit line BL0 (BL potential) equal to the potential of the plate line PL0 (PL potential), and / or make the potential of the plate line PL0 (PL potential) equal to the potential of the bit line BL0 (BL potential). The equipotentialization performed by the equipotentialization circuit 101 is also called "potential copying".

[0035] The equipotentialization circuit 101 has an input terminal (specifically, a signal input terminal) on one side of the bit line BL0 and the plate line PL0, and an output terminal (specifically, a signal output terminal) on the other side. The equipotentialization circuit 101 is controlled by the control circuit 100.

[0036] (Example 1 of the equipotentialization circuit configuration) Figure 5A is a diagram showing Example 1 of the configuration of the equipotentialization circuit 101 of the memory device 10 according to Embodiment 1 of the first embodiment of the present technology.

[0037] In Configuration Example 1, as shown in FIG. 5A, the equipotentialization circuit 101 is configured to include a CMOS switch formed of a CMOS (Complementary Metal-Oxide-Semiconductor) FET (Field-Effect Transistor) as a switching element. An input terminal of the CMOS switch is connected to a switch line SW, and an output terminal thereof is connected to a switch line / SW. In the CMOS switch, a source of a pMOS is connected to a bit line BL, and a source of an nMOS is connected to a plate line PL. At least the switch line SW among the switch line SW and the switch line / SW is connected to the control circuit 100.

[0038] In Configuration Example 1, the control circuit 100 sets the potential of the switch line SW to HIGH when performing equipotentialization, and sets the potential of the switch line SW to LOW when not performing equipotentialization.

[0039] (Configuration Example 2 of Equipotentialization Circuit) FIG. 5B is a diagram illustrating Configuration Example 2 of the equipotentialization circuit 101 of the memory device 10 according to Example 1 of the first embodiment of the present technology.

[0040] In Configuration Example 2, as shown in FIG. 5B, the equipotentialization circuit 101 is configured to include a MOS switch (for example, an nMOS switch) formed of a MOSFET (metal-oxide-semiconductor field-effect transistor) as a switching element. A gate of the MOS switch is connected to the switch line SW. In the nMOS switch, a drain is connected to the bit line BL, and a source is connected to the plate line PL. The switch line SW is connected to the control circuit 100. Note that the MOS switch may be a pMOS switch.

[0041] In Configuration Example 2, the control circuit 100 sets the potential of the switch line SW to HIGH when performing equipotentialization, and sets the potential of the switch line SW to LOW when not performing equipotentialization.

[0042] (Configuration Example 3 of Equipotentialization Circuit) FIG. 6 is a diagram illustrating Configuration Example 3 of the equipotentialization circuit 101 of the memory device 10 according to Example 1 of the first embodiment of the present technology.

[0043] In Configuration Example 3, as shown in FIG. 6, the equipotentialization circuit 101 is configured to include a logic operation circuit. Specifically, the equipotentialization circuit 101 includes a plurality of logic operation circuits (for example, first and second AND circuits 101a1, 101b1) and a plurality of conduction control units (for example, first and second CMOS switches 101a2, 101b2).

[0044] The first CMOS switch 101a2 (conduction control unit) controls turning on / off of power supply to the first AND circuit 101a1 (logic operation circuit). The first CMOS switch 101a2 is connected between the bit line BL and the first AND circuit 101a1.

[0045] The second CMOS switch 101b2 (conduction control unit) controls turning on / off of power supply to the second AND circuit 101b1 (logic operation circuit). The second CMOS switch 101b2 is connected between the plate line PL and the second AND circuit 101b2.

[0046] The first AND circuit 101a1 has one input terminal connected to the switch line BL-SW, the other input terminal connected to the plate line PL, and an output terminal connected to the source of the pMOS of the first CMOS switch 101a2.

[0047] In the first CMOS switch 101a2, the source of the nMOS is connected to the bit line BL, the input terminal is connected to the analog switch line BL-ASW, and the output terminal is connected to the analog switch line / BL-ASW.

[0048] The second AND circuit 101b1 has one input terminal connected to the bit line BL, the other input terminal connected to the switch line PL-SW, and an output terminal connected to the source of the pMOS of the second CMOS switch 101b2.

[0049] In the second CMOS switch 101b2, the source of the nMOS is connected to the plate line PL, the input terminal is connected to the analog switch line PL-ASW, and the output terminal is connected to the analog switch line / PL-ASW.

[0050] At least the switch wire BL-SW, analog switch wire BL-ASW, switch wire PL-SW, and analog switch wire PL-ASW are connected to the control circuit 100.

[0051] In Configuration Example 3, the control circuit 100 sets the potential of only the switch line PL-SW and the analog switch line PL-ASW to HIGH when making the BL potential equal to the PL potential.

[0052] In configuration example 3, the control circuit 100 sets the potential of only the switch wire BL-SW and the analog switch wire BL-ASW to HIGH when making the PL potential equal to the BL potential.

[0053] In the configuration example 3, a MOS switch, relay switch, or the like may be used instead of a CMOS switch as the power supply control unit.

[0054] (Plate wire potential keeping circuit) Figure 7 shows an example of the configuration of the plate wire potential keeping circuit 102 and the energization control unit of the memory device 10 according to Example 1 of the first embodiment of this technology.

[0055] The plate wire potential keeping circuit 102 is connected to the plate wire PL (see Figure 3). The plate wire potential keeping circuit 102 includes a latch circuit (PL-Latch) as shown in Figure 7. The plate wire potential keeping circuit 102 and the CMOS switch 112, which acts as a current control unit, are controlled by the control circuit 100. The CMOS switch 112, which acts as a current control unit, controls the on / off state of the current supply to the plate wire potential keeping circuit 102.

[0056] The latch circuit has an inverter pair 102a consisting of two CMOS inverters connected in cascade in a loop.

[0057] The node of inverter pair 102a is connected to the pMOS source of the CMOS switch 112. The CMOS switch 112 has its input terminal connected to the switch line KSW, its output terminal connected to switch / KSW, and the nMOS source connected to the PL line.

[0058] Of the switch wire KSW and switch wire / KSW, at least the switch wire KSW is connected to the control circuit 100.

[0059] The control circuit 100 sets the potential of switch wire KSW to HIGH when maintaining the PL potential, and to LOW at all other times.

[0060] In addition, instead of a CMOS switch, a MOS switch, relay switch, or the like may be used as the power supply control unit.

[0061] (Plate wire potential control circuit) Figure 8 shows an example of the configuration of the plate wire potential control circuit 103 and the energization control unit of the memory device 10 according to Embodiment 1 of the first embodiment of this technology.

[0062] The plate line potential control circuit 103 (PL-Driver) is connected to the plate line PL (see Figure 3). As shown in Figure 8, the plate line potential control circuit 103 includes a PL logic circuit 103a and a pair of inverters 103b consisting of a plurality (e.g., two) of inverters connected in cascaded order. The plate line potential control circuit 103 and the CMOS switch 113, which acts as a power supply control unit, are controlled by the control circuit 100. The CMOS switch 113, which acts as a power supply control unit, controls the on / off switching of power to the plate line potential control circuit 103.

[0063] The output terminal of the PL logic circuit 103a is connected to the input terminal of the inverter pair 103b. The output terminal of the inverter pair 103b is connected to the source of the pMOS of the CMOS switch 113. The CMOS switch 113 has its input terminal connected to the switch line DSW, its output terminal connected to the switch line / DSW, and the source of the nMOS connected to the plate line PL.

[0064] Of the switch wire DSW and the switch wire / DSW, at least the switch wire DSW is connected to the control circuit 100.

[0065] The control circuit 100 sets the potential of the switch line DSW to LOW except when a HIGH / LOW input is being received to the PL line.

[0066] (Bit line potential control circuit) Figure 9 is a diagram showing an example of the configuration of the bit line potential control circuit 104 and the power supply control unit of the memory device 10 according to Embodiment 1 of the first embodiment of this technology.

[0067] The bit line potential control circuit 104 (BL-Driver) is connected to the bit line BL (see Figure 3). As shown in Figure 9, the bit line potential control circuit 104 includes a BL logic circuit 104a and a pair of inverters 104b consisting of multiple (e.g., two) inverters connected in cascaded order. The bit line potential control circuit 104 and the CMOS switch 114, which acts as a power supply control unit, are controlled by the control circuit 100. The CMOS switch 114, which acts as a power supply control unit, controls the on / off state of power supply to the bit line potential control circuit 104.

[0068] The output terminal of the BL logic circuit 104a is connected to the input terminal of the inverter pair 104b. The output terminal of the inverter pair 104b is connected to the source of the pMOS of the CMOS switch 114. The CMOS switch 114 has its input terminal connected to the switch line DSW and its output terminal connected to the switch line / DSW. The source of the nMOS of the CMOS switch 114 is connected to the bit line BL.

[0069] Of the switch wire DSW and the switch wire / DSW, at least the switch wire DSW is connected to the control circuit 100.

[0070] The control circuit 100 sets the potential of the switch line DSW to LOW except when a HIGH / LOW input is being received to the BL line.

[0071] (Sense Amplifier) ​​Returning to Figure 3, the sense amplifier SA has one input terminal connected to the BL line, the other input terminal to which a reference voltage Vref is input, and the output terminal is output to an external device (e.g., a logic circuit). The sense amplifier SA detects a low-power signal from the bit line BL that indicates a data bit (1 or 0) stored in the memory cell MC, and amplifies the small voltage swing to a recognizable logic level so that the data can be properly interpreted by a logic circuit outside the memory device.

[0072] (Memory cell array and equipotentialization circuit) Figure 10 is a circuit diagram showing an example configuration of the memory cell array MCA and equipotentialization circuit 101 of a memory device 10 according to Example 1 of the first embodiment of this technology.

[0073] As an example, the memory cell array MCA, as shown in Figure 10, has three word lines WL (WL0, WL1, WL2), and two sets of bit lines BL and plate lines PL corresponding to each word line WL (a set of bit line BL0 and plate line PL0, and a set of bit line BL1 and plate line PL1), resulting in a total of six memory cell MCs.

[0074] The six memory cells MC include memory cell MC000 connected to word line WL0, bit line BL0 and plate line PL0, memory cell MC100 connected to word line WL1, bit line BL0 and plate line PL0, memory cell MC200 connected to word line WL2, bit line BL0 and plate line PL0, memory cell MC011 connected to word line WL0, bit line BL1 and plate line PL1, memory cell MC111 connected to word line WL1, bit line BL1 and plate line PL1, and memory cell MC211 connected to word line WL2, bit line BL1 and plate line PL1.

[0075] Switch lines SW0 and / SW0 are provided in the memory cell array MCA, parallel to the word line WL and orthogonal to the bit line BL and plate line PL, while being insulated from them. A CMOS switch 101A, which serves as an equipotentialization circuit 101, is provided in the region partitioned by the switch lines SW0 and / SW0, the bit line BL0, and the plate line PL0. A CMOS switch 101B, which serves as an equipotentialization circuit 101, is provided in the region partitioned by the switch lines SW0 and / SW0, the bit line BL1, and the plate line PL1.

[0076] The CMOS switch 101A has its input terminal connected to switch line SW0, its output terminal connected to switch line SW0, the source of the pMOS connected to bit line BL0, and the source of the nMOS connected to plate line PL0.

[0077] The CMOS switch 101B has its input terminal connected to switch line SW0, its output terminal connected to switch line SW0, the pMOS source connected to bit line BL1, and the nMOS source connected to plate line PL1.

[0078] Of the switch wires SW0 and SW1, at least switch wire SW0 is connected to the control circuit 100.

[0079] ≪Operation of the Memory Device≫ Figure 11 is a timing diagram showing the operation (read operation after data writing) of the memory device 10 according to Embodiment 1 of the first embodiment of this technology. The example in Figure 11 is an example of the operation sequence when a CMOS switch is incorporated into the equipotentialization circuit 101 of the memory cell MC (when using the memory cell array MCA and equipotentialization circuit 101 of Figure 10). The series of operation sequences shown in Figure 11 are executed by the control circuit 100. Here, the case in which memory cell MC000 is selected will be explained as an example.

[0080] 0: Set the WL potential to High to start the reading sequence. 1: Set the PL potential to High (PL-Driver ON) to start reading Data0 and Data1. 2: Enable (turn on) SA (ends the normal reading sequence). 3: Set the PL potential to FLT (PL-Driver OFF) and turn on the CMOS switch 101A to start equalizing the PL potential with the BL potential (copying the BL potential to the PL potential). 4: Turn off SA and the CMOS switch 101A to end equalizing the PL potential with the BL potential, set the BL potential to High (BL-Driver ON), and turn on PL-Latch to start Data0 recovery. 5: Set the BL potential to Low to end Data0 recovery and start Data1 recovery. 6: Turn on the CMOS switch 101A to start equalizing the BL potential with the PL potential (copying the PL potential to the BL potential), and set the BL potential to FLT (BL-Driver OFF) to finish the recovery of Data1. 7: Turn on the SA, turn off the CMOS switch 101A to finish equalizing the BL potential with the PL potential, set the PL potential to Low, and turn off the PL-Latch to start the Write-Back of Data1. 8: Set the PL potential to High to finish the Write-Back of Data1 and start the Write-Back of Data0. 9: Turn off the SA, and set the PL potential and BL potential to Low. 10: Set the WL potential to Low to complete the read sequence.

[0081] In the data read operation described above, the imprint is restored by the equipotential recovery process. This suppresses the decrease in the difference between the high-level VBLH and low-level VBLL bit line potentials as the data retention time increases, thereby reducing the occurrence of read errors. Furthermore, since the original data is not corrupted during the read operation compared to when a cycling pulse is applied, there is no need to store the original data in a separate cell.

[0082] Similarly, even in the case of writing different data after data has been written, the imprint is restored by performing a recovery operation within the operation sequence. This suppresses the decrease in the difference between the high-level VBLH and low-level VBLL bit line potentials as the data retention time increases, thereby suppressing the occurrence of write errors. Furthermore, since the original data is not corrupted during the write operation compared to when a cycling pulse is applied, there is no need to store the original data in a separate cell.

[0083] (Comparative Example) Figure 12 is a circuit diagram showing the configuration of a comparative example memory device (1T1C type FeRAM). As shown in Figure 12, the comparative example memory device (1T1C type FeRAM) has memory cells similar to the memory cells MC of the memory device 10.

[0084] Figure 13 is a timing diagram showing the operation (read operation and write operation) of a comparative example memory device (1T1C type FeRAM). The series of operations shown in Figure 13 are executed by a control circuit that controls the memory cell.

[0085] 0: Set WL potential to High to start the read sequence. 1: Set PL potential to High to start reading Data0 and Data1. 2: Enable (turn on) SA. 3: Set PL potential to Low to start Write-Back. 4: Turn off SA and set BL potential to Low to end Write-Back. 5: Set WL potential to Low to complete the read sequence. 10: Set WL potential to High to start the write sequence. 11: Set PL potential and BL potential to High to start writing Data0 and Data1. 12: Set PL potential and BL potential to Low to end writing Data0 and Data1. 13: Set WL potential to Low to complete the write sequence.

[0086] <<Effects of the Memory Device>> The memory device 10 comprises a memory cell MC, a bit line BL to which one end of the memory cell MC is connected, a plate line PL to which the other end of the memory cell MC is connected, and an equipotentialization circuit 101 connected between the bit line BL and the plate line PL, which can make the potential of the bit line BL equal to the potential of the plate line PL, and / or make the potential of the plate line PL equal to the potential of the bit line BL.

[0087] The memory device 10 eliminates the need to store the original data in a separate cell and enables the realization of a memory device that can recover imprints.

[0088] Furthermore, the equipotentialization process in the memory device 10 is easily incorporated into a series of operation sequences.

[0089] Figure 14A is a graph showing whether data can be read after it has been written to the memory device 10 (1TIC type). Figure 14B is a graph showing whether data can be written to the memory device 10 (1TIC type) and then retained, allowing different data to be written. In Figures 14A and 14B, the horizontal axis represents time and the vertical axis represents voltage.

[0090] In the memory device 10, as shown in Figure 14A, during reading, the difference between VBLL and VBLH gradually increases with increasing data retention time, so read errors are hardly a concern. The memory device 10 has the read margin shown in Figure 14A compared to the comparative memory device (1T1C type FeRAM) in Figure 12.

[0091] In memory device 10, as shown in Figure 14B, during writing, the difference between VBLL and VBLH decreases as the data retention time increases, raising concerns about write errors. Memory device 10 has a write margin as shown in Figure 14B compared to the comparative memory device (1T1C type FeRAM) in Figure 12.

[0092] The equipotentialization circuit 101 may have an input terminal on one side of the bit line BL and the plate line PL, and an output terminal on the other side. This simplifies the circuit configuration of the equipotentialization circuit 101.

[0093] The memory device 10 may further include a control circuit 100 that controls at least the equipotentialization circuit 101. This makes it possible to drive the equipotentialization circuit 101 at any desired timing.

[0094] The control circuit 100 can drive the equipotentialization circuit 101 at a predetermined timing (for example, 3-4 in Figure 11) to make the potential of the bit line BL equal to the potential of the plate line PL. This makes it possible to recover the imprint at a desired timing after the imprint occurs, for example, and to sufficiently suppress read and write errors caused by the imprint.

[0095] The control circuit 100 can drive the equipotentialization circuit 101 at a predetermined timing (for example, 6-7 in Figure 11) to make the potential of the plate line PL equal to the potential of the bit line BL. This allows, for example, a write-back operation to be performed after the completion of a read operation or a write operation.

[0096] The control circuit 100 can drive the equipotentialization circuit 101 at a first predetermined timing (for example, 3-4 in Figure 11) to make the potential of the bit line BL equal to the potential of the plate line PL, and drive the equipotentialization circuit 101 at a second predetermined timing (for example, 6-7 in Figure 11) to make the potential of the plate line PL equal to the potential of the bit line BL. This sufficiently suppresses read and write errors due to imprinting, and allows write-back to be performed after the completion of a read or write operation.

[0097] The equipotentialization circuit 101 may include a switching element. This allows for further simplification of the equipotentialization circuit 101.

[0098] The equipotentialization circuit 101 may include a logic operation circuit. This reduces the parasitic capacitance of the equipotentialization circuit 101.

[0099] The memory device 10 may further include a plate wire potential keeping circuit 102 connected to the plate wire PL for maintaining the potential of the plate wire PL. This allows, for example, the PL potential to be made equal to the BL potential and then kept (held) at that PL potential.

[0100] The plate wire potential keeping circuit 102 can be driven by the control circuit 100 at a predetermined timing (for example, 4-7 in Figure 11). For example, after making the PL potential equal to the BL potential, the PL potential can be kept at that level for a desired time.

[0101] The plate wire potential keeping circuit 102 may include a latch circuit. This may simplify the circuit configuration of the plate wire potential keeping circuit 102.

[0102] The memory device 10 may further include a sense amplifier SA connected to the bit line BL. This allows for the detection and amplification of low-power signals from the bit line BL.

[0103] The sense amplifier SA can be driven by the control circuit 100 at predetermined timings (for example, 2-4 and 7-9 in Figure 11). This allows for the detection and amplification of low-power signals from the bit line BL at desired timings, such as during read operations or write operations.

[0104] The memory device 10 may further include a plate wire potential control circuit 103 connected to the plate wire PL, which controls the potential of the plate wire PL. This allows the potential of the plate wire PL to be controlled at any desired timing.

[0105] The plate wire potential control circuit 103 can be driven by the control circuit 100 at predetermined timings (for example, 1-3 and 7-10 in Figure 11). This allows the potential of the plate wire PL to be controlled at desired timings.

[0106] The plate line potential control circuit 103 may include a PL logic circuit 103a. This reduces the parasitic capacitance of the plate line potential control circuit 103.

[0107] The memory device 10 may further include a bit line potential control circuit 104 connected to the bit line BL, which controls the potential of the bit line BL. This allows the potential of the bit line BL to be controlled at any desired timing.

[0108] The bit line potential control circuit 104 can be driven by the control circuit 100 at predetermined timings (for example, 4-6 and 9-10 in Figure 11). This allows the potential of the bit line BL to be controlled at desired timings.

[0109] The bit line potential control circuit 104 may include a BL logic circuit 104a. This reduces the parasitic capacitance of the bit line potential control circuit 104.

[0110] The memory device 10 may further include a plate line potential control circuit 103 connected to the plate line PL and controlling the potential of the plate line PL, and a bit line potential control circuit 104 connected to the bit line BL and controlling the potential of the bit line BL. This allows the potential of the plate line PL to be controlled at any timing, and the potential of the bit line BL to be controlled at any timing.

[0111] <2. Memory device according to Example 2 of the first embodiment of this technology>

[0112] <<Configuration of Memory Device>> Figure 15 is a circuit diagram showing the configuration of a memory device 20 according to Example 2 of the first embodiment of this technology.

[0113] As shown in Figure 15, the memory device 20 has the same configuration as the memory device 10 according to Embodiment 1, except that the equipotentialization circuit 101 has two logic circuits and two MOS switches (power supply control units). Note that instead of MOS switches, for example, CMOS switches, relay switches, etc., may be used as power supply control units.

[0114] The equipotentialization circuit 101 includes a first circuit system for making the potential of the plate line PL equal to the potential of the bit line BL (copying the BL potential to the PL potential), and a second circuit system for making the potential of the bit line BL equal to the potential of the plate line PL (copying the PL potential to the BL potential).

[0115] The first circuit system includes a first AND circuit 101a1 as a logic operation circuit and a first MOS switch 101a3 as a power supply control unit that controls the on / off state of the power supply between the first AND circuit 101a1 and the bit line BL0. As an example, a first MOS switch 101a2 is connected between the bit line BL and the first AND circuit 101a1.

[0116] The second circuit system includes a second AND circuit 101b1 as a logic operation circuit and a second MOS switch 101b3 as a power supply control unit that controls the on / off state of the current supply between the second AND circuit 101b1 and the plate wire PL0. As an example, a second MOS switch 101b2 is connected between the plate wire PL and the second AND circuit 101b1.

[0117] The first AND gate 101a1 has one input terminal connected to the switch line BL-SW0, the other input terminal connected to the plate line PL, and its output terminal connected to the source of the first MOS switch 101a3. The drain of the first MOS switch 101a3 is connected to the bit line BL. A gate voltage is applied to the gate of the first MOS switch 101a3 by the control circuit 100.

[0118] The second AND gate 101b1 has one input terminal connected to the switch line PL-SW0, the other input terminal connected to the bit line BL, and its output terminal connected to the source of the second MOS switch 101b3. The drain of the second MOS switch 101b3 is connected to the plate line PL. A gate voltage is applied to the gate of the second MOS switch 101b3 by the control circuit 100.

[0119] It may also be interpreted that the memory device 20 has two equipotentialization circuits 101, and each equipotentialization circuit 101 has a logic operation circuit and a power supply control unit.

[0120] <<Operation of the Memory Device>> Figure 16 is a timing diagram showing the operation (read operation after data writing) of the memory device 20 according to Embodiment 2 of the first embodiment of this technology. The series of operation sequences shown in Figure 16 are executed by the control circuit 100. Here, the case in which memory cell MC000 is selected will be explained as an example.

[0121] 0: Set the WL potential to High to start the reading sequence. 1: Set the PL potential to High (PL-Driver ON) to start reading Data0 and Data1. 2: Enable (turn on) SA (ends the normal reading sequence). 3: Set the PL potential to FLT (PL-Driver OFF), and turn on the second MOS switch 101b3 by setting the switch line PL-SW potential to High to start equalizing the PL potential with the BL potential (copying the BL potential to the PL potential). 4: Turn off SA, and turn off the second MOS switch 101b3 by setting the switch line PL-SW potential to Low to end equalizing the PL potential with the BL potential, and also set the BL potential to High (BL-Driver ON), and turn on PL-Latch to start recovering Data0. 5: Set the BL potential to Low to end the recovery of Data0 and start recovering Data1. 6: Set the potential of switch line BL-SW to High and turn on the first MOS switch 101a3 to start making the BL potential equal to the PL potential (copying the PL potential to the BL potential), and finish the recovery of Data1. 7: Turn on SA, and set the potential of switch line BL-SW to Low and turn off the first MOS switch 101a3 to finish making the BL potential equal to the PL potential, and also set the PL potential to Low, and turn off PL-Latch, and start the Write-Back of Data1. 8: Set the PL potential to High to finish the Write-Back of Data1, and start the Write-Back of Data0. 9: Turn off SA, and set the PL potential and BL potential to Low. 10: Set the WL potential to Low to complete the read sequence.

[0122] <<Effects of the Memory Device>> In the memory device 20, each circuit system of the equipotentialization circuit 101 is composed of a logic operation circuit and a MOS switch. Therefore, compared to the case where the equipotentialization circuit 101 is composed only of CMOS switches or MOS switches, as in the memory device 10 of Embodiment 1, the parasitic capacitance of the MOS switches can be reduced, making it possible to improve the charging speed to the plate line PL and bit line BL.

[0123] <3. Memory device according to Example 3 of the first embodiment of this technology>

[0124] Figure 17 is a circuit diagram showing the configuration of a memory device 30 according to Embodiment 3 of the first embodiment of this technology.

[0125] As shown in Figure 17, the memory device 30 has the same configuration as the memory device 10 according to Embodiment 1, except that the equipotentialization circuit 101 has a CMOS switch 101A as a switching element.

[0126] Figure 18 is a timing diagram showing the write operation of the memory device 30 according to Embodiment 3 of the first embodiment of this technology. The series of operations shown in Figure 18 are executed by the control circuit 100. Here, the case in which memory cell MC000 is selected will be explained as an example.

[0127] 0: Set the WL potential to High to start the write sequence. 1: Apply a cycling pulse (positive bias to the plate line PL and bit line BL) to restore the imprint. 2: Write New Data 1, 0. 3: Set the PL potential and BL potential to Low to finish writing New Data 1, 0. 10: Set the WL potential to Low to complete the write sequence.

[0128] To elaborate, since it's acceptable to overwrite previous data during the writing process, a cycling pulse can be introduced before writing new data. The cycling pulse applied remains the same regardless of the previous data, and reading is not necessary.

[0129] <4. Memory device according to Example 4 of the first embodiment of this technology>

[0130] Figure 19 is a circuit diagram showing the configuration of a memory device 40 according to Embodiment 4 of the first embodiment of this technology.

[0131] As shown in Figure 19, the memory device 40 has the same configuration as the memory device 30 according to Embodiment 3.

[0132] In the memory device 40, the DC bias as the BL potential is applied (copied) to the PL potential by reading Old Data0 and Old Data1 in order to recover the imprint.

[0133] Figure 20 is a timing diagram showing the write operation of the memory device 40 according to Embodiment 4 of the first embodiment of this technology. The series of operations shown in Figure 20 are executed by the control circuit 100. Here, the case in which memory cell MC000 is selected will be explained as an example.

[0134] 0: Set the WL potential to High to start the write sequence. 1: Set the PL potential to High (PL-Driver ON) to start reading Old Data0 and Old Data1. 2: Enable (turn on) SA. 3: Set the PL potential to FLT (PL-Driver OFF) and turn on the CMOS switch 101A to start equalizing the PL potential with the BL potential (copying the BL potential to the PL potential). 4: Turn off SA and the CMOS switch 101A to finish equalizing the PL potential with the BL potential, set the BL potential to High (BL-Driver ON), and turn on PL-Latch to start recovering Old Data0. 5: Set the BL potential to Low to finish recovering Old Data0 and start recovering Old Data1. 6: Turn on the CMOS switch 101A to start the process of making the BL potential equal to the PL potential (copying the PL potential to the BL potential), and turn off the PL-Latch to finish the recovery of Old Data1 and start writing New Data0 and New Data1 (it is recommended to finish the read sequence at this point). 7: Set the PL potential and BL potential to Low, and turn off the CMOS switch 101A to finish making the BL potential equal to the PL potential. 8: Set the WL potential to Low to complete the write sequence.

[0135] To elaborate, in the memory device 40, the polarity of the DC bias introduced for recovery differs depending on the data being held (Old Data), so it is necessary to read it once. Note that pre-reading is not performed during normal write operations, so the recovery operation is not triggered.

[0136] The following describes the method for adjusting the DC bias. Figure 21 shows an example of a bias adjustment method using bias application time. Figure 22 shows an example of a bias adjustment method using bias application voltage. Here, when the system returns from standby, all bits are restored by applying a DC bias all at once. Specifically, the DC bias application time or applied voltage is changed according to the time from the last access time to the peripheral circuit until the system returns.

[0137] In the example shown in Figure 21, when there is access to the peripheral circuit of the memory cell, all bits are recovered simultaneously by applying a DC bias. The bias application time at this time is t bias = f ( t wait ) However, t wait This is defined as the time from the last access to the peripheral circuit to the next access.

[0138] In the example shown in Figure 22, when there is access to the peripheral circuit of the memory cell, all bits are recovered simultaneously by applying a DC bias. The bias voltage applied at this time is V bias = g ( t wait ) However, t wait This is defined as the time from the last access to the peripheral circuit to the next access.

[0139] To elaborate, the absence of access to peripheral circuits is equivalent to all bits being uniformly affected by the imprint, so whenever there is access to peripheral circuits from standby, non-destructive recovery using DC bias is performed each time.

[0140] <5. Memory device according to Example 1 of the second embodiment of this technology>

[0141] Figure 23 is a circuit diagram showing the configuration of the memory cell array MCA and equipotentialization circuit 101 of the memory device 50 according to Example 1 of the second embodiment of this technology.

[0142] As an example, the memory device 50 includes a memory cell MC which is a real cell, a reference cell RC, a bit line BL0 to which one end of the memory cell MC is connected, a bit line / BL0 to which one end of the reference cell RC is connected, a plate line PL0 to which the other end of the memory cell MC and the other end of the reference cell RC are connected, a CMOS switch 101A as an equipotentialization circuit 101 connected between the bit line BL0 and the plate line PL0, and a CMOS switch 101B as an equipotentialization circuit 101 connected between the bit line / BL0 and the plate line PL0. The memory device 50 further includes a sense amplifier connected to the bit line BL0 and a sense amplifier connected to the bit line / BL0. The bit line BL0, the bit line / BL0 and the plate line PL0 are arranged parallel to each other, and the plate line PL0 is located between the bit line BL0 and the bit line / BL0. Multiple (e.g., three) word lines WL (e.g., WL0, WL1, WL2) and switch lines SW0, / SW0, SW1, / SW1 are arranged orthogonally, insulated from the bit line BL0, bit line / BL0, and plate line PL0.

[0143] The memory device 50, as an example, includes two equipotentialization circuits 101, a plate line potential keeping circuit 102, a plate line potential control circuit 103, a bit line potential control circuit 104, and a control circuit 100. The control circuit 100 controls the potential of each word line WL (WL potential), as well as the plate line potential keeping circuit 102, the plate line potential control circuit 103, the bit line potential control circuit 104, and each sense amplifier.

[0144] The memory device 10, as an example, has a memory cell array that includes a plurality (e.g., three) of memory cells MC and a plurality (e.g., three) of reference cells RC. The memory array has a 2T2C type memory cell structure in which the memory cells MC and reference cells RC are arranged adjacent to each other.

[0145] As an example, the three memory cell MCs include memory cell MC000 connected to word line WL0, bit line BL0, and plate line PL0; memory cell MC100 connected to word line WL1, bit line BL0, and plate line PL0; and memory cell MC200 connected to word line WL2, bit line BL0, and plate line PL0.

[0146] As an example, the three reference cells RC include reference cell RC000 connected to word line WL0, bit line / BL0 and plate line PL0, reference cell RC100 connected to word line WL1, bit line / BL0 and plate line PL0, and reference cell RC200 connected to word line WL2, bit line / BL0 and plate line PL0.

[0147] Memory cell MC000 corresponds to reference cell RC000. Memory cell MC100 corresponds to reference cell RC100. Memory cell MC200 corresponds to reference cell RC200.

[0148] The memory cell MC consists of a transistor Tr1 (cell selection transistor) and a variable capacitance capacitor VC1. The reference cell RC consists of a transistor Tr2 (cell selection transistor) and a variable capacitance capacitor VC2.

[0149] In each memory cell MC and each reference cell RC, a MOSFET (metal-oxide-semiconductor field-effect transistor) as a transistor Tr and a ferroelectric capacitor as a variable capacitance capacitor VC are connected in series.

[0150] A ferroelectric capacitor has a three-layer structure in which a ferroelectric material is sandwiched between a pair of electrodes (conductors). The direction of polarization of the ferroelectric material corresponds to the "high" or "low" logical values. Examples of ferroelectric materials include barium titanate (BaTiO3), PZT (lead zirconate titanate: PbZrTiO3), SBT (strontium bismuth tantalate: SrBi2Ta2O9), and hafnium oxide (HfOx).

[0151] For example, a transistor Tr1 (e.g., an nMOSFET) has its drain connected to the bit line BL0 and its source connected to one electrode of a variable capacitance capacitor VC1. The other electrode of the variable capacitance capacitor VC1 is connected to the plate line PL0.

[0152] For example, a transistor Tr2 (e.g., an nMOSFET) has its drain connected to the bit line / BL0 and its source connected to one electrode of a variable capacitance capacitor VC2. The other electrode of the variable capacitance capacitor VC2 is connected to the plate line PL0.

[0153] A word line WL is provided for each pair of corresponding memory cells MC and reference cells RC. The gate of transistor Tr1 of memory cell MC000 is connected to the corresponding word line WL0. The gate of transistor Tr1 of memory cell MC100 is connected to the corresponding word line WL1. The gate of transistor Tr1 of memory cell MC200 is connected to the corresponding word line WL2. The gate of transistor Tr2 of reference cell RC000 is connected to the corresponding word line WL0. The gate of transistor Tr2 of reference cell RC100 is connected to the corresponding word line WL1. The gate of transistor Tr2 of reference cell RC200 is connected to the corresponding word line WL2.

[0154] The CMOS switch 101A, acting as an equipotentialization circuit 101, can make the potential of the bit line BL0 (BL potential) equal to the potential of the plate line PL0 (PL potential), and / or make the potential of the plate line PL0 (PL potential) equal to the potential of the bit line BL0 (BL potential). Equipotentialization by the equipotentialization circuit 101 is also called "potential copying".

[0155] The CMOS switch 101B, acting as an equipotentialization circuit 101, can make the potential of the bit line / BL0 (BL potential) equal to the potential of the plate line PL0 (PL potential), and / or make the potential of the plate line PL0 equal to the potential of the bit line / BL0. Equipotentialization by the equipotentialization circuit 101 is also called "potential copying".

[0156] The CMOS switch 101A, acting as the equipotential circuit 101, has an input terminal on one side (bit line BL0) and the other side (plate line PL0), and an output terminal on the other side. In this configuration, the input terminal of the CMOS switch 101A is connected to the switch line SW0, the output terminal is connected to the switch line SW0, the source of the pMOS is connected to the bit line BL0, and the source of the nMOS is connected to the plate line PL0.

[0157] The CMOS switch 101B, acting as the equipotential circuit 101, has an input terminal on one side (bit line / BL0) and an output terminal on the other side (plate line PL0). In this configuration, the input terminal of the CMOS switch 101B is connected to the switch line SW1, the output terminal is connected to the switch line / SW1, the source of the pMOS is connected to the bit line / BL0, and the source of the nMOS is connected to the plate line PL0.

[0158] Each equipotential circuit 101 is controlled by the control circuit 100.

[0159] The memory device 50 is capable of performing operations (including recovery sequences) that are generally similar to the operations (including recovery sequences) of the memory devices 10, 30, and 40 according to Examples 1, 3, and 4 of the first embodiment.

[0160] The memory device 50 provides a 2T2C type memory device that simplifies the configuration of the equipotentialization circuit 101.

[0161] In the 2T2C type, unlike the 1T1C type, the reference cell that holds complementary data indicates the reference potential. In the 2T2C type, during reading, both VBLL and VBLH are downward sloping, so it is hardly affected by imprinting (see Figure 24A). During writing, VBLL is upward sloping and VBLH is downward sloping, so it is affected by imprinting (see Figure 24B). Therefore, recovery is also necessary in the 2T2C type.

[0162] <6. Memory device according to Example 2 of the second embodiment of this technology>

[0163] Figure 25 is a circuit diagram showing the configuration of a memory device 60 according to Embodiment 6 of the second embodiment of this technology.

[0164] As shown in Figure 25, the memory device 60 has the same configuration as the memory device 50 according to Embodiment 2 of the second embodiment, except that it includes two equipotentialization circuits 101C and 101D, and each equipotentialization circuit has two logic operation circuits and two power supply control units.

[0165] Each equipotentialization circuit 101 includes a first circuit system for making the potential of the plate line PL equal to the potential of the bit line BL (copying the BL potential to the PL potential), and a second circuit system for making the potential of the bit line BL equal to the potential of the plate line PL (copying the PL potential to the BL potential).

[0166] The first circuit system of the equipotentialization circuit 101C includes an AND circuit 101a1 as a logic operation circuit and a MOS switch 101a3 as a power supply control unit that controls the on / off switching of power between the AND circuit 101a1 and the bit line BL0.

[0167] The second circuit system of the equipotentialization circuit 101C includes an AND circuit 101b1 as a logic operation circuit and a MOS switch 101b3 as a power supply control unit that controls the on / off switching of the current between the AND circuit 101b1 and the plate wire PL0.

[0168] The first circuit system of the equipotentialization circuit 101D includes an AND circuit 101c1 as a logic operation circuit and a MOS switch 101c3 as a power supply control unit that controls the on / off switching of power between the AND circuit 101c1 and the bit line / BL0.

[0169] The second circuit system of the equipotentialization circuit 101C includes an AND circuit 101d1 as a logic operation circuit and a MOS switch 101d3 as a power supply control unit that controls the on / off switching of the current between the AND circuit 101d1 and the plate wire PL0.

[0170] As an example, a MOS switch 101a3 is connected between the bit line BL and the AND circuit 101a1. As an example, a MOS switch 101b3 is connected between the plate line PL and the AND circuit 101b1.

[0171] As an example, a MOS switch 101c3 is connected between the bit line / BL and the AND circuit 101c1. As an example, a MOS switch 101d3 is connected between the plate line PL and the AND circuit 101d1.

[0172] The AND gate 101a1 has one input terminal connected to the switch line BL-SW00, the other input terminal connected to the plate line PL, and the output terminal connected to the source of the MOS switch 101a3. The drain of the MOS switch 101a3 is connected to the bit line BL. The gate voltage of the MOS switch 101a3 is applied by the control circuit 100.

[0173] The AND gate 101b1 has one input terminal connected to the switch line PL-SW00, the other input terminal connected to the bit line BL, and the output terminal connected to the source of the MOS switch 101b3. The drain of the MOS switch 101b3 is connected to the plate line PL. The gate voltage of the MOS switch 101b3 is applied by the control circuit 100.

[0174] The AND gate 101c1 has one input terminal connected to the switch line BL-SW01, the other input terminal connected to the plate line PL, and the output terminal connected to the source of the MOS switch 101c3. The drain of the MOS switch 101c3 is connected to the bit line / BL. The gate voltage of the MOS switch 101c3 is applied by the control circuit 100.

[0175] The AND gate 101d1 has one input terminal connected to the switch line PL-SW01, the other input terminal connected to the bit line / BL, and the output terminal connected to the source of the MOS switch 101d3. The drain of the MOS switch 101d3 is connected to the plate line PL. The gate voltage of the MOS switch 101d3 is applied by the control circuit 100.

[0176] The memory device 60 is capable of performing operations (including recovery sequences) that are generally similar to those of the memory device 20 according to Embodiment 2 of the first embodiment.

[0177] The memory device 60 provides a 2T2C type memory device that can reduce the parasitic capacitance of the equipotentialization circuit 101.

[0178] Although the first and second embodiments have been described above, this technology is not limited to these embodiments and can be modified as appropriate.

[0179] For example, the number of word lines, bit lines, and plate lines can be changed as appropriate, and the number of memory cells can be changed accordingly. At least one memory cell is sufficient.

[0180] For example, parts of the configuration of the memory device according to each embodiment of the first and second embodiments described above may be combined within a range that is not contradictory to one another.

[0181] <7. Examples of use of a solid-state imaging device equipped with a memory device to which this technology is applied> Figure 28 shows examples of use of a solid-state imaging device (image sensor) equipped with a memory device according to this technology (for example, the memory device according to the first and second embodiments).

[0182] Each of the embodiments described above can be used in various cases of sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as shown below. That is, as shown in Figure 33, it can be used in devices used in fields such as the field of viewing images for viewing purposes, the field of transportation, the field of home appliances, the field of medical care and healthcare, the field of security, the field of beauty, the field of sports, and the field of agriculture.

[0183] Specifically, in the field of appreciation, for example, a solid-state imaging device equipped with a memory device according to this technology can be used in devices for capturing images intended for appreciation, such as digital cameras, smartphones, and mobile phones with camera functions.

[0184] In the field of transportation, for example, a solid-state imaging device equipped with a memory device according to this technology can be used in devices used for transportation purposes, such as in-vehicle sensors that photograph the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping, or for recognizing the driver's condition; surveillance cameras that monitor moving vehicles and roads; and distance measuring sensors that measure distances between vehicles.

[0185] In the field of home appliances, for example, a solid-state imaging device equipped with a memory device related to this technology can be used in devices used in home appliances such as television sets, refrigerators, and air conditioners to capture user gestures and perform device operations according to those gestures.

[0186] In the medical and healthcare fields, for example, a solid-state imaging device equipped with a memory device related to this technology can be used in devices used for medical and healthcare purposes, such as endoscopes and devices that perform angiography using infrared light reception.

[0187] In the field of security, for example, a solid-state imaging device equipped with a memory device related to this technology can be used in security devices such as surveillance cameras for crime prevention or cameras for person authentication.

[0188] In the field of beauty, for example, a solid-state imaging device equipped with a memory device according to this technology can be used in devices used for beauty purposes, such as skin measuring devices for photographing skin or microscopes for photographing the scalp.

[0189] In the field of sports, for example, a solid-state imaging device equipped with a memory device according to this technology can be used in sports equipment such as action cameras and wearable cameras for sports purposes.

[0190] In the field of agriculture, for example, a solid-state imaging device equipped with a memory device according to this technology can be used in agricultural equipment such as cameras for monitoring the condition of fields and crops.

[0191] Next, we will specifically describe examples of the use of a solid-state imaging device equipped with a memory device according to this technology (for example, the memory devices according to the first and second embodiments). For example, the memory devices according to the first and second embodiments described above can be used in any type of electronic device equipped with an imaging function, such as camera systems such as digital still cameras and video cameras, or mobile phones with imaging functions. Figure 29 shows a schematic configuration of an electronic device 510 (camera) as an example. This electronic device 510 is, for example, a video camera capable of shooting still images or moving images, and includes a solid-state imaging device 501, an optical system (optical lens) 502, a shutter device 503, a drive unit 504 that drives the solid-state imaging device 501 and the shutter device 503, and a signal processing unit 505.

[0192] The optical system 502 guides the image light (incident light) from the subject to the pixel area of ​​the solid-state imaging device 501. This optical system 502 may be composed of multiple optical lenses. The shutter device 503 controls the light irradiation period and the light shielding period for the solid-state imaging device 501. The drive unit 504 controls the transfer operation of the solid-state imaging device 501 and the shutter operation of the shutter device 503. The signal processing unit 505 performs various signal processing on the signal output from the solid-state imaging device 501. The video signal Dout after signal processing is stored in the memory device according to this technology or output to a monitor or the like.

[0193] <8. Examples of Application to Objects> The technology relating to this disclosure (this technology) can be applied to various products (objects). For example, the technology relating to this disclosure may be realized as a device mounted on any of the above-mentioned types of mobile objects such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots, or on low-power devices (e.g., smartphones, smartwatches, tablets, laptops, eyewear (e.g., head-mounted displays), etc.).

[0194] Figure 30 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0195] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 30, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0196] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0197] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0198] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0199] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0200] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0201] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including vehicle collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0202] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0203] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0204] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 30, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0205] Figure 31 shows an example of the installation position of the imaging unit 12031.

[0206] In Figure 31, the vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0207] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by imaging units 12101 and 12105 are mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0208] Figure 31 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0209] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0210] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, etc., that drives autonomously without driver operation, can be performed.

[0211] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0212] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0213] The above describes an example of a vehicle control system to which the technology relating to this disclosure (this technology) may be applied. The technology relating to this disclosure can be applied to, for example, the imaging unit 12031, among the configurations described above. Specifically, the solid-state imaging device 501 of this disclosure can be applied to the imaging unit 12031. By applying the technology relating to this disclosure to the imaging unit 12031, it is possible to improve yield and reduce manufacturing costs.

[0214] <9. Examples of Application to Endoscopic Surgical Systems> This technology can be applied to various products. For example, the technology disclosed herein (this technology) may be applied to an endoscopic surgical system.

[0215] Figure 32 is a diagram showing an example of a schematic configuration of an endoscopic surgical system to which the technology described herein (the technology) may be applied.

[0216] Figure 32 illustrates a surgeon (physician) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgical system 11000. As shown in the figure, the endoscopic surgical system 11000 consists of an endoscope 11100, other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy treatment device 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 equipped with various devices for endoscopic surgery.

[0217] The endoscope 11100 consists of a barrel 11101, the tip of which is inserted into the body cavity of the patient 11132 for a predetermined length, and a camera head 11102 connected to the base end of the barrel 11101. In the illustrated example, the endoscope 11100 is shown as a so-called rigid endoscope having a rigid barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible endoscope having a flexible barrel.

[0218] An opening into which an objective lens is fitted is provided at the tip of the microscope tube 11101. A light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the tip of the microscope tube by a light guide extending inside the microscope tube 11101, and is irradiated through the objective lens towards the object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a straight-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0219] The camera head 11102 contains an optical system and an image sensor. Reflected light from the object being observed (observation light) is focused onto the image sensor by the optical system. The image sensor converts the observation light into electrical signals, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0220] The CCU 11201 is composed of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and other components, and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various image processing operations on that image signal, such as development processing (demosaic processing), to display the image based on that image signal.

[0221] The display device 11202 displays an image based on an image signal that has been processed by the CCU 11201, under control from the CCU 11201.

[0222] The light source device 11203 consists of a light source such as an LED (Light Emitting Diode) and supplies illumination light to the endoscope 11100 when photographing the surgical area, etc.

[0223] The input device 11204 is an input interface for the endoscopic surgical system 11000. The user can input various types of information and instructions to the endoscopic surgical system 11000 via the input device 11204. For example, the user can input instructions to change the imaging conditions (type of light, magnification, focal length, etc.) of the endoscope 11100.

[0224] The treatment instrument control device 11205 controls the drive of the energy treatment instrument 11112 for purposes such as tissue cauterization, incision, or blood vessel sealing. The insufflation device 11206 injects gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity for the purpose of securing a field of view by the endoscope 11100 and securing the operator's workspace. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, images, or graphs.

[0225] The light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical area can be configured as a white light source consisting of, for example, an LED, a laser light source, or a combination thereof. When the white light source is configured as a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to capture images corresponding to each of the RGB colors in time-division by irradiating the observation target with laser light from each of the RGB laser light sources in time-division and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter on the image sensor.

[0226] Furthermore, the light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the drive of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity, images can be acquired in time-division order, and these images can be combined to generate high dynamic range images without so-called black crushing and white clipping.

[0227] Furthermore, the light source device 11203 may be configured to supply light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption in body tissue and irradiating with narrow-band light compared to the irradiation light used in normal observation (i.e., white light), so-called narrow-band imaging is performed to image predetermined tissues such as blood vessels on the surface of mucosa with high contrast. Alternatively, in special light observation, fluorescence observation may be performed to obtain an image from fluorescence generated by irradiation with excitation light. In fluorescence observation, excitation light is irradiated onto body tissue and fluorescence from the body tissue is observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) is injected into body tissue and excitation light corresponding to the fluorescence wavelength of the reagent is irradiated onto the body tissue to obtain a fluorescence image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0228] Figure 33 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in Figure 32.

[0229] The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0230] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and then incident on the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses, including a zoom lens and a focus lens.

[0231] The imaging unit 11402 is composed of image sensors. The imaging unit 11402 may consist of one image sensor (a so-called single-chip type) or multiple image sensors (a so-called multi-chip type). If the imaging unit 11402 is composed of multiple chips, for example, each image sensor may generate image signals corresponding to RGB, and these may be combined to obtain a color image. Alternatively, the imaging unit 11402 may be configured to have a pair of image sensors for acquiring image signals for the right eye and left eye, respectively, corresponding to 3D (Dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical area. In addition, if the imaging unit 11402 is composed of multiple chips, multiple lens units 11401 may also be provided corresponding to each image sensor.

[0232] Furthermore, the imaging unit 11402 does not necessarily have to be located on the camera head 11102. For example, the imaging unit 11402 may be located inside the lens barrel 11101, directly behind the objective lens.

[0233] The drive unit 11403 is composed of actuators and, under control from the camera head control unit 11405, moves the zoom lens and focus lens of the lens unit 11401 along the optical axis by a predetermined distance. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted as appropriate.

[0234] The communication unit 11404 is composed of communication devices for sending and receiving various types of information with the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0235] Furthermore, the communication unit 11404 receives a control signal from the CCU 11201 to control the drive of the camera head 11102 and supplies it to the camera head control unit 11405. The control signal includes information about imaging conditions, such as information to specify the frame rate of the captured image, information to specify the exposure value at the time of imaging, and / or information to specify the magnification and focus of the captured image.

[0236] The imaging conditions such as frame rate, exposure value, magnification, and focus may be specified by the user as appropriate, or they may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 will be equipped with so-called AE (Auto Exposure), AF (Auto Focus), and AWB (Auto White Balance) functions.

[0237] The camera head control unit 11405 controls the drive of the camera head 11102 based on the control signal received from the CCU 11201 via the communication unit 11404.

[0238] The communication unit 11411 is comprised of a communication device for sending and receiving various types of information with the camera head 11102. The communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400.

[0239] Furthermore, the communication unit 11411 transmits control signals to the camera head 11102 to control the driving of the camera head 11102. Image signals and control signals can be transmitted by telecommunications, optical communications, etc.

[0240] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102.

[0241] The control unit 11413 performs various controls related to imaging the surgical area, etc., by the endoscope 11100, and the display of the images obtained from imaging the surgical area, etc. For example, the control unit 11413 generates a control signal to control the driving of the camera head 11102.

[0242] Furthermore, the control unit 11413 displays the captured image showing the surgical area, etc., on the display device 11202 based on the image signal processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical instruments such as forceps, specific biological sites, bleeding, mist when using the energy treatment device 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When the control unit 11413 displays the captured image on the display device 11202, it may use the recognition results to superimpose various surgical support information onto the image of the surgical area. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can proceed with the surgery reliably.

[0243] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable thereof.

[0244] In the illustrated example, communication was performed via a wired connection using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.

[0245] The above describes an example of an endoscopic surgical system to which the technology relating to this disclosure may be applied. The technology relating to this disclosure can be applied to the endoscope 11100, the camera head 11102 (and its imaging unit 11402), etc., among the configurations described above. Specifically, the solid-state imaging device 111 of this disclosure can be applied to the imaging unit 10402. By applying the technology relating to this disclosure to the endoscope 11100, the camera head 11102 (and its imaging unit 11402), etc., it is possible to improve yield and reduce manufacturing costs.

[0246] Here, an endoscopic surgical system has been described as an example, but the technology relating to this disclosure may also be applied to other systems, such as microsurgical systems.

[0247] Furthermore, this technology can also take the following configurations: (1) A memory device comprising: a memory cell; a bit line to which one end of the memory cell is connected; a plate line to which the other end of the memory cell is connected; and an equipotentialization circuit connected between the bit line and the plate line, which is capable of making the potential of the bit line equal to the potential of the plate line, and / or making the potential of the plate line equal to the potential of the bit line. (2) The memory device according to (1), wherein the equipotentialization circuit has an input terminal on one of the bit line side and the plate line side, and an output terminal on the other. (3) The memory device according to (1) or (2), further comprising a control circuit for controlling at least the equipotentialization circuit. (4) The memory device according to (3), wherein the control circuit drives the equipotentialization circuit at a predetermined timing to make the potential of the bit line equal to the potential of the plate line. (5) The memory device according to (3) or (4), wherein the control circuit drives the equipotentialization circuit at a predetermined timing to make the potential of the plate line equal to the potential of the bit line. (6) The memory device according to any one of (3) to (5), wherein the control circuit drives the equipotentialization circuit at a first predetermined timing to make the potential of the bit line equal to the potential of the plate line, and drives the equipotentialization circuit at a second predetermined timing to make the potential of the plate line equal to the potential of the bit line. (7) The memory device according to any one of (1) to (6), wherein the equipotentialization circuit includes a switching element. (8) The memory device according to any one of (1) to (7), wherein the equipotentialization circuit includes a logic operation circuit. (9) The memory device according to (8), wherein the equipotentialization circuit includes a power supply control unit that controls the on / off of power supply to the logic operation circuit. (10) A memory device according to any one of (3) to (9), further comprising a plate wire potential keeping circuit connected to the plate wire for keeping the potential of the plate wire. (11) A memory device according to (10), wherein the plate wire potential keeping circuit is driven at predetermined timings by the control circuit. (12) A memory device according to (10) or (11), further comprising a power supply control unit for controlling the on / off switching of power supply to the plate wire potential keeping circuit.(13) The memory device according to any one of (10) to (12), wherein the plate line potential keeping circuit includes a latch circuit. (14) The memory device according to any one of (3) to (13), further comprising a sense amplifier connected to the bit line. (15) The memory device according to (14), wherein the sense amplifier is driven at a predetermined timing by the control circuit. (16) The memory device according to (3), further comprising a plate line potential control circuit connected to the plate line and controlling the potential of the plate line. (17) The memory device according to (16), wherein the plate line potential control circuit is driven at a predetermined timing by the control circuit. (18) The memory device according to (16) or (17), further comprising a power supply control unit that controls the on / off of the power supply to the plate line potential control circuit. (19) The memory device according to any one of (16) to (18), wherein the plate line potential control circuit includes a logic circuit. (20) A memory device according to any one of (3) to (19), further comprising a bit line potential control circuit connected to the bit line and controlling the potential of the bit line. (21) A memory device according to (20), wherein the bit line potential control circuit is driven at predetermined timings by the control circuit. (22) A memory device according to (20) or (21), further comprising a power supply control unit that controls the on / off switching of power to the bit line potential control circuit. (23) A memory device according to any one of (20) to (22), wherein the bit line potential control circuit includes a logic circuit. (24) A memory device according to any one of (1) to (23), further comprising a plate line potential control circuit connected to the plate line and controlling the potential of the plate line, and a bit line potential control circuit connected to the bit line and controlling the potential of the bit line. (25) A memory device according to any one of (1) to (24), wherein the memory cell includes a transistor and a variable capacitance capacitor connected to the transistor. (26) The memory device according to (25), wherein the variable capacitance capacitor includes a ferroelectric material. (27) The memory device according to any one of (1) to (26), wherein a plurality of the memory cells are arranged in an array. (28) An electronic device comprising the memory device according to any one of (1) to (27).

[0248] 10, 20, 30, 40, 50, 60: Memory devices 101: Equipotentialization circuit 101A: CMOS switch (equipotentialization circuit) 101B: CMOS switch (equipotentialization circuit) 101a1: AND circuit (logic operation circuit) 101b1: AND circuit (logic operation circuit) 101a3: MOS switch (power control unit) 101b3: MOS switch (power control unit) 101c1: AND circuit (logic operation circuit) 101c2: MOS switch 101d1: AND circuit (logic operation circuit) 101d2: MOS switch 102: Plate line potential keeping circuit 103: Plate line potential control circuit 104: Bit line potential control circuit BL: Bit line PL: Plate line MC (MC000, MC100, MC200, MC011, MC111, MC211): Memory cells MCA: Memory cell array SA: SenseAmp

Claims

1. A memory device comprising: a memory cell; a bit line to which one end of the memory cell is connected; a plate line to which the other end of the memory cell is connected; and an equipotentialization circuit connected between the bit line and the plate line, which is capable of making the potential of the bit line equal to the potential of the plate line, and / or making the potential of the plate line equal to the potential of the bit line.

2. The memory device according to claim 1, wherein the equipotentializing circuit has an input terminal on one of the bit line side and the plate line side, and an output terminal on the other side.

3. The memory device according to claim 1, further comprising a control circuit for controlling at least the equipotential circuit.

4. The memory device according to claim 3, wherein the control circuit drives the equipotential circuit at a predetermined timing to make the potential of the bit line equal to the potential of the plate line.

5. The memory device according to claim 3, wherein the control circuit drives the equipotential circuit at a predetermined timing to make the potential of the plate line equal to the potential of the bit line.

6. The memory device according to claim 3, wherein the control circuit drives the equipotentialization circuit at a first predetermined timing to make the potential of the bit line equal to the potential of the plate line, and drives the equipotentialization circuit at a second predetermined timing to make the potential of the plate line equal to the potential of the bit line.

7. The memory device according to claim 1, wherein the equipotentialization circuit includes a switching element.

8. The memory device according to claim 1, wherein the equipotentialization circuit includes a logic operation circuit.

9. The memory device according to claim 3, further comprising a plate wire potential keeping circuit connected to the plate wire for keeping the potential of the plate wire.

10. The memory device according to claim 9, wherein the plate wire potential keeping circuit is driven at a predetermined timing by the control circuit.

11. The memory device according to claim 9, wherein the plate wire potential keeping circuit includes a latch circuit.

12. The memory device according to claim 3, further comprising a sense amplifier connected to the bit line.

13. The memory device according to claim 12, wherein the sense amplifier is driven at a predetermined timing by the control circuit.

14. The memory device according to claim 3, further comprising a plate wire potential control circuit connected to the plate wire and controlling the potential of the plate wire.

15. The memory device according to claim 14, wherein the plate wire potential control circuit is driven at a predetermined timing by the control circuit.

16. The memory device according to claim 14, wherein the plate wire potential control circuit includes a logic circuit.

17. The memory device according to claim 3, further comprising a bit line potential control circuit connected to the bit line and controlling the potential of the bit line.

18. The memory device according to claim 17, wherein the bit line potential control circuit is driven by the control circuit at a predetermined timing.

19. The memory device according to claim 17, wherein the bit line potential control circuit includes a logic circuit.

20. The memory device according to claim 1, further comprising: a plate line potential control circuit connected to the plate line and controlling the potential of the plate line; and a bit line potential control circuit connected to the bit line and controlling the potential of the bit line.

Images