Imaging device and electronic apparatus

Abstract

An imaging device according to an embodiment of the present invention comprises: a pixel that generates a pixel signal; a generation circuit that generates a reference signal; a compensation circuit that corrects the reference signal on the basis of a power supply voltage; and an analog-to-digital (AD) conversion circuit that converts the reference signal into a digital signal. The AD conversion circuit includes: an amplification circuit that amplifies the reference signal corrected by the compensation circuit; a comparator that compares the reference signal amplified by the amplification circuit with the pixel signal generated by the pixel; and a cancellation capacitor electrically connected between the amplification circuit and the comparator.

Description

Imaging device and electronic apparatus

[0001] The present disclosure relates to an imaging device and an electronic apparatus.

[0002] Among imaging devices such as solid-state imaging devices (image sensors), an imaging device has been proposed that performs in-phase cancellation of power supply noise (e.g., power supply ripple) superimposed on vertical signal lines connected to pixels by superimposing the noise on a differential reference signal (RAMP) by means of a PSRR (Power Supply Rejection Ratio) compensation circuit (see, for example, Patent Document 1).

[0003] Japanese Unexamined Patent Publication No. 2021-93697

[0004] However, when an imaging device is increased in size due to an increase in the number of pixels, the wiring length of a ramp signal line through which a reference signal is transmitted becomes longer, which increases the wiring load and reduces the bandwidth of a low-pass filter formed by the wiring load. As a result, it becomes difficult for a high-frequency component correction signal from the PSRR compensation circuit to be transmitted, and high-frequency power supply noise may remain in a signal after AD (analog-to-digital) conversion without being canceled.

[0005] Therefore, the present disclosure provides an imaging device and an electronic apparatus capable of reducing power supply noise.

[0006] An imaging device according to an embodiment includes: a pixel that generates a pixel signal; a generation circuit that generates a reference signal; a compensation circuit that corrects the reference signal based on a power supply voltage; and an AD conversion circuit that converts the reference signal into a digital signal. The AD conversion circuit includes: an amplification circuit that amplifies the reference signal corrected by the compensation circuit; a comparator that compares the reference signal amplified by the amplification circuit with the pixel signal generated by the pixel; and a cancellation capacitor electrically connected between the amplification circuit and the comparator.

[0007] The electronic device according to the embodiment includes an imaging device, the imaging device includes pixels that generate pixel signals, a generation circuit that generates a reference signal, a compensation circuit that corrects the reference signal based on a power supply voltage, and an AD conversion circuit that converts the reference signal into a digital signal, the AD conversion circuit includes an amplification circuit that amplifies the reference signal corrected by the compensation circuit, a comparator that compares the reference signal amplified by the amplification circuit with the pixel signal generated by the pixels, and a cancellation capacitor electrically connected between the amplification circuit and the comparator.

[0008] This is a diagram showing an example configuration of an imaging device according to an embodiment. This is a diagram showing an example configuration of a pixel according to an embodiment. This is a diagram showing an example configuration of an AD conversion unit according to an embodiment. This is a diagram showing an example configuration of a reference signal generation unit and an AD conversion circuit according to an embodiment. This is a diagram showing an example configuration of a reference signal generation unit and an AD conversion circuit according to an embodiment. This is a graph for explaining the correction signal according to an embodiment. This is a graph for explaining the cutoff frequency change of a low-pass filter due to a wiring load according to an embodiment. This is a graph for explaining the gain change with and without a low-pass filter due to a wiring load according to an embodiment. This is a graph for explaining the gain change with and without a high-pass filter due to a cancellation capacitance according to an embodiment. This is a diagram showing an example configuration of a comparator in Embodiment 1 according to an embodiment. This is a diagram showing an example configuration of a comparator in Embodiment 2 according to an embodiment. This is a diagram showing an example configuration of a comparator in Embodiment 3 according to an embodiment. This is a diagram showing an application example of the imaging device according to the above-described embodiment. This is a diagram showing an example configuration of an imaging device according to an application example. This is a diagram showing an example configuration of a distance measuring device according to an application example.

[0009] Embodiments of this disclosure will be described in detail below with reference to the drawings. Embodiments include examples and modifications. However, the technology relating to this disclosure is not limited by the embodiments. In addition, in the following embodiments, the same reference numerals are used for essentially the same parts to omit redundant explanations.

[0010] This disclosure will be described in the following order of items: 1. Embodiments 1-1. Example of imaging device configuration 1-2. Example of pixel configuration 1-3. Example of AD conversion unit configuration 1-4. Example of reference signal generation unit and AD conversion circuit configuration 1-5. Example of reference signal generation 1-6. Example of comparator configuration 2. Operation and effects of the embodiment 3. Other embodiments 4. Application examples 4-1. Various devices 4-2. Imaging device 4-3. Distancing device 5. Notes

[0011] <1. Embodiments> <1-1. Example of Imaging Device Configuration> An imaging device 10 according to an embodiment will be described with reference to Figure 1. Figure 1 is a diagram showing an example of the configuration of an imaging device 10 according to an embodiment.

[0012] As shown in Figure 1, the imaging device 10 according to this embodiment comprises a pixel array unit 11 and a peripheral circuit unit of the pixel array unit 11. The peripheral circuit unit of the pixel array unit 11 is composed of, for example, a vertical scanning unit 12, a column processing unit 13, a horizontal scanning unit 14, a digital signal calculation unit 15, and a timing control unit 16.

[0013] The imaging device 10 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor, which is a type of X-Y addressing image sensor. A CMOS image sensor is an image sensor manufactured by applying or partially using the CMOS process.

[0014] The pixel array section 11 has a configuration in which pixels 20, including photoelectric conversion sections (photoelectric conversion elements), are arranged in a two-dimensional matrix in the row and column directions. Here, the row direction is the arrangement direction of the pixels 20 in a pixel row (for example, the X-axis direction), and the column direction is the arrangement direction of the pixels 20 in a pixel column (for example, the Y-axis direction). The pixels 20 generate and store photocharges corresponding to the amount of incident light by performing photoelectric conversion.

[0015] For example, the pixel arrangement of the pixel array unit 11 is an m x n pixel arrangement (where m and n are integers). That is, m represents the number of rows and n represents the number of columns. In the pixel array unit 11, a pixel control line 31 is wired for each pixel row of the m x n pixel arrangement. In addition, a pixel signal line 32 is wired for each pixel column.

[0016] The pixel control line 31 transmits the drive signals output from the vertical scanning unit 12 in pixel row units when reading signals from the pixels 20. In the example in Figure 1, the pixel control line 31 is shown as a single wire, but it is not limited to one wire. One end of the pixel control line 31 is connected to the output terminal corresponding to each row of the vertical scanning unit 12. The pixel signal line 32 transmits the signals read from the pixels 20 to the column processing unit 13.

[0017] The following describes each component of the peripheral circuit section of the pixel array section 11, namely the vertical scanning section 12, the column processing section 13, the horizontal scanning section 14, the digital signal calculation section 15, and the timing control section 16.

[0018] The vertical scanning unit 12 is composed of a shift register, an address decoder, and the like. When selecting each pixel 20 of the pixel array unit 11, the vertical scanning unit 12 controls the scanning of the pixel row and the address of the pixel row based on a timing control signal supplied from the timing control unit 16. The vertical scanning unit 12 is configured to have, for example, two scanning systems: a read scanning system and a sweep scanning system.

[0019] The column processing unit 13 reads pixel signals from each pixel 20 of the pixel array unit 11 based on the timing control signal supplied from the timing control unit 16, performs analog-to-digital conversion processing and correlated double sampling (CDS processing), and then outputs the pixel signals.

[0020] The horizontal scanning unit 14 is composed of a shift register, an address decoder, and the like. Based on the timing control signal supplied from the timing control unit 16, the horizontal scanning unit 14 sequentially selects and scans each pixel 20 of the pixel array unit 11. Through this selective scanning by the horizontal scanning unit 14, the pixel signals, which have been converted into digital signals for each unit circuit in the column processing unit 13, are sequentially output to the digital signal calculation unit 15.

[0021] The digital signal calculation unit 15 performs predetermined digital calculations on the pixel signals output sequentially from the horizontal scanning unit 14 based on the timing control signal supplied from the timing control unit 16, and uses the calculation result as the image output.

[0022] The timing control unit 16 generates various timing signals, clock signals, and control signals based on synchronization signals provided from an external source. Based on these generated signals, the timing control unit 16 controls the drive of the vertical scanning unit 12, column processing unit 13, horizontal scanning unit 14, and digital signal calculation unit 15.

[0023] <1-2. Example of Pixel Configuration> The pixel 20 (pixel circuit) according to the embodiment will be described with reference to Figure 2. Figure 2 is a diagram showing an example of the configuration of the pixel 20 according to the embodiment.

[0024] The pixel 20 includes a photoelectric conversion unit 21, a charge transfer unit 22, a charge-voltage conversion unit 23, a charge reset unit 24, a signal amplification unit 25, and a pixel selection unit 26. The charge reset unit 24 and the signal amplification unit 25 are supplied with a predetermined voltage from the power supply of the pixel 20 (pixel power supply).

[0025] For example, N-channel MOS field-effect transistors (NMOS transistors) are used as the charge transfer unit 22, charge reset unit 24, signal amplification unit 25, and pixel selection unit 26. However, the combination of conductivity types of the four NMOS transistors exemplified in Figure 2 is merely an example and is not limited to these combinations.

[0026] Here, the pixel control lines 31 described above consist of multiple pixel control lines that are commonly wired to each pixel 20 in the same pixel row. These multiple pixel control lines are connected to the output terminals corresponding to each pixel row of the vertical scanning unit 12 on a pixel row basis. The vertical scanning unit 12 outputs a transfer signal TRG, a reset signal RST, and a selection signal SEL to the multiple pixel control lines as appropriate. A constant current source 33 is connected to one end of a pixel signal line 32 wired for each pixel row of the pixel array unit 11.

[0027] The photoelectric conversion unit 21 is a PN junction photodiode (PD). The photodiode has its anode electrode connected to a low-potential power supply (for example, ground) and generates and stores charge in proportion to the amount of incident light.

[0028] The charge transfer unit 22 transfers the charge accumulated in the photoelectric conversion unit 21 to the charge-voltage conversion unit 23 according to the transfer signal TRG provided by the vertical scanning unit 12. Specifically, the gate electrodes of the transistors constituting the charge transfer unit 22 are supplied by the vertical scanning unit 12 with a transfer signal TRG that becomes active at a high level. As a result, the transistors constituting the charge transfer unit 22 become conductive and transfer the charge accumulated in the photoelectric conversion unit 21 to the charge-voltage conversion unit 23.

[0029] The charge-voltage conversion unit 23 is the capacitance of the floating diffusion (FD) region formed between the drain region of the transistor constituting the charge transfer unit 22 and the source region of the transistor constituting the charge reset unit 24. This charge-voltage conversion unit 23 converts the charge transferred from the photoelectric conversion unit 21 by the charge transfer unit 22 into a voltage.

[0030] The charge reset unit 24 resets the charge stored in the charge-voltage conversion unit 23 according to the reset signal RST provided by the vertical scanning unit 12. Specifically, the gate electrodes of the transistors constituting the charge reset unit 24 are supplied with a reset signal RST from the vertical scanning unit 12, which activates at a high level. As a result, the transistors constituting the charge reset unit 24 become conductive, resetting the charge stored in the charge-voltage conversion unit 23.

[0031] The signal amplification unit 25 amplifies the voltage converted by the charge-voltage conversion unit 23 and outputs a pixel signal (AMP) at a level corresponding to the charge stored in the charge-voltage conversion unit 23. The gate electrodes of the transistors constituting this signal amplification unit 25 are connected to the charge-voltage conversion unit 23, and the drain electrodes are connected to the power supply voltage node. The transistors constituting the signal amplification unit 25 then become the input to a readout circuit, i.e., a source follower circuit, which reads out the charge obtained by photoelectric conversion in the photoelectric conversion unit 21. In other words, the transistors constituting the signal amplification unit 25 form a source follower circuit with a constant current source 33 connected to one end of the pixel signal line 32, by having their source electrodes connected to the pixel signal line 32 via the pixel selection unit 26.

[0032] The pixel selection unit 26 selects any pixel 20 in the pixel array unit 11 under the selective scanning performed by the vertical scanning unit 12. The transistor constituting the pixel selection unit 26 is connected between the source electrode of the transistor constituting the signal amplification unit 25 and the pixel signal line 32, and a selection signal SEL, which becomes active at a high level, is supplied to its gate electrode from the vertical scanning unit 12. When the selection signal SEL reaches a high level, the transistor constituting the pixel selection unit 26 becomes conductive. As a result, the pixel 20 is selected. When the pixel 20 is selected, the pixel signal output from the signal amplification unit 25 is read to the column processing unit 13 via the pixel signal line 32.

[0033] For example, the pixel 20 described above outputs, in sequence, a reset signal (so-called P-phase signal), which is the reset level when the charge-voltage conversion unit 23 is reset by the charge reset unit 24, and a data signal (so-called D-phase signal), which is a signal level corresponding to the charge based on the photoelectric conversion by the photoelectric conversion unit 21. In other words, the pixel signal output from the pixel 20 includes, for example, the reset signal at the time of reset and the data signal at the time of photoelectric conversion by the photoelectric conversion unit 21.

[0034] <1-3. Example of AD Conversion Unit Configuration> The AD (analog-to-digital) conversion unit 50 according to the embodiment will be described with reference to Figure 3. Figure 3 is a diagram showing an example of the configuration of the AD conversion unit 50 according to the embodiment. In the example of Figure 3, the peripheral circuitry of the AD conversion unit 50 is also shown.

[0035] As shown in Figure 3, the AD conversion unit 50 is one of the functional units of the column processing unit 13. Based on the timing control signal supplied from the timing control unit 16, the AD conversion unit 50 acquires analog pixel signals supplied from each pixel 20 of the pixel array unit 11 through the pixel signal line 32 and sequentially converts them into digital pixel signals.

[0036] The AD conversion unit 50 is composed of a plurality of AD conversion circuits 51. Each AD conversion circuit 51 is provided corresponding to each pixel row of the pixel array unit 11. As the AD conversion circuit 51, for example, a single-slope type AD conversion circuit is used. The single-slope type AD conversion circuit is an example of a reference signal comparison type AD conversion circuit.

[0037] A reference signal generation unit 60 is connected to such an AD conversion unit 50. The reference signal generation unit 60 generates a ramp wave reference signal (ramp signal) RAMP based on the timing control signal supplied from the timing control unit 16. The reference signal generation unit 60 is configured, for example, using a DA (digital-to-analog) conversion circuit.

[0038] The ramp wave reference signal RAMP is a sloped waveform reference signal that changes linearly with a predetermined slope over time (for example, monotonically decreasing). This reference signal RAMP is input to the AD conversion unit 50 and used by the AD conversion unit 50 as a reference signal during AD conversion. Specifically, the reference signal RAMP is used by the AD conversion unit 50, which includes, for example, a single-slope type AD conversion circuit 51.

[0039] The AD conversion circuit 51 includes a comparator 52 and a column counter 55. This AD conversion circuit 51 is provided, for example, for each pixel row of the pixel array section 11. Alternatively, the AD conversion circuit 51 may be provided for each pixel 20.

[0040] The comparator 52 receives, as a comparison input, an analog pixel signal Vsig supplied from each pixel 20 of the pixel array unit 11 through a pixel signal line 32, and receives, as a reference input, a ramp-wave reference signal RAMP generated by a reference signal generation unit 60, and compares the two signals. For example, at the timing when the reference signal RAMP exceeds the voltage value of the analog pixel signal Vsig, the comparator 52 outputs a pulse signal (comparison result) Vco notifying of this. Accordingly, the comparator 52 outputs, as a comparison result, the pulse signal Vco having a pulse width corresponding to the signal level of the analog pixel signal Vsig, specifically, corresponding to the magnitude of the signal level.

[0041] The column counter 55 is supplied with a clock signal CLK from the timing control unit 16 at the same timing as the supply start timing of the reference signal RAMP to the comparator 52. The column counter 55 performs a counting operation in synchronization with the clock signal CLK, thereby measuring the period of the pulse width of the output pulse of the comparator 52, that is, the period from the start of the comparison operation to the end of the comparison operation. The count result (count value) of the column counter 55 is supplied to the horizontal scanning unit 14 as a digital value obtained by digitizing the analog pixel signal Vsig.

[0042] As described above, in the AD conversion unit 50, the analog pixel signal Vsig output from the pixel 20 is compared with the reference signal RAMP generated by the reference signal generation unit 60. Then, a digital value is obtained from time information from the start of comparison to the timing at which the magnitude relationship between the analog pixel signal Vsig and the reference signal RAMP changes (that is, the timing at which the output of the comparator 52 is inverted).

[0043] <1-4. Configuration Example of Reference Signal Generation Unit and AD Conversion Circuit> A configuration example of the reference signal generation unit 60 and the AD conversion circuit 51 according to the embodiment will be described with reference to FIGS. 4 and 5. FIGS. 4 and 5 are diagrams each illustrating a configuration example of the reference signal generation unit 60 and the AD conversion circuit 51 according to the embodiment. In the examples of FIGS. 4 and 5, the pixel 20 is also illustrated. Further, in the example of FIG. 5, one pixel 20 and one AD conversion circuit 51 are illustrated as examples.

[0044] As shown in FIG. 4 and FIG. 5, the reference signal generation unit 60 includes a DAC (digital-to-analog conversion circuit) 61 and a PSRR (power supply rejection ratio) compensation circuit 62. The DAC 61 is an example of a generation circuit, and the PSRR compensation circuit 62 is an example of a compensation circuit. Note that the power supply voltage VDDH in FIG. 4 and FIG. 5 corresponds to, for example, a pixel voltage.

[0045] The DAC 61 generates a ramp-wave reference signal RAMP, and outputs the generated reference signal RAMP. This reference signal RAMP is corrected by the PSRR compensation circuit 62, and is finally input to the input terminal of the comparator 52. The reference signal RAMP functions, in the comparator 52, as a signal for performing AD (Analog to Digital) conversion on a pixel signal output from the pixel 20.

[0046] The PSRR compensation circuit 62 corrects the reference signal RAMP formed by the DAC 61. The PSRR compensation circuit 62 removes power supply noise in common mode by, for example, superimposing power supply noise on the pixel signal line 32 onto the input of the comparator 52. The power supply noise is caused by, for example, power supply fluctuation (e.g., power supply ripple).

[0047] For example, power supply noise (e.g., noise of a pixel power supply) propagates to the pixel signal line 32 via the pixel 20. When power supply noise is input to the comparator 52 of the AD conversion circuit 51 through the pixel signal line 32, a conversion error occurs in AD conversion, which may make it impossible to obtain an accurate pixel value. This is one of the factors that causes deterioration in the image quality of a captured image.

[0048] Further, the PSRR compensation circuit 62 includes a VDDH correction circuit 62a. The VDDH correction circuit 62a adjusts the power supply voltage VDDH to generate a correction signal, and outputs the generated correction signal. The VDDH correction circuit 62a performs, for example, gain adjustment on the power supply voltage VDDH. The PSRR compensation circuit 62 superimposes the correction signal generated by the VDDH correction circuit 62a onto the reference signal RAMP, and outputs the reference signal RAMP with the correction signal superimposed thereon to each of the AD conversion circuits 51.

[0049] The reference signal RAMP is input to the AD conversion circuit 51 via the ramp signal line 70. The ramp signal line 70 connects the PSRR compensation circuit 62 and each AD conversion circuit 51. In the example in Figure 5, the ramp signal line 70 has a wiring load 71 (e.g., a resistor or capacitor). The wiring load 71 increases as the wiring length of the ramp signal line 70 increases. The ramp signal line 70 extends, for example, along the pixel array section 11 and has a length approximately the same as or greater than one side of the pixel array section 11. The ramp signal line 70 is an example of a first signal line.

[0050] The AD conversion circuit 51 includes the aforementioned comparator 52 and an amplification unit 53. The amplification unit 53 is electrically connected between the reference signal generation unit 60 and the comparator 52. In the example shown in Figure 4, the AD conversion circuit 51 includes a constant current source 33, but is not limited to this.

[0051] The amplification unit 53 includes an amplification circuit 53a, a current source 53b, and a cancellation capacitor 53c. This amplification unit 53 is electrically connected between the reference signal generation unit 60 and the comparator 52.

[0052] The amplification circuit 53a is an amplification circuit that amplifies the reference signal RAMP. For example, a source follower circuit using a MOS transistor can be used as the amplification circuit 53a. The source follower circuit can be used as a voltage buffer, for example.

[0053] The amplifier circuit 53a is connected to the comparator 52 via a source follower signal line 80. The source follower signal line 80 connects the amplifier circuit 53a and the comparator 52. The wiring length of the source follower signal line 80 is shorter than the wiring length of the ramp signal line 70 from the PSRR compensation circuit 62 to the amplifier circuit 53a. The source follower signal line 80 is an example of a second signal line.

[0054] The current source 53b is electrically connected between the amplifier circuit 53a and the comparator 52. For example, one end of the current source 53b is connected to the power line 90 (at the potential of the power supply voltage VDDH) of the power supply voltage VDDH, and the other end of the current source 53b is electrically connected to the source follower signal line 80. That is, the other end of the current source 53b is electrically connected to the output of the amplifier circuit 53a and the input of the comparator 52.

[0055] The cancellation capacitor 53c, like the current source 53b, is electrically connected between the amplifier circuit 53a and the comparator 52. For example, one end of the cancellation capacitor 53c is electrically connected to the power line 90 of the power supply voltage VDDH, and the other end of the cancellation capacitor 53c is electrically connected to the source follower signal line 80. That is, the other end of the cancellation capacitor 53c is electrically connected to the output of the amplifier circuit 53a and the input of the comparator 52. The cancellation capacitor 53c functions as a high-pass filter (HPF) for the power supply voltage VDDH.

[0056] As the cancellation capacitance 53c, for example, a variable capacitance with a variable capacitance or a fixed capacitance with a fixed capacitance can be used. The variable capacitance is composed of, for example, multiple capacitances with different capacitances and a switch. The capacitance of the cancellation capacitance 53c can be changed by switching between the multiple capacitances with different capacitances using the switch.

[0057] In the example shown in Figure 4, the capacitance of each cancellation capacitor 53c for each AD conversion circuit 51 may decrease as the cancellation capacitor 53c moves away from the reference signal generation unit 60. It is desirable to keep the capacitance C of the wiring load 71 (resistance R × cancellation capacitor 53c) constant (R × C = constant). The wiring load 71 increases in accordance with the increase in the wiring length of the lamp signal line 70.

[0058] Furthermore, the capacitance of each cancellation capacitor 53c for each AD conversion circuit 51 may differ for each predetermined group. For example, the capacitance of each cancellation capacitor 53c for each AD conversion circuit 51 may decrease as the position of the predetermined group moves away from the reference signal generation unit 60. The predetermined group may be, for example, a group of a predetermined number of cancellation capacitors 53c, or it may be a group of predetermined regions (for example, multiple regions arranged in the row direction) corresponding to the pixel array unit 11, divided into multiple regions (for example, multiple regions arranged in the row direction).

[0059] <1-5. Example of Reference Signal Generation> An example of generating the reference signal RAMP according to the embodiment will be described with reference to Figures 6 to 9 (Figure 5 will also be referred to as appropriate). Figure 6 is a graph for explaining the correction signal A3 according to the embodiment. Figure 7 is a graph for explaining the cutoff frequency change of the low-pass filter B1 due to the wiring load 71 according to the embodiment. Figure 8 is a graph for explaining the gain change with and without the low-pass filter C3 due to the wiring load 71 according to the embodiment. Figure 9 is a graph for explaining the gain change with and without the high-pass filter D4 due to the cancellation capacitor 53c according to the embodiment.

[0060] In the VDDH correction circuit 62a of the PSRR compensation circuit 62 shown in Figure 5, a low-pass filter (LPF) A1 and a high-pass filter (HPF) A2 are used, as shown in Figure 6, and a correction signal A3 (see solid line) is generated from the power supply voltage VDDH. This correction signal A3 is output from the VDDH correction circuit 62a, and the output correction signal A3 is superimposed on the reference signal RAMP.

[0061] In the lamp signal line 70 shown in Figure 5, a low-pass filter B1 is formed by the wiring load 71, as shown in Figure 7. The cutoff frequency of this low-pass filter B1 decreases as the imaging device 10 becomes larger and the wiring length of the lamp signal line 70 increases, and the bandwidth of the low-pass filter B1 narrows (see thick solid line). As a result, the high-frequency components (high-frequency correction components) of the correction signal A3 mentioned above are no longer transmitted. Note that the wiring length of the lamp signal line 70 increases as the imaging device 10 becomes larger.

[0062] Here, as shown in the upper part of Figure 8 (upper diagram), the waveform C1 of the pixel signal of the pixel signal line (VSL) 32 and the waveform C2 of the reference signal RAMP output from the amplification circuit 53a have almost the same shape (gain). In this case, the correction signal A3 is normal. The remaining high-frequency correction Ca is not actually visible (irrelevant), so there is no problem.

[0063] On the other hand, as shown in the lower part of Figure 8 (bottom diagram), the waveform C1 of the pixel signal on the pixel signal line (VSL) 32 and the waveform C2 of the reference signal RAMP output from the amplification circuit 53a have different shapes (gains). This is because of the low-pass filter (RAMP LPF) C3 by the wiring load 71 mentioned above. In this case, the correction signal A3 is abnormal. The remaining correction Cb is visible at a lower frequency than the remaining correction Ca mentioned above.

[0064] As shown in Figure 9, the waveform D1 of the pixel signal on the pixel signal line 32 (see solid line) and the waveform D2 of the reference signal RAMP output from the amplification circuit 53a have different shapes (gains). In this case, the cancellation capacitor 53c is not provided (no SFOUT capacitor). On the other hand, the waveform D1 of the pixel signal on the pixel signal line 32 and the waveform D3 of the reference signal RAMP output from the amplification circuit 53a have almost the same shape (gain). In this case, the cancellation capacitor 53c is provided (SFOUT capacitor present), and a high-pass filter D4 is present due to the cancellation capacitor 53c. As a result, the high-frequency component (high-frequency correction component) of the correction signal A3 is also transmitted normally.

[0065] In this embodiment, the cancellation capacitor 53c is electrically connected between the amplification circuit 53a and the comparator 52. For example, the high-frequency component of the power supply voltage VDDH is superimposed on the reference signal RAMP, which has its high-frequency component of the correction signal reduced by the low-pass filter of the wiring load 71, via the high-pass filter of the cancellation capacitor 53c. In other words, in addition to the low-frequency component of the correction signal, the high-frequency component of the correction signal is also appropriately included in the reference signal RAMP. Therefore, even in situations where high-frequency components of power supply noise tend to remain during AD conversion due to a decrease in the low-pass filter bandwidth on the ramp signal line 70 side due to an increase in the wiring load 71, or an increase in the coupling to the power supply capacitance around the pixel signal line 32, it becomes possible to suppress the high-frequency component of the power supply noise, thereby reducing power supply noise.

[0066] <1-6. Examples of Comparator Configurations> Examples of comparator configurations according to the embodiment will be described with reference to Figures 10 to 12. Figure 10 is a diagram showing an example of comparator 52A configuration according to Embodiment 1 of the embodiment. Figure 11 is a diagram showing an example of comparator 52B configuration according to Embodiment 2 of the embodiment. Figure 12 is a diagram showing an example of comparator 52C configuration according to Embodiment 3 of the embodiment.

[0067] (Example 1) As shown in Figure 10, the comparator 52A of Example 1 includes a first-stage comparator (first-stage comparator) 200 and a second-stage comparator (second-stage comparator) 210. This comparator 52A is used, for example, as the comparator 52 of the AD conversion circuit 51 described above. Various control signals are supplied to the comparator 52A as needed. For example, each of the control signals is generated by a control unit such as the timing control unit 16 and supplied to the comparator 52A.

[0068] The first-stage comparator 200 is configured as a differential comparator. This first-stage comparator 200 includes PMOS transistors 201 and 202, NMOS transistors 203 and 204, and a current source 205. PMOS transistors 201 and 202 constitute an active load, and NMOS transistors 203 and 204 constitute a differential pair.

[0069] The gate of NMOS transistor 203 is connected to source follower signal line 80 via capacitor 206. The reference signal RAMP output from amplifier 53 is input to the gate of NMOS transistor 203. The gate of NMOS transistor 204 is connected to pixel signal line 32 via capacitor 207. The pixel signal output from pixel 20 is input to the gate of NMOS transistor 204.

[0070] A switch 208 is connected between the gate and drain of NMOS transistor 203. The on / off control of switch 208 is performed by a predetermined control signal. Similarly, a switch 209 is connected between the gate and drain of NMOS transistor 204. The on / off control of switch 209 is also performed by a predetermined control signal. These switches 208 and 209 are provided to perform auto-zero operation.

[0071] The next-stage comparator 210 includes a PMOS transistor 211, an NMOS transistor 212, a NAND circuit 213, a switch 214, and a capacitor 215.

[0072] The gate of the PMOS transistor 211 is connected to the output terminal of the first-stage comparator 200. The source of the PMOS transistor 211 is connected to a predetermined potential (for example, the potential of the power supply voltage VDDH). The drain of the PMOS transistor 211 is connected to the drain of the NMOS transistor 212. The source of the NMOS transistor 212 is connected to a predetermined potential (for example, the ground potential).

[0073] A switch 214 is connected between the gate and drain of an NMOS transistor 212. The on / off control of the switch 214 is performed by a predetermined control signal. One end of a capacitor 215 is connected to the gate of the NMOS transistor 212. The other end of the capacitor 215 is connected to a predetermined potential (for example, ground potential).

[0074] One input terminal of the NAND circuit 213 is connected to the connection point where the PMOS transistor 211 and NMOS transistor 212 are connected. An output signal is taken from this connection point and input to the other input terminal of the NAND circuit 213. A predetermined signal (for example, signal STB) is input to the other input terminal of the NAND circuit 213. Signal STB functions, for example, as a mask signal to mask signals unnecessary for comparator operation. The output of the NAND circuit 213 becomes the output signal of the next stage comparator 210. For example, a pulse signal (binary signal) V indicating the comparison result is output from the NAND circuit 213. ＣＯ This is output and input to column counter 55.

[0075] (Example 2) As shown in Figure 11, the comparator 52B of Example 2 includes a first-stage comparator (first-stage comparator: 1stOUT) 220 and a second-stage comparator (second-stage comparator: 2ndOUT) 230, similar to Example 1. This comparator 52B is used, for example, as the comparator 52 of the AD conversion circuit 51 described above. Various control signals are supplied to the comparator 52B as needed. For example, each control signal is generated by a control unit such as the timing control unit 16 and supplied to the comparator 52B.

[0076] The first-stage comparator 220 includes two PMOS transistors 221 and 222, two capacitors 223 and 224, an NMOS transistor 225, and a current source 226.

[0077] The gate of the PMOS transistor 221 is connected to a capacitor (C ＡＺIt is connected to the source follower signal line 80 via 223. The gate of this PMOS transistor 221 is input to the reference signal RAMP output from the amplifier 53. The source of the PMOS transistor 221 is connected to the pixel signal line 32, and the drain of the PMOS transistor 221 is connected to the current source (I ＬＭ It is connected to 226. The source of the PMOS transistor 221 is input to the pixel signal output from the pixel 20.

[0078] A switch 227 is connected between the gate and drain of the PMOS transistor 221. The on / off control of this switch 227 is performed by a predetermined control signal (for example, control signal XAZP).

[0079] Capacitor 224 is connected between the drain and source of PMOS transistor 221. PMOS transistor 222 and NMOS transistor 225 are each connected in parallel with capacitor 224, between the drain and source of PMOS transistor 221. A predetermined control signal (e.g., control signal NCLP) is input to the gate of NMOS transistor 225.

[0080] The next-stage comparator 230 includes a PMOS transistor 231, an NMOS transistor 232, and a current source 233.

[0081] The gate of PMOS transistor 231 is connected to the output terminal of the first-stage comparator 220. The source of PMOS transistor 231 is connected to the respective sources of PMOS transistors 221 and 222, and to the drain of NMOS transistor 225. The drain of PMOS transistor 231 is connected to the current source 233.

[0082] The drain of NMOS transistor 232 is connected to the respective sources of PMOS transistors 221, 222, and 231, and to the drain of NMOS transistor 225. The source of NMOS transistor 232 is connected to the drain of PMOS transistor 231. A predetermined control signal (for example, control signal NCLP2) is input to the gate of NMOS transistor 232.

[0083] The two NMOS transistors 225 and 232 constitute a clamp circuit for the input and output of the PMOS transistor 231, respectively. The PMOS transistor 231 functions as an output transistor for the next-stage comparator 230, i.e., the output of comparator 52B. A binary signal indicating the comparison result is output from comparator 52B as the output signal (2ndOUT) of the next-stage comparator 230.

[0084] (Example 3) As shown in Figure 12, the comparator 52C of Example 3 includes a first-stage comparator (first-stage comparator: 1stOUT) 240 and a second-stage comparator (second-stage comparator) 250, similar to Examples 1 and 2. This comparator 52C is used, for example, as the comparator 52 of the AD conversion circuit 51 described above. Various control signals are supplied to the comparator 52C as needed. For example, each control signal is generated by a control unit such as the timing control unit 16 and supplied to the comparator 52C.

[0085] The first-stage comparator 240 includes a PMOS transistor 241, a capacitor 242, two NMOS transistors 243 and 244, three switches 245, 246 and 248, and a current source 247.

[0086] The gate of the PMOS transistor 241 is connected to a capacitor (C ＡＺ The source of the PMOS transistor 241 is connected to the pixel signal line 32, and the drain of the PMOS transistor 241 is connected to the current source (I) via the NMOS transistor 243. ＬＭ It is connected to 247.

[0087] A switch 248 is connected between the gate and drain of the PMOS transistor 241. The on / off control of this switch 248 is performed by a predetermined control signal (for example, control signal XAZP1). Two switches 245 and 246 are connected in series between the drain and source of the PMOS transistor 241. The on / off control of switch 245 is performed by a predetermined control signal (for example, control signal XAZN1), and the on / off control of switch 246 is performed by a predetermined control signal (for example, control signal XAZP3).

[0088] The drain of the NMOS transistor 243 is connected to the drain of the PMOS transistor 241, and the source of the NMOS transistor 243 is connected to the current source 247. A predetermined control signal (for example, signal XAZN2) is input to the gate of the NMOS transistor 243.

[0089] The drain of NMOS transistor 244 is connected to the connection point where two switches 245 and 246 are connected. The source of NMOS transistor 244 is connected to the connection point where current source 247 and NMOS transistor 243 are connected. A predetermined control signal (e.g., signal NCLP) is input to the gate of NMOS transistor 244.

[0090] The next-stage comparator 250 includes a PMOS transistor 251, an NMOS transistor 252, a capacitor 253, a NAND circuit 254, and a current source 255.

[0091] The gate of the PMOS transistor 251 is connected to the output terminal of the first-stage comparator 240. The drain of the PMOS transistor 251 is connected to a predetermined potential (e.g., voltage VSS), and the source of the PMOS transistor 251 is connected to the source of the NMOS transistor 252.

[0092] The gate of the NMOS transistor 252 is connected to the capacitor 253. A switch 256 is connected between the drain and gate of the NMOS transistor 252. The on / off control of the switch 256 is performed by a predetermined control signal (e.g., control signal AZN). The signal Vshift is input to the connection point where the gate of the NMOS transistor 252 and the switch 256 are connected, via the capacitor 253.

[0093] One input terminal of the NAND circuit 254 is connected to a current source (I ２ｎｄ ) 255 and NMOS transistor 252 are connected to a connection point. An output signal is taken from this connection point and input to one input terminal of the NAND circuit 254. A predetermined signal (for example, signal STB) is input to the other input terminal of the NAND circuit 254. The output of the NAND circuit 254 becomes the output signal of the next stage comparator 250. For example, a pulse signal (binary signal) V indicating the comparison result is taken from the NAND circuit 254. ＣＯ This is output and input to column counter 55.

[0094] The comparators 52A, 52B, and 52C in Examples 1 to 3 described above are merely examples, and comparators 52 with configurations other than those of each comparator 52A, 52B, and 52C may be used. Furthermore, parts of each comparator 52A, 52B, and 52C may be modified as appropriate.

[0095] <2. Operation and Effects of the Embodiment> As described above, the imaging device 10 according to the embodiment includes a pixel 20 that generates a pixel signal, a generation circuit (for example, DAC 61) that generates a reference signal RAMP, a compensation circuit (for example, PSRR compensation circuit 62) that corrects the reference signal RAMP based on the power supply voltage VDDH, and an AD conversion circuit 51 that converts the reference signal RAMP into a digital signal. The AD conversion circuit 51 includes an amplification circuit 53a that amplifies the reference signal RAMP corrected by the compensation circuit, a comparator 52 that compares the reference signal RAMP amplified by the amplification circuit 53a with the pixel signal generated by the pixel 20, and a cancellation capacitor 53c electrically connected between the amplification circuit 53a and the comparator 52 (see Figures 4 and 5). As a result, even in situations where high-frequency components of power supply noise tend to remain in AD conversion due to a decrease in the low-pass filter bandwidth on the ramp signal line 70 side due to an increase in wiring load 71, the high-frequency components of the corrected reference signal RAMP are appropriately supplied to the comparator 52 by the cancellation capacitor 53c. Therefore, it becomes possible to suppress the high-frequency components of power supply noise, thereby reducing power supply noise.

[0096] Furthermore, the imaging device 10 may also include a first signal line (e.g., a ramp signal line 70) connecting a compensation circuit (e.g., a PSRR compensation circuit 62) and an amplification circuit 53a, and a second signal line (e.g., a source follower signal line 80) connecting the amplification circuit 53a and the comparator 52 (see Figures 4 and 5). Power supply noise can also be reduced with such a configuration.

[0097] Furthermore, one end of the cancellation capacitor 53c may be electrically connected to the power line 90 of the power supply voltage VDDH, and the other end of the cancellation capacitor 53c may be electrically connected to a second signal line (for example, a source follower signal line 80) (see Figures 4 and 5). This ensures a reliable reduction in power supply noise.

[0098] Furthermore, the cancellation capacitance 53c may function as a high-pass filter for the power supply voltage VDDH (see Figures 4 and 5). This ensures a reliable reduction in power supply noise.

[0099] Furthermore, the wiring length of the second signal line (for example, the source follower signal line 80) may be shorter than the wiring length of the first signal line (for example, the lamp signal line 70) (see Figures 4 and 5). This ensures a reliable reduction in power supply noise.

[0100] Furthermore, the cancellation capacitance 53c may be a variable capacitance (see Figures 4 and 5). This makes it possible to change the capacitance of the cancellation capacitance 53c, thereby reliably reducing power supply noise.

[0101] Furthermore, the amplification circuit 53a may be a source follower circuit (see Figures 4 and 5). This ensures a reliable reduction in power supply noise.

[0102] Furthermore, the compensation circuit (for example, the PSRR compensation circuit 62) may be superimposed on the reference signal RAMP by adjusting the power supply voltage VDDH (see Figures 4 and 5). This ensures a reliable reduction in power supply noise.

[0103] Alternatively, the compensation circuit may be a PSRR compensation circuit 62 (see Figures 4 and 5). This ensures a reliable reduction in power supply noise.

[0104] Furthermore, multiple pixels 20 are arranged in a matrix, and an AD conversion circuit 51 is provided for each row of pixels 20. A generation circuit (e.g., DAC 61) and a compensation circuit (e.g., PSRR compensation circuit 62) may be provided in common to the AD conversion circuit 51 for each row (see Figures 1, 3 to 5). Power supply noise can also be reduced with such a configuration.

[0105] Furthermore, the capacitance of each cancellation capacitance 53c in each column may decrease as the cancellation capacitance 53c moves away from the generating circuit and the compensation circuit (see Figures 4 and 5). This ensures a reliable reduction in power supply noise.

[0106] Furthermore, the capacitance of each cancellation capacitance 53c for each row may differ for each predetermined group (for example, groups of a predetermined number, groups of a predetermined area, etc.) (see Figures 4 and 5). This ensures that power supply noise is reliably reduced.

[0107] Furthermore, the capacitance of each cancellation capacitance 53c for each row may decrease as the position of a predetermined group moves away from the generating circuit and the compensation circuit (see Figures 4 and 5). This ensures a reliable reduction in power supply noise.

[0108] <3. Other Embodiments> The configurations and processes described in the above-described embodiments (including examples and modifications) may be implemented in various other forms besides those described above. For example, the configurations and processes may be in various forms, not limited to the examples described above. Also, for example, the configurations, processing procedures, specific names, and information including various data and parameters shown in the above document and drawings may be changed at will unless otherwise specified.

[0109] Furthermore, the configurations and processes described in the above-mentioned embodiments (including examples and modifications) do not necessarily have to be physically configured as shown in the figures. In other words, the specific forms of distribution and integration of each configuration and process are not limited to those shown in the figures, and all or part of them may be functionally or physically distributed and integrated in any unit depending on various loads and usage conditions.

[0110] Furthermore, the various configurations and processes described in the above-mentioned embodiments (including examples and modifications) may be combined as appropriate. For example, at least a part of one embodiment may be combined with at least a part of another embodiment as appropriate. Also, the effects described in the embodiments are merely illustrative and not limiting, and other effects may also occur.

[0111] <4. Application Examples> <4-1. Various Devices> Application examples of the imaging device 10 according to the above-described embodiment (including examples and modified versions) will be explained with reference to Figure 13. Figure 13 is a diagram showing an application example of the imaging device 10 according to the above-described embodiment.

[0112] The imaging device 10 according to the above embodiment may be applied to various cases of sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows. For example, the imaging device 10 may be applied to various devices (electronic devices) or electronic devices mounted on various devices, as described below.

[0113] As shown in Figure 13, the imaging device 10 according to the above embodiment can be used, for example, in: "devices that capture images for viewing purposes, such as digital cameras and portable devices with camera functions"; "devices used for traffic purposes, such as in-vehicle sensors that photograph the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles"; "devices used in home appliances such as TVs, refrigerators, and air conditioners to capture user gestures and perform device operations according to those gestures"; "devices used for medical and healthcare purposes, such as endoscopes and devices that perform angiography by receiving infrared light"; "devices used for security purposes, such as surveillance cameras for crime prevention and cameras for person recognition"; "devices used for beauty purposes, such as skin measuring devices that photograph skin and microscopes that photograph the scalp"; "devices used for sports purposes, such as action cameras and wearable cameras for sports use"; and "devices used for agriculture, such as cameras for monitoring the condition of fields and crops."

[0114] Furthermore, the technology disclosed herein can be applied to a variety of products. For example, the technology disclosed herein may be implemented as electronic equipment mounted on any type of mobile device, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, robots, construction machinery, or agricultural machinery (tractors). Alternatively, for example, the technology disclosed herein may be implemented as electronic equipment mounted on endoscopic surgical systems or microsurgical systems.

[0115] <4-2. Imaging Device> An imaging device 300 relating to an application example will be described with reference to Figure 14. Figure 14 is a diagram showing an example configuration of an imaging device 300 relating to an application example. This imaging device 300 is an example of an electronic device to which the imaging device 10 according to the above-described embodiment is applied. Examples of imaging devices 300 include digital still cameras, video cameras, smartphones and mobile phones with imaging functions, and other electronic devices.

[0116] As shown in Figure 14, the imaging device 300 includes an optical system 301, a shutter device 302, an image sensor (solid-state imager) 303, a control circuit (drive circuit) 304, a signal processing circuit 305, a monitor 306, and a memory 307. This imaging device 300 is capable of capturing both still and moving images.

[0117] The optical system 301 has one or more lenses. This optical system 301 guides light from the subject (incident light) to the image sensor 303 and forms an image on the light-receiving surface of the image sensor 303.

[0118] The shutter device 302 is positioned between the optical system 301 and the image sensor 303. The shutter device 302 controls the light illumination period and the light shielding period for the image sensor 303 according to the control of the control circuit 304.

[0119] The image sensor 303 accumulates signal charge for a certain period of time in response to light formed on the light-receiving surface via the optical system 301 and shutter device 302. The signal charge accumulated in the image sensor 303 is transferred according to a drive signal (timing signal) supplied from the control circuit 304. As the image sensor 303, for example, the imaging device 10 according to the above embodiment is used.

[0120] The control circuit 304 drives the image sensor 303 and the shutter device 302 by outputting drive signals that control the transfer operation of the image sensor 303 and the shutter operation of the shutter device 302.

[0121] The signal processing circuit 305 performs various signal processing operations on the signal charge output from the image sensor 303. The image (image data) obtained by the signal processing circuit 305 is supplied to the monitor 306 and also to the memory 307.

[0122] The monitor 306 displays video or still images captured by the image sensor 303 based on image data supplied from the signal processing circuit 305. For example, the monitor 306 may be a panel-type display device such as a liquid crystal panel or an organic EL (Electro-Luminescence) panel.

[0123] The memory 307 stores image data supplied from the signal processing circuit 305, that is, image data of moving or still images captured by the image sensor 303. Various types of storage devices can be used as the memory 307.

[0124] Even in the imaging device 300 configured in this way, by applying the imaging device 10 according to the above-described embodiment as the image sensor 303, the same effects as in the above-described embodiment can be obtained.

[0125] <4-3. Distance Measuring Device> The distance measuring device 400 according to the application example will be described with reference to Figure 15. Figure 15 is a diagram showing an example of the configuration of the distance measuring device 400 according to the application example. This distance measuring device 400 is an example of an electronic device to which the imaging device 10 according to the above-described embodiment is applied.

[0126] As shown in Figure 15, the distance measuring device (distance image sensor) 400 comprises a light source unit 401, an optical system 402, an image sensor (solid-state imager) 403, a control circuit (drive circuit) 404, a signal processing circuit 405, a monitor 406, and a memory 407. This distance measuring device 400 can acquire a distance image corresponding to the distance to the subject by projecting light from the light source unit 401 toward the subject and receiving the light (modulated light or pulsed light) reflected from the surface of the subject.

[0127] The light source unit 401 projects light toward the subject. The light source unit 401 can be, for example, a vertical cavity surface-emitting laser (VCSEL) array that emits laser light as a surface light source, or a laser diode array in which laser diodes are arranged in a line. The laser diode array is supported by a predetermined drive unit (not shown) and scanned in a direction perpendicular to the arrangement of the laser diodes.

[0128] The optical system 402 has one or more lenses. This optical system 402 guides light from the subject (incident light) to the image sensor 403 and forms an image on the light-receiving surface (sensor part) of the image sensor 403.

[0129] The image sensor 403 accumulates signal charge in response to light formed on the light-receiving surface via the optical system 402. A distance signal indicating the distance, determined from the light-receiving signal (APD OUT) output from the image sensor 403, is supplied to the signal processing circuit 405. As the image sensor 403, for example, the imaging device 10 according to the above embodiment is used.

[0130] The control circuit 404 outputs drive signals (control signals) that control the operation of the light source unit 401 and the image sensor 403, and drives the light source unit 401 and the image sensor 403.

[0131] The signal processing circuit 405 performs various signal processing operations on the distance signal supplied from the image sensor 403. For example, the signal processing circuit 405 performs image processing (e.g., histogram processing and peak detection processing) to construct a distance image based on the distance signal. The image (image data) obtained by the signal processing circuit 405 is supplied to the monitor 406 and also to the memory 407.

[0132] The monitor 406 displays the distance image captured by the image sensor 403 based on the image data supplied from the signal processing circuit 405. For example, a panel-type display device such as a liquid crystal panel or an organic EL panel can be used as the monitor 406.

[0133] The memory 407 stores image data supplied from the signal processing circuit 405, that is, image data of the distance image captured by the image sensor 403. Various types of storage devices can be used as the memory 407.

[0134] Even in the distance measuring device 400 configured in this way, by applying the imaging device 10 according to the above-described embodiment as the image sensor 403, the same effects as in the above-described embodiment can be obtained.

[0135] As described above, the imaging device 10 according to the above embodiment can be mounted on various electronic devices. For example, the imaging device 10 according to the above embodiment may be mounted on various electronic devices other than the imaging device 300 and the distance measuring device 400, such as HDDs (hard disk drives), notebook PCs (personal computers), mobile devices (e.g., smartphones and tablet PCs), PDAs (personal digital assistants), wearable devices, game consoles, and music players.

[0136] <5. Notes> The technology can also be configured as follows: (1) An imaging device comprising: a pixel that generates a pixel signal; a generation circuit that generates a reference signal; a compensation circuit that corrects the reference signal based on the power supply voltage; and an AD (analog-to-digital) conversion circuit that converts the reference signal into a digital signal, wherein the AD conversion circuit includes: an amplification circuit that amplifies the reference signal corrected by the compensation circuit; a comparator that compares the reference signal amplified by the amplification circuit with the pixel signal generated by the pixel; and a cancellation capacitor electrically connected between the amplification circuit and the comparator. (2) The imaging device according to (1), further comprising: a first signal line connecting the compensation circuit and the amplification circuit; and a second signal line connecting the amplification circuit and the comparator. (3) The imaging device according to (2), wherein one end of the cancellation capacitor is electrically connected to the power supply line of the power supply voltage, and the other end of the cancellation capacitor is electrically connected to the second signal line. (4) The imaging apparatus according to (3), wherein the cancellation capacitor functions as a high-pass filter for the power supply voltage. (5) The imaging apparatus according to any one of (2) to (4), wherein the wiring length of the second signal line is shorter than the wiring length of the first signal line. (6) The imaging apparatus according to any one of (1) to (5), wherein the cancellation capacitor is a variable capacitor. (7) The imaging apparatus according to any one of (1) to (6), wherein the amplification circuit is a source follower circuit. (8) The imaging apparatus according to any one of (1) to (7), wherein the compensation circuit adjusts the power supply voltage and superimposes it on the reference signal. (9) The imaging apparatus according to any one of (1) to (8), wherein the compensation circuit is a PSRR (Power Supply Voltage Rejection Ratio) compensation circuit. (10) The imaging apparatus according to any one of (1) to (9), wherein the pixels are arranged in a matrix, the AD conversion circuit is provided for each row of the pixels, and the generation circuit and the compensation circuit are provided in common to the AD conversion circuit for each row.(11) The imaging apparatus according to (10), wherein the capacitance of each of the cancellation capacitors for each row decreases as the cancellation capacitor moves away from the generation circuit and the compensation circuit. (12) The imaging apparatus according to (10), wherein the capacitance of each of the cancellation capacitors for each row differs for each predetermined group. (13) The imaging apparatus according to (12), wherein the capacitance of each of the cancellation capacitors for each row decreases as the position of the predetermined group moves away from the generation circuit and the compensation circuit. (14) Electronic device comprising an imaging apparatus, the imaging apparatus comprising: pixels that generate a pixel signal; a generation circuit that generates a reference signal; a compensation circuit that corrects the reference signal based on a power supply voltage; an AD (analog-to-digital) conversion circuit that converts the reference signal into a digital signal, wherein the AD conversion circuit includes: an amplification circuit that amplifies the reference signal corrected by the compensation circuit; a comparator that compares the reference signal amplified by the amplification circuit with the pixel signal generated by the pixel; and a cancellation capacitor electrically connected between the amplification circuit and the comparator. (15) An electronic device comprising an imaging device as described in any one of (1) to (13).

[0137] 10 Imaging device 11 Pixel array unit 12 Vertical scanning unit 13 Column processing unit 14 Horizontal scanning unit 15 Digital signal calculation unit 16 Timing control unit 20 Pixel 21 Photoelectric conversion unit 22 Charge transfer unit 23 Charge-voltage conversion unit 24 Charge reset unit 25 Signal amplification unit 26 Pixel selection unit 31 Pixel control line 32 Pixel signal line 33 Constant current source 50 AD conversion unit 51 AD conversion circuit 52 Comparator 52A Comparator 52B Comparator 52C Comparator 53 Amplification unit 53a Amplification circuit 53b Current source 53c Cancellation capacitance 55 Column counter 60 Reference signal generation unit 61 DAC 62 PSRR compensation circuit 62a VDDH correction circuit 70 Ramp signal line 71 Wiring load 80 Source follower signal line 90 Power line 300 Imaging device 400 Distance measuring device

Claims

1. An imaging device comprising: a pixel that generates a pixel signal; a generation circuit that generates a reference signal; a compensation circuit that corrects the reference signal based on the power supply voltage; and an AD (analog-to-digital) conversion circuit that converts the reference signal into a digital signal, wherein the AD conversion circuit includes: an amplification circuit that amplifies the reference signal corrected by the compensation circuit; a comparator that compares the reference signal amplified by the amplification circuit with the pixel signal generated by the pixel; and a cancellation capacitor electrically connected between the amplification circuit and the comparator.

2. The imaging apparatus according to claim 1, further comprising: a first signal line connecting the compensation circuit and the amplification circuit; and a second signal line connecting the amplification circuit and the comparator.

3. The imaging apparatus according to claim 2, wherein one end of the cancellation capacitor is electrically connected to the power line of the power supply voltage, and the other end of the cancellation capacitor is electrically connected to the second signal line.

4. The imaging apparatus according to claim 3, wherein the cancellation capacitance functions as a high-pass filter for the power supply voltage.

5. The imaging apparatus according to claim 2, wherein the wiring length of the second signal line is shorter than the wiring length of the first signal line.

6. The imaging apparatus according to claim 1, wherein the cancellation capacitance is a variable capacitance.

7. The imaging apparatus according to claim 1, wherein the amplification circuit is a source follower circuit.

8. The imaging apparatus according to claim 1, wherein the compensation circuit adjusts the power supply voltage and superimposes it on the reference signal.

9. The imaging apparatus according to claim 1, wherein the compensation circuit is a PSRR (power supply voltage rejection ratio) compensation circuit.

10. The imaging apparatus according to claim 1, wherein a plurality of pixels are arranged in a matrix, the AD conversion circuit is provided for each row of pixels, and the generation circuit and the compensation circuit are provided in common to the AD conversion circuit for each row.

11. The imaging apparatus according to claim 10, wherein the capacitance of each of the cancellation capacitors in each of the rows decreases as the cancellation capacitor moves away from the generation circuit and the compensation circuit.

12. The imaging apparatus according to claim 10, wherein the capacitance of each cancellation capacitance for each row is different for each predetermined group.

13. The imaging apparatus according to claim 12, wherein the capacitance of each of the cancellation capacitances for each row decreases as the position of the predetermined group moves away from the generation circuit and the compensation circuit.

14. An electronic device comprising an imaging device, the imaging device comprising: pixels that generate pixel signals; a generation circuit that generates a reference signal; a compensation circuit that corrects the reference signal based on a power supply voltage; and an AD (analog-to-digital) conversion circuit that converts the reference signal into a digital signal, wherein the AD conversion circuit includes: an amplification circuit that amplifies the reference signal corrected by the compensation circuit; a comparator that compares the reference signal amplified by the amplification circuit with the pixel signal generated by the pixels; and a cancellation capacitor electrically connected between the amplification circuit and the comparator.

Images