Semiconductor module

Abstract

A semiconductor module 1 comprises a plurality of semiconductor elements (second semiconductor elements 30a, 30b, 30c) connected in parallel, and a heat capacity connector 50 for collectively connecting the same type of electrodes in the plurality of semiconductor elements to a connection destination. A first semiconductor element and the second semiconductor elements 30a, 30b, 30c in the semiconductor module 1 are arranged so as to at least partially overlap each other in plan view. A semiconductor element arrangement direction in at least one circuit element among circuit elements composed of a combination of the first semiconductor element, the second semiconductor elements 30a, 30b, 30c, and die pad connectors 40a, 40b, 40c is different from a semiconductor element arrangement direction in an adjacent circuit element. In the semiconductor module 1 of the present invention, compared with a conventional semiconductor module, integration and high density can be achieved more easily and thermal conductivity and heat dissipation can be improved.

Description

Semiconductor Module Cross Reference

[0001] This application claims priority based on Japanese Patent Application No. 2025-48330, Japanese Patent Application No. 2025-48331 and Japanese Patent Application No. 2025-48332 filed in Japan on March 24, 2025, and all contents described in those applications are hereby incorporated by reference herein in their entireties.

[0002] The present invention relates to a semiconductor module.

[0003] Conventionally, there has been known a semiconductor module including a plurality of semiconductor elements each having an electrode and connected in parallel, and a connector that connects the electrodes of the plurality of semiconductor elements to a connection destination (e.g., a substrate or a terminal) (see, for example, Patent Document 1).

[0004] There is also known a semiconductor module including a first semiconductor element, a second semiconductor element, and a connector (inter-semiconductor-element connector) that connects an electrode of the first semiconductor element and an electrode of the second semiconductor element (see, for example, Patent Document 1).

[0005] Semiconductor module 900, which is an example of a conventional semiconductor module, includes a substrate 910, first semiconductor elements 920a, 920b, 920c, second semiconductor elements 930a, 930b, 930c, connectors 940a, 940b, 940c, 950a, 950b, 950c, and a case 970 (see FIG. 15). The first semiconductor elements 920a, 920b, 920c and the second semiconductor elements 930a, 930b, 930c are diodes.

[0006] Note that the connectors 940a, 940b, 940c are connectors that connect the electrodes (anode electrodes) of the first semiconductor elements 920a, 920b, 920c to the electrodes (cathode electrodes) of the second semiconductor elements 930a, 930b, 930c. The connectors 940a, 940b, 940c can also be referred to as inter-semiconductor-element connectors. Further, the connectors 950a, 950b, 950c are connectors that connect the electrodes (anode electrodes) of the plurality of second semiconductor elements 930a, 930b, 930c to a connection destination (a wiring pattern of the substrate 910). The connectors 950a, 950b, 950c can also be referred to as other connectors.

[0007] The connectors 940a, 940b, and 940c directly connect the electrodes (anode electrodes) of the first semiconductor elements 920a, 920b, and 920c to wiring patterns provided on the substrate 910 that are connected to the electrodes (cathode electrodes) of the second semiconductor elements 930a, 930b, and 930c (these are not shown in reference numerals).

[0008] The semiconductor module 900 is a so-called three-phase bridge diode module. While the semiconductor module 900 also includes terminals, a case cover, and other components in addition to those described above, these are not essential for explaining the background technology and are therefore omitted from the illustration and description.

[0009] In conventional semiconductor modules, it was common to arrange connectors 950a, 950b, and 950c for each semiconductor element (second semiconductor elements 930a, 930b, and 930c) that were connected in parallel, as in semiconductor module 900.

[0010] Furthermore, when viewed from above, the directions from the first semiconductor elements 920a, 920b, and 920c to the corresponding second semiconductor elements 930a, 930b, and 930c are defined as semiconductor element arrangement directions D1, D2, and D3, respectively. In the semiconductor module 900, the semiconductor element arrangement directions D1, D2, and D3 are all in the same direction (see Figure 16).

[0011] Japanese Patent Publication No. 2008-91787

[0012] In the field of semiconductor module technology, the advancement of integration and density, along with the resulting improvement in heat dissipation, are becoming increasingly important challenges.

[0013] Therefore, the present invention (Aspect 1) has been made in view of the above problems, and aims to provide a semiconductor module that is easier to integrate and increase in density compared to conventional semiconductor modules, and that can improve thermal conductivity and heat dissipation.

[0014] Furthermore, the present invention (Aspect 2) has also been made in view of the above problems, and aims to provide a semiconductor module that can reduce the internal wiring space compared to conventional semiconductor modules.

[0015] Furthermore, the present invention (Aspect 3) has also been made in view of the above problems, and aims to provide a semiconductor module that can improve heat dissipation compared to conventional semiconductor modules.

[0016] A semiconductor module according to one embodiment of the present invention (Aspect 1) is characterized by comprising a plurality of semiconductor elements, each having a plurality of electrodes and connected in parallel, and a thermal capacitive connector that connects electrodes of the same type from the plurality of semiconductor elements to a destination.

[0017] A semiconductor module according to one embodiment of the present invention (Aspect 2) comprises a first semiconductor element having a first electrode and a second electrode, a second semiconductor element having a third electrode and a fourth electrode, and a die pad connector connecting the second electrode and the third electrode, wherein at least a portion of the die pad connector is placed on the second electrode of the first semiconductor element, at least a portion of the third electrode of the second semiconductor element is placed on the die pad connector, and the first semiconductor element and the second semiconductor element are arranged such that at least a portion of them overlap when viewed from above.

[0018] A semiconductor module according to one embodiment of the present invention (Aspect 3) is a semiconductor module comprising a first semiconductor element having a first electrode and a second electrode, a second semiconductor element having a third electrode and a fourth electrode, and an inter-semiconductor element connector that directly or indirectly connects the second electrode and the third electrode, wherein the semiconductor module comprises a plurality of circuit elements consisting of a combination of the first semiconductor element, the second semiconductor element, and the inter-semiconductor element connector, and when the direction from the first semiconductor element toward the second semiconductor element in a plan view is defined as the semiconductor element arrangement direction, the semiconductor element arrangement direction in at least one of the plurality of circuit elements is different from the semiconductor element arrangement direction in adjacent circuit elements.

[0019] The semiconductor module of the present invention (Aspect 1) includes a thermal capacitive connector that connects electrodes of the same type from multiple semiconductor elements to a destination. Therefore, according to the semiconductor module of the present invention (Aspect 1), by using a thermal capacitive connector to connect multiple electrodes, integration and high density are made easier compared to conventional semiconductor modules.

[0020] Furthermore, in configurations where a connector is placed for each semiconductor element, such as in the semiconductor module 900, it was difficult to improve the thermal characteristics (especially the thermal capacity) of the connectors due to limitations in the size of the connectors. On the other hand, in the semiconductor module of the present invention (Aspect 1), since multiple electrodes are connected together with a thermal capacity connector, it is easy to make the thermal capacity connector larger than conventional multiple connectors (for example, connectors 950a, 950b, and 950c of the semiconductor module 900). Therefore, the semiconductor module of the present invention (Aspect 1) makes it possible to improve thermal conductivity and heat dissipation compared to conventional semiconductor modules.

[0021] Therefore, the semiconductor module of the present invention (Aspect 1) is a semiconductor module that is easier to integrate and increase in density compared to conventional semiconductor modules, and is capable of improving thermal conductivity and heat dissipation.

[0022] The semiconductor module of the present invention (Aspect 2) includes a die pad connector that connects the second electrode of the first semiconductor element and the third electrode of the second semiconductor element. Furthermore, in the semiconductor module of the present invention (Aspect 2), at least a portion of the die pad connector is placed on the second electrode of the first semiconductor element, and at least a portion of the third electrode of the second semiconductor element is placed on the die pad connector, and the first and second semiconductor elements are arranged so that at least a portion of them overlap when viewed from above. Therefore, according to the semiconductor module of the present invention (Aspect 2), by using a die pad connector, it is possible to connect the first semiconductor element and the second semiconductor element without other wiring or connectors and to arrange them three-dimensionally. Accordingly, the semiconductor module of the present invention (Aspect 2) is a semiconductor module that can reduce the internal wiring space compared to conventional semiconductor modules.

[0023] In the semiconductor module of the present invention (Aspect 3), the semiconductor element arrangement direction in at least one of the multiple circuit elements is different from the semiconductor element arrangement direction in adjacent circuit elements. Therefore, according to the semiconductor module of the present invention (Aspect 3), it is possible to suppress thermal interference between adjacent semiconductor elements by shifting the arrangement of the semiconductor elements. As a result, the semiconductor module of the present invention (Aspect 3) is a semiconductor module that can improve heat dissipation compared to conventional semiconductor modules.

[0024] This figure shows the external appearance of the semiconductor module 1 according to embodiments 1, 2, and 4. Figure 1(a) is a perspective view, and Figure 1(b) is a plan view. This figure shows the internal structure of the semiconductor module 1 according to embodiments 1, 2, and 4. Figure 2 is a view of Figure 1 with the terminals and case cover 72 hidden. Figure 2(a) is a perspective view, and Figure 2(b) is a plan view. In Figure 2(b), the outlines of the second semiconductor elements 30a, 30b, and 30c hidden by the thermal capacitive connector 50 are shown with dashed lines. This figure shows the internal structure of the semiconductor module 1 according to embodiments 1, 2, and 4. Figure 3 is a view of Figure 2 with the thermal capacitive connector 50 hidden. Figure 3(a) is a perspective view, and Figure 3(b) is a plan view. In Figure 3(b), the outlines of the first semiconductor elements 20a, 20b, and 20c hidden by the die pad connectors 40a, 40b, and 40c are shown with dashed lines. This figure shows the internal structure of the semiconductor module 1 according to embodiments 1, 2, and 4. Figure 4 is a diagram from Figure 3 with the second semiconductor elements 30a, 30b, 30c and die pad connectors 40a, 40b, 40c hidden. Figure 4(a) is a perspective view, and Figure 4(b) is a plan view. This figure shows the circuit element C1 (combination of first semiconductor element 20a, second semiconductor element 30a, and die pad connector 40a) in embodiments 1, 2, and 4. Figure 5(a) is a perspective view, Figure 5(b) is a plan view, and Figure 5(c) is a right side view. In Figure 5(b), the outline of the first semiconductor element 20a hidden by the die pad connector 40a is shown with a dashed line. This figure shows the thermal capacitance connector 50 in embodiments 1, 2, and 4. Figure 6(a) is a perspective view, and Figure 6(b) is a plan view. This figure shows the external appearance of the semiconductor module 2 according to embodiment 3. Figure 7(a) is a perspective view, and Figure 7(b) is a plan view. This figure shows the internal structure of the semiconductor module 2 according to embodiment 3. Figure 8 is a view of Figure 8 with the terminals and sealing resin 170 hidden. Figure 8(a) is a perspective view, and Figure 8(b) is a plan view. In Figure 8(b), the outline of the second semiconductor element 130 hidden by the connector 150 is shown with a dashed line. This figure shows the internal structure of the semiconductor module 2 according to Embodiment 3. Figure 9 is a view of Figure 8 with the connector 150 hidden. Figure 9(a) is a perspective view, and Figure 9(b) is a plan view.Figure 9(b) shows the outline of the first semiconductor element 120 hidden by the die pad connector 140 with a dashed line. This figure shows the internal structure of the semiconductor module 2 according to Embodiment 3. Figure 10 is a view from Figure 9 with the second semiconductor element 130 and the die pad connector 140 hidden. Figure 10(a) is a perspective view, and Figure 10(b) is a plan view. This figure shows the circuit element C (combination of the first semiconductor element 120, the second semiconductor element 130, and the die pad connector 140) in Embodiment 3. Figure 11(a) is a perspective view, Figure 11(b) is a plan view, and Figure 11(c) is a right side view. In Figure 11(b), the outline of the first semiconductor element 120 hidden by the die pad connector 140 is shown with a dashed line. This figure shows the connector 150 in Embodiment 3. Figure 12(a) is a perspective view, and Figure 12(b) is a plan view. This figure shows the internal structure of the semiconductor module 3 according to a modified example and Embodiment 5. Figure 13 corresponds to Figure 3 in Embodiments 2 and 4. Figure 13(a) is a perspective view, and Figure 13(b) is a plan view. This figure shows the internal structure of a modified example and Embodiment 5 of the semiconductor module 3. Figure 14 corresponds to Figure 4 in Embodiments 2 and 4. Figure 14(a) is a perspective view, and Figure 14(b) is a plan view. This is a plan view showing the internal structure of a conventional semiconductor module 900. This is a plan view showing the internal structure of a conventional semiconductor module 900.

[0025] The semiconductor module of the present invention will be described below based on the embodiments shown in the figures. In the embodiments described below, components having exactly the same or substantially the same function will be given common reference numerals in each embodiment, even if their shape or other characteristics differ slightly, and explanations that have already been given may be omitted. The embodiments described below do not limit the invention as defined in the claims. Furthermore, not all of the elements and their combinations described in each embodiment are necessarily essential to the solution of the present invention.

[0026] [The Invention (Aspect 1)] [Embodiment 1] The semiconductor module 1 according to Embodiment 1 comprises a substrate 10, first semiconductor elements 20a, 20b, 20c, second semiconductor elements 30a, 30b, 30c, die pad connectors 40a, 40b, 40c, thermal capacitive connector 50, first power terminal 60, second power terminal 62, midpoint terminals 64a, 64b, 64c, case 70, and case cover 72 (see Figures 1 to 4). The semiconductor module 1 may also include components other than those described above. Each component will be described below.

[0027] The first semiconductor elements 20a, 20b, and 20c are mounted on the substrate 10. When simply referring to "mounted," it is not necessary to specify whether the mounted object is electrically connected to the base on which it is mounted. Furthermore, when referring to "mounted," the mounted object and the base on which it is mounted may be in direct contact, or there may be an intervening material between the mounted object and the base on which it is mounted.

[0028] The substrate 10 has wiring patterns 12, 14, 16, and 18 made of conductive material on one side (the side on which the first semiconductor elements 20a, 20b, and 20c are mounted) (see Figure 4). The wiring patterns 12, 14, 16, and 18 will be described later along with other related components.

[0029] In the semiconductor module 1, a DCB (Direct Copper Bonding) substrate can be suitably used as the substrate 10, in which copper wiring patterns 12, 14, 16, and 18 are directly bonded to a base (not shown in reference numerals) made of ceramic (alumina, aluminum nitride, silicon nitride, etc.).

[0030] Furthermore, in the semiconductor module 1, other ceramic substrates such as AMB (Active Metal Brazing) substrates, or metal-based substrates such as copper-based or aluminum-based substrates can be used as the substrate 10. In addition, metal materials other than copper (for example, aluminum) can be used as the material for the wiring patterns 12, 14, 16, and 18.

[0031] The first semiconductor element 20a has a first electrode 22a and a second electrode 24a (see Figures 4 and 5). The first semiconductor elements 20b and 20c also have a first electrode (not shown) and second electrodes 24b and 24c, similar to the first semiconductor element 20a. The first semiconductor elements 20a, 20b, and 20c are mounted on the wiring pattern 12 of the substrate 10. The first electrodes of the first semiconductor elements 20a, 20b, and 20c are connected to the wiring pattern 12 by a conductive bonding material (not shown). For example, solder can be used as the conductive bonding material.

[0032] Furthermore, when simply stating "connection," the objects being connected must be electrically connected (in a state where they can conduct electricity). Also, when stating "connection," the objects being connected may be in direct contact with each other, or there may be an intermediary between them.

[0033] The first semiconductor elements 20a, 20b, and 20c are diodes. In the first semiconductor element 20a, the first electrode 22a is the cathode electrode, and the second electrode 24a is the anode electrode. Similarly to the first semiconductor element 20a, the first electrode of the first semiconductor elements 20b and 20c is the cathode electrode, and the second electrodes 24b and 24c are the anode electrodes.

[0034] The second semiconductor element 30a has a third electrode 32a and a fourth electrode 34a (see Figures 3 and 5). The second semiconductor elements 30b and 30c also have a third electrode (not shown) and fourth electrodes 34b and 34c, similar to the second semiconductor element 30a. The second semiconductor elements 30a, 30b, and 30c are "multiple semiconductor elements, each having multiple electrodes and connected in parallel." The second semiconductor elements 30a, 30b, and 30c, which are multiple semiconductor elements, are composed of three semiconductor elements.

[0035] The second semiconductor elements 30a, 30b, and 30c are diodes. In the second semiconductor element 30a, the third electrode 32a is the cathode electrode, and the fourth electrode 34a is the anode electrode. Similarly to the second semiconductor element 30a, the third electrode of the second semiconductor elements 30b and 30c is the cathode electrode, and the fourth electrodes 34b and 34c are the anode electrodes.

[0036] When viewed from above, the first semiconductor elements 20a, 20b, 20c and the second semiconductor elements 30a, 30b, 30c are arranged non-linearly. In this specification, "arranged non-linearly" means that when viewed from above, the centers of gravity of the semiconductor elements are not on a straight line. In the semiconductor module 1, the first semiconductor element 20c and the second semiconductor element 30c are arranged outside the arrangement of the first semiconductor elements 20a, 20b and the arrangement of the second semiconductor elements 30a, 30b, respectively.

[0037] The first semiconductor element 20a and the second semiconductor element 30a are connected in a bridge configuration. The first semiconductor element 20a is the high-side element that constitutes the high-side of the bridge connection, and the second semiconductor element 30a is the low-side element that constitutes the low-side of the bridge connection. The relationship between the first semiconductor element 20b and the second semiconductor element 30b, and the relationship between the first semiconductor element 20c and the second semiconductor element 30c are the same as the relationship between the first semiconductor element 20a and the second semiconductor element 30a described above. For this reason, the semiconductor module 1 is a so-called three-phase bridge diode module.

[0038] In this specification, "bridge connection" means that the first semiconductor element and the second semiconductor element are connected such that they can form the main current path of a bridge circuit and constitute the high-side and low-side of the bridge circuit. In this case, "bridge circuit" also includes those that require components other than semiconductor modules.

[0039] The die pad connector 40a connects the second electrode 24a and the third electrode 32a (see Figure 5). The die pad connector 40a is a structure made of a conductive material.

[0040] At least part (the entirety in the semiconductor module 1) of the third electrode 32a in the second semiconductor element 30a is placed on the die pad connector 40a. Further, at least part (a part in the semiconductor module 1) of the die pad connector 40a is placed on the second electrode 24a of the first semiconductor element 20a. Note that a conductive bonding material 80 is interposed between the die pad connector 40a and the second electrode 24a. Although not shown in the drawings, a conductive bonding material is also interposed between the third electrode 32a and the die pad connector 40a.

[0041] Furthermore, the first semiconductor element 20a and the second semiconductor element 30a are arranged such that at least portions thereof overlap each other when viewed in plan (see FIG. 3(b) and FIG. 5(b)). Also, the first semiconductor element 20a and the second semiconductor element 30a are arranged such that the entirety thereof does not overlap each other when viewed in plan.

[0042] The die pad connector 40a includes a first semiconductor element side placement portion 42a placed on the second electrode 24a of the first semiconductor element 20a, and a substrate side placement portion 44a placed on the substrate 10 (see FIG. 5). The substrate side placement portion 44a has a greater thickness than the first semiconductor element side placement portion 42a.

[0043] The substrate side placement portion 44a is placed on the wiring pattern 14 of the substrate 10. Note that the wiring pattern 14 is an isolated wiring pattern that is not connected to any constituent elements other than the substrate side placement portion 44a. A planar die pad surface 46a is formed on a side of the die pad connector 40a opposite to the first semiconductor element 20a side and the substrate 10 side. The second semiconductor element 30a is placed on the die pad surface 46a.

[0044] Although individual illustration and reference sign designation are omitted, the die pad connectors 40b and 40c also have a structure corresponding to the structure of the die pad connector 40a described above. Also, the first semiconductor elements 20b and 20c, the second semiconductor elements 30b and 30c, and the die pad connectors 40b and 40c also have a positional relationship corresponding to the positional relationship of the first semiconductor element 20a, the second semiconductor element 30a, and the die pad connector 40a described above.

[0045] The semiconductor module 1 comprises a plurality of circuit elements, each consisting of a combination of a first semiconductor element, a second semiconductor element, and a die pad connector. Specifically, the semiconductor module 1 comprises three circuit elements C1, C2, and C3. Circuit element C1 consists of a combination of a first semiconductor element 20a, a second semiconductor element 30a, and a die pad connector 40a. Circuit element C2 consists of a combination of a first semiconductor element 20b, a second semiconductor element 30b, and a die pad connector 40b. Circuit element C3 consists of a combination of a first semiconductor element 20c, a second semiconductor element 30c, and a die pad connector 40c.

[0046] Here, the direction from the first semiconductor element to the second semiconductor element when viewed from above is defined as the semiconductor element arrangement direction. The semiconductor element arrangement direction D3 in at least one of the multiple circuit elements C1, C2, and C3 (in this case, circuit element C3) is different from the semiconductor element arrangement direction D2 in the adjacent circuit element (in this case, circuit element C2) (see Figure 3). Note that the above "different direction" is in opposite directions. Also, the semiconductor element arrangement direction D1 in circuit element C1 is the same direction as the semiconductor element arrangement direction D2 in circuit element C2.

[0047] The thermal capacitive connector 50 connects the fourth electrodes 34a, 34b, and 34c of multiple second semiconductor elements 30a, 30b, and 30c to a destination. The destination of the thermal capacitive connector 50 is the substrate 10. The fourth electrodes 34a, 34b, and 34c are "electrodes of the same type among the electrodes of multiple semiconductor elements (second semiconductor elements 30a, 30b, and 30c)".

[0048] The heat-capacitive connector 50 has a head portion 52 connected to a plurality of fourth electrodes 34a, 34b, and 34c, and a tail portion 56 that protrudes from the head portion 52 and whose tip is connected to the substrate 10. The heat-capacitive connector 50 has a plurality of tail portions 56. The tail portions 56 are connected to the region 17a of the wiring pattern 16 on the substrate 10.

[0049] Furthermore, the heat-capacitive connector 50 protrudes from the head portion 52, its tip rests on the substrate 10, and it further has a heat-dissipating tail portion 58 that does not constitute part of the main current path. The heat-dissipating tail portion 58 is connected to the wiring pattern 18 on the substrate 10. The wiring pattern 18 is an isolated wiring pattern that is not connected to any components other than the heat-dissipating tail portion 58.

[0050] The head portion 52 covers the multiple fourth electrodes 34a, 34b, and 34c when viewed from above. The head portion 52 also has electrode mounting portions 53a, 53b, and 53c that are placed on the multiple fourth electrodes 34a, 34b, and 34c, and a heat capacity securing portion 54 that extends to the outer edges of the electrode mounting portions 53a, 53b, and 53c.

[0051] Furthermore, the head portion 52 does not need to completely cover the multiple fourth electrodes 34a, 34b, and 34c without any gaps; it is sufficient if it covers most of them (for example, 80% or more).

[0052] The first power terminal 60 is a terminal that electrically connects the first electrodes of the first semiconductor elements 20a, 20b, and 20c to the outside. The first power terminal 60 is connected to a region 13 of the wiring pattern 12 on the substrate 10 and is connected to the first electrodes of the first semiconductor elements 20a, 20b, and 20c via the wiring pattern 12.

[0053] The second power terminal 62 is a terminal that electrically connects the fourth electrodes 34a, 34b, and 34c of the second semiconductor elements 30a, 30b, and 30c to the outside. The second power terminal 62 is connected to the region 17b of the wiring pattern 16 on the substrate 10, and is connected to the fourth electrodes 34a, 34b, and 34c of the second semiconductor elements 30a, 30b, and 30c via the wiring pattern 16 and the thermal capacitance connector 50.

[0054] The center terminal 64a is a terminal that electrically connects the die pad connector 40a (the current path between the first semiconductor element 20a and the second semiconductor element 30a) to the outside. The center terminal 64b is a terminal that electrically connects the die pad connector 40b (the current path between the first semiconductor element 20b and the second semiconductor element 30b) to the outside. The center terminal 64c is a terminal that electrically connects the die pad connector 40c (the current path between the first semiconductor element 20c and the second semiconductor element 30c) to the outside.

[0055] The center terminal 64a is connected to area 41a of the die pad connector 40a. The center terminal 64b is connected to area 41b of the die pad connector 40b. The center terminal 64b is connected to area 41c of the die pad connector 40b.

[0056] The case 70 is for housing the main components of the semiconductor module 1. The case lid 72 is the lid of the case 70. Although not shown in the illustration, the back surface of the substrate 10 (the surface opposite to the surface on which the wiring patterns 12, 14, 16, and 18 are located) is exposed to the outside of the case 70. The case lid 72 also has holes formed therein for passing the first power terminal 60, the second power terminal 62, and the center terminals 64a, 64b, and 64c.

[0057] The semiconductor module 1 according to Embodiment 1 includes a thermal capacitive connector 50 that connects electrodes of the same type (fourth electrodes 34a, 34b, 34c) among multiple semiconductor elements (second semiconductor elements 30a, 30b, 30c) to a connection point. Therefore, with the semiconductor module 1, by using the thermal capacitive connector 50 to connect multiple electrodes (fourth electrodes 34a, 34b, 34c), integration and high density are made easier compared to conventional semiconductor modules.

[0058] Furthermore, in the semiconductor module 1 according to Embodiment 1, since multiple electrodes (fourth electrodes 34a, 34b, 34c) are connected together with a thermal capacitive connector 50, it is easy to make the thermal capacitive connector 50 larger than conventional connectors (for example, connectors 950a, 950b, 950c of semiconductor module 900). Therefore, the semiconductor module 1 makes it possible to improve thermal conductivity and heat dissipation compared to conventional semiconductor modules.

[0059] Therefore, the semiconductor module 1 according to Embodiment 1 is a semiconductor module that is easier to integrate and increase in density compared to conventional semiconductor modules, and that can improve thermal conductivity and heat dissipation.

[0060] Furthermore, in the semiconductor module 1 according to Embodiment 1, the plurality of semiconductor elements (second semiconductor elements 30a, 30b, 30c) are composed of at least three semiconductor elements, and the thermal capacitive connector 50 connects at least three identical electrodes (fourth electrodes 34a, 34b, 34c) to the connection destination. As a result, the semiconductor module 1 allows for the connection of a large number of electrodes together, making further integration and density increases easier, and enabling further improvements in thermal conductivity and heat dissipation.

[0061] Furthermore, in the semiconductor module 1 according to Embodiment 1, the semiconductor elements constituting the plurality of semiconductor elements (second semiconductor elements 30a, 30b, 30c) are low-side elements that constitute the low-side of the bridge connection. Therefore, the semiconductor module 1 is a semiconductor module that can be used to configure a bridge circuit.

[0062] Furthermore, the semiconductor module 1 according to Embodiment 1 further comprises a substrate 10, and the thermal capacitive connector 50 is connected to the substrate 10. Therefore, the semiconductor module 1 makes it possible to connect identical electrodes (fourth electrodes 34a, 34b, 34c) of multiple semiconductor elements (second semiconductor elements 30a, 30b, 30c) to the substrate 10.

[0063] Furthermore, according to the semiconductor module 1 of Embodiment 1, the thermal capacitive connector 50 has a head portion 52 and a tail portion 56, making it possible to stably connect the same type of electrodes (fourth electrodes 34a, 34b, 34c) of multiple semiconductor elements (second semiconductor elements 30a, 30b, 30c) to the substrate 10.

[0064] Furthermore, according to the semiconductor module 1 of Embodiment 1, the thermal capacitive connector 50 has a heat dissipation tail portion 58, which makes it possible to promote heat conduction from the thermal capacitive connector 50 to the connection destination (substrate 10).

[0065] Furthermore, according to the semiconductor module 1 of Embodiment 1, the head portion 52 covers the same type of electrodes (fourth electrodes 34a, 34b, 34c) when viewed from above, making it possible to efficiently conduct the heat generated by the semiconductor element to the head portion 52.

[0066] Furthermore, according to the semiconductor module 1 of Embodiment 1, the head portion 52 has electrode mounting portions 53a, 53b, and 53c, and a heat capacity securing portion 54, which makes it possible to absorb even more heat with the head portion 52.

[0067] Although the present invention (Aspect 1) has been described above based on Embodiment 1, the present invention (Aspect 1) is not limited to Embodiment 1. It can be implemented in various forms without departing from its spirit, and for example, the following modifications are also possible.

[0068] (1) The positions, sizes, shapes, etc. of each component described in Embodiment 1 above and shown in each drawing are illustrative examples and can be changed within the scope that does not impair the effects of the present invention (Embodiment 1).

[0069] For example, in Embodiment 1 described above, the second semiconductor elements 30a, 30b, and 30c, which are a plurality of semiconductor elements, are composed of three semiconductor elements, but the present invention (Aspect 1) is not limited thereto. The plurality of semiconductor elements having electrodes connected together by a thermal capacitive connector may be composed of two semiconductor elements, or of four or more semiconductor elements.

[0070] (2) In Embodiment 1 described above, the first semiconductor elements 20a, 20b, 20c and the second semiconductor elements 30a, 30b, 30c were diodes, but the present invention (Aspect 1) is not limited thereto. The semiconductor elements in the semiconductor module of the present invention (Aspect 1) can be changed as appropriate as long as the gist of the present invention (Aspect 1) is not altered, and may be other semiconductor elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), or Schottky barrier diodes (especially SiC Schottky barrier diodes).

[0071] (3) In Embodiment 1 described above, the first semiconductor elements 20a, 20b, 20c and the second semiconductor elements 30a, 30b, 30c were vertical semiconductor elements (where the electrodes constituting the main current path are on different surfaces), but the present invention (Aspect 1) is not limited thereto. The semiconductor elements in the semiconductor module of the present invention (Aspect 1) may be horizontal semiconductor elements (where the electrodes constituting the main current path are on the same surface). Examples of horizontal semiconductor elements include horizontal transistor elements (for example, GaN-HEMT composed of GaN-on-Si material, and other Ga ２ O ３ Examples include compound semiconductor transistor devices composed of on-Si materials.

[0072] (4) In Embodiment 1 described above, the first semiconductor elements 20a, 20b, 20c and the second semiconductor elements 30a, 30b, 30c were all of the same type, but the present invention (Aspect 1) is not limited thereto. The first semiconductor elements and the second semiconductor elements in the semiconductor module of the present invention (Aspect 1) may be of different types.

[0073] (5) The semiconductor module 1 according to Embodiment 1 above includes a case 70 and a case lid 72, but the present invention (Aspect 1) is not limited thereto. The type and shape of components for protecting the internal structure, such as the case and sealing resin, can be changed as appropriate according to the product specifications, etc. Furthermore, the semiconductor module of the present invention (Aspect 1) does not need to include components for protecting the internal structure, such as the case and sealing resin.

[0074] [The Invention (Aspect 2)] [Embodiment 2] The semiconductor module 1 according to Embodiment 2 comprises a substrate 10, first semiconductor elements 20a, 20b, 20c, second semiconductor elements 30a, 30b, 30c, die pad connectors 40a, 40b, 40c, thermal capacitive connector 50, first power terminal 60, second power terminal 62, midpoint terminals 64a, 64b, 64c, case 70, and case cover 72 (see Figures 1 to 4). The semiconductor module 1 may also include components other than those described above. Each component will be described below.

[0075] The first semiconductor elements 20a, 20b, and 20c are mounted on the substrate 10. When simply referring to "mounted," it is not necessary to specify whether the mounted object is electrically connected to the base on which it is mounted. Furthermore, when referring to "mounted," the mounted object and the base on which it is mounted may be in direct contact, or there may be an intervening material between the mounted object and the base on which it is mounted.

[0076] The substrate 10 has wiring patterns 12, 14, 16, and 18 made of conductive material on one side (the side on which the first semiconductor elements 20a, 20b, and 20c are mounted) (see Figure 4). The wiring patterns 12, 14, 16, and 18 will be described later along with other related components.

[0077] In the semiconductor module 1, a DCB (Direct Copper Bonding) substrate can be suitably used as the substrate 10, in which copper wiring patterns 12, 14, 16, and 18 are directly bonded to a base (not shown in reference numerals) made of ceramic (alumina, aluminum nitride, silicon nitride, etc.).

[0078] Furthermore, in the semiconductor module 1, other ceramic substrates such as AMB (Active Metal Brazing) substrates, or metal-based substrates such as copper-based or aluminum-based substrates can be used as the substrate 10. In addition, metal materials other than copper (for example, aluminum) can be used as the material for the wiring patterns 12, 14, 16, and 18.

[0079] The first semiconductor element 20a has a first electrode 22a and a second electrode 24a (see Figures 4 and 5). The first semiconductor elements 20b and 20c also have a first electrode (not shown) and second electrodes 24b and 24c, similar to the first semiconductor element 20a. The first semiconductor elements 20a, 20b, and 20c are mounted on the wiring pattern 12 of the substrate 10. The first electrodes of the first semiconductor elements 20a, 20b, and 20c are connected to the wiring pattern 12 by a conductive bonding material (not shown). For example, solder can be used as the conductive bonding material.

[0080] Furthermore, when simply stating "connection," the objects being connected must be electrically connected (in a state where they can conduct electricity). Also, when stating "connection," the objects being connected may be in direct contact with each other, or there may be an intermediary between them.

[0081] The first semiconductor elements 20a, 20b, and 20c are diodes. In the first semiconductor element 20a, the first electrode 22a is the cathode electrode, and the second electrode 24a is the anode electrode. Similarly to the first semiconductor element 20a, the first electrode of the first semiconductor elements 20b and 20c is the cathode electrode, and the second electrodes 24b and 24c are the anode electrodes.

[0082] The second semiconductor element 30a has a third electrode 32a and a fourth electrode 34a (see Figures 3 and 5). The second semiconductor elements 30b and 30c also have a third electrode (not shown) and fourth electrodes 34b and 34c, similar to the second semiconductor element 30a.

[0083] The second semiconductor elements 30a, 30b, and 30c are diodes. In the second semiconductor element 30a, the third electrode 32a is the cathode electrode, and the fourth electrode 34a is the anode electrode. Similarly to the second semiconductor element 30a, the third electrode of the second semiconductor elements 30b and 30c is the cathode electrode, and the fourth electrodes 34b and 34c are the anode electrodes.

[0084] When viewed from above, the first semiconductor elements 20a, 20b, 20c and the second semiconductor elements 30a, 30b, 30c are arranged non-linearly. In this specification, "arranged non-linearly" means that when viewed from above, the centers of gravity of the semiconductor elements are not on a straight line. In the semiconductor module 1, the first semiconductor element 20c and the second semiconductor element 30c are arranged outside the arrangement of the first semiconductor elements 20a, 20b and the arrangement of the second semiconductor elements 30a, 30b, respectively.

[0085] The first semiconductor element 20a and the second semiconductor element 30a are connected in a bridge configuration. The first semiconductor element 20a is the high-side element that constitutes the high-side of the bridge connection, and the second semiconductor element 30a is the low-side element that constitutes the low-side of the bridge connection. The relationship between the first semiconductor element 20b and the second semiconductor element 30b, and the relationship between the first semiconductor element 20c and the second semiconductor element 30c are the same as the relationship between the first semiconductor element 20a and the second semiconductor element 30a described above. For this reason, the semiconductor module 1 is a so-called three-phase bridge diode module.

[0086] In this specification, "bridge connection" means that the first semiconductor element and the second semiconductor element are connected such that they can form the main current path of a bridge circuit and constitute the high-side and low-side of the bridge circuit. In this case, "bridge circuit" also includes those that require components other than semiconductor modules.

[0087] The die pad connector 40a connects the second electrode 24a and the third electrode 32a (see Figure 5). The die pad connector 40a is a structure made of a conductive material.

[0088] At least a portion (all in the case of semiconductor module 1) of the third electrode 32a of the second semiconductor element 30a is mounted on the die pad connector 40a. Also, at least a portion (part in the case of semiconductor module 1) of the die pad connector 40a is mounted on the second electrode 24a of the first semiconductor element 20a. A conductive bonding material 80 is interposed between the die pad connector 40a and the second electrode 24a. Although not shown in the figures, a conductive bonding material is also interposed between the third electrode 32a and the die pad connector 40a.

[0089] Furthermore, the first semiconductor element 20a and the second semiconductor element 30a are arranged such that at least a portion of them overlap when viewed from above (see Figures 3(b) and 5(b)). Also, the first semiconductor element 20a and the second semiconductor element 30a are arranged such that they do not completely overlap when viewed from above.

[0090] The die pad connector 40a has a first semiconductor element-side mounting portion 42a that is mounted on the second electrode 24a of the first semiconductor element 20a, and a substrate-side mounting portion 44a that is mounted on the substrate 10 (see Figure 5). The substrate-side mounting portion 44a is thicker than the first semiconductor element-side mounting portion 42a.

[0091] The substrate-side mounting portion 44a is mounted on the wiring pattern 14 of the substrate 10. The wiring pattern 14 is an isolated wiring pattern that is not connected to any components other than the substrate-side mounting portion 44a. A planar die pad surface 46a is formed on the side of the die pad connector 40a that is opposite to the first semiconductor element 20a and the substrate 10. The second semiconductor element 30a is mounted on the die pad surface 46a.

[0092] Although the individual figures and reference numerals are omitted, the die pad connectors 40b and 40c also have a structure corresponding to the structure of the die pad connector 40a described above. Furthermore, the first semiconductor elements 20b and 20c, the second semiconductor elements 30b and 30c, and the die pad connectors 40b and 40c also have a positional relationship corresponding to the positional relationship of the first semiconductor element 20a, the second semiconductor element 30a, and the die pad connector 40a described above.

[0093] The semiconductor module 1 comprises a plurality of circuit elements, each consisting of a combination of a first semiconductor element, a second semiconductor element, and a die pad connector. Specifically, the semiconductor module 1 comprises three circuit elements C1, C2, and C3. Circuit element C1 consists of a combination of a first semiconductor element 20a, a second semiconductor element 30a, and a die pad connector 40a. Circuit element C2 consists of a combination of a first semiconductor element 20b, a second semiconductor element 30b, and a die pad connector 40b. Circuit element C3 consists of a combination of a first semiconductor element 20c, a second semiconductor element 30c, and a die pad connector 40c.

[0094] Here, the direction from the first semiconductor element to the second semiconductor element when viewed from above is defined as the semiconductor element arrangement direction. The semiconductor element arrangement direction D3 in at least one of the multiple circuit elements C1, C2, and C3 (in this case, circuit element C3) is different from the semiconductor element arrangement direction D2 in the adjacent circuit element (in this case, circuit element C2) (see Figure 3). Note that the above "different direction" is in opposite directions. Also, the semiconductor element arrangement direction D1 in circuit element C1 is the same direction as the semiconductor element arrangement direction D2 in circuit element C2.

[0095] The thermal capacitive connector 50 connects the fourth electrodes 34a, 34b, and 34c of multiple second semiconductor elements 30a, 30b, and 30c to a destination. The destination of the thermal capacitive connector 50 is the substrate 10.

[0096] The heat-capacitive connector 50 has a head portion 52 connected to a plurality of fourth electrodes 34a, 34b, and 34c, and a tail portion 56 that protrudes from the head portion 52 and whose tip is connected to the substrate 10. The heat-capacitive connector 50 has a plurality of tail portions 56. The tail portions 56 are connected to the region 17a of the wiring pattern 16 on the substrate 10.

[0097] Furthermore, the heat-capacitive connector 50 protrudes from the head portion 52, its tip rests on the substrate 10, and it further has a heat-dissipating tail portion 58 that does not constitute part of the main current path. The heat-dissipating tail portion 58 is connected to the wiring pattern 18 on the substrate 10. The wiring pattern 18 is an isolated wiring pattern that is not connected to any components other than the heat-dissipating tail portion 58.

[0098] The head portion 52 covers the multiple fourth electrodes 34a, 34b, and 34c when viewed from above. The head portion 52 also has electrode mounting portions 53a, 53b, and 53c that are placed on the multiple fourth electrodes 34a, 34b, and 34c, and a heat capacity securing portion 54 that extends to the outer edges of the electrode mounting portions 53a, 53b, and 53c.

[0099] Furthermore, the head portion 52 does not need to completely cover the multiple fourth electrodes 34a, 34b, and 34c without any gaps; it is sufficient if it covers most of them (for example, 80% or more).

[0100] The first power terminal 60 is a terminal that electrically connects the first electrodes of the first semiconductor elements 20a, 20b, and 20c to the outside. The first power terminal 60 is connected to a region 13 of the wiring pattern 12 on the substrate 10 and is connected to the first electrodes of the first semiconductor elements 20a, 20b, and 20c via the wiring pattern 12.

[0101] The second power terminal 62 is a terminal that electrically connects the fourth electrodes 34a, 34b, and 34c of the second semiconductor elements 30a, 30b, and 30c to the outside. The second power terminal 62 is connected to the region 17b of the wiring pattern 16 on the substrate 10, and is connected to the fourth electrodes 34a, 34b, and 34c of the second semiconductor elements 30a, 30b, and 30c via the wiring pattern 16 and the thermal capacitance connector 50.

[0102] The center terminal 64a is a terminal that electrically connects the die pad connector 40a (the current path between the first semiconductor element 20a and the second semiconductor element 30a) to the outside. The center terminal 64b is a terminal that electrically connects the die pad connector 40b (the current path between the first semiconductor element 20b and the second semiconductor element 30b) to the outside. The center terminal 64c is a terminal that electrically connects the die pad connector 40c (the current path between the first semiconductor element 20c and the second semiconductor element 30c) to the outside.

[0103] The center terminal 64a is connected to area 41a of the die pad connector 40a. The center terminal 64b is connected to area 41b of the die pad connector 40b. The center terminal 64b is connected to area 41c of the die pad connector 40b.

[0104] The case 70 is for housing the main components of the semiconductor module 1. The case lid 72 is the lid of the case 70. Although not shown in the illustration, the back surface of the substrate 10 (the surface opposite to the surface on which the wiring patterns 12, 14, 16, and 18 are located) is exposed to the outside of the case 70. The case lid 72 also has holes formed therein for passing the first power terminal 60, the second power terminal 62, and the center terminals 64a, 64b, and 64c.

[0105] The semiconductor module 1 according to Embodiment 2 includes die pad connectors 40a, 40b, 40c that connect the second electrodes 24a, 24b, 24c of the first semiconductor elements 20a, 20b, 20c to the third electrodes of the second semiconductor elements 30a, 30b, 30c. In the semiconductor module 1, at least a portion of the die pad connectors 40a, 40b, 40c is placed on the second electrodes 24a, 24b, 24c of the first semiconductor elements 20a, 20b, 20c, and at least a portion of the third electrodes of the second semiconductor elements 30a, 30b, 30c is placed on the die pad connectors 40a, 40b, 40c. The first semiconductor elements 20a, 20b, 20c and the second semiconductor elements 30a, 30b, 30c are arranged such that at least a portion of them overlap when viewed from above. Therefore, with semiconductor module 1, by using die pad connectors 40a, 40b, and 40c, the first semiconductor elements 20a, 20b, and 20c and the second semiconductor elements 30a, 30b, and 30c can be connected without other wiring or connectors and arranged three-dimensionally. Consequently, semiconductor module 1 is a semiconductor module that can reduce the internal wiring space compared to conventional semiconductor modules.

[0106] Furthermore, in the semiconductor module 1 according to Embodiment 2, the first semiconductor elements 20a, 20b, and 20c and the second semiconductor elements 30a, 30b, and 30c are connected in a bridge configuration. The first semiconductor elements 20a, 20b, and 20c are high-side elements that constitute the high-side of the bridge connection, and the second semiconductor elements 30a, 30b, and 30c are low-side elements that constitute the low-side of the bridge connection. Therefore, the semiconductor module 1 is a semiconductor module that can be used to configure a bridge circuit.

[0107] Furthermore, the semiconductor module 1 according to Embodiment 2 includes a substrate 10 on which the first semiconductor elements 20a, 20b, and 20c are mounted, and the die pad connectors 40a, 40b, and 40c have a first semiconductor element side mounting portion mounted on the second electrodes 24a, 24b, and 24c of the first semiconductor elements 20a, 20b, and 20c, and a substrate side mounting portion mounted on the substrate 10. Therefore, the semiconductor module 1 makes it possible to arrange the die pad connectors 40a, 40b, and 40c in a stable state.

[0108] Furthermore, in the semiconductor module 1 according to Embodiment 2, the substrate-side mounting portion is thicker than the first semiconductor-side element connection portion, and a planar die pad surface is formed on the side of the die pad connectors 40a, 40b, 40c opposite to the first semiconductor elements 20a, 20b, 20c and the substrate 10, and the second semiconductor elements 30a, 30b, 30c are mounted on the die pad surface. Therefore, according to the semiconductor module 1, it is possible to stably position the second semiconductor elements 30a, 30b, 30c on the die pad connectors 40a, 40b, 40c.

[0109] Furthermore, the semiconductor module 1 according to Embodiment 2 includes a plurality of circuit elements consisting of a combination of a first semiconductor element, a second semiconductor element, and a die pad connector (including circuit elements C1, C2, and C3). Therefore, the semiconductor module 1 is a semiconductor module that compactly integrates a plurality of circuit elements C1, C2, and C3.

[0110] Furthermore, the semiconductor module 1 according to Embodiment 2 includes a thermal capacitive connector 50 that connects the fourth electrodes 34a, 34b, and 34c of a plurality of second semiconductor elements 30a, 30b, and 30c to a destination. Therefore, with the semiconductor module 1, by using the thermal capacitive connector 50 to connect a plurality of electrodes (fourth electrodes 34a, 34b, and 34c), integration and high density are made easier compared to conventional semiconductor modules.

[0111] Furthermore, in the semiconductor module 1 according to Embodiment 2, since multiple electrodes (fourth electrodes 34a, 34b, 34c) are connected together with a thermal capacitive connector 50, it is easy to make the thermal capacitive connector 50 larger than conventional connectors (for example, connectors 950a, 950b, 950c of semiconductor module 900). Therefore, with semiconductor module 1, it is possible to improve thermal conductivity and heat dissipation compared to conventional semiconductor modules.

[0112] [Embodiment 3] The semiconductor module 2 according to Embodiment 3 differs from the semiconductor module 1 according to Embodiment 2 mainly in terms of the number and type of semiconductor elements. The semiconductor module 2 according to Embodiment 3 comprises a substrate 110, a first semiconductor element 120, a second semiconductor element 130, a die pad connector 140, a connector 150, a first power terminal 160, a second power terminal 162, a center terminal 164, control terminals 166a, 166b, detection terminals 168a, 168b, 168c, and a sealing resin 170 (see Figures 7 to 10).

[0113] The semiconductor module 2 further includes temperature detection terminals T1 and T2 and a temperature detection element TE, but these do not constitute the essential features of the present invention (Aspect 2), and therefore their description is omitted. Furthermore, the semiconductor module 2 may include other components not described above. Each component will be described below.

[0114] A first semiconductor element 120 is mounted on the substrate 110. The substrate 110 has wiring patterns 112, 114, 116, 118, 119a, 119b, 119c, and 119d made of conductive material on one side (the side on which the first semiconductor element 120 is mounted) (see Figure 10). The wiring patterns 112, 114, 116, 118, 119a, 119b, 119c, and 119d will be described later along with other related components.

[0115] In semiconductor module 2, as in the case of semiconductor module 1 according to embodiment 2, a DCB substrate can be suitably used as the substrate 110. In semiconductor module 2, other ceramic substrates such as AMB substrates, or metal substrates such as copper-based or aluminum-based substrates can also be used as the substrate 110. Furthermore, metal materials other than copper (for example, aluminum) can be used as the material for the wiring patterns 112, 114, 116, 118, 119a, 119b, 119c, and 119d.

[0116] The first semiconductor element 120 has a first electrode 122 and a second electrode 124 (see Figures 10 and 11). The first semiconductor element 120 also has a control electrode 126. The first semiconductor element 120 is placed on a wiring pattern 112 of a substrate 110. The first electrode 122 of the first semiconductor element 120 is connected to the wiring pattern 112 by (not shown). For example, solder can be used as the conductive bonding material.

[0117] The first semiconductor element 120 is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In the first semiconductor element 120, the first electrode 122 is the drain electrode, the second electrode 124 is the source electrode, and the control electrode 126 is the gate electrode. The first semiconductor element 120 is a vertical transistor element. The control electrode 126 is located on the side where the second electrode 124 is located.

[0118] The second semiconductor element 130 has a third electrode 132 and a fourth electrode 134 (see Figures 9 and 11). The second semiconductor element 130 also has a control electrode 136. The second semiconductor element 130 is a MOSFET. In the second semiconductor element 130, the third electrode 132 is the drain electrode, the fourth electrode 134 is the source electrode, and the control electrode 136 is the gate electrode. The second semiconductor element 130 is a vertical transistor element. The control electrode 136 is located on the side where the fourth electrode 134 is located.

[0119] The first semiconductor element 120 and the second semiconductor element 130 are connected in a bridge configuration. The first semiconductor element 120 is the high-side element that constitutes the high-side of the bridge connection, and the second semiconductor element 130 is the low-side element that constitutes the low-side of the bridge connection. Therefore, the semiconductor module 2 is a so-called half-bridge MOSFET module.

[0120] The die pad connector 140 connects the second electrode 124 and the third electrode 132 (see Figure 11). The die pad connector 140 is a structure made of a conductive material.

[0121] At least a portion (all in the case of semiconductor module 2) of the third electrode 132 of the second semiconductor element 130 is mounted on the die pad connector 140. Also, at least a portion (part in the case of semiconductor module 2) of the die pad connector 140 is mounted on the second electrode 124 of the first semiconductor element 120. A conductive bonding material 180 is interposed between the die pad connector 140 and the second electrode 124. Although not shown in the figures, a conductive bonding material is also interposed between the third electrode 132 and the die pad connector 140.

[0122] Furthermore, the first semiconductor element 120 and the second semiconductor element 130 are arranged such that at least a portion of them overlap when viewed from above (see Figures 9(b) and 11(b)). Also, the first semiconductor element 120 and the second semiconductor element 130 are arranged such that they do not completely overlap when viewed from above.

[0123] The die pad connector 140 has a first semiconductor element-side mounting portion 142 which is mounted on the second electrode 124 of the first semiconductor element 120, and a substrate-side mounting portion 144 which is mounted on the substrate 110 (see Figure 11). The substrate-side mounting portion 144 is thicker than the first semiconductor element-side mounting portion 142.

[0124] The substrate-side mounting portion 144 is mounted on the region 115a of the wiring pattern 114 on the substrate 110. A planar die pad surface 146 is formed on the side of the die pad connector 140 opposite to the first semiconductor element 120 and the substrate 110. The second semiconductor element 130 is mounted on the die pad surface 146.

[0125] Furthermore, the die pad connector 140 further includes a detection tail portion 148a whose tip is connected to the substrate 110, and a non-current path tail portion 148b whose tip is placed on the substrate 110. The detection tail portion 148a is connected to the wiring pattern 119a of the substrate 110. The non-current path tail portion 148b is connected to the wiring pattern 118a of the substrate 110. Note that the wiring pattern 118a is an isolated wiring pattern that is not connected to any components other than the non-current path tail portion 148b.

[0126] The semiconductor module 2 includes one circuit element C consisting of a combination of a first semiconductor element 120, a second semiconductor element 130, and a die pad connector 140.

[0127] The connector 150 connects the fourth electrode 134 of the second semiconductor element 130 to a destination. The destination of the connector 150 is the substrate 110. The connector 150 has a head portion 152 connected to the fourth electrode 134 and a tail portion 156 that protrudes from the head portion 152 and whose tip is connected to the substrate 110. The tail portion 156 is connected to the region 117a of the wiring pattern 116 on the substrate 110.

[0128] Furthermore, the connector 150 protrudes from the head portion 152, its tip rests on the substrate 110, and it further has a heat dissipation tail portion 158 that does not constitute part of the main current path. The heat dissipation tail portion 158 is connected to the wiring pattern 118b of the substrate 110. Note that the wiring pattern 118b is an isolated wiring pattern that is not connected to any components other than the heat dissipation tail portion 158.

[0129] Furthermore, the connector 150 has a detection tail portion 159 that protrudes from the head portion 152 and whose tip is connected to the wiring pattern 119c on the substrate 110.

[0130] The first power terminal 160 is a terminal that electrically connects the first electrode 122 of the first semiconductor element 120 to the outside. The first power terminal 160 is connected to region 113 of the wiring pattern 112 on the substrate 110 and is connected to the first electrode 122 of the first semiconductor element 120 via the wiring pattern 112.

[0131] The second power terminal 162 is a terminal that electrically connects the fourth electrode 134 of the second semiconductor element 130 to the outside. The second power terminal 162 is connected to the region 117b of the wiring pattern 116 on the substrate 110, and is connected to the fourth electrode 134 of the second semiconductor element 130 via the wiring pattern 116 and the connector 150.

[0132] The center terminal 164 is a terminal that electrically connects the die pad connector 140 (the current path between the first semiconductor element 120 and the second semiconductor element 130) to the outside. The center terminal 164 is connected to the region 115b of the wiring pattern 114 on the substrate 110 and is connected to the die pad connector 140 via the wiring pattern 114.

[0133] Control terminal 166a is connected to wiring pattern 119b on substrate 110 and is connected to control electrode 126 of first semiconductor element 120 via wiring pattern 119b and connector 190a. Control terminal 166b is connected to wiring pattern 119d on substrate 110 and is connected to control electrode 136 of second semiconductor element 130 via wiring pattern 119d and connector 190b.

[0134] The detection terminal 168a is connected to region 113b of the wiring pattern 112 on the substrate 110 and is connected to the first electrode 122 of the first semiconductor element 120 via the wiring pattern 112. The detection terminal 168b is connected to the wiring pattern 119a on the substrate 110 and is connected to the die pad connector 140 via the wiring pattern 119a. The detection terminal 168c is connected to the wiring pattern 119c on the substrate 110 and is connected to the fourth electrode 134 of the second semiconductor element 130 via the wiring pattern 119c and the connector 150.

[0135] The sealing resin 170 is used to seal the main components of the semiconductor module 2. The back surface of the substrate 110 (the surface opposite to the surface on which the wiring pattern 112 is located, not shown) and the outer sides of each terminal are exposed to the outside of the sealing resin 170.

[0136] The semiconductor module 2 according to Embodiment 3 includes a die pad connector 140 that connects the second electrode 124 of the first semiconductor element 120 and the third electrode 132 of the second semiconductor element 130. In the semiconductor module 2, at least a portion of the die pad connector 140 is placed on the second electrode 124 of the first semiconductor element 120, and at least a portion of the third electrode 132 of the second semiconductor element 130 is placed on the die pad connector 140, so that at least a portion of the first semiconductor element 120 and the second semiconductor element 130 overlap when viewed from above. Therefore, with the semiconductor module 2, by using the die pad connector 140, it is possible to connect the first semiconductor element 120 and the second semiconductor element 130 without using other wiring or connectors, and to arrange them three-dimensionally. Accordingly, the semiconductor module 2 is a semiconductor module that can reduce the internal wiring space compared to conventional semiconductor modules.

[0137] Furthermore, in the semiconductor module 2 according to Embodiment 3, the first semiconductor element 120 and the second semiconductor element 130 are connected in a bridge configuration, the first semiconductor element 120 is a high-side element that constitutes the high-side of the bridge connection, and the second semiconductor element 130 is a low-side element that constitutes the low-side of the bridge connection. Therefore, the semiconductor module 2 is a semiconductor module that can be used to configure a bridge circuit.

[0138] Furthermore, the semiconductor module 2 according to Embodiment 3 includes a substrate 110 on which the first semiconductor element 120 is mounted, and the die pad connector 140 has a first semiconductor element side mounting portion 142 mounted on the second electrode 124 of the first semiconductor element 120 and a substrate side mounting portion 144 mounted on the substrate 110. Therefore, the semiconductor module 2 makes it possible to position the die pad connector 140 in a stable state.

[0139] Furthermore, in the semiconductor module 2 according to Embodiment 3, the substrate-side mounting portion 144 is thicker than the first semiconductor element-side mounting portion 142, a planar die pad surface 146 is formed on the die pad connector 140 opposite to the first semiconductor element 120 and the substrate 110, and the second semiconductor element 130 is mounted on the die pad surface 146. Therefore, according to the semiconductor module 2, it is possible to stably position the second semiconductor element 130 on the die pad connector 140.

[0140] Although the present invention (Aspect 2) has been described above based on Embodiments 2 and 3, the present invention (Aspect 2) is not limited to Embodiments 2 and 3. It can be implemented in various forms without departing from its spirit, and for example, the following modifications are also possible.

[0141] (1) The positions, sizes, shapes, etc. of each component described in embodiments 2 and 3 above and shown in each drawing are illustrative examples and can be changed within the scope that does not impair the effects of the present invention (embodiment 2).

[0142] (2) In the above embodiment 2, the semiconductor module 1 is provided with a thermal capacitive connector 50 that connects the fourth electrodes 34a, 34b, and 34c of a plurality of second semiconductor elements 30a, 30b, and 30c to a destination, but the present invention (embodiment 2) is not limited thereto. The semiconductor module may be provided with a plurality of connectors that connect the fourth electrodes of a plurality of second semiconductor elements to a destination, respectively.

[0143] (3) In Embodiment 2 above, the first semiconductor elements 20a, 20b, 20c and the second semiconductor elements 30a, 30b, 30c were diodes, and in Embodiment 3 above, the first semiconductor element 120 and the second semiconductor element 130 were MOSFETs, but the present invention (Aspect 2) is not limited thereto. The semiconductor elements in the semiconductor module of the present invention (Aspect 2) can be changed as appropriate as long as the gist of the present invention (Aspect 2) is not changed, and other semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) and Schottky barrier diodes (especially SiC Schottky barrier diodes) may be used.

[0144] (4) In each of the above embodiments 2, the first semiconductor elements 20a, 20b, 20c, 120 and the second semiconductor elements 30a, 30b, 30c, 130 were vertical semiconductor elements (where the electrodes constituting the main current path are on different faces), but the present invention (Aspect 2) is not limited thereto. The semiconductor elements in the semiconductor module of the present invention (Aspect 2) may be horizontal semiconductor elements (where the electrodes constituting the main current path are on the same face). Examples of horizontal semiconductor elements include horizontal transistor elements (for example, GaN-HEMT composed of GaN-on-Si material, and other Ga ２ O ３ Examples include compound semiconductor transistor devices composed of on-Si materials.

[0145] (5) In each of the above embodiments 2, the first semiconductor elements 20a, 20b, 20c, 120 and the second semiconductor elements 30a, 30b, 30c, 130 were of the same type, but the present invention (Aspect 2) is not limited thereto. The first semiconductor elements and the second semiconductor elements in the semiconductor module of the present invention (Aspect 2) may be of different types.

[0146] (6) In each of the above embodiments 2, the first semiconductor elements 20a, 20b, 20c, and 120 were high-side elements and the second semiconductor elements 30a, 30b, 30c, and 130 were low-side elements, but the present invention (embodiment 2) is not limited thereto. The first semiconductor elements may be low-side elements and the second semiconductor elements may be high-side elements.

[0147] (7) In Embodiment 2 described above, the semiconductor element arrangement direction D3 in circuit element C3 is in a different direction from the semiconductor element arrangement directions D1 and D2 in circuit elements C1 and C2, but the present invention (Embodiment 2) is not limited thereto. The modified semiconductor module 3 basically has the same configuration as the semiconductor module 1 according to Embodiment 2, but the semiconductor element arrangement direction D1 of circuit element C1 is different from that of semiconductor module 1 (see Figure 13). Specifically, in semiconductor module 3, the semiconductor element arrangement direction D1 in circuit element C1 is in the opposite direction to that of semiconductor module 1, so the semiconductor element arrangement direction D2 in circuit element C2 is in a different direction (opposite direction) from the semiconductor element arrangement directions D1 and D3 in circuit elements C1 and C3. Furthermore, in relation to the above differences, semiconductor module 3 includes a substrate 10a having wiring patterns 12a and 14a in different positions and shapes from the wiring patterns 12 and 14 in Embodiment 2 (see Figure 14). Thus, in the semiconductor module of the present invention (Aspect 2), if there are circuit elements with different semiconductor element arrangement directions, any of these circuit elements may be used.

[0148] (8) In addition, in the semiconductor module of the present invention (Aspect 2), the arrangement direction of semiconductor elements in all circuit elements may be the same. In this case, the first semiconductor element and the second semiconductor element may be arranged in a straight line.

[0149] (9) The semiconductor module 1 according to Embodiment 2 comprises a case 70 and a case lid 72, and the semiconductor module 2 according to Embodiment 3 comprises a sealing resin 170, but the present invention (Aspect 2) is not limited thereto. The type and shape of components for protecting the internal structure, such as the case and sealing resin, can be appropriately changed according to the product specifications, etc. Furthermore, the semiconductor module of the present invention (Aspect 2) does not have to include components for protecting the internal structure, such as the case and sealing resin.

[0150] [The Invention (Aspect 3)] [Embodiment 4] The semiconductor module 1 according to Embodiment 4 comprises a substrate 10, first semiconductor elements 20a, 20b, 20c, second semiconductor elements 30a, 30b, 30c, die pad connectors 40a, 40b, 40c, thermal capacitive connector 50, first power terminal 60, second power terminal 62, midpoint terminals 64a, 64b, 64c, case 70, and case cover 72 (see Figures 1 to 4). The semiconductor module 1 may also include components other than those described above. Each component will be described below.

[0151] The first semiconductor elements 20a, 20b, and 20c are mounted on the substrate 10. When simply referring to "mounted," it is not necessary to specify whether the mounted object is electrically connected to the base on which it is mounted. Furthermore, when referring to "mounted," the mounted object and the base on which it is mounted may be in direct contact, or there may be an intervening material between the mounted object and the base on which it is mounted.

[0152] The substrate 10 has wiring patterns 12, 14, 16, and 18 made of conductive material on one side (the side on which the first semiconductor elements 20a, 20b, and 20c are mounted) (see Figure 4). The wiring patterns 12, 14, 16, and 18 will be described later along with other related components.

[0153] In the semiconductor module 1, a DCB (Direct Copper Bonding) substrate can be suitably used as the substrate 10, in which copper wiring patterns 12, 14, 16, and 18 are directly bonded to a base (not shown in reference numerals) made of ceramic (alumina, aluminum nitride, silicon nitride, etc.).

[0154] Furthermore, in the semiconductor module 1, other ceramic substrates such as AMB (Active Metal Brazing) substrates, or metal-based substrates such as copper-based or aluminum-based substrates can be used as the substrate 10. In addition, metal materials other than copper (for example, aluminum) can be used as the material for the wiring patterns 12, 14, 16, and 18.

[0155] The first semiconductor element 20a has a first electrode 22a and a second electrode 24a (see Figures 4 and 5). The first semiconductor elements 20b and 20c also have a first electrode (not shown) and second electrodes 24b and 24c, similar to the first semiconductor element 20a. The first semiconductor elements 20a, 20b, and 20c are mounted on the wiring pattern 12 of the substrate 10. The first electrodes of the first semiconductor elements 20a, 20b, and 20c are connected to the wiring pattern 12 by a conductive bonding material (not shown). For example, solder can be used as the conductive bonding material.

[0156] Furthermore, when simply stating "connection," the objects being connected must be electrically connected (in a state where they can conduct electricity). Also, when stating "connection," the objects being connected may be in direct contact with each other, or there may be an intermediary between them.

[0157] The first semiconductor elements 20a, 20b, and 20c are diodes. In the first semiconductor element 20a, the first electrode 22a is the cathode electrode, and the second electrode 24a is the anode electrode. Similarly to the first semiconductor element 20a, the first electrode of the first semiconductor elements 20b and 20c is the cathode electrode, and the second electrodes 24b and 24c are the anode electrodes.

[0158] The second semiconductor element 30a has a third electrode 32a and a fourth electrode 34a (see Figures 3 and 5). The second semiconductor elements 30b and 30c also have a third electrode (not shown) and fourth electrodes 34b and 34c, similar to the second semiconductor element 30a.

[0159] The second semiconductor elements 30a, 30b, and 30c are diodes. In the second semiconductor element 30a, the third electrode 32a is the cathode electrode, and the fourth electrode 34a is the anode electrode. Similarly to the second semiconductor element 30a, the third electrode of the second semiconductor elements 30b and 30c is the cathode electrode, and the fourth electrodes 34b and 34c are the anode electrodes.

[0160] When viewed from above, the first semiconductor elements 20a, 20b, 20c and the second semiconductor elements 30a, 30b, 30c are arranged non-linearly. In this specification, "arranged non-linearly" means that when viewed from above, the centers of gravity of the semiconductor elements are not on a straight line. In the semiconductor module 1, the first semiconductor element 20c and the second semiconductor element 30c are arranged outside the arrangement of the first semiconductor elements 20a, 20b and the arrangement of the second semiconductor elements 30a, 30b, respectively.

[0161] The first semiconductor element 20a and the second semiconductor element 30a are connected in a bridge configuration. The first semiconductor element 20a is the high-side element that constitutes the high-side of the bridge connection, and the second semiconductor element 30a is the low-side element that constitutes the low-side of the bridge connection. The relationship between the first semiconductor element 20b and the second semiconductor element 30b, and the relationship between the first semiconductor element 20c and the second semiconductor element 30c are the same as the relationship between the first semiconductor element 20a and the second semiconductor element 30a described above. For this reason, the semiconductor module 1 is a so-called three-phase bridge diode module.

[0162] In this specification, "bridge connection" means that the first semiconductor element and the second semiconductor element are connected such that they can form the main current path of a bridge circuit and constitute the high-side and low-side of the bridge circuit. In this case, "bridge circuit" also includes those that require components other than semiconductor modules.

[0163] In semiconductor module 1, the "inter-semiconductor element connectors that directly or indirectly connect the second electrode and the third electrode" are die pad connectors 40a, 40b, and 40c. Die pad connector 40a connects the second electrode 24a and the third electrode 32a (see Figure 5). Die pad connector 40a is a structure made of a conductive material.

[0164] At least a portion (all in the case of semiconductor module 1) of the third electrode 32a of the second semiconductor element 30a is mounted on the die pad connector 40a. Also, at least a portion (part in the case of semiconductor module 1) of the die pad connector 40a is mounted on the second electrode 24a of the first semiconductor element 20a. A conductive bonding material 80 is interposed between the die pad connector 40a and the second electrode 24a. Although not shown in the figures, a conductive bonding material is also interposed between the third electrode 32a and the die pad connector 40a.

[0165] Furthermore, the first semiconductor element 20a and the second semiconductor element 30a are arranged such that at least a portion of them overlap when viewed from above (see Figures 3(b) and 5(b)). Also, the first semiconductor element 20a and the second semiconductor element 30a are arranged such that they do not completely overlap when viewed from above.

[0166] The die pad connector 40a has a first semiconductor element-side mounting portion 42a that is mounted on the second electrode 24a of the first semiconductor element 20a, and a substrate-side mounting portion 44a that is mounted on the substrate 10 (see Figure 5). The substrate-side mounting portion 44a is thicker than the first semiconductor element-side mounting portion 42a.

[0167] The substrate-side mounting portion 44a is mounted on the wiring pattern 14 of the substrate 10. The wiring pattern 14 is an isolated wiring pattern that is not connected to any components other than the substrate-side mounting portion 44a. A planar die pad surface 46a is formed on the side of the die pad connector 40a that is opposite to the first semiconductor element 20a and the substrate 10. The second semiconductor element 30a is mounted on the die pad surface 46a.

[0168] Although the individual figures and reference numerals are omitted, the die pad connectors 40b and 40c also have a structure corresponding to the structure of the die pad connector 40a described above. Furthermore, the first semiconductor elements 20b and 20c, the second semiconductor elements 30b and 30c, and the die pad connectors 40b and 40c also have a positional relationship corresponding to the positional relationship of the first semiconductor element 20a, the second semiconductor element 30a, and the die pad connector 40a described above.

[0169] The semiconductor module 1 comprises a plurality of circuit elements, each consisting of a combination of a first semiconductor element, a second semiconductor element, and a die pad connector. Specifically, the semiconductor module 1 comprises three circuit elements C1, C2, and C3. Circuit element C1 consists of a combination of a first semiconductor element 20a, a second semiconductor element 30a, and a die pad connector 40a. Circuit element C2 consists of a combination of a first semiconductor element 20b, a second semiconductor element 30b, and a die pad connector 40b. Circuit element C3 consists of a combination of a first semiconductor element 20c, a second semiconductor element 30c, and a die pad connector 40c.

[0170] Here, the direction from the first semiconductor element to the second semiconductor element when viewed from above is defined as the semiconductor element arrangement direction. The semiconductor element arrangement direction D3 in at least one of the multiple circuit elements C1, C2, and C3 (in this case, circuit element C3) is different from the semiconductor element arrangement direction D2 in the adjacent circuit element (in this case, circuit element C2) (see Figure 3). Note that the above "different direction" is in opposite directions. Also, the semiconductor element arrangement direction D1 in circuit element C1 is the same direction as the semiconductor element arrangement direction D2 in circuit element C2.

[0171] The thermal capacitive connector 50 connects the fourth electrodes 34a, 34b, and 34c of multiple second semiconductor elements 30a, 30b, and 30c to a destination. The destination of the thermal capacitive connector 50 is the substrate 10.

[0172] The heat-capacitive connector 50 has a head portion 52 connected to a plurality of fourth electrodes 34a, 34b, and 34c, and a tail portion 56 that protrudes from the head portion 52 and whose tip is connected to the substrate 10. The heat-capacitive connector 50 has a plurality of tail portions 56. The tail portions 56 are connected to the region 17a of the wiring pattern 16 on the substrate 10.

[0173] Furthermore, the heat-capacitive connector 50 protrudes from the head portion 52, its tip rests on the substrate 10, and it further has a heat-dissipating tail portion 58 that does not constitute part of the main current path. The heat-dissipating tail portion 58 is connected to the wiring pattern 18 on the substrate 10. The wiring pattern 18 is an isolated wiring pattern that is not connected to any components other than the heat-dissipating tail portion 58.

[0174] The head portion 52 covers the multiple fourth electrodes 34a, 34b, and 34c when viewed from above. The head portion 52 also has electrode mounting portions 53a, 53b, and 53c that are placed on the multiple fourth electrodes 34a, 34b, and 34c, and a heat capacity securing portion 54 that extends to the outer edges of the electrode mounting portions 53a, 53b, and 53c.

[0175] Furthermore, the head portion 52 does not need to completely cover the multiple fourth electrodes 34a, 34b, and 34c without any gaps; it is sufficient if it covers most of them (for example, 80% or more).

[0176] The first power terminal 60 is a terminal that electrically connects the first electrodes of the first semiconductor elements 20a, 20b, and 20c to the outside. The first power terminal 60 is connected to a region 13 of the wiring pattern 12 on the substrate 10 and is connected to the first electrodes of the first semiconductor elements 20a, 20b, and 20c via the wiring pattern 12.

[0177] The second power terminal 62 is a terminal that electrically connects the fourth electrodes 34a, 34b, and 34c of the second semiconductor elements 30a, 30b, and 30c to the outside. The second power terminal 62 is connected to the region 17b of the wiring pattern 16 on the substrate 10, and is connected to the fourth electrodes 34a, 34b, and 34c of the second semiconductor elements 30a, 30b, and 30c via the wiring pattern 16 and the thermal capacitance connector 50.

[0178] The center terminal 64a is a terminal that electrically connects the die pad connector 40a (the current path between the first semiconductor element 20a and the second semiconductor element 30a) to the outside. The center terminal 64b is a terminal that electrically connects the die pad connector 40b (the current path between the first semiconductor element 20b and the second semiconductor element 30b) to the outside. The center terminal 64c is a terminal that electrically connects the die pad connector 40c (the current path between the first semiconductor element 20c and the second semiconductor element 30c) to the outside.

[0179] The center terminal 64a is connected to area 41a of the die pad connector 40a. The center terminal 64b is connected to area 41b of the die pad connector 40b. The center terminal 64b is connected to area 41c of the die pad connector 40b.

[0180] The case 70 is for housing the main components of the semiconductor module 1. The case lid 72 is the lid of the case 70. Although not shown in the illustration, the back surface of the substrate 10 (the surface opposite to the surface on which the wiring patterns 12, 14, 16, and 18 are located) is exposed to the outside of the case 70. The case lid 72 also has holes formed therein for passing the first power terminal 60, the second power terminal 62, and the center terminals 64a, 64b, and 64c.

[0181] In the semiconductor module 1 according to Embodiment 4, the semiconductor element arrangement direction D3 in at least one circuit element (circuit element C3) among the plurality of circuit elements C1, C2, and C3 is in a different direction from the semiconductor element arrangement direction D2 in the adjacent circuit element (circuit element C2). Therefore, according to the semiconductor module 1, it is possible to suppress thermal interference between adjacent semiconductor elements by shifting the arrangement of the semiconductor elements. As a result, the semiconductor module 1 is a semiconductor module that can improve heat dissipation compared to conventional semiconductor modules.

[0182] Furthermore, according to the semiconductor module 1 of Embodiment 4, since the different directions are opposite directions, it is possible to improve heat dissipation without increasing the internal wiring space.

[0183] Furthermore, in the semiconductor module 1 according to Embodiment 4, three or more circuit elements are provided (circuit elements C1, C2, C3 are provided), and when viewed from above, the first semiconductor elements 20a, 20b, 20c and the second semiconductor elements 30a, 30b, 30c are arranged in a non-linear manner. Therefore, the semiconductor module 1 makes it possible to further suppress thermal interference and further improve heat dissipation.

[0184] Furthermore, in the semiconductor module 1 according to Embodiment 4, the semiconductor element connectors are die pad connectors 40a, 40b, and 40c that directly connect the second electrode and the third electrode. In the semiconductor module 1, at least a portion of the die pad connectors 40a, 40b, and 40c is placed on the second electrode of the first semiconductor element 20a, 20b, and 20c, and at least a portion of the third electrode of the second semiconductor element 30a, 30b, and 30c is placed on the die pad connectors 40a, 40b, and 40c. In addition, in the semiconductor module 1, the first semiconductor element 20a, 20b, and 20c and the second semiconductor element 30a, 30b, and 30c are arranged so that they do not overlap when viewed from above. Therefore, with semiconductor module 1, by using die pad connectors 40a, 40b, and 40c, the first semiconductor elements 20a, 20b, and 20c and the second semiconductor elements 30a, 30b, and 30c can be connected without other wiring or connectors and arranged three-dimensionally. Consequently, semiconductor module 1 is a semiconductor module that can reduce the internal wiring space compared to conventional semiconductor modules.

[0185] Furthermore, according to the semiconductor module 1 of Embodiment 4, the first semiconductor elements 20a, 20b, 20c and the second semiconductor elements 30a, 30b, 30c are arranged so that they partially overlap when viewed from above, which makes it possible to further reduce the internal wiring space.

[0186] Furthermore, the semiconductor module 1 according to Embodiment 4 includes a thermal capacitive connector 50 that connects the fourth electrodes 34a, 34b, and 34c of a plurality of second semiconductor elements 30a, 30b, and 30c to a destination. Therefore, with the semiconductor module 1, by using the thermal capacitive connector 50 to connect a plurality of electrodes (fourth electrodes 34a, 34b, and 34c), integration and high density are made easier compared to conventional semiconductor modules.

[0187] Furthermore, in the semiconductor module 1 according to Embodiment 4, since multiple electrodes (fourth electrodes 34a, 34b, 34c) are connected together with a thermal capacitive connector 50, it is easy to make the thermal capacitive connector 50 larger than conventional connectors (for example, connectors 950a, 950b, 950c of semiconductor module 900). Therefore, with semiconductor module 1, it is possible to improve thermal conductivity and heat dissipation compared to conventional semiconductor modules.

[0188] Furthermore, in the semiconductor module 1 according to Embodiment 4, the first semiconductor elements 20a, 20b, and 20c and the second semiconductor elements 30a, 30b, and 30c are connected in a bridge configuration. The first semiconductor elements 20a, 20b, and 20c are high-side elements that constitute the high-side of the bridge connection, and the second semiconductor elements 30a, 30b, and 30c are low-side elements that constitute the low-side of the bridge connection. Therefore, the semiconductor module 1 is a semiconductor module that can be used to configure a bridge circuit.

[0189] [Embodiment 5] The semiconductor module 3 according to Embodiment 5 basically has the same configuration as the semiconductor module 1 according to Embodiment 4, but the semiconductor element arrangement direction D1 of the circuit element C1 is different from that of the semiconductor module 1 (see Figure 13). Specifically, in the semiconductor module 3, the semiconductor element arrangement direction D1 in the circuit element C1 is in the opposite direction to that of the semiconductor module 1, so the semiconductor element arrangement direction D2 in the circuit element C2 is in a different direction (opposite direction) from the semiconductor element arrangement directions D1 and D3 in the circuit elements C1 and C3. In addition, related to the above differences, the semiconductor module 3 is equipped with a substrate 10a having wiring patterns 12a and 14a in different positions and shapes from the wiring patterns 12 and 14 in Embodiment 4 (see Figure 14).

[0190] As described above, the semiconductor module 3 according to Embodiment 5 differs from the semiconductor module 1 in the semiconductor element arrangement direction D1 of the circuit element C1. However, in the semiconductor module 3, the semiconductor element arrangement direction D2 of at least one circuit element (circuit element C2) among the multiple circuit elements C1, C2, and C3 is in a different direction from the semiconductor element arrangement directions D1 and D3 of adjacent circuit elements (circuit elements C1 and C3). Therefore, with the semiconductor module 3, as with the semiconductor module 1, it is possible to suppress thermal interference between adjacent semiconductor elements by shifting the arrangement of the semiconductor elements. As a result, the semiconductor module 3, as with the semiconductor module 1, is a semiconductor module that can improve heat dissipation compared to conventional semiconductor modules.

[0191] Furthermore, since the semiconductor module 3 according to Embodiment 5 has basically the same configuration as the semiconductor module 1 according to Embodiment 4, it has the same effects as the semiconductor module 1 according to Embodiment 4.

[0192] Although the present invention (Aspect 3) has been described above based on Embodiments 4 and 5, the present invention (Aspect 3) is not limited to Embodiments 4 and 5. It can be implemented in various forms without departing from its spirit, and for example, the following modifications are also possible.

[0193] (1) The positions, sizes, shapes, etc. of the components described in embodiments 4 and 5 above and shown in each drawing are illustrative examples and can be changed within the scope that does not impair the effects of the present invention (embodiment 3).

[0194] For example, in embodiments 4 and 5 described above, the semiconductor modules 1 and 3 are equipped with three circuit elements C1, C2, and C3, but the present invention (embodiment 3) is not limited thereto. The number of circuit elements may be two, or four or more.

[0195] (2) In embodiments 4 and 5 described above, the semiconductor modules 1 and 3 are provided with a thermal capacitive connector 50 (not shown in Figures 13 and 14 relating to embodiment 5) that connects the fourth electrodes 34a, 34b, and 34c of a plurality of second semiconductor elements 30a, 30b, and 30c to a destination. However, the present invention (embodiment 3) is not limited thereto. The semiconductor module may be provided with a plurality of connectors that connect the fourth electrodes of a plurality of second semiconductor elements to a destination.

[0196] (3) In embodiments 4 and 5 described above, the first semiconductor elements 20a, 20b, 20c and the second semiconductor elements 30a, 30b, 30c were diodes, but the present invention (Aspect 3) is not limited thereto. The semiconductor elements in the semiconductor module of the present invention (Aspect 3) can be changed as appropriate as long as the gist of the present invention (Aspect 3) is not altered, and may be other semiconductor elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), or Schottky barrier diodes (especially SiC Schottky barrier diodes).

[0197] (4) In embodiments 4 and 5 described above, the first semiconductor elements 20a, 20b, 20c and the second semiconductor elements 30a, 30b, 30c were vertical semiconductor elements (where the electrodes constituting the main current path are on different faces), but the present invention (Aspect 3) is not limited thereto. The semiconductor elements in the semiconductor module of the present invention (Aspect 3) may be horizontal semiconductor elements (where the electrodes constituting the main current path are on the same face). Examples of horizontal semiconductor elements include horizontal transistor elements (for example, GaN-HEMT composed of GaN-on-Si material, and other Ga ２ O ３ Examples include compound semiconductor transistor devices composed of on-Si materials.

[0198] (5) In embodiments 4 and 5 described above, the first semiconductor elements 20a, 20b, and 20c and the second semiconductor elements 30a, 30b, and 30c were of the same type, but the present invention (Aspect 3) is not limited thereto. The first semiconductor elements and the second semiconductor elements in the semiconductor module of the present invention (Aspect 3) may be of different types.

[0199] (6) In embodiments 4 and 5 described above, the first semiconductor elements 20a, 20b, and 20c were high-side elements and the second semiconductor elements 30a, 30b, and 30c were low-side elements, but the present invention (embodiment 3) is not limited thereto. The first semiconductor element may be a low-side element and the second semiconductor element may be a high-side element.

[0200] (7) In embodiments 4 and 5 described above, the semiconductor element connectors were die pad connectors 40a, 40b, and 40c that connect the second electrode and the third electrode, but the present invention (Aspect 3) is not limited thereto. The semiconductor element connectors in the semiconductor module of the present invention (Aspect 3) may be those that connect the second electrode and the third electrode via a substrate (wiring pattern) (for example, connectors such as the connectors 940a, 940b, and 940c in Figure 9).

[0201] (8) The semiconductor module 1 according to the above embodiments 4 and 5 includes a case 70 and a case cover 72, but the present invention (embodiment 3) is not limited thereto. The type and shape of components for protecting the internal structure, such as the case and sealing resin, can be appropriately changed according to the product specifications, etc. Furthermore, the semiconductor module of the present invention (embodiment 3) does not need to include components for protecting the internal structure, such as the case and sealing resin.

[0202] 1, 2, 3... Semiconductor module, 10, 10a, 110... Substrate, 20a, 20b, 20c, 120... First semiconductor element, 22a, 122... First electrode, 24a, 24b, 24c, 124... Second electrode, 30a, 30b, 30c, 130... Second semiconductor element, 32a, 132... Third electrode, 34a, 34b, 34c, 134... Fourth electrode, 40a, 40b, 40c, 140... Die pad connector, 42a, 142... First semiconductor element side mounting section, 44a, 144... Substrate side mounting section, 46a, 146... Die pad surface, 50... Thermal capacitance connector, C, C1, C2, C3... Circuit element, D1, D2, D3... Semiconductor element arrangement direction

Claims

1. A semiconductor module characterized by comprising a plurality of semiconductor elements, each having a plurality of electrodes and connected in parallel, and a thermal capacitive connector that connects electrodes of the same type from the plurality of semiconductor elements to a destination.

2. The semiconductor module according to claim 1, wherein the plurality of semiconductor elements are composed of at least three of the semiconductor elements, and the thermal capacitive connector connects at least three of the same type of electrodes to the connection destination.

3. The semiconductor module according to claim 1 or 2, characterized in that the semiconductor elements constituting the plurality of semiconductor elements are low-side elements constituting the low-side of the bridge connection.

4. The semiconductor module according to any one of claims 1 to 3, further comprising a substrate, wherein the connection destination of the thermal capacitive connector is the substrate.

5. The semiconductor module according to claim 4, characterized in that the thermal capacitive connector has a head portion connected to the same type of electrode in the plurality of semiconductor elements, and a tail portion protruding from the head portion and having its tip connected to the substrate.

6. The semiconductor module according to claim 5, wherein the thermal capacitance connector further has a heat dissipation tail portion that protrudes from the head portion, has its tip resting on the substrate, and does not constitute part of the main current path.

7. The semiconductor module according to claim 5 or 6, characterized in that the head portion covers the electrodes of the same type when viewed from above.

8. The semiconductor module according to claim 7, characterized in that the head portion has an electrode mounting portion that is placed on the electrode of the same type and a heat capacity securing portion that extends to the outer edge of the electrode mounting portion.

9. A semiconductor module comprising: a first semiconductor element having a first electrode and a second electrode; a second semiconductor element having a third electrode and a fourth electrode; and a die pad connector connecting the second electrode and the third electrode, wherein at least a portion of the die pad connector is placed on the second electrode of the first semiconductor element, at least a portion of the third electrode of the second semiconductor element is placed on the die pad connector, and the first semiconductor element and the second semiconductor element are arranged such that at least a portion of them overlap when viewed from above.

10. The semiconductor module according to claim 9, characterized in that the first semiconductor element and the second semiconductor element are connected in a bridge, the first semiconductor element is a high-side element constituting the high-side of the bridge connection, and the second semiconductor element is a low-side element constituting the low-side of the bridge connection.

11. The semiconductor module according to claim 9 or 10, further comprising a substrate on which the first semiconductor element is mounted, wherein the die pad connector has a first semiconductor element side mounting portion mounted on the second electrode of the first semiconductor element and a substrate side mounting portion mounted on the substrate.

12. The semiconductor module according to claim 11, characterized in that the substrate-side mounting portion is thicker than the first semiconductor element-side mounting portion, a planar die pad surface is formed on the side of the die pad connector opposite to the first semiconductor element and the substrate, and the second semiconductor element is mounted on the die pad surface.

13. The semiconductor module according to any one of 9 to 12, characterized in that the semiconductor module comprises a plurality of circuit elements consisting of a combination of the first semiconductor element, the second semiconductor element, and the die pad connector.

14. The semiconductor module according to claim 13, further comprising a thermal capacitive connector for collectively connecting the fourth electrodes of a plurality of the second semiconductor elements to a connection destination.

15. A semiconductor module comprising a first semiconductor element having a first electrode and a second electrode, a second semiconductor element having a third electrode and a fourth electrode, and an inter-semiconductor element connector that directly or indirectly connects the second electrode and the third electrode, wherein the semiconductor module comprises a plurality of circuit elements consisting of combinations of the first semiconductor element, the second semiconductor element, and the inter-semiconductor element connector, and when the direction from the first semiconductor element to the second semiconductor element in a plan view is defined as the semiconductor element arrangement direction, the semiconductor element arrangement direction in at least one of the plurality of circuit elements is different from the semiconductor element arrangement direction in adjacent circuit elements.

16. The semiconductor module according to claim 15, characterized in that the different directions are opposite directions.

17. The semiconductor module according to claim 15 or 16, wherein the semiconductor module comprises three or more of the circuit elements, and when viewed from a plan view, the first semiconductor element and the second semiconductor element are each arranged in a non-linear manner.

18. The semiconductor module according to any one of claims 15 to 17, wherein the semiconductor element connector is a die pad connector connecting the second electrode and the third electrode, at least a portion of the die pad connector is placed on the second electrode of the first semiconductor element, at least a portion of the third electrode of the second semiconductor element is placed on the die pad connector, and the first semiconductor element and the second semiconductor element are arranged such that they do not overlap when viewed from above.

19. The semiconductor module according to claim 18, characterized in that the first semiconductor element and the second semiconductor element are arranged such that they partially overlap when viewed from above.

20. The semiconductor module according to claim 18 or 19, further comprising a thermal capacitive connector for collectively connecting the fourth electrodes of a plurality of the second semiconductor elements to a connection destination.

21. The semiconductor module according to any one of claims 15 to 20, characterized in that the first semiconductor element and the second semiconductor element are connected in a bridge, the first semiconductor element is a high-side element constituting the high-side of the bridge connection, and the second semiconductor element is a low-side element constituting the low-side of the bridge connection.

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