Selection device and selection method

Abstract

This selection device (100) is a selection device connected to a plurality of processors (for example, targets (210, 220, and 230)) and a debugger (for example, a host (400)) that executes debugging of the plurality of processors, the debugger being multidrop-connected to the plurality of processors, and comprises: a selection circuit (120) having a plurality of connection units (for example, connection terminals (121, 122, and 123)) connected to the plurality of processors on a one-to-one basis; and a switching circuit (170) that acquires number information indicating any of the connection destinations of the plurality of connection units, and causes the selection circuit (120) to output, to the debugger, only data input from a connection unit connected to the connection destination indicated by the number information among one or more pieces of data input from one or more connection units among the plurality of connection units.

Description

Selection apparatus and selection method

[0001] The present disclosure relates to a selection apparatus and a selection method.

[0002] Conventionally, there are systems that debug a plurality of processors. Patent Document 1 discloses a system in which a debugger performs debugging of a plurality of cores included in a multiprocessor. The plurality of cores disclosed in Patent Document 1 are connected in a ring shape.

[0003] Japanese Unexamined Patent Publication No. 2018-88048

[0004] A debugger that debugs a plurality of processors arranged on one chip may be connected to the plurality of processors via a multi-drop connection. Even in such a connection configuration, it is desired that the debugger can properly debug the plurality of processors.

[0005] The present disclosure provides a selection apparatus and the like that can reduce the possibility that a debugger cannot appropriately execute debugging of a processor.

[0006] A selection apparatus according to an aspect of the present disclosure is a selection apparatus connected to a plurality of processors and a debugger that executes debugging of the plurality of processors, the debugger being multi-drop connected to the plurality of processors, the selection apparatus comprising: a selection circuit having a plurality of connection portions connected one-to-one to the plurality of processors; and a switching circuit that acquires number information indicating a connection destination of any one of the plurality of connection portions, and causes the selection circuit to output, to the debugger, only data input from the connection portion connected to the connection destination indicated by the number information among one or more pieces of data input from one or more connection portions among the plurality of connection portions.

[0007] A selection method according to one aspect of the present disclosure is a selection method performed by a selection device connected to a debugger that performs debugging of a plurality of processors and is multidrop-connected to the plurality of processors, wherein the selection device obtains number information indicating the connection destination of one of a plurality of connection parts that are connected one-to-one with the plurality of processors, and causes the selection circuit having the plurality of connection parts to output to the debugger only the data input from the connection part connected to the connection destination indicated by the number information, out of the one or more data input from one or more connection parts among the plurality of connection parts.

[0008] According to one aspect of this disclosure, the selection device, etc., can reduce the possibility that the debugger may not be able to properly debug the processor.

[0009] Figure 1 is a block diagram illustrating the configuration of a debugging system according to an embodiment. Figure 2 is a diagram illustrating the debugging interface provided by the host according to an embodiment. Figure 3 is a diagram illustrating the debugging interface provided by the target according to an embodiment. Figure 4 is a sequence diagram showing a first example of the processing procedure of the debugging system according to an embodiment. Figure 5 is a sequence diagram showing a second example of the processing procedure of the debugging system according to an embodiment. Figure 6 is a flowchart illustrating a specific example of the processing procedure of the selection device according to an embodiment. Figure 7 is a flowchart illustrating the selection method according to an embodiment.

[0010] (Background to this disclosure) In recent years, with the development of wearable devices, there has been an increasing demand for smaller and thinner devices. In addition, systems are becoming more complex, and the number of LSIs (Large Scale Integrations) equipped with multiple processors such as CPUs (Central Processing Units) has been increasing in recent years.

[0011] Such processors have an interface (access port) for debugging. One example of such an interface (also called a debug interface) is JTAG (Joint Test Action Group). Another example of a debug interface is SWD (Serial Wire Debug).

[0012] SWD is an interface that employs a serial communication method with fewer pins compared to JTAG, while retaining the same debugging capabilities as JTAG. Because SWD has fewer pins than JTAG, it can be expected to have a smaller footprint (i.e., be more compact) compared to LSIs that use JTAG.

[0013] As a connection method for SWD, a multidrop connection (multidrop connection method) is defined, which connects to multiple processors. This makes it possible to debug multiple processors on an LSI without increasing the number of pins on the LSI.

[0014] In SWD, multidrop connectivity facilitates processor design and verification, and offers greater flexibility in terms of memory map configuration and per-core debugging connection control.

[0015] However, the SWD multidrop connection specification does not include a way to avoid race conditions that occur when multiple processors respond simultaneously due to unexpected failures such as noise (e.g., abnormalities in the debugging path).

[0016] Therefore, the inventors of the present invention came to create the present invention.

[0017] Specifically, this invention makes it easier to establish a connection (debug access) between any processor (specifically, a processor core) and a debugger in a multiprocessor system, even when a multi-drop connection of SWDs within the LSI is employed, even if a failure occurs. Furthermore, for example, this invention implements an anomaly monitoring function for detecting a failed processor.

[0018] The term "failure" here refers to, for example, unexpected failures due to noise, insufficient output care during power outages, the same identifier being assigned to two or more processors, the presence of processors that do not support multidrop connections, the presence of severely noisy wiring to processors, or the presence of processors that behave in other unexpected ways.

[0019] The embodiments will be described in detail below with reference to the drawings.

[0020] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit this disclosure. Furthermore, any components in the following embodiments that are not described in the independent claims of this disclosure will be described as optional components.

[0021] Furthermore, ordinal numbers such as "first," "second," etc., unless otherwise specified, do not indicate the number or order of components, but are used to avoid confusion and distinguish similar components.

[0022] (Embodiment) [Configuration] Figure 1 is a block diagram showing the configuration of the debugging system 10 according to the embodiment.

[0023] The debugging system 10 is a system for debugging multiple processors (specifically, programs executed by multiple processor cores). In this embodiment, the debugging system 10 comprises a host 400 and an LSI 300, and the host 400 performs debugging of n targets provided by the LSI 300. Note that n can be 2 or more. In this embodiment, the LSI 300 has three targets: targets 210, 220, and 230. The host 400 performs debugging of targets 210, 220, and 230 provided by the LSI 300.

[0024] The host 400 is a computer that performs debugging. The host 400 is implemented, for example, by including non-volatile memory where the program is stored, volatile memory which is a temporary storage area for executing the program, and a processor that executes the program. The host 400 also includes a debug interface for performing debugging of targets 210, 220, and 230 provided by the LSI 300.

[0025] Figure 2 is a diagram illustrating the debug interface provided by the host 400 according to the embodiment.

[0026] For example, the host 400 has a debug interface that has a port for communicating a clock signal (CLK shown in Figure 2) for synchronizing with targets 210, 220, and 230, and a port for communicating data (DIO shown in Figure 2) for performing debugging. The debug interface of the host 400 is serially connected to, for example, a port 310 of the LSI 300. This enables serial communication between the host 400 and the LSI 300.

[0027] Note that host 400 is an example of a debugger.

[0028] Although not shown in the diagram, the clock generator may be implemented using any components.

[0029] LSI 300 is an LSI comprising multiple processors that are subject to debugging by the host 400. LSI 300 is implemented, for example, on a single chip (i.e., a single semiconductor substrate). LSI 300 comprises a selection device 100, registers 150 and 160, targets 210, 220 and 230, a CPU 240, and a port section 310. The selection device 100, registers 150 and 160, targets 210, 220 and 230, CPU 240, and port section 310 are all provided on a single chip. That is, for example, the selection circuit 120 and targets 210, 220 and 230 are provided on a single chip.

[0030] Registers 150 and 160 are registers that hold (store) information, respectively. Register 150 is connected to targets 210, 220, and 230, as well as the CPU 240, via the bus 320. Registers 150 and 160 are also connected to the switching circuit 170, respectively. Registers 150 and 160 are implemented, for example, by latch circuits, but may be implemented with any configuration, such as flip-flop circuits. The information held in registers 150 and 160 will be described later.

[0031] Note that register 150 is an example of a first holding circuit.

[0032] Bus 320 is a bus (more specifically, a memory bus) that connects register 150 to targets 210, 220, and 230, as well as CPU 240.

[0033] Targets 210, 220, and 230 are, respectively, processors (specifically, CPU processor cores) that are subject to debugging by the host 400. Targets 210, 220, and 230 each have a debug interface for the host 400 to debug targets 210, 220, and 230.

[0034] Figure 3 is a diagram illustrating the debug interface provided by the target 200 according to the embodiment.

[0035] Targets 210, 220, and 230 have a configuration similar to the debug interface provided by target 200 shown in Figure 3. In the following, descriptions common to targets 210, 220, and 230 may be described as referring to target 200.

[0036] The target 200 includes a debug interface that includes, for example, a port for communicating a clock signal to synchronize with the host 400, a port for inputting data from the host 400 (DI shown in Figure 3), a port for outputting data to the host 400 (DO shown in Figure 3), and a debug access port for outputting an enable signal (EN shown in Figure 3). The data and enable signal output from the target 200 are output to the host 400 via the selection device 100 and the port unit 310.

[0037] Host 400 is connected via multidrop to targets 210, 220, and 230. Therefore, data output by host 400 is input to targets 210, 220, and 230, respectively. For example, the data output by host 400 includes a target ID (Identified). The target ID is information that identifies one of targets 210, 220, or 230. Targets 210, 220, and 230 each store a target ID that identifies themselves, and based on the acquired target ID, if the target indicated by that target ID is their own target, they output data and an enable signal corresponding to the acquired data to host 400. If the target indicated by that target ID is not their own target, they do not output data or an enable signal to host 400.

[0038] Through this process, when the host 400 debugs any of targets 210, 220, or 230, for example, it outputs data containing a target ID indicating the target to be debugged, thereby establishing one-to-one communication with a single target and executing the debug.

[0039] CPU 240 is a processor that is not subject to debugging performed by host 400. CPU 240 may or may not be connected to host 400.

[0040] The port unit 310 is a port that is serially connected to the host 400. The port unit 310 has two ports, for example, one for communicating a clock signal and another for communicating data. The data and enable signal output from the target 200 are output to the host 400 from the data communication port of the port unit 310, for example. Specifically, the data input to the selection circuit 120 from the target 210, 220, or 230 is output to the host 400 from the data communication port, only when the host 400 is not using a data line, after a switch is switched using the enable signal to prevent input and output conflicts in the host 400.

[0041] The selection device 100 is an electronic circuit connected to the host 400 and the targets 210, 220, and 230. Specifically, the selection device 100 is connected to the targets 210, 220, and 230 by separate buses, and outputs data and enable signals output from the targets 210, 220, and 230 to the host 400 via the port section 310. The selection device 100 is also connected to the registers 150 and 160 via a bus. The selection device 100 comprises a register 110, a selection circuit 120, and a switching circuit 170.

[0042] Register 110 is a register that holds a target ID (also called a first target ID) that indicates one of targets 210, 220, and 230. Specifically, register 110 obtains and holds a target ID that indicates one of targets 210, 220, and 230 from the host 400. Register 110 is an example of a second holding circuit. The target ID is an example of identification information. Register 110 can be implemented, for example, with a latch circuit, but it may be implemented with any configuration such as a flip-flop circuit.

[0043] For example, the register 110 holds a target ID included in data output from the host 400 to the targets 210, 220, and 230. For example, when the host 400 starts debugging any one of the targets 210, 220, and 230, it first outputs the target ID and a request (also referred to as a debug request). For example, the register 110 latches the target ID output at this time. Note that the request is an example of data output by the host 400.

[0044] Note that the LSI 300 may be provided with a port for accepting input of the target ID to the register 110. The port is connected to, for example, the register 110 and an external computer. The external computer causes the register 110 to hold the target ID by outputting the target ID to the register 110, for example. Accordingly, the register 110 may hold the target ID. Note that the external computer may be the host 400 or may not be the host 400.

[0045] The selection circuit 120 is an electronic circuit that outputs, to the host 400, data output by the targets 210, 220, and 230. The selection circuit 120 includes, for example, connection terminals 121, 122, and 123. The connection terminal 121 is a terminal connected one-to-one with the target 210. The connection terminal 122 is a terminal connected one-to-one with the target 220. The connection terminal 123 is a terminal connected one-to-one with the target 230. As described above, the connection terminals 121, 122, and 123 are connected one-to-one with the targets 210, 220, and 230.

[0046] Data output from the target 210, which is the connection destination of the connection terminal 121, is input from the connection terminal 121, in other words, via the connection terminal 121, to the selection circuit 120. Data output from the target 220, which is the connection destination of the connection terminal 122, is input from the connection terminal 122, in other words, via the connection terminal 122, to the selection circuit 120. Data output from the target 230, which is the connection destination of the connection terminal 123, is input from the connection terminal 123, in other words, via the connection terminal 123, to the selection circuit 120.

[0047] For example, the selection circuit 120 outputs, to the host 400, an acknowledgment and an enable signal that are responses to a request output from the targets 210, 220, and 230. The acknowledgment and the enable signal are an example of data output by the targets 210, 220, and 230. Furthermore, the connection terminals 121, 122, and 123 are an example of a connection unit.

[0048] As described above, normally, when the target indicated by a target ID is the own target, the targets 210, 220, and 230 output an acknowledgment to the host 400, and when the target indicated by the target ID is not the own target, the targets 210, 220, and 230 do not output an acknowledgment to the host 400. That is, even if a request is output to the targets 210, 220, and 230, normally only any one of the targets 210, 220, and 230 outputs an acknowledgment.

[0049] Here, let's assume that an abnormality (failure) has occurred in at least one of targets 210, 220, and 230. Examples of abnormalities include unexpected failures due to noise, etc. Another example of an abnormality is that the same target ID has been incorrectly assigned to two or more targets. Another example of an abnormality is that an error occurred in fixing the output value when the power was cut off in at least one of targets 210, 220, and 230. Another example of an abnormality is that at least one of targets 210, 220, and 230 includes a target that operates on a standard that does not support multidrop connections. Another example of an abnormality is that an unexpected failure has occurred in at least one of targets 210, 220, and 230. When such abnormalities occur, there is a possibility that unintended targets, that is, targets other than the target indicated by the target ID, may also output an ACK to the host 400. In such cases, the host 400 may not be able to debug properly.

[0050] Therefore, if a race condition occurs in which, for example, two or more of the multiple targets 200 simultaneously output an ACK in response to a request output by the host 400 for debugging, the selection circuit 120 outputs only one ACK to the host 400. In this way, the selection circuit 120 outputs only the data output from one of the targets 210, 220, and 230 (e.g., ACKs and enable signals) to the host 400. More specifically, the selection circuit 120 outputs only the single data output from one of the one or more data outputs from one or more targets to the host 400.

[0051] The data output by the selection circuit 120 to the host 400 is, for example, an ACC and an EVEN signal, but is not particularly limited and may be any data.

[0052] The switching circuit 170 is an electronic circuit that causes the selection circuit 120 to output only the data output from one or more targets among targets 210, 220, and 230 to the host 400. More specifically, the switching circuit 170 acquires the target number (specifically, information indicating the target number) and, from the one or more acks input from one or more connection terminals among connection terminals 121, 122, and 123, causes the selection circuit 120 to output only the acks input from the connection terminal connected to the destination indicated by the target number (specifically, the target indicated by the target number among targets 210, 220, and 230) to the host 400.

[0053] The target number is information indicating the connection destination of one of the connection terminals 121, 122, and 123 (specifically, one of targets 210, 220, and 230).

[0054] For example, any of targets 210, 220, and 230, or the CPU 240, outputs a target number to register 150. Register 150 holds the target number output by any of targets 210, 220, and 230, or the CPU 240. The switching circuit 170 retrieves the target number from register 150 at a predetermined timing, for example. The target number is an example of number information.

[0055] Each target, for example, 210, 220, and 230, is assigned a unique, arbitrary numerical number. For instance, target 210 is assigned target number 0, target 220 is assigned target number 1, and target 230 is assigned target number 2.

[0056] Targets 210, 220, and 230 each have, for example, memory, which stores the respective target ID and target number of each target 210, 220, and 230.

[0057] Targets 210, 220, and 230, for example, when being debugged by host 400, that is, while connected to host 400 for debugging, each acquires information from host 400 indicating the target that host 400 will debug next, and each stores the target number of the target indicated by that information in register 150. For example, if target 210 acquires information indicating target 220 from host 400 while connected to host 400 for debugging, it stores the target number of target 220 in register 150. This information can be any information indicating the target that host 400 will debug next, and may be a target ID, a target number, or any other arbitrary information.

[0058] Furthermore, for example, the CPU 240 may store the target number in register 150. For example, the program executed by the CPU 240 may include a program that stores the target number in register 150. For example, when the LSI 300 starts up, if the CPU 240 is the first to start up among targets 210, 220, and 230, the CPU 240 may store the target number in register 150 at startup.

[0059] The LSI 300 may also be provided with a port for receiving output of a target number to register 150 or CPU 240. This port is connected, for example, to register 150 or CPU 240 and an external computer. The external computer can, for example, output the target number to register 150 or CPU 240, causing register 150 to directly hold the target number, or causing CPU 240 to hold the target number in register 150.

[0060] Furthermore, the target 200 may output information indicating its target number along with data such as ACK to the selection circuit 120. The selection circuit 120 or switching circuit 170 may also store information indicating the connection relationship between connection terminals 121, 122, and 123 and targets 210, 220, and 230, for example in a memory provided by the selection circuit 120 or switching circuit 170. For example, the selection circuit 120 may output to the host 400 only the data input from the connection terminal connected to the target corresponding to the target number, based on the information indicating the connection relationship. Alternatively, the switching circuit 170 may control the selection circuit 120 to output to the host 400 only the data input from the connection terminal connected to the target corresponding to the target number, based on the information indicating the connection relationship.

[0061] Furthermore, if the host 400 and the target 200 are connected via debug, the target 200 may store its own target number in register 150.

[0062] Furthermore, the predetermined timing can be arbitrary and is not particularly limited. The predetermined timing is, for example, the timing when a line reset signal is output from the host 400 to targets 210, 220, and 230 to reset targets 210, 220, and 230. When targets 210, 220, and 230 receive the line reset signal, they transition to a reset state. The switching circuit 170, for example, receives (detects) the line reset signal via the bus connecting the host 400 and the register 110, and obtains the target number from the register 150.

[0063] Furthermore, for example, the switching circuit 170 determines one or more processors from among targets 210, 220, and 230 based on status information related to the LSI 300, and causes the selection circuit 120 to output only the data (e.g., ACK) output by the determined one or more processors to the host 400. In other words, the switching circuit 170 may restrict the data output from the selection circuit 120 based on status information. Status information is an example of LSI information.

[0064] The target 200 may be, for example, a security device used in vehicles. If it is a security device, there may be restrictions on the communication it can perform. Therefore, for example, the switching circuit 170 does not need to output data from such a target to the selection circuit 120.

[0065] The status information is not particularly limited and may be any information relating to the LSI 300. For example, the status information may include information indicating targets that are permitted to output data from the selection circuit 120, or information indicating targets that are prohibited from outputting data from the selection circuit 120. For example, if the status information includes information indicating targets 210 and 220 as targets that are permitted to output data from the selection circuit 120, the switching circuit 170 may control the selection circuit 120 so that it outputs data output from target 210 and data output from target 220 to the host 400, but does not output data output from target 230 to the host 400. Furthermore, for example, if the status information includes information indicating target 210 and target 220 as targets for which data output from the selection circuit 120 is prohibited, the switching circuit 170 may control the selection circuit 120 so as to prevent data output from target 210 and data output from target 220 from being output to the host 400, while allowing data output from target 230 to be output to the host 400.

[0066] Furthermore, the status information may include information indicating whether the target 200 is genuine or counterfeit. For example, the switching circuit 170 may control the selection circuit 120 so that if the target 200 is genuine, the data output from the target 200 is output to the host 400 via the selection circuit 120, but if the target 200 is counterfeit, the data output from the target 200 is not output to the host 400 via the selection circuit 120.

[0067] Furthermore, the status information may include information indicating whether the target 200 is operational or not (for example, whether the target 200 is powered off or not). For example, the switching circuit 170 may control the selection circuit 120 so that when the target 200 is operational, i.e., when the target 200 is not powered off, the data output from the target 200 is output to the host 400 from the selection circuit 120, but when the target 200 is not operational, i.e., when the target 200 is powered off, the data output from the target 200 is not output to the host 400 from the selection circuit 120.

[0068] Status information may be pre-stored in register 160, stored in register 160 by an external computer, or acquired from a power control circuit (power management unit) (not shown) that controls the power supply of the components of the LSI 300 and stored in register 160.

[0069] Furthermore, the switching circuit 170 may decide whether to select data (e.g., ACKs) to output from the selection circuit 120 to the host 400 based on either the target number or the target ID. For example, if the switching circuit 170 decides to select ACKs to output from the selection circuit 120 to the host 400 based on the target number, it will output only the ACKs input from the connection part connected to the connection destination indicated by the number information from the selection circuit 120 to the host 400. If the switching circuit 170 decides to select ACKs to output from the selection circuit 120 to the host 400 based on the identification information, it will output only the ACKs output from the processor indicated by the identification information among the multiple targets 200 from the selection circuit 120 to the host 400.

[0070] The selection device 100 determines, for example, whether to select data to output from the selection circuit to the debugger based on number information or identification information, based on selection information indicating whether to select data to output from the selection circuit to the debugger based on number information or identification information. The selection information is stored, for example, in register 150. The selection information may also be output from the host 400 and held in register 150 by any of the targets 210, 220, and 230. Alternatively, an external computer may output the selection information to a register or the CPU 240, causing the external computer to directly hold the selection information in register 150, or the CPU 240 to hold the selection information in register 150.

[0071] The timing at which the switching circuit 170 obtains the target ID from register 110, the timing at which it obtains selection information from register 150, and the timing at which it obtains status information from register 160 are arbitrary and not particularly limited. These timings may be the same as or different from each other. Furthermore, these timings may be the same as or different from the timing at which the switching circuit 170 obtains the target number from register 150.

[0072] When the switching circuit 170 receives a line reset signal, for example, it first obtains selection information from register 150 and status information from register 160. Next, the switching circuit 170 decides, for example, whether to use the target number or the target ID based on the selection information. If the switching circuit 170 decides to use the target number, for example, it obtains the target number from register 150 and controls the selection circuit 120 using the target number and status information. On the other hand, if the switching circuit 170 decides to use the target ID, for example, it obtains the target ID from register 110 and controls the selection circuit 120 using the target ID and status information.

[0073] The selection device 100 may also include a detection circuit 130 and a register 140.

[0074] The detection circuit 130 is an electronic circuit that detects a race condition in which data is output simultaneously from multiple targets 200. Specifically, when a race condition occurs in which data is output from two or more targets among targets 210, 220, and 230, the detection circuit 130 stores race information related to the race condition in the register 140.

[0075] Register 140 is a register that holds (stores) race information. Register 140 can be implemented, for example, by a latch circuit, but it may be implemented with any configuration such as a flip-flop circuit.

[0076] Conflict information includes, for example, the enable signals output by each of two or more targets. For example, the detection circuit 130 stores the enable signals output by targets 210, 220, and 230 in the register 140.

[0077] Furthermore, for example, the conflict information is a target ID (second target ID) that indicates two or more targets. For example, the detection circuit 130 stores in register 140 the target ID of the target that output data to the selection circuit 120 from among targets 210, 220, and 230. For example, the selection device 100 may store the target IDs of targets 210, 220, and 230 in advance in a memory (not shown), and the detection circuit 130 may use this memory to identify the target ID indicating the target from which the data was output when data is output from a target, and store the identified target ID as conflict information in register 140.

[0078] Of course, the detection circuit 130 may also store both the target ID of each of the two or more targets, and the enable signal output by each of those two or more targets, as conflict information in the register 140.

[0079] Furthermore, the detection circuit 130 may store the target numbers of two or more targets as conflict information in the register 140.

[0080] The host 400 and the register 140 may be connected in a way that enables communication. Specifically, the register 140 may be configured so that the host 400 can access the conflict information. For example, the host 400 communicates with the register via a bus used when components such as the CPU of the LSI 300 access the register 140. The conflict information held in the register 140 may be located in an address space or memory space accessible from the host 400. The conflict information may be located in an address space or memory space accessible only from the host 400, or it may be located in an address space or memory space accessible from devices other than the host 400.

[0081] [Processing Procedure] Next, the processing procedure of the debugging system 10 according to the embodiment will be described. In the first and second examples described below, the processing procedure will be described when debugging of target 210 among targets 210, 220, and 230 is performed.

[0082] <First Example> Figure 4 is a sequence diagram showing a first example of the processing procedure of the debugging system 10 according to the embodiment. The first example is the processing procedure of the debugging system 10 when no race condition occurs.

[0083] First, the host 400 outputs the target ID (specifically, the target ID indicating target 210) and the request (debug request) to the LSI 300 (S110). As a result, the target ID and the request are output to targets 210, 220, and 230, respectively.

[0084] Examples of methods by which host 400 can connect to a target (also called a debug connection) in order to debug that target include a reset vector catch connection and an attach connection.

[0085] A reset vector catch connection is a connection method that manipulates the reset negate timing on the host 400 and triggers a breakpoint when the reset vector is fetched. A reset vector catch connection is used, for example, when you want to debug the target program from the beginning (startup).

[0086] An attach connection is a method by which the host 400 connects to a target while the target is already executing a program. In this connection method, for example, the program being executed on the target will not stop until a break operation is performed. In an attach connection, the host 400 may also set a break during a debug connection.

[0087] In the debug system 10, either a reset vector catch connection or an attach connection may be used. When a reset vector catch connection is used, for example, after the power is turned on (power-on reset) but before the reset is released and the boot sequence starts, the debug connection is initiated (i.e., the target ID and request are output).

[0088] When the target ID and request are output in step S110, the selection device 100 holds the outputted target ID (S120).

[0089] Furthermore, target 210 outputs an ACK in response to a request (S130). Specifically, target 210 outputs an ACK and an enable signal.

[0090] Furthermore, in this example, targets 220 and 230 do not output an ACK.

[0091] The selection device 100 outputs the ACK acquired from the target 210 as is (S140). As a result, the host 400 acquires the ACK of the target 210, establishes a debug connection between the host 400 and the target 210, and starts debugging the target 210 (S150).

[0092] Furthermore, in the communication between the host 400 and the target 210 during debugging from step S150 onward, the host 400 may or may not output the target ID. Also, in this communication, the selection device 100 does not need to retain the target ID if it is output from the host 400. Also, in this communication, the selection device 100 may or may not determine whether or not to output debugging data to the host 400 based on the target ID. For example, if the selection device 100 obtains debugging data from the target indicated by the target ID, it may output that data to the host 400, but if it obtains debugging data from a target other than the target indicated by the target ID, it does not need to output that data to the host 400.

[0093] <Second Example> Figure 5 is a sequence diagram showing a second example of the processing procedure of the debugging system 10 according to the embodiment. The second example is the processing procedure of the debugging system 10 when a race condition occurs. In the description of each step in the second example, if the processing is substantially the same as in the first example, the same reference numerals will be used, and the description may be simplified or omitted.

[0094] First, the host 400 outputs a target ID indicating the target 210 and a request to the LSI 300 (S210).

[0095] Furthermore, the selection device 100 obtains the target number from the register 150 (S220).

[0096] Furthermore, target 210 outputs an ack in response to a request (S230).

[0097] In this example, let's assume that some kind of abnormality has occurred in target 230, and that it has output an ACK (specifically, an ACK and an enable signal) in response to the request (S240). In this case, the selection device 100 will acquire ACKs from both target 210 and target 230 simultaneously.

[0098] In this case, the selection device 100 outputs to the host 400 only the ack obtained from the target indicated by the target number obtained in step S220, out of the two acquired acks (S250). Specifically, the selection device 100 outputs to the host 400 only the ack and enable signal obtained from target 210.

[0099] As a result, host 400 acquires only the ACK of target 210, establishes a debug connection between host 400 and target 210, and starts debugging target 210 (S260).

[0100] The selection device 100 may also retain conflict information. For example, the detection circuit 130 may store the two enable signals output along with the two ACKs as conflict information in the register 140.

[0101] Furthermore, for example, if the selection device 100 acquires only one ack, and the target that output the ack is not the target indicated by the target number, the ack may or may not be output to the host 400. In this case, the enable signal that the target that output the ack wants to output, and / or the target ID indicating that target, may be stored in a register 140 or the like.

[0102] Furthermore, the selection device 100 may hold the target ID output from the host 400.

[0103] Alternatively, instead of steps S220 and S250, the selection device 100 may, for example, obtain selection information from register 150 before acquiring the ack, and decide whether to use the target number or the target ID based on the selection information. If the selection device 100 decides to use the target number, for example, it executes steps S220 and S250. If it decides to use the target ID, in step S220 it obtains the target ID from register 110, and in step S250 it outputs only the ack acquired from the target indicated by the target number to the host 400.

[0104] <Processing Procedure of the Selection Device> Figure 6 is a flowchart showing a specific example of the processing procedure of the selection device 100 according to the embodiment.

[0105] First, the selection device 100 obtains the target number from the register 150 (S310). The selection device 100 executes step S310, for example, when it obtains a line reset signal.

[0106] Next, the selection device 100 acquires an ack from at least one of the targets 210, 220, and 230 (S320).

[0107] Next, the selection device 100 determines whether the number of acks acquired in step S320 is 2 or more (S330).

[0108] If the selection device 100 determines that the number of acquired acks is not two or more (No in S330), that is, if the number of acquired acks is one, it outputs the acquired ack to the host 400 (S340).

[0109] On the other hand, if the selection device 100 determines that the number of acquired acks is two or more (Yes in S330), that is, if it determines that a conflict has occurred, it outputs to the host 400 only the acks that were output from the target indicated by the target number out of the two or more acquired acks (S350).

[0110] Furthermore, the selection device 100 stores, for example, two or more enable signals acquired together with two or more ACCs as conflict information (S360).

[0111] Note that the process in step S330 does not necessarily have to be executed. In this case, for example, after step S320, the selection device 100 determines whether the target that output the acquired ack is the target indicated by the target number. For example, if the target is the target indicated by the target number, the selection device 100 transfers the acquired ack to the host 400, and if it is not the target indicated by the target number, it does not transfer the acquired ack to the host 400.

[0112] In the first example as well, the selection device 100 may acquire a target number and, based on the target number, select an ACK to be output from the selection circuit 120 to the host 400.

[0113] Furthermore, for example, if debugging is performed consecutively, the selection device 100 may determine the data to be output from the selection circuit 120 using the target ID for the first debugging, and use the target number for subsequent debugging to determine the data to be output from the selection circuit 120.

[0114] Host 400 may also output the target number and the request. Host 400 may also output the target ID, target number, and the request.

[0115] <Representative Example> Figure 7 is a flowchart illustrating a selection method according to an embodiment. Specifically, Figure 7 is a flowchart illustrating the basic processing steps of a selection method performed by the selection device 100. For example, the selection device 100 includes a circuit and a register, and the circuit uses the register to perform the following processing.

[0116] First, the selection device 100 obtains number information indicating the connection destination of one of the multiple connection points that are connected one-to-one with multiple processors (S10). The selection device 100 obtains the number information, for example, from the register 150.

[0117] The multiple processors are, for example, targets 210, 220, and 230 above. The multiple connection points are, for example, connection terminals 121, 122, and 123 above. The destination of each of the multiple connection points is, for example, one of the multiple processors. The number information is, for example, the target number above.

[0118] Next, the selection device 100 outputs to the debugger only the data input from the connection point that corresponds to the connection destination indicated by the number information, out of the one or more data inputs from one or more of the multiple connection points, via the selection circuit 120 which has multiple connection points (S20).

[0119] The debugger is, for example, host 400 mentioned above.

[0120] [Effects, etc.] The selection device 100 according to the embodiment is a selection device 100 connected to a host 400 that is multidrop connected to a plurality of targets 200. The host 400 performs debugging of the plurality of targets 200. The selection device 100 includes a selection circuit 120 having a plurality of connection parts (for example, connection terminals 121, 122, and 123) that are connected one-to-one with the plurality of targets 200, and a switching circuit 170 that acquires number information (specifically, target number) indicating the connection destination of any of the plurality of connection parts (specifically, any of the plurality of targets 200), and outputs from the selection circuit 120 to the host 400 only the ack input from the connection part connected to the connection destination indicated by the number information (specifically, the target 200 among the plurality of targets 200 to which the target number indicated by the number information is associated) out of the ack input from one or more connection parts among the plurality of connection parts.

[0121] When the host 400 debugs multiple targets 200, for example, it communicates with one of the multiple targets 200 on a one-to-one basis. In this case, for example, the host 400 outputs (transmits) a target ID indicating that target 200 to the target 200 in order to establish communication with that target 200. Here, if the host 400 and the multiple targets 200 are connected via multidrop, the target ID output from the host 400 is acquired by each of the multiple targets 200. Based on the target ID, the multiple targets 200 output an ACK to the host 400 if the target indicated by the target ID is their own target, and do not output an ACK to the host 400 if the target indicated by the target ID is not their own target. This establishes one-to-one communication between the host 400 and the one target 200. In a system comprising a selection device 100, multiple targets 200, and a host 400, if an unexpected failure occurs due to noise or other reasons, or if two or more of the multiple targets 200 are incorrectly assigned the same identifier, or if there is a mistake in fixing the output value when the power is cut off, or if one of the multiple targets 200 is operating on a standard that does not support multidrop connections, or if an unexpected failure occurs in a target 200, then unintended targets 200 may also output acks to the host 400. In such cases, the host 400 may not be able to debug properly. Therefore, based on the target number, the selection device 100, for example, if a race condition occurs in which acks are simultaneously output from two or more of the multiple targets 200 in response to a debug request output by the host 400 for debugging, outputs only the ack obtained from the one target 200 indicated by the target number to the host 400. This reduces the possibility that the host 400 may not be able to perform debugging due to obtaining multiple acks.Therefore, the selection device 100 makes it easier for the host 400 to properly acquire an acknowledgment from the target 200 to be debugged, thereby reducing the possibility that the host 400 may not be able to properly debug the target 200.

[0122] Furthermore, for example, the switching circuit 170 obtains a target number at a predetermined timing from a register 150 that holds a target number output by one of two or more processors, which include multiple targets 200.

[0123] In a multidrop connection, the host 400 typically obtains identification information (specifically, a target ID) indicating one of several processors, and the selection circuit 120 outputs data based on this identification information. Each processor that supports multidrop connections is associated with a unique target ID. Therefore, the host 400 and the processor can establish a one-to-one debug connection using the target ID. On the other hand, processors that do not support multidrop connections may not be assigned such a target ID. In this case, a debug connection may not be properly established between the non-multidrop compatible processor and the host 400.

[0124] Therefore, a target number is obtained from a register 150 that holds a target number output by one of the multiple processors (for example, targets 210, 220, and 230, and CPU 240) located on the LSI 300, and the data output from the selection circuit 120 is determined based on this target number. This allows a one-to-one debug connection to be established between the processor and the host 400 even if the processor does not support multidrop connections, that is, even if the processor is not assigned a target ID. In other words, by using a target number defined for each of the multiple targets 200, separate from the target ID normally used in multidrop connections, a debug connection can be established even if some of the multiple targets 200 do not support multidrop connections.

[0125] Furthermore, for example, the predetermined timing is the timing when the host 400 outputs a line reset signal to the multiple targets 200 to cause them to reset.

[0126] If, during debugging of one processor (for example, target 210), the processor indicated by the target number acquired by the switching circuit 170 is switched from that processor to another processor (for example, target 220), an error may occur in the debug connection between that processor and the host 400, potentially terminating the debug connection. Such errors can be suppressed if a line reset signal is output at the appropriate time.

[0127] Furthermore, for example, the switching circuit 170 determines one or more processors from among the multiple targets 200 based on status information relating to the selection device 100 and the LSI 300 on which the multiple targets 200 are arranged, and causes the selection circuit 120 to output only the ACK output by that one or more processors to the host 400.

[0128] In other words, the selection device 100 limits the output from the selection circuit 120 based on the status information.

[0129] According to this, by using status information that indicates setting values ​​defined for components of the LSI 300, such as the current value set for the eFuse (electronic fuse) of the LSI 300, it is possible to restrict debug connections to a specific target 200 among multiple targets 200 that has a higher level of security than other targets 200, such as security devices.

[0130] Furthermore, for example, the selection device 100 also includes a register 110 that obtains and stores a target ID from the host 400 that indicates one of the multiple targets 200.

[0131] According to this, the selection device 100 can easily obtain the target ID from the register 110.

[0132] Furthermore, for example, the switching circuit 170 obtains a target ID from the register 110 and decides whether to select the ack to be output from the selection circuit 120 to the host 400 based on the target number or the target ID. If it is decided to select the ack to be output from the selection circuit 120 to the host 400 based on the target number, only the ack input from the connection connected to the connection destination indicated by the target number is output from the selection circuit 120 to the host 400. If it is decided to select the ack to be output from the selection circuit 120 to the host 400 based on the target ID, only the ack output from the processor indicated by the target ID among the multiple targets 200 is output from the selection circuit 120 to the host 400. In other words, the selection device 100 decides whether to select the data to be output from the selection circuit 120 to the debugger based on the target number or the target ID, based on selection information indicating whether to select the data to be output from the selection circuit 120 to the debugger based on the target number or the target ID. The selection information is held in, for example, the second holding circuit.

[0133] Using target IDs makes debugging easier compared to using target numbers, because the debug connection is established solely from the information provided by the debugger. Therefore, when the debugger and multiple processors support multi-drop connections, using target IDs requires less processing power than using target numbers. This allows for a proper balance between reducing processing power and minimizing the possibility of debugging failures.

[0134] (Other Embodiments) Embodiments have been described above as examples of the technology relating to this disclosure. However, the technology relating to this disclosure is not limited thereto and can be applied to embodiments that are modified, replaced, added to, or omitted as appropriate. For example, the following modified examples are also included in one embodiment of this disclosure.

[0135] For example, the selection device 100 does not need to include the detection circuit 130.

[0136] Furthermore, for example, the selection device 100 does not necessarily have to include a register 140.

[0137] Furthermore, for example, the selection device 100 does not necessarily have to include a register 110.

[0138] Furthermore, for example, the selection device 100 may include a register 150.

[0139] Furthermore, for example, the selection device 100 may include a register 160.

[0140] Furthermore, for example, the LSI300 does not necessarily need to have a CPU240.

[0141] Furthermore, the connection part may be a connection terminal, or it may be a wire connecting the target and the selection circuit 120.

[0142] Furthermore, for example, the number of targets (processors) that the LSI 300 has may be two or four or more. The selection circuit 120 only needs to have a number of connection terminals corresponding to the number of targets (processors) that the LSI 300 has.

[0143] Furthermore, for example, the LSI 300 and the host 400 may be connected via multidrop outside the LSI 300. Therefore, the LSI 300 may have the same number of ports connected to the host 400 as the number of targets the LSI 300 has.

[0144] Furthermore, for example, the selection device 100 and the multiple processors are provided on a single chip, but the selection device 100 and the multiple processors may be provided on separate chips.

[0145] Furthermore, each of the holding circuits can be implemented, for example, by registers, but they only need to have the function of storing information, and may also be implemented by memory such as RAM (Random Access Memory).

[0146] Furthermore, for example, some or all of the functions of the selection device 100 according to the above embodiment are typically implemented in an LSI 300, which is an integrated circuit. These may be individually integrated into a single chip, or some or all of them may be integrated into a single chip. Moreover, the integration is not limited to an LSI, but may also be implemented in a dedicated circuit or a general-purpose processor. An FPGA (Field Programmable Gate Array) that can be programmed after LSI manufacturing, or a reconfigurable processor that can reconfigure the connections and settings of circuit cells inside the LSI may also be used.

[0147] Furthermore, if advances in semiconductor technology or other derived technologies lead to the emergence of integrated circuit technologies that can replace LSIs, then naturally, those technologies may be used to integrate each component included in the selection device 100 into an integrated circuit.

[0148] Furthermore, for example, in the above embodiment, a process executed by a specific processing unit may be executed by another processing unit. Also, the order of multiple processes may be changed, or multiple processes may be executed in parallel.

[0149] Furthermore, this disclosure also includes forms obtained by applying various modifications to the embodiments that a person skilled in the art could conceive, and forms realized by arbitrarily combining the components and functions of each embodiment without departing from the spirit of this disclosure.

[0150] (Note) The following describes examples of technologies that can be obtained from the disclosures in this specification, and explains the effects that can be obtained from the technologies described.

[0151] (Technology 1) A selection device connected to a debugger that performs debugging of a plurality of processors, wherein the debugger is connected to the plurality of processors via multidrop connection, and the selection device comprises: a selection circuit having a plurality of connection parts that are connected one-to-one with the plurality of processors; and a switching circuit that acquires number information indicating the connection destination of any of the plurality of connection parts, and outputs from the selection circuit to the debugger only the data input from the connection part connected to the connection destination indicated by the number information, out of the one or more data input from one or more of the plurality of connection parts.

[0152] The selection device is, for example, the selection device 100 described above. The multiple processors are, for example, the targets 210, 220, and 230 described above. The selection circuit is, for example, the selection circuit 120 described above. The multiple connection points are, for example, the connection terminals 121, 122, and 123 described above. The debugger is, for example, the host 400 described above. Each of the multiple connection points is connected to, for example, one of the multiple processors. Each of the multiple connection points is connected one-to-one with a different processor, for example. The number information is, for example, the target number described above that indicates the processor that the debugger is debugging.

[0153] This reduces the possibility that the debugger may be unable to perform debugging due to obtaining multiple data points. Therefore, this makes it easier for the debugger to properly obtain data from the processor being debugged, thus reducing the possibility that the debugger may be unable to properly debug the processor.

[0154] (Technical 2) The selection device according to Technical 1, wherein the switching circuit acquires the number information at a predetermined timing from a first holding circuit that holds the number information output by any of the two or more processors, including the plurality of processors.

[0155] The switching circuit is, for example, the switching circuit 170 described above. The two or more processors are, for example, the targets 210, 220, and 230 described above, and the CPU 240. The first holding circuit is, for example, the register 150 described above.

[0156] According to this, by using a number information assigned to each of the multiple processors, separate from the identification information normally used in multidrop connections, a debug connection can be established even if some of the multiple processors do not support multidrop connections.

[0157] (Technical 3) The selection device according to Technical 2, wherein the predetermined timing is the timing at which a reset signal is output from the debugger to the plurality of processors to reset the plurality of processors.

[0158] The reset signal is, for example, the line reset signal mentioned above.

[0159] According to this, the occurrence of errors in debug connections can be suppressed.

[0160] (Technical 4) The selection device according to any one of Technical 1 to 3, wherein the switching circuit determines one or more of the multiple processors based on LSI information relating to the selection device and the multiple processors arranged in the LSI, and causes the selection circuit to output only the data output by the one or more processors to the debugger.

[0161] The LSI is, for example, the LSI300 mentioned above. The LSI information is, for example, the status information mentioned above.

[0162] According to this, debugging connections to specific processors can be restricted.

[0163] (Technical 5) The selection device according to any one of Technical 1 to 4, further comprising a second holding circuit that acquires and holds identification information indicating any one of the plurality of processors from the debugger.

[0164] The identification information is, for example, information indicating the target ID mentioned above. The second holding circuit is, for example, the register 110 mentioned above.

[0165] According to this, the selection device can easily obtain identification information from the second holding circuit.

[0166] (Technical 6) The switching circuit further acquires the identification information from the second holding circuit, and determines whether to select the data to be output from the selection circuit to the debugger based on the number information or the identification information, and if it is determined that the data to be output from the selection circuit to the debugger is to be selected based on the number information, the selection circuit outputs only the data input from the connection part connected to the connection destination indicated by the number information to the debugger, and if it is determined that the data to be output from the selection circuit to the debugger is to be selected based on the identification information, the selection circuit outputs only the data output from the processor indicated by the identification information among the plurality of processors to the debugger, the selection device according to Technical 5.

[0167] The selection device determines, for example, whether to select the data to be output from the selection circuit to the debugger based on number information or identification information, based on selection information indicating whether to select the data to be output from the selection circuit to the debugger based on number information or identification information. The selection information is held, for example, in a second holding circuit.

[0168] This allows for a proper balance between reducing processing load and minimizing the possibility of being unable to perform debugging.

[0169] (Technical 7) A selection method performed by a selection device connected to a debugger that performs debugging of a plurality of processors, wherein the selection device obtains number information indicating the connection destination of one of a plurality of connection parts that are connected one-to-one with the plurality of processors, and causes the selection circuit having the plurality of connection parts to output to the debugger only the data input from the connection part connected to the connection destination indicated by the number information, out of the one or more data input from one or more connection parts among the plurality of connection parts.

[0170] According to this, it will have the same effect as the selection device described in Technology 1.

[0171] These comprehensive or specific embodiments may be implemented as a system, method, integrated circuit, computer program, or non-temporary recording medium such as a computer-readable CD-ROM, or as any combination of a system, method, integrated circuit, computer program, and recording medium.

[0172] This disclosure can be applied to LSIs and the like that have multiple processors to be debugged.

[0173] 10 Debugging System 100 Selection Device 110, 140, 150, 160 Register 120 Selection Circuit 121, 122, 123 Connection Terminal 130 Detection Circuit 170 Switching Circuit 200, 210, 220, 230 Target 240 CPU 300 LSI 310 Port Section 320 Bus 400 Host

Claims

1. A selection device connected to a debugger that performs debugging of a plurality of processors, wherein the debugger is multidrop connected to the plurality of processors, the selection device comprising: a selection circuit having a plurality of connection parts that are connected one-to-one with the plurality of processors; and a switching circuit that acquires number information indicating the connection destination of any of the plurality of connection parts, and outputs from the selection circuit to the debugger only the data input from the connection part connected to the connection destination indicated by the number information, out of the one or more data input from one or more of the plurality of connection parts.

2. The selection device according to claim 1, wherein the switching circuit acquires the number information at a predetermined timing from a first holding circuit that holds the number information output by any of the two or more processors, including the plurality of processors.

3. The selection device according to claim 2, wherein the predetermined timing is the timing at which a reset signal is output from the debugger to the plurality of processors to cause the plurality of processors to reset.

4. The selection device according to claim 1, wherein the switching circuit determines one or more processors from among the plurality of processors based on LSI information relating to the selection device and the plurality of processors arranged in the LSI, and causes the selection circuit to output only the data output by the one or more processors to the debugger.

5. The selection device according to any one of claims 1 to 4, further comprising a second holding circuit that acquires and holds identification information indicating any one of the plurality of processors from the debugger.

6. The switching circuit further acquires the identification information from the second holding circuit, determines whether to select data to be output from the selection circuit to the debugger based on the number information or the identification information, and if it is determined to select data to be output from the selection circuit to the debugger based on the number information, the selection circuit outputs only the data input from the connection part connected to the connection destination indicated by the number information to the debugger, and if it is determined to select data to be output from the selection circuit to the debugger based on the identification information, the selection circuit outputs only the data output from the processor indicated by the identification information among the plurality of processors to the debugger, the selection device according to claim 5.

7. A selection method performed by a selection device connected to a debugger that performs debugging of a plurality of processors, wherein the selection device obtains number information indicating the connection destination of one of a plurality of connection parts that are connected one-to-one with the plurality of processors, and causes the selection circuit having the plurality of connection parts to output to the debugger only the data input from the connection part connected to the connection destination indicated by the number information, out of the one or more data inputs from one or more of the plurality of connection parts.

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