Video signal processing device and video signal processing method

Abstract

This video signal processing device (100) comprises: an interrupt processing unit (101) that performs interrupt processing for acquiring a count value of a free-run counter (400) when a prescribed signal is generated; a delay time calculation unit (102) that calculates a delay time from the generation of the prescribed signal to the start of the interrupt processing on the basis of a count value of a prescribed counter (500) periodically reset in response to the generation of the prescribed signal; a signal generation timing calculation unit (103) that calculates a timing at which the prescribed signal is generated by subtracting the delay time from the count value of the free-run counter (400) acquired by the interrupt processing; and a period measurement unit (104) that measures the period of the prescribed signal by calculating the difference between the timing at which the current prescribed signal is generated and the timing at which the previous prescribed signal was generated.

Description

Video signal processing apparatus and video signal processing method

[0001] The present disclosure relates to a video signal processing apparatus and a video signal processing method.

[0002] Patent Document 1 discloses a technique for controlling a video synchronization signal.

[0003] Japanese Patent No. 6128901

[0004] For example, some cameras used in electronic mirrors change the exposure time according to ambient brightness, and dynamically change the vertical synchronization signal output from the camera. For example, some cameras dynamically change the vertical synchronization signal between 60 Hz and 30 Hz. In contrast, the technique disclosed in Patent Document 1 does not assume a case where the cycle of the vertical synchronization signal dynamically changes, and thus the display may fail to perform correct display.

[0005] On the other hand, even if the cycle of the vertical synchronization signal of the video signal dynamically changes, in order to keep the cycle of the output vertical synchronization signal constant and output the vertical synchronization signal within a range allowable for a display, it is conceivable to measure the cycle of the vertical synchronization signal by performing interrupt processing for acquiring the count value of a free-running counter when the vertical synchronization signal is generated. It should be noted that the measurement can be similarly performed not only for vertical synchronization signals, but also for cycles of predetermined signals that periodically occur in processing of video signals such as vertical synchronization signals.

[0006] However, when such a predetermined signal occurs, if interrupt processing with higher priority than the interrupt processing for acquiring the count value of the free-running counter is being executed, the interrupt processing for acquiring the count value of the free-running counter does not start until the higher-priority interrupt processing ends, which may cause an error in the measurement of the cycle of the predetermined signal.

[0007] Therefore, the present disclosure provides a video signal processing apparatus and the like capable of accurately measuring the cycle of a predetermined signal that periodically occurs in video signal processing.

[0008] The video signal processing device according to this disclosure is a video signal processing device that measures the period of a predetermined signal that occurs periodically in the processing of a video signal, and comprises: an interrupt processing unit that performs an interrupt processing to acquire the count value of a free-run counter when the predetermined signal occurs; a delay time calculation unit that calculates a delay time from the occurrence of the predetermined signal to the start of the interrupt processing based on the count value of a predetermined counter that is periodically reset in response to the occurrence of the predetermined signal; a signal generation timing calculation unit that calculates the timing at which the predetermined signal occurs by subtracting the delay time from the count value of the free-run counter acquired by the interrupt processing; and a period measurement unit that measures the period of the predetermined signal by calculating the difference between the timing at which the predetermined signal occurred this time and the timing at which the predetermined signal occurred last time.

[0009] The video signal processing method according to this disclosure is a video signal processing method performed by a video signal processing device that measures the period of a predetermined signal that occurs periodically in the processing of a video signal, and includes the steps of: obtaining a count value of a free-running counter by performing an interrupt process when the predetermined signal occurs; calculating a delay time from the occurrence of the predetermined signal to the start of the interrupt process based on the count value of a predetermined counter that is periodically reset in response to the occurrence of the predetermined signal; calculating the timing at which the predetermined signal occurred by subtracting the delay time from the count value of the free-running counter obtained by the interrupt process; and measuring the period of the predetermined signal by calculating the difference between the timing at which the predetermined signal occurred this time and the timing at which the predetermined signal occurred last time.

[0010] These comprehensive or specific embodiments may be implemented as a system, method, integrated circuit, computer program, or recording medium such as a computer-readable CD-ROM, or as any combination of a system, method, integrated circuit, computer program, and recording medium.

[0011] According to one aspect of this disclosure, a video signal processing device, etc., can accurately measure the period of a predetermined signal that occurs periodically in the processing of a video signal.

[0012] This is a block diagram showing an example of a video signal processing device according to an embodiment. This diagram illustrates a method for measuring the period of a predetermined signal by a free-run counter measurement interrupt process. This diagram illustrates a method for measuring the period of a predetermined signal in an embodiment. This is a block diagram showing an example of a video display system to which the video signal processing device according to an embodiment is applied. This is a flowchart showing an example of the operation of the video display system according to an embodiment. This is a flowchart showing another example of the operation of the video display system according to an embodiment. This is a flowchart showing an example of a video signal processing method according to another embodiment.

[0013] The embodiments will be described in detail below with reference to the drawings.

[0014] The embodiments described below are all general or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit this disclosure.

[0015] (Embodiment) The following describes the video signal processing device according to the embodiment.

[0016] Figure 1 is a block diagram showing an example of a video signal processing device 100 according to an embodiment. In addition to the video signal processing device 100, Figure 1 also shows a free-run counter 400 and a predetermined counter 500. The video signal processing device 100 may also include the free-run counter 400 and the predetermined counter 500.

[0017] The video signal processing device 100 is a device that processes video signals. The video signal processing device 100 has a function to measure the period of a predetermined signal that is periodically generated in the processing of video signals. For example, the predetermined signal is a vertical synchronization signal.

[0018] The free-running counter 400 is a counter that does not accept external reset commands and automatically returns to 0 when the counted value exceeds the maximum value, meaning it is a counter that repeatedly overflows. Since the time per count by the free-running counter 400 is a fixed value, time can be measured, for example, by using the counter value of the free-running counter 400. For this reason, as will be described later, the period of a predetermined signal that occurs periodically can be measured by using the counter value of the free-running counter 400.

[0019] The predetermined counter 500 is a counter whose count value is periodically reset in response to the occurrence of a predetermined signal. If the predetermined signal is a vertical synchronization signal, the predetermined counter 500 is either a line counter or a pixel counter. If the predetermined counter 500 is a line counter, it is reset when it has counted the number of vertical lines in one frame. If the predetermined counter 500 is a pixel counter, it is reset when it has counted the number of pixels in one frame.

[0020] The video signal processing device 100 includes an interrupt processing unit 101, a delay time calculation unit 102, a signal generation timing calculation unit 103, and a period measurement unit 104. Each component included in the video signal processing device 100 may be implemented by dedicated hardware or by executing a software program suitable for each component. Each component may be implemented by a program execution unit such as a CPU (Central Processing Unit) or processor reading and executing a software program recorded on a recording medium such as a hard disk or semiconductor memory. For example, the video signal processing device 100 may be a computer including a processor and memory. The memory may be ROM (Read Only Memory) or RAM (Random Access Memory), and can store programs executed by the processor. For example, the interrupt processing unit 101, the delay time calculation unit 102, the signal generation timing calculation unit 103, and the period measurement unit 104 may be implemented by a processor that executes a program stored in memory.

[0021] The interrupt processing unit 101 performs an interrupt process (hereinafter also referred to as the free-run counter measurement interrupt process) to obtain the count value of the free-run counter 400 when a predetermined signal occurs. In other words, the interrupt processing unit 101 performs the free-run counter measurement interrupt process at each cycle of the predetermined signal. Here, the method for measuring the cycle of the predetermined signal by the free-run counter measurement interrupt process will be explained.

[0022] Figure 2 illustrates a method for measuring the period of a predetermined signal using a free-run counter measurement interrupt. Here, the predetermined signal is the vertical synchronization signal.

[0023] As shown in the "Signal Generation" section on the left side of Figure 2, the generation of a vertical synchronization signal initiates the free-run counter measurement interrupt process, and the count value Tvi of the free-run counter 400 is measured. Since the vertical synchronization signal is generated periodically, as shown in the "Signal Generation" section on the right side of Figure 2, the generation of the next vertical synchronization signal initiates the free-run counter measurement interrupt process, and the count value Tnow of the free-run counter 400 is measured. Then, by calculating the difference between the count value Tnow and the count value Tvi, the period Pvi of the vertical synchronization signal can be measured. As mentioned above, the time per count by the free-run counter 400 is a fixed value and is known in advance, so the period, i.e., time, can be measured by calculating the difference between each count value.

[0024] However, if a higher-priority interrupt process is executed when a predetermined signal, such as a vertical synchronization signal, is generated, the free-run counter measurement interrupt process will not start until the higher-priority interrupt process is completed, which may result in errors in measuring the period of the predetermined signal.

[0025] In contrast, the video signal processing device 100 includes a delay time calculation unit 102, a signal generation timing calculation unit 103, and a period measurement unit 104 as functions for accurately measuring the period of a predetermined signal, even when an interrupt process with a higher priority than the free-run counter measurement interrupt process is being executed when a predetermined signal is generated.

[0026] The delay time calculation unit 102 calculates the delay time from the occurrence of a predetermined signal to the start of the free-run counter measurement interrupt processing, based on the count value of a predetermined counter 500 which is periodically reset in response to the occurrence of a predetermined signal.

[0027] The signal generation timing calculation unit 103 calculates the timing at which a predetermined signal is generated by subtracting the delay time calculated by the delay time calculation unit 102 from the count value of the free-run counter 400 obtained by the free-run counter measurement interrupt processing.

[0028] The period measurement unit 104 measures the period of a predetermined signal by calculating the difference between the timing at which the predetermined signal was generated this time and the timing at which the predetermined signal was generated last time, as calculated by the signal generation timing calculation unit 103. For example, the period measurement unit 104 outputs the measured period of the predetermined signal to a functional unit or device that performs processing using the period of the predetermined signal.

[0029] The operation of the delay time calculation unit 102, the signal generation timing calculation unit 103, and the period measurement unit 104 will be explained in detail with reference to Figure 3.

[0030] Figure 3 is a diagram illustrating a method for measuring the period of a predetermined signal in an embodiment. In the explanation of Figure 3, the predetermined counter 500 is referred to as a line counter.

[0031] As shown in "Signal Generation" on the left side of Figure 3, the generation of a vertical synchronization signal initiates the free-run counter measurement interrupt process, and the count value Tvi of the free-run counter 400 is measured. Since the vertical synchronization signal is generated periodically, as shown in "Signal Generation" on the right side of Figure 3, the next vertical synchronization signal is generated. However, if an interrupt process with a higher priority than the free-run counter measurement interrupt process is being executed when this vertical synchronization signal is generated, the free-run counter measurement interrupt process will not start until the higher-priority interrupt process is completed.

[0032] On the other hand, the designated counter 500 (line counter) resets the count value it has counted so far in response to the generation of the vertical synchronization signal. In other words, it starts counting in response to the generation of the vertical synchronization signal, and therefore starts counting the number of vertical lines from the timing of "signal generation" on the right side of Figure 3.

[0033] Subsequently, after the high-priority interrupt processing is completed, the free-run counter measurement interrupt processing is started, and the count value Tnow of the free-run counter 400 is measured. The count value Tnow includes the delay time from the generation of the vertical synchronization signal to the start of the free-run counter measurement interrupt processing. The delay time calculation unit 102 then calculates the delay time Td from the generation of the vertical synchronization signal to the start of the free-run counter measurement interrupt processing based on the count value of a predetermined counter 500. Specifically, the delay time Td can be calculated by multiplying the count value Cl of the predetermined counter 500 from the generation of the vertical synchronization signal to the start of the free-run counter measurement interrupt processing by the horizontal period Ph of one line (i.e., the time per count of the predetermined counter 500). The signal generation timing calculation unit 103 then calculates the timing when the vertical synchronization signal was generated by subtracting the delay time Td calculated by the delay time calculation unit 102 from the count value Tnow of the free-run counter 400 obtained by the free-run counter measurement interrupt processing.

[0034] Furthermore, the period measurement unit 104 measures the period Pvi of the vertical synchronization signal by calculating the difference between the timing at which the vertical synchronization signal was generated this time and the timing at which the vertical synchronization signal was generated last time, as calculated by the signal generation timing calculation unit 103. In other words, the period measurement unit 104 can measure the period Pvi of the vertical synchronization signal by calculating the current count value Tnow - previous count value Tvi - delay time Td.

[0035] As explained above, while the count value of the free-running counter 400 is obtained by the free-running counter measurement interrupt process, the count value of a predetermined counter 500, which is periodically reset in response to the occurrence of a vertical synchronization signal, is also obtained. The delay time from the occurrence of the vertical synchronization signal to the start of the free-running counter measurement interrupt process is calculated using the count value of the predetermined counter 500. Therefore, by subtracting the delay time from the count value of the free-running counter 400, the exact timing of the occurrence of the vertical synchronization signal can be calculated, and consequently, the period of the vertical synchronization signal can be accurately measured. This allows for accurate measurement of the period of the vertical synchronization signal even if the free-running counter measurement interrupt process (i.e., the interrupt process for period measurement) is delayed by other interrupt processes with higher priority. For example, this allows for more flexibility in the interrupt design of the software, enabling lower priority for the interrupt process for period measurement, higher priority for other interrupt processes, or relaxation of constraints on other interrupt processes. Furthermore, avoiding duplicate interrupt processes reduces the load on the CPU.

[0036] Although the example described uses a vertical synchronization signal as the specified signal, the specified signal is not limited to a vertical synchronization signal; it is any signal that occurs periodically in the processing of video signals.

[0037] Next, examples of applications of the video signal processing device 100 will be explained using Figures 4 to 6.

[0038] Figure 4 is a block diagram showing an example of a video display system 1 to which the video signal processing device 100 according to the embodiment is applied. In addition to the video display system 1, Figure 4 also shows a camera 200 and an LCD panel 300.

[0039] Camera 200 captures images and outputs a video signal indicating the captured images to the video display system 1. For example, when camera 200 is used with an electronic mirror, camera 200 changes the exposure time according to the ambient brightness and dynamically changes the vertical synchronization signal output from camera 200. For example, camera 200 dynamically changes the vertical synchronization signal between 60 Hz and 30 Hz. Under the condition that the input and output horizontal periods are the same, a 30 Hz input video signal is input into the effective area at the same speed as a 60 Hz signal, but the vertical blanking becomes twice as long, resulting in a 30 Hz video signal per frame. Camera 200 is a camera that lengthens vertical blanking as a means of making the vertical period 30 Hz, and the video display system 1 receives the input video signal from such camera 200.

[0040] The LCD panel 300 is an example of a display that receives the output video signal from the video display system 1. Specifically, the input video signal from the camera 200 to the video display system 1 is output from the video display system 1 to the LCD panel 300 as an output video signal. For example, if the refresh rate of the LCD panel 300 is 60 Hz, and the vertical synchronization signal output from the camera 200 changes from 60 Hz to 30 Hz, the LCD panel 300 may not be able to display the image correctly.

[0041] Therefore, the following describes a video signal processing device 100 and a video display system 1 that enable the LCD panel 300 to display correctly even when the vertical synchronization signal of the input video signal changes dynamically.

[0042] The video display system 1 includes a video input unit 110, a memory 120, a video output unit 130, and a video signal processing device 100.

[0043] The video input unit 110 is an interface that receives the input video signal output from the camera 200. The video input unit 110 outputs the input video signal to the memory 120 and also outputs the input synchronization signal, which is the vertical synchronization signal of the input video signal, to the video signal processing device 100.

[0044] The memory 120 is a frame memory that holds video. For example, the memory 120 has at least a one-bank configuration. When the input video signal and the output video signal are synchronized, the memory 120 may have a one-bank configuration. By starting output at the timing when an image of the input video signal has been written to about half of the bank, display can be performed without outputting an image in the middle of writing. Note that when the input video signal and the output video signal are not synchronized, the memory 120 may require two or more banks.

[0045] The video output unit 130 is an interface that outputs the video signal held in the memory 120. The video output unit 130 outputs the video signal held in the memory 120 as an output video signal to the LCD panel 300.

[0046] The video signal processing device 100 includes an interrupt processing unit 101, a delay time calculation unit 102, a signal generation timing calculation unit 103, and a cycle measurement unit 104, and further includes a correction value control unit 10, a PLL (Phase Locked Loop) 20, a pixel counter 30, a line counter 40, and a synchronization generation unit 50. Note that illustration of the interrupt processing unit 101, the delay time calculation unit 102, the signal generation timing calculation unit 103, and the cycle measurement unit 104 is omitted here. For example, the correction value control unit 10 and the synchronization generation unit 50 may be implemented by a processor or the like that executes a program stored in a memory.

[0047] The correction value control unit 10 acquires an input synchronization signal, and determines whether the cycle of the input synchronization signal is equal to or greater than a switching threshold that is larger than the cycle corresponding to the refresh rate of an LCD panel 300 to which an output video signal is input. The switching threshold is an example of a predetermined threshold. The correction value control unit 10 acquires the cycle of the input synchronization signal from a cycle measurement unit 104. When the correction value control unit 10 determines that the cycle of the input synchronization signal is equal to or greater than the switching threshold, it generates a set cycle based on a 1 / N cycle of the input synchronization signal (N is an integer of 2 or greater), and when it determines that the cycle of the input synchronization signal is less than the switching threshold, it generates the set cycle based on the cycle of the input synchronization signal. The correction value control unit 10 also compares the phase difference between the phase of the input synchronization signal and the phase of an output synchronization signal, which is the vertical synchronization signal of the output video signal, with a target phase difference, generates a correction value that causes the phase difference to approach the target phase difference based on the comparison result, and further generates the set cycle based on the correction value. Details of the operation of the correction value control unit 10 will be described later.

[0048] The PLL 20 generates a pixel clock for a pixel counter 30. For example, the correction value control unit 10 outputs a clock cycle generated based on the set cycle to the PLL 20, and the PLL 20 generates the pixel clock based on the clock cycle. For example, in the following description, it is assumed that the input vertical frequency is 60 Hz, the number of output pixels is 1650 pixels, and the number of output lines is 750 lines. When the set cycle is a cycle corresponding to 60 Hz, which is the input vertical frequency, while the number of pixels of the output video signal (the number of horizontal pixels × the number of vertical lines) is 1650×750, the PLL 20 generates a pixel clock of (60×1650×750) Hz.

[0049] The pixel counter 30 outputs a signal to a line counter 40 each time it counts pixels corresponding to the number of horizontal pixels of the output video signal. For example, the pixel counter 30 counts 1650 pixels as pixels for one line, and notifies the line counter 40 that it has counted pixels for one line.

[0050] The line counter 40 outputs a signal to the synchronization generation unit 50 each time it counts a number of lines equal to the vertical lines of the output video signal. For example, the line counter 40 counts 750 lines as one frame and notifies the synchronization generation unit 50 that it has counted one frame's worth of lines.

[0051] The pixel counter 30 or line counter 40 is an example of a predetermined counter 500.

[0052] The synchronization generation unit 50 generates an output synchronization signal, which is a vertical synchronization signal for the output video signal, based on the set period. Specifically, the timing at which the line counter 40 counts one frame of lines is at a frequency corresponding to the set period, and the synchronization generation unit 50 generates an output synchronization signal with a frequency corresponding to the set period. As described above, if the set period corresponds to the input vertical frequency of 60 Hz, the synchronization generation unit 50 generates an output synchronization signal of 60 Hz.

[0053] Next, the operation of the video display system 1 will be explained in detail using Figure 5.

[0054] Figure 5 is a flowchart showing an example of the operation of the video display system 1 according to the embodiment.

[0055] First, the interrupt processing unit 101 determines whether or not an input Vsync (vertical synchronization) interrupt has occurred for the input video signal (step S11). In other words, the interrupt processing unit 101 determines whether or not it has acquired the input synchronization signal. In this example, the predetermined signal is the input synchronization signal.

[0056] If it is determined that an input Vsync interrupt has occurred (Yes in step S11), the delay time calculation unit 102 calculates the delay time Td = count value Cl × horizontal period Ph for the input synchronization signal (step S12).

[0057] Next, the period measurement unit 104 measures the period of the input Vsync (i.e., the period of the input synchronization signal) and records the time of the interrupt of the input Vsync (step S13). Specifically, the period measurement unit 104 measures the period Pvi of the input synchronization signal by calculating the current count value Tnow - previous count value Tvi - delay time Td. Furthermore, for the measurement of the next period, the period measurement unit 104 records the current count value Tnow as the time of the interrupt of the previous input Vsync in the measurement of the next period by substituting the current count value Tnow for the previous count value Tvi.

[0058] If it is determined that no input Vsync interrupt has occurred (No in step S11), the processing in steps S12 and S13 is skipped.

[0059] Next, the correction value control unit 10 determines whether the period Pvi of the input Vsync is greater than or equal to a threshold (switching threshold) (step S14). For example, if the refresh rate of the LCD panel 300 is 60 Hz, the period corresponding to that refresh rate is (1 / 60) sec, and the switching threshold is (1 / 40) sec, which is greater than (1 / 60) sec. When the camera 200 changes the vertical synchronization signal from 60 Hz to 30 Hz, the period of the input Vsync becomes (1 / 30) sec, which is greater than or equal to the switching threshold (1 / 40) sec. Therefore, in such a case, the correction value control unit 10 determines that the period of the input Vsync is greater than or equal to the switching threshold.

[0060] If the correction value control unit 10 determines that the period of the input Vsync is greater than or equal to the switching threshold (Yes in step S14), it generates a set period based on 1 / N times the period of the input Vsync (step S15). As described above, when the camera 200 changes the vertical synchronization signal from 60 Hz to 30 Hz, N = 2. In other words, the correction value control unit 10 generates a set period corresponding to 60 Hz before the camera 200 changes the frequency of the vertical synchronization signal to 30 Hz. The set period is used as the reference for the output Vsync.

[0061] As explained above, when the period of the input sync signal is greater than or equal to the switching threshold, that is, when the period of the input sync signal changes dynamically (specifically, becomes larger), the set period is generated based on 1 / N times the period of the input sync signal. For example, if the refresh rate of the LCD panel 300 is 60 Hz, and the period of the input sync signal doubles (i.e., the frequency changes from 60 Hz to 30 Hz), the set period is generated based on 1 / 2 times the period of the input sync signal, so the frequency of the output sync signal can be maintained at 60 Hz. Therefore, the LCD panel 300 can display correctly even if the vertical sync signal of the input video signal changes dynamically. For example, the image from camera 200, which dynamically changes the output vertical sync signal between 60 Hz and 30 Hz depending on the ambient brightness, can be displayed on the LCD panel 300, which cannot tolerate fluctuations in the period of the vertical sync signal. In particular, because the period of the input sync signal can be measured accurately, the LCD panel 300 can display more correctly even if the vertical sync signal of the input video signal changes dynamically.

[0062] There is a conventional technology that supports a camera 200 that dynamically changes the vertical synchronization signal between 60Hz and 30Hz by providing two or more frame memory banks. However, in such conventional technology, the input synchronization signal and the output synchronization signal are asynchronous, which can cause fluctuations in input / output latency, or result in frames being displayed twice or missing frames. In contrast, the video signal processing device 100 is less prone to such problems.

[0063] Furthermore, there is a conventional technology that allows for the dynamic change of the vertical synchronization signal between 60Hz and 30Hz by adjusting the number of output lines, thus accommodating the camera 200. However, with such conventional technology, the number of lines increases or decreases with each vertical synchronization, and in some cases, the LCD panel 300 may not be able to display correctly. Also, when the input synchronization signal is 30Hz, the error in the output synchronization signal becomes larger compared to when it is 60Hz. In contrast, the video signal processing device 100 is less prone to these problems.

[0064] Next, another example of the operation of the video display system 1 will be explained using Figure 6.

[0065] Figure 6 is a flowchart showing another example of the operation of the video display system 1 according to the embodiment.

[0066] First, the interrupt processing unit 101 determines whether or not an output Vsync (vertical synchronization) interrupt for the output video signal has occurred (step S21). In other words, the interrupt processing unit 101 determines whether or not an output synchronization signal has been acquired. In this example, the predetermined signal is the output synchronization signal.

[0067] If it is determined that no output Vsync interrupt has occurred (No in step S21), the process in step S21 is repeated. In other words, the system waits for an output Vsync interrupt to occur.

[0068] If it is determined that an output Vsync interrupt has occurred (Yes in step S21), the delay time calculation unit 102 calculates the delay time Td = count value Cl × horizontal period Ph for the output synchronization signal (step S22). The delay time for the output synchronization signal can be calculated in the same way as for the input synchronization signal.

[0069] Next, the period measurement unit 104 measures the period of the output Vsync (i.e., the period of the output synchronization signal) and records the time of the interrupt of the output Vsync (step S23). Specifically, the period measurement unit 104 measures the period Pvo of the output synchronization signal by calculating the current count value Tnow - previous count value Tvo - delay time Td. In addition, for the measurement of the next period, the period measurement unit 104 records the current count value Tnow as the time of the interrupt of the previous output Vsync in the measurement of the next period by substituting the current count value Tnow into the previous count value Tvo.

[0070] Next, the correction value control unit 10 calculates the phase difference between the input and output Vsyncs (step S24). Specifically, the correction value control unit 10 calculates the phase difference phase by subtracting the interrupt occurrence time of the latest input Vsync (i.e., count value Tvi) from the interrupt occurrence time of the latest output Vsync (i.e., count value Tvo).

[0071] Next, the correction value control unit 10 calculates the difference between the target phase difference and the phase difference of the input / output Vsync (step S25). Specifically, the correction value control unit 10 calculates the difference diff by subtracting the phase difference phase from the target phase difference target.

[0072] Next, the correction value control unit 10 calculates an adjustment value (in other words, a correction value) (step S26). Specifically, the correction value control unit 10 calculates the adjustment value adjuster by multiplying the difference diff between the target phase difference and the phase difference of input / output Vsync by a correction gain gain.

[0073] Next, the correction value control unit 10 calculates the period of the target output Vsync (step S27). For example, the correction value control unit 10 calculates the period obtained by adding the adjustment value adjuster to the period Pvi of the input Vsync as the period Pvt of the output Vsync (i.e., the set period), and outputs it to the PLL 20.

[0074] The PLL 20 calculates the output clock frequency (in other words, the pixel clock frequency) using the set period output from the correction value control unit 10. Specifically, the PLL 20 calculates the output clock frequency f_clko by (1 / Pvt) × (width of the output image (i.e., number of horizontal pixels)) × (height of the output image (i.e., number of vertical lines)).

[0075] The PLL20 then changes the output clock frequency. This allows the next output Vsync interrupt to be generated so that the period of the output Vsync becomes the target period Pvt, that is, so that the phase difference phase approaches the target phase difference target. For example, if the phase difference phase is smaller than the target phase difference target, the output clock frequency becomes lower, and as a result the period of the output Vsync becomes larger. Therefore, the phase difference phase becomes larger and approaches the target phase difference target.

[0076] As explained above, if there is a variation in the phase difference between the input sync signal and the output sync signal, it becomes necessary to temporarily store the video data corresponding to the variation, which increases the frame memory capacity. Therefore, by maintaining the above phase difference at the target phase difference, the required frame memory capacity can be reduced. For example, the memory 120 can be configured with only one bank. In particular, since the generation timing of the input sync signal and the generation timing of the output sync signal can be calculated accurately, the above phase difference can be maintained at the target phase difference more accurately.

[0077] (Other Embodiments) Embodiments have been described above as examples of the technology relating to this disclosure. However, the technology relating to this disclosure is not limited thereto and can be applied to embodiments that are modified, replaced, added to, or omitted as appropriate. For example, the following modified examples are also included in one embodiment of this disclosure.

[0078] For example, this disclosure can be implemented not only as a video signal processing device 100, but also as a video signal processing method that includes steps (processing) performed by the components constituting the video signal processing device 100.

[0079] Figure 7 is a flowchart showing an example of a video signal processing method according to another embodiment.

[0080] The video signal processing method is a video signal processing method performed by a video signal processing device 100 that measures the period of a predetermined signal that occurs periodically in the processing of a video signal, and includes, as shown in Figure 7, the steps of: acquiring the count value of a free-run counter 400 by performing an interrupt processing when a predetermined signal occurs (step S101); calculating a delay time from the occurrence of a predetermined signal to the start of interrupt processing based on the count value of a predetermined counter 500 that is periodically reset in response to the occurrence of a predetermined signal (step S102); calculating the timing when a predetermined signal occurs by subtracting the delay time from the count value of the free-run counter 400 acquired by the interrupt processing (step S103); and measuring the period of a predetermined signal by calculating the difference between the timing when the predetermined signal occurred this time and the timing when the predetermined signal occurred last time (step S104).

[0081] For example, this disclosure can be implemented as a program that causes a computer (processor) to execute steps included in a video signal processing method. Furthermore, this disclosure can be implemented as a non-temporary computer-readable recording medium, such as a CD-ROM, on which the program is recorded.

[0082] For example, if this disclosure is implemented in a program (software), each step is executed by the program using hardware resources such as the computer's CPU, memory, and input / output circuits. In other words, each step is executed by the CPU obtaining data from memory or input / output circuits, performing calculations, and outputting the calculation results to memory or input / output circuits.

[0083] In the above embodiment, each component included in the video signal processing device 100 may be implemented by dedicated hardware or by executing a software program suitable for each component. Each component may also be implemented by a program execution unit such as a CPU or processor reading and executing a software program recorded on a recording medium such as a hard disk or semiconductor memory.

[0084] Some or all of the functions of the video signal processing device 100 according to the above embodiment are typically implemented as an LSI, which is an integrated circuit. These may be individually integrated onto a single chip, or some or all of them may be integrated onto a single chip. Furthermore, the implementation is not limited to an LSI, but may also be implemented using dedicated circuits or general-purpose processors. An FPGA (Field Programmable Gate Array) that can be programmed after LSI manufacturing, or a reconfigurable processor that can reconfigure the connections and settings of circuit cells inside the LSI may also be used.

[0085] Furthermore, if advances in semiconductor technology or other derived technologies lead to the emergence of integrated circuit technology that can replace LSIs, then naturally, that technology may be used to integrate each component included in the video signal processing device 100 into an integrated circuit.

[0086] Furthermore, this disclosure also includes forms obtained by applying various modifications to the embodiments that a person skilled in the art could conceive, and forms realized by arbitrarily combining the components and functions of each embodiment without departing from the spirit of this disclosure.

[0087] (Note) The above description of embodiments discloses the following technology.

[0088] (Technical 1) A video signal processing device for measuring the period of a predetermined signal that occurs periodically in the processing of a video signal, comprising: an interrupt processing unit that performs an interrupt processing to acquire the count value of a free-run counter when the predetermined signal occurs; a delay time calculation unit that calculates a delay time from the occurrence of the predetermined signal to the start of the interrupt processing based on the count value of a predetermined counter that is periodically reset in response to the occurrence of the predetermined signal; a signal generation timing calculation unit that calculates the timing at which the predetermined signal occurs by subtracting the delay time from the count value of the free-run counter acquired by the interrupt processing; and a period measurement unit that measures the period of the predetermined signal by calculating the difference between the timing at which the predetermined signal occurred this time and the timing at which the predetermined signal occurred last time.

[0089] According to this method, while the count value of a free-running counter is obtained via interrupt processing, the count value of a predetermined counter, which is periodically reset in response to the occurrence of a predetermined signal, is also obtained. The delay time from the occurrence of the predetermined signal to the start of the interrupt processing is then calculated using the count value of the predetermined counter. Therefore, by subtracting the delay time from the count value of the free-running counter, the precise timing of the occurrence of the predetermined signal can be calculated, and consequently, the period of the predetermined signal can be accurately measured. This allows for the accurate measurement of the period of a predetermined signal that occurs periodically in video signal processing, even if the interrupt processing for obtaining the count value of the free-running counter (i.e., the interrupt processing for period measurement) is delayed by other interrupt processing with higher priority. For example, this allows for more flexibility in the interrupt design of the software, enabling lower priority for the interrupt processing for period measurement, higher priority for other interrupt processing, or relaxation of constraints on other interrupt processing. Furthermore, avoiding duplicate interrupt processing reduces the load on the CPU.

[0090] (Technical 2) The video signal processing apparatus according to Technical 1, wherein the predetermined signal is a vertical synchronization signal.

[0091] According to this method, the period of the vertical synchronization signal can be accurately measured.

[0092] (Technical 3) The video signal processing apparatus according to Technical 2, wherein the predetermined counter is a line counter.

[0093] According to this, by using a line counter, the delay time from the generation of the vertical synchronization signal to the start of interrupt processing can be calculated.

[0094] (Technical 4) The video signal processing apparatus according to Technical 2, wherein the predetermined counter is a pixel counter.

[0095] According to this method, the delay time from the generation of the vertical synchronization signal to the start of interrupt processing can be calculated by using a pixel counter.

[0096] (Technical 5) A video signal processing device according to any one of Technical 2 to 4, further comprising a correction value control unit and a synchronization generation unit, wherein the predetermined signal is an input synchronization signal which is a vertical synchronization signal of an input video signal, the correction value control unit determines whether the period of the input synchronization signal is greater than or equal to a predetermined threshold which is greater than the period corresponding to the refresh rate of a display to which the output video signal is input, and if it determines that the period of the input synchronization signal is greater than or equal to the predetermined threshold, it generates a set period based on a period of 1 / N times the input synchronization signal (where N is an integer of 2 or more), and if it determines that the period of the input synchronization signal is less than the predetermined threshold, it generates the set period based on the period of the input synchronization signal, and the synchronization generation unit generates an output synchronization signal which is a vertical synchronization signal of the output video signal based on the set period.

[0097] According to this, if the period of the input synchronization signal is above a predetermined threshold, that is, if the period of the input synchronization signal changes dynamically (specifically, increases), the set period is generated based on 1 / N times the period of the input synchronization signal. For example, if the refresh rate of the display is 60 Hz, and the period of the input synchronization signal doubles (i.e., the frequency changes from 60 Hz to 30 Hz), the set period is generated based on 1 / 2 times the period of the input synchronization signal, so the frequency of the output synchronization signal can be maintained at 60 Hz. Therefore, the display can display correctly even if the vertical synchronization signal of the input video signal changes dynamically. In particular, because the period of the input synchronization signal can be measured accurately, the display can display more correctly even if the vertical synchronization signal of the input video signal changes dynamically.

[0098] (Technical 6) The video signal processing apparatus according to Technical 5, wherein the correction value control unit compares the phase difference between the phase of the input synchronization signal and the phase of the output synchronization signal with a target phase difference, generates a correction value based on the result of the comparison such that the phase difference approaches the target phase difference, and further generates the set period based on the correction value.

[0099] According to this, if there is a variation in the phase difference between the input sync signal and the output sync signal, it is necessary to temporarily store the video data corresponding to the variation, which increases the frame memory capacity. Therefore, by maintaining the above phase difference at a target phase difference, the required frame memory capacity can be reduced. For example, the frame memory can be configured with only one bank. In particular, because the generation timing of the input sync signal and the generation timing of the output sync signal can be calculated accurately, the above phase difference can be maintained at the target phase difference more accurately.

[0100] (Technical 7) A video signal processing method performed by a video signal processing device that measures the period of a predetermined signal that occurs periodically in the processing of a video signal, the method comprising: obtaining a count value of a free-running counter by performing an interrupt process when the predetermined signal occurs; calculating a delay time from the occurrence of the predetermined signal to the start of the interrupt process based on the count value of a predetermined counter that is periodically reset in response to the occurrence of the predetermined signal; calculating the timing at which the predetermined signal occurs by subtracting the delay time from the count value of the free-running counter obtained by the interrupt process; and measuring the period of the predetermined signal by calculating the difference between the timing at which the predetermined signal occurred this time and the timing at which the predetermined signal occurred last time.

[0101] This provides a video signal processing method that can accurately measure the period of a predetermined signal that occurs periodically during video signal processing.

[0102] This disclosure can be applied to systems that display images from a camera that dynamically changes the output vertical synchronization signal on a display device.

[0103] 1 Video display system 10 Correction value control unit 20 PLL 30 Pixel counter 40 Line counter 50 Synchronization generation unit 100 Video signal processing unit 101 Interrupt processing unit 102 Delay time calculation unit 103 Signal generation timing calculation unit 104 Period measurement unit 110 Video input unit 120 Memory 130 Video output unit 200 Camera 300 LCD panel 400 Free-run counter 500 Predetermined counter

Claims

1. A video signal processing device for measuring the period of a predetermined signal that occurs periodically in the processing of a video signal, comprising: an interrupt processing unit that performs an interrupt processing to acquire the count value of a free-run counter when the predetermined signal occurs; a delay time calculation unit that calculates a delay time from the occurrence of the predetermined signal to the start of the interrupt processing based on the count value of a predetermined counter that is periodically reset in response to the occurrence of the predetermined signal; a signal generation timing calculation unit that calculates the timing at which the predetermined signal occurs by subtracting the delay time from the count value of the free-run counter acquired by the interrupt processing; and a period measurement unit that measures the period of the predetermined signal by calculating the difference between the timing at which the predetermined signal occurred this time and the timing at which the predetermined signal occurred last time.

2. The video signal processing apparatus according to claim 1, wherein the predetermined signal is a vertical synchronization signal.

3. The video signal processing apparatus according to claim 2, wherein the predetermined counter is a line counter.

4. The video signal processing apparatus according to claim 2, wherein the predetermined counter is a pixel counter.

5. The video signal processing apparatus according to any one of claims 2 to 4, further comprising a correction value control unit and a synchronization generation unit, wherein the predetermined signal is an input synchronization signal which is a vertical synchronization signal of an input video signal, the correction value control unit determines whether the period of the input synchronization signal is greater than or equal to a predetermined threshold which is greater than the period corresponding to the refresh rate of a display to which the output video signal is input, and if it is determined that the period of the input synchronization signal is greater than or equal to the predetermined threshold, it generates a set period based on a period of 1 / N times the input synchronization signal (where N is an integer of 2 or more), and if it is determined that the period of the input synchronization signal is less than the predetermined threshold, it generates the set period based on the period of the input synchronization signal, and the synchronization generation unit generates an output synchronization signal which is a vertical synchronization signal of the output video signal based on the set period.

6. The video signal processing apparatus according to claim 5, wherein the correction value control unit compares the phase difference between the phase of the input synchronization signal and the phase of the output synchronization signal with a target phase difference, generates a correction value based on the result of the comparison such that the phase difference approaches the target phase difference, and further generates the set period based on the correction value.

7. A video signal processing method performed by a video signal processing device that measures the period of a predetermined signal that occurs periodically in the processing of a video signal, comprising: a step of obtaining a count value of a free-running counter by performing an interrupt process when the predetermined signal occurs; a step of calculating a delay time from the occurrence of the predetermined signal to the start of the interrupt process based on the count value of a predetermined counter that is periodically reset in response to the occurrence of the predetermined signal; a step of calculating the timing when the predetermined signal occurs by subtracting the delay time from the count value of the free-running counter obtained by the interrupt process; and a step of measuring the period of the predetermined signal by calculating the difference between the timing when the predetermined signal occurred this time and the timing when the predetermined signal occurred last time.

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