Reference voltage generation circuit, ldo circuit, and control method

Abstract

A reference voltage generation circuit (10) comprises a resistor (R11), a resistor (R12), a switch (SW1), a switch (SW2), a switch (SW3), a capacitor (C1), and a capacitor (Cref). The switch (SW1) and the switch (SW3) turn on, then the switch (SW3) turns off, and then the switch (SW1) turns off and the switch (SW2) turns on.

Description

Reference Voltage Generation Circuit, LDO Circuit, and Control Method

[0001] The present disclosure relates to a reference voltage generation circuit that generates a reference voltage and the like.

[0002] Patent Documents 1 to 3 disclose technologies related to a reference voltage generation circuit that generates a reference voltage for an amplifier circuit, a voltage monitoring circuit, or an LDO (Low Dropout Regulator) circuit.

[0003] Japanese Patent Application Laid-Open No. 2024-117327, Japanese Patent Application Laid-Open No. 2021-071392, Japanese Patent Application Laid-Open No. 2015-132990

[0004] There is a reference voltage generation circuit capable of transitioning a reference voltage. Such a reference voltage generation circuit uses a plurality of voltage dividing resistors and a switch to transition the reference voltage. The transition time required to transition the reference voltage is determined by the product of the sum of resistance values of the plurality of voltage dividing resistors and the capacitance of a capacitor for suppressing noise. To shorten the transition time, it is conceivable to (i) reduce the resistance values of the plurality of voltage dividing resistors, or (ii) reduce the capacitance of the capacitor. However, the method (i) has a problem of increased current consumption, and the method (ii) has a problem of degraded noise characteristics (for example, reduced stability of an error amplifier of an LDO circuit).

[0005] Accordingly, the present disclosure provides a reference voltage generation circuit and the like that can speed up the transition of a reference voltage while suppressing an increase in current consumption and degradation of noise characteristics.

[0006] The reference voltage generation circuit according to this disclosure comprises a first resistor, a second resistor, a first switch, a second switch, a third switch, a first capacitor, and a second capacitor, wherein the first resistor and the second resistor are connected in series with each other between a power supply and ground, from ground to the power supply in the order of the first resistor and the second resistor, one end of the first switch is connected to a first node between ground and the first resistor, one end of the second switch is connected to a second node between the first resistor and the second resistor, and one end of the third switch is connected to a second node between the second resistor and the power supply. The three switches are connected to a third node, the other end of the third switch is connected to an output terminal, one end of the first capacitor is connected to a fourth node between the other end of the third switch and the output terminal, the other end of the first capacitor is connected to the other end of the first switch and the other end of the second switch, one end of the second capacitor is connected to the fourth node, and the other end of the second capacitor is connected to ground. The first and third switches are turned on, then the third switch is turned off, then the first switch is turned off, and the second switch is turned on.

[0007] The reference voltage generation circuit according to this disclosure comprises a first resistor, a second resistor, a first switch, a second switch, a third switch, a first capacitor, and a second capacitor, wherein the first resistor and the second resistor are connected in series with each other between a power supply and ground, from ground to the power supply in the order of the first resistor and the second resistor, one end of the first switch is connected to a first node between ground and the first resistor, one end of the second switch is connected to a second node between the first resistor and the second resistor, and one end of the third switch is connected to a second node between the second resistor and the power supply. The third switch is connected to three nodes, the other end of the third switch is connected to an output terminal, one end of the first capacitor is connected to a fourth node between the other end of the third switch and the output terminal, the other end of the first capacitor is connected to the other end of the first switch and the other end of the second switch, one end of the second capacitor is connected to the fourth node, the other end of the second capacitor is connected to ground, the second switch and the third switch are turned on, then the third switch is turned off, then the second switch is turned off, and the first switch is turned on.

[0008] The LDO circuit according to this disclosure comprises the above-mentioned reference voltage generation circuit, an error amplifier, an output driver, and a feedback resistor connected between the output driver and ground, wherein the error amplifier controls the output driver based on the difference between the reference voltage output from the output terminal and the voltage generated across the feedback resistor.

[0009] The control method according to this disclosure is a control method for a reference voltage generation circuit, the reference voltage generation circuit comprising a first resistor, a second resistor, a first switch, a second switch, a third switch, a first capacitor, and a second capacitor, wherein the first resistor and the second resistor are connected in series with each other between a power source and ground, from ground to the power source in the order of the first resistor and the second resistor, one end of the first switch is connected to a first node between ground and the first resistor, one end of the second switch is connected to a second node between the first resistor and the second resistor, and one end of the third switch is connected to the second resistor and The third switch is connected to a third node between it and the power supply, the other end of the third switch is connected to an output terminal, one end of the first capacitor is connected to a fourth node between the other end of the third switch and the output terminal, the other end of the first capacitor is connected to the other end of the first switch and the other end of the second switch, one end of the second capacitor is connected to the fourth node, and the other end of the second capacitor is connected to ground. In the control method, the first switch and the third switch are turned on, then the third switch is turned off, then the first switch is turned off, and the second switch is turned on.

[0010] The control method according to this disclosure is a control method for a reference voltage generation circuit, the reference voltage generation circuit comprising a first resistor, a second resistor, a first switch, a second switch, a third switch, a first capacitor, and a second capacitor, wherein the first resistor and the second resistor are connected in series with each other between a power source and ground, from ground to the power source in the order of the first resistor and the second resistor, one end of the first switch is connected to a first node between ground and the first resistor, one end of the second switch is connected to a second node between the first resistor and the second resistor, and one end of the third switch is connected to the second resistor and The third switch is connected to a third node between it and the power supply, the other end of the third switch is connected to an output terminal, one end of the first capacitor is connected to a fourth node between the other end of the third switch and the output terminal, the other end of the first capacitor is connected to the other end of the first switch and the other end of the second switch, one end of the second capacitor is connected to the fourth node, and the other end of the second capacitor is connected to ground. In the control method, the second switch and the third switch are turned on, then the third switch is turned off, then the second switch is turned off, and the first switch is turned on.

[0011] These comprehensive or specific embodiments may be implemented as a system, method, integrated circuit, computer program, or recording medium such as a computer-readable CD-ROM, or as any combination of a system, method, integrated circuit, computer program, and recording medium.

[0012] According to one aspect of this disclosure, a reference voltage generation circuit, etc., enables faster transitions of the reference voltage while suppressing an increase in current consumption and deterioration of noise characteristics.

[0013] This is a circuit diagram showing an example of an LDO circuit according to a comparative example. This is a timing chart showing an example of switching of each switch according to a comparative example. This is a circuit diagram showing an example of an LDO circuit according to Embodiment 1. This is a timing chart showing a first example of switching of each switch in the reference voltage generation circuit according to Embodiment 1. This is a timing chart showing a second example of switching of each switch in the reference voltage generation circuit according to Embodiment 1. This is a circuit diagram showing an example of an LDO circuit according to Embodiment 2. This is a timing chart showing an example of switching of each switch in the reference voltage generation circuit according to Embodiment 2. This is a flowchart showing a first example of a control method according to another embodiment. This is a flowchart showing a second example of a control method according to another embodiment.

[0014] (Background leading to one aspect of this disclosure) First, the background leading to one aspect of this disclosure will be explained using Figures 1 and 2.

[0015] Figure 1 is a circuit diagram showing an example of an LDO circuit 100a according to a comparative example.

[0016] The LDO circuit 100a is a linear regulator that can operate even when the difference between the input voltage and the output voltage is small. The LDO circuit 100a comprises a reference voltage generation circuit 10a, an error amplifier 20, an output driver 30, and resistors Rf and Rs. Resistors Rf and Rs are examples of feedback resistors connected between the output driver 30 and ground. Note that resistor Rf may be omitted.

[0017] The error amplifier 20 controls the output driver 30 based on the difference between the reference voltage output from the output terminal t1 of the reference voltage generation circuit 10a and the voltage generated across the feedback resistor. Specifically, the error amplifier 20 compares the reference voltage (VREF output) generated by the reference voltage generation circuit 10a with the feedback voltage (voltage generated across the feedback resistor) corresponding to the output voltage (LDO output) of the LDO circuit 100a, and controls the output driver 30 according to the relative magnitudes of these two voltages.

[0018] The output driver 30 controls the output voltage of the LDO circuit 100a in accordance with the output of the error amplifier 20. Specifically, when the output voltage of the LDO circuit 100a is greater than the reference voltage, the resistance component of the output driver 30 increases in accordance with the output of the error amplifier 20, and the feedback voltage corresponding to the output voltage of the LDO circuit 100a decreases so as to approach the reference voltage. Conversely, when the output voltage of the LDO circuit 100a is less than the reference voltage, the resistance component of the output driver 30 decreases in accordance with the output of the error amplifier 20, and the feedback voltage corresponding to the output voltage of the LDO circuit 100a increases so as to approach the reference voltage. This makes it possible to set the output voltage of the LDO circuit 100a to a target voltage corresponding to the reference voltage.

[0019] The reference voltage generation circuit 10a generates a reference voltage that is input to the error amplifier 20. The reference voltage generation circuit 10a comprises a power supply 1, a control circuit 2a, resistors R1 and R2, switches SWA and SWB, a capacitor Cref, and an output terminal t1. The output terminal t1 is connected to the input terminal of the error amplifier 20, and the reference voltage generated by the reference voltage generation circuit 10a is input to the error amplifier 20.

[0020] For example, power supply 1 is a constant current source. Power supply 1 may also be a constant voltage source. Furthermore, the reference voltage generation circuit 10a does not necessarily have power supply 1, and power supply 1 may be provided outside the reference voltage generation circuit 10a.

[0021] The control circuit 2a controls switches SWA and SWB. The reference voltage generation circuit 10a does not necessarily have to include the control circuit 2a, and the control circuit 2a may be located outside the reference voltage generation circuit 10a. For example, the control circuit 2a may be provided in the LDO circuit 100a, or in the device on which the LDO circuit 100a is installed.

[0022] Resistors R1 and R2 are connected in series between power supply 1 and ground, with R1 connected to power supply 1 from ground, and R2 connected to power supply 1 in that order.

[0023] One end of switch SWA is connected to the node between resistors R1 and R2, and the other end of switch SWA is connected to output terminal t1. One end of switch SWB is connected to the node between resistor R2 and power supply 1, and the other end of switch SWB is connected to output terminal t1.

[0024] One end of capacitor Cref is connected to the node between the other ends of switches SWA and SWB and output terminal t1, and the other end of capacitor Cref is connected to ground.

[0025] The control circuit 2a switches the reference voltage generated by the reference voltage generation circuit 10a between a first reference voltage and a second reference voltage by controlling switches SWA and SWB. Specifically, when the control circuit 2a turns on switch SWA and turns off switch SWB, a voltage V1 is generated as the first reference voltage, which is the product of the resistance value of resistor R1 and the bias current of power supply 1. When the control circuit 2a turns off switch SWA and turns on switch SWB, a voltage V2 is generated as the second reference voltage, which is the product of the sum of the resistance values ​​of resistors R1 and R2 and the bias current of power supply 1.

[0026] Here, the problem of the reference voltage generation circuit 10a related to the comparative example will be explained using Figure 2.

[0027] Figure 2 is a timing chart showing an example of the switching of each switch in the comparative example.

[0028] As shown in Figure 2, when switching from the first reference voltage to the second reference voltage, switch SWA is controlled from the ON state to the OFF state, and switch SWB is controlled from the OFF state to the ON state. At this time, the transition time required to transition from the first reference voltage to the second reference voltage is determined by the product of the sum of the resistance values ​​of resistors R1 and R2 and the capacitance of capacitor Cref. If the resistance value of resistor R1 is R1, the resistance value of resistor R2 is R2, and the capacitance of capacitor Cref is Cref, then the product is expressed as (R1 + R2) × Cref. Also, when switching from the second reference voltage to the first reference voltage, switch SWA is controlled from the OFF state to the ON state, and switch SWB is controlled from the ON state to the OFF state. At this time, the transition time required to transition from the second reference voltage to the first reference voltage is determined by the product of the resistance value of resistor R1 and the capacitance of capacitor Cref, R1 × Cref.

[0029] Since the switching of the reference voltage needs to be done as quickly as possible, the transition time needs to be shortened. To shorten the transition time, one could consider reducing the resistance values ​​of resistors R1 and R2, or reducing the capacitance of capacitor Cref. However, reducing the resistance values ​​of resistors R1 and R2 has the problem of increasing current consumption. Reducing the capacitance of capacitor Cref has the problem of degrading the noise characteristics (for example, the stability of error amplifier 20 decreases).

[0030] Therefore, the following will specifically describe, with reference to the diagrams, a reference voltage generation circuit, an LDO circuit, and a control method that enable faster transitions of the reference voltage while suppressing increases in current consumption and deterioration of noise characteristics.

[0031] The embodiments described below are all general or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit this disclosure.

[0032] (Embodiment 1) The reference voltage generation circuit and LDO circuit according to Embodiment 1 will be described below.

[0033] Figure 3 is a circuit diagram showing an example of an LDO circuit 100 according to Embodiment 1.

[0034] The LDO circuit 100 is a linear regulator that can operate even when the difference between the input voltage and the output voltage is small. The LDO circuit 100 comprises a reference voltage generation circuit 10, an error amplifier 20, an output driver 30, and resistors Rf and Rs.

[0035] The LDO circuit 100 differs from the comparative example LDO circuit 100a in that it includes a reference voltage generation circuit 10 instead of a reference voltage generation circuit 10a. Other aspects are the same as those of the LDO circuit 100a, so the following explanation will focus on the differences from the comparative example.

[0036] The reference voltage generation circuit 10 generates a reference voltage that is input to the error amplifier 20. The reference voltage generation circuit 10 comprises a power supply 1, a control circuit 2, resistors R11 and R12, switches SW1, SW2 and SW3, capacitors C1 and Cref, and an output terminal t1. Resistor R11 is an example of a first resistor. Resistor R12 is an example of a second resistor. Switch SW1 is an example of a first switch. Switch SW2 is an example of a second switch. Switch SW3 is an example of a third switch. Capacitor C1 is an example of a first capacitor. Capacitor Cref is an example of a second capacitor. The output terminal t1 is connected to the input terminal of the error amplifier 20, and the reference voltage generated by the reference voltage generation circuit 10 is input to the error amplifier 20.

[0037] For example, power supply 1 is a constant current source. Power supply 1 may also be a constant voltage source. Furthermore, the reference voltage generation circuit 10 does not necessarily have a power supply 1, and power supply 1 may be provided outside the reference voltage generation circuit 10.

[0038] Control circuit 2 controls switches SW1, SW2, and SW3. Note that the reference voltage generation circuit 10 does not necessarily have control circuit 2, and control circuit 2 may be located outside the reference voltage generation circuit 10. For example, control circuit 2 may be provided in the LDO circuit 100, or in a device equipped with the LDO circuit 100. Control circuit 2 is a computer including a processor and memory. For example, control circuit 2 is a microcontroller.

[0039] Resistors R11 and R12 are connected in series between power supply 1 and ground, with resistor R11 connected from ground to power supply 1, followed by resistor R12.

[0040] One end of switch SW1 (the left terminal in Figure 3) is connected to node N1 between ground and resistor R11. Node N1 is an example of a first node. One end of switch SW2 (the left terminal in Figure 3) is connected to node N2 between resistor R11 and resistor R12. Node N2 is an example of a second node. One end of switch SW3 (the left terminal in Figure 3) is connected to node N3 between resistor R12 and power supply 1. Node N3 is an example of a third node. The other end of switch SW3 (the right terminal in Figure 3) is connected to output terminal t1.

[0041] One end of capacitor C1 (the upper terminal in Figure 3) is connected to node N4, which is located between the other end of switch SW3 and the output terminal t1. Node N4 is an example of a fourth node. The other end of capacitor C1 (the lower terminal in Figure 3) is connected to the other end of switch SW1 (the right terminal in Figure 3) and the other end of switch SW2 (the right terminal in Figure 3).

[0042] One end of capacitor Cref (the upper terminal in Figure 3) is connected to node N4. The other end of capacitor Cref (the lower terminal in Figure 3) is connected to ground.

[0043] Hereinafter, the resistance value of the resistor R2 included in the reference voltage generation circuit 10a according to the comparative example is assumed to be the same as (resistance value of the resistor R11) × (capacitance of the capacitor C1) / (capacitance of the capacitor C1 + capacitance of the capacitor Cref). Further, the resistance value of the resistor R1 included in the reference voltage generation circuit 10a according to the comparative example is assumed to be the same as the combined resistance value of the resistors R11 and R12 included in the reference voltage generation circuit 10 according to the first embodiment. Further, the capacitance of the capacitor Cref included in the reference voltage generation circuit 10a according to the comparative example is assumed to be the same as the capacitance of the capacitor Cref included in the reference voltage generation circuit 10 according to the first embodiment.

[0044] In the reference voltage generation circuit 10, each switch operates as follows. The switches SW1 and SW3 are turned on, then the switch SW3 is turned off, then the switch SW1 is turned off and the switch SW2 is turned on. Alternatively, the switches SW2 and SW3 are turned on, then the switch SW3 is turned off, then the switch SW2 is turned off and the switch SW1 is turned on. Here, a timing chart of switching of each switch will be described with reference to FIG. 4 and FIG. 5.

[0045] First, a timing chart of switching of each switch in the case where switching is performed from the first reference voltage to the second reference voltage and then from the second reference voltage to the first reference voltage will be described with reference to FIG. 4.

[0046] FIG. 4 is a timing chart showing a first example of switching of each switch included in the reference voltage generation circuit 10 according to the first embodiment.

[0047] First, the control circuit 2 turns on the switches SW1 and SW3 and turns off the switch SW2. Accordingly, the voltage V1 corresponding to the product of the sum of the resistance values of the resistors R11 and R12 and the bias current of the power supply 1 is supplied to one end (Vrefp) of the capacitor C1, and the ground voltage V3 is supplied to the other end (Vrefn) of the capacitor C1. That is, the voltage V1 is generated as the first reference voltage, and a potential difference of the voltage V1 minus the voltage V3 is generated across the capacitor C1.

[0048] Next, the control circuit 2 turns off the switch SW3. At this time, electric charge corresponding to the first reference voltage is held in the capacitor C1.

[0049] Next, the control circuit 2 turns off the switch SW1 and turns on the switch SW2. Accordingly, a voltage V4 corresponding to the product of the resistance value of the resistor R11 and the bias current of the power supply 1 is supplied to the other end (Vrefn) of the capacitor C1. Since electric charge of (capacitance of capacitor C1)×(voltage V1 - voltage V3) is held in the capacitor C1, voltage V1 + (voltage V4 - voltage V3) is generated as the second reference voltage.

[0050] As described above, when switching from the first reference voltage to the second reference voltage, the control circuit 2 turns on the switches SW1 and SW3, then turns off the switch SW3, and then turns off the switch SW1 and turns on the switch SW2.

[0051] Furthermore, after the switch SW1 is turned off and the switch SW2 is turned on, the switch SW2 may be turned off and the switch SW1 may be turned on. In other words, after turning off the switch SW1 and turning on the switch SW2, the control circuit 2 may turn off the switch SW2 and turn on the switch SW1. Accordingly, the ground voltage V3 is supplied to the other end (Vrefn) of the capacitor C1. Since electric charge of (capacitance of capacitor C1)×(voltage V1 - voltage V3) is held in the capacitor C1, the voltage V1 is generated as the first reference voltage.

[0052] As described above, when switching back from the second reference voltage to the first reference voltage after switching from the first reference voltage to the second reference voltage, the control circuit 2 turns off the switch SW2 and turns on the switch SW1.

[0053] Next, a timing chart of switching timing of each switch when switching from the first reference voltage to the third reference voltage and then switching back from the third reference voltage to the first reference voltage will be described with reference to FIG. 5.

[0054] FIG. 5 is a timing chart showing a second example of switching of each switch included in the reference voltage generation circuit 10 according to the first embodiment.

[0055] First, the control circuit 2 turns on switches SW2 and SW3, and turns off switch SW1. As a result, a voltage V1 corresponding to the product of the sum of the resistance values ​​of resistors R11 and R12 and the bias current of power supply 1 is supplied to one end (Vrefp) of capacitor C1, and a voltage V4 corresponding to the product of the resistance value of resistor R11 and the bias current of power supply 1 is supplied to the other end (Vrefn) of capacitor C1. In other words, a voltage V1 is generated as a first reference voltage, and a potential difference of voltage V1 - voltage V4 is created across capacitor C1.

[0056] Next, the control circuit 2 turns off switch SW3. At this time, capacitor C1 holds a charge corresponding to the first reference voltage.

[0057] Next, the control circuit 2 turns off switch SW2 and turns on switch SW1. As a result, the ground voltage V3 is supplied to the other end (Vrefn) of capacitor C1. A charge of (capacitance of capacitor C1) × (voltage V1 - voltage V4) is held in capacitor C1, so a third reference voltage of voltage V1 + voltage V3 - voltage V4 is generated. Note that the second reference voltage > first reference voltage > third reference voltage.

[0058] Thus, when the control circuit 2 switches from the first reference voltage to the third reference voltage, it turns on switches SW2 and SW3, then turns off switch SW3, then turns off switch SW2, and turns on switch SW1.

[0059] Alternatively, switch SW2 may be turned off and switch SW1 turned on, then switch SW1 may be turned off and switch SW2 may be turned on. In other words, control circuit 2 may turn off switch SW2 and switch SW1 on, then turn off switch SW1 and switch SW2 on. As a result, a voltage V4 corresponding to the product of the resistance value of resistor R11 and the bias current of power supply 1 is supplied to the other end (Vrefn) of capacitor C1. A charge of (capacitance of capacitor C1) × (voltage V1 - voltage V4) is held in capacitor C1, so a voltage V1 is generated as the first reference voltage.

[0060] Thus, when the control circuit 2 switches from the first reference voltage to the third reference voltage and then back to the first reference voltage, it turns off switch SW1 and turns on switch SW2.

[0061] In the first example of Embodiment 1, the transition time when transitioning from the first reference voltage generated when switches SW1 and SW3 are ON and switch SW2 is OFF to the second reference voltage generated when switches SW1 and SW3 are OFF and switch SW2 is ON is the product of the resistance value of resistor R11 and the combined capacitance of capacitors C1 and Cref connected in series. Similarly, the transition time when transitioning from the second reference voltage generated when switch SW2 is ON and switches SW1 and SW3 are OFF to the first reference voltage generated when switch SW2 is OFF and switch SW1 is ON is the product of the resistance value of resistor R11 and the combined capacitance of capacitors C1 and Cref connected in series.

[0062] In the second example of Embodiment 1, the transition time when transitioning from the first reference voltage generated when switches SW2 and SW3 are ON and switch SW1 is OFF to the third reference voltage generated when switches SW2 and SW3 are OFF and switch SW1 is ON is the product of the resistance value of resistor R11 and the combined capacitance of capacitors C1 and Cref connected in series. Similarly, the transition time when transitioning from the third reference voltage generated when switch SW1 is ON and switches SW2 and SW3 are OFF to the first reference voltage generated when switch SW1 is OFF and switch SW2 is ON is the product of the resistance value of resistor R11 and the combined capacitance of capacitors C1 and Cref connected in series.

[0063] On the other hand, the transition time in the comparative example is the product of the sum of the resistance values ​​of resistor R2 and resistor R1 and the capacitance of capacitor Cref. The resistance value of resistor R11 in Embodiment 1 is smaller than the sum of the resistance values ​​of resistor R2 and resistor R1 in the comparative example, and the combined capacitance of capacitor C1 and Cref in Embodiment 1 is smaller than the capacitance of capacitor Cref in the comparative example.

[0064] Therefore, the reference voltage generation circuit 10 according to Embodiment 1 enables faster transitions of the reference voltage. Furthermore, since the sum of the resistance values ​​of the resistors in the reference voltage generation circuit 10a according to the comparative example and the reference voltage generation circuit 10 according to Embodiment 1 is the same, the current consumption does not increase in Embodiment 1 compared to the comparative example. Also, since the capacitance of the capacitor Cref in the reference voltage generation circuit 10a according to the comparative example and the capacitance of the capacitor Cref in the reference voltage generation circuit 10 according to Embodiment 1 is the same, the noise characteristics do not deteriorate in Embodiment 1 compared to the comparative example. Thus, it is possible to speed up the transitions of the reference voltage while suppressing increases in current consumption and deterioration of noise characteristics.

[0065] (Embodiment 2) Next, the reference voltage generation circuit and LDO circuit according to Embodiment 2 will be described.

[0066] Figure 6 is a circuit diagram showing an example of an LDO circuit 101 according to Embodiment 2.

[0067] The LDO circuit 101 differs from the LDO circuit 100 according to Embodiment 1 in that it includes a reference voltage generation circuit 11 instead of a reference voltage generation circuit 10. Furthermore, the reference voltage generation circuit 11 differs from the reference voltage generation circuit 10 according to Embodiment 1 in that it includes a control circuit 3 instead of a control circuit 2, and also includes a resistor R2 and switches SW4 and SW5. As other aspects are the same as in Embodiment 1, the following description will focus on the differences from Embodiment 1.

[0068] Resistor R2 is an example of a third resistor. Switch SW4 is an example of a fourth switch. Switch SW5 is an example of a fifth switch.

[0069] The control circuit 3 controls switches SW1, SW2, SW3, SW4, and SW5. The reference voltage generation circuit 11 does not necessarily have to include the control circuit 3, and the control circuit 3 may be located outside the reference voltage generation circuit 11. For example, the control circuit 3 may be included in the LDO circuit 101, or in a device equipped with the LDO circuit 101. The control circuit 3 is a computer including a processor and memory. For example, the control circuit 3 is a microcontroller.

[0070] Resistors R11, R12, and R2 are connected in series with respect to the power supply 1 and ground, from ground to power supply 1 in the order of resistor R11, resistor R12, and resistor R2. In Embodiment 2, node N3 is the node between resistor R12 and resistor R2.

[0071] One end of switch SW4 (the left terminal in Figure 6) is connected to node N3. One end of switch SW5 (the left terminal in Figure 6) is connected to node N5 between resistor R2 and power supply 1. Node N5 is an example of a fifth node. One end of switch SW3 (the left terminal in Figure 6) is connected to the other end of switch SW4 (the right terminal in Figure 6) and the other end of switch SW5 (the right terminal in Figure 6). The other connection relationships are the same as in Embodiment 1.

[0072] The resistance value of resistor R2 in the reference voltage generation circuit 10a according to the comparative example is the same as the resistance value of resistor R2 in the reference voltage generation circuit 11 according to embodiment 2. Also, the resistance value of resistor R1 in the reference voltage generation circuit 10a according to the comparative example is the same as the combined resistance value of resistors R11 and R12 in the reference voltage generation circuit 11 according to embodiment 2. Also, the capacitance of capacitor Cref in the reference voltage generation circuit 10a according to the comparative example is the same as the capacitance of capacitor Cref in the reference voltage generation circuit 11 according to embodiment 2. Furthermore, the resistance value of resistor R2 in the reference voltage generation circuit 11 according to embodiment 2 is designed to satisfy (resistance value of resistor R11) × (capacitance of capacitor C1) / (capacitance of capacitor C1 + capacitance of capacitor Cref).

[0073] In the reference voltage generation circuit 11, each switch operates as follows: Switches SW1, SW3, and SW4 are turned on, then switch SW3 is turned off, then switches SW1 and SW4 are turned off, and switches SW2 and SW5 are turned on, then switch SW3 is turned on. Alternatively, switches SW2 and SW5 are turned on, then switch SW3 is turned on, then switch SW3 is turned off, then switches SW2 and SW5 are turned off, and switches SW1 and SW4 are turned on, then switch SW3 is turned on. The timing chart for switching each switch will be explained using Figure 7.

[0074] Figure 7 is a timing chart showing an example of the switching of each switch in the reference voltage generation circuit 11 according to Embodiment 2. Figure 7 shows the timing chart of the switching of each switch when switching from the first reference voltage to the second reference voltage, and then from the second reference voltage to the first reference voltage.

[0075] First, let's explain the case where the voltage can be switched from the first reference voltage to the second reference voltage.

[0076] The control circuit 3 turns on switches SW1, SW3, and SW4, and turns off switches SW2 and SW5. As a result, a voltage V1 corresponding to the product of the sum of the resistance values ​​of resistors R11 and R12 and the bias current of power supply 1 is supplied to one end (Vrefp) of capacitor C1, and the ground voltage V3 is supplied to the other end (Vrefn) of capacitor C1. In other words, a voltage V1 is generated as a first reference voltage, and a potential difference of voltage V1 - voltage V3 is created across capacitor C1.

[0077] Next, the control circuit 3 turns off the switch SW3. At this time, the capacitor C1 holds a charge corresponding to the first reference voltage.

[0078] Next, the control circuit 3 turns off switches SW1 and SW4, and turns on switches SW2 and SW5. As a result, a voltage V4 corresponding to the product of the resistance value of resistor R11 and the bias current of power supply 1 is supplied to the other end (Vrefn) of capacitor C1. Since capacitor C1 holds a charge of (capacitance of capacitor C1) × (voltage V1 - voltage V3), a second reference voltage of voltage V1 + (voltage V4 - voltage V3) is generated.

[0079] After transitioning from the first reference voltage to the second reference voltage, there is a risk that the second reference voltage may drop due to leakage current from switch SW3, etc. Therefore, the control circuit 3 turns on switch SW3 after transitioning from the first reference voltage to the second reference voltage and applies the voltage V2 of node N5 to output terminal t1. At this time, since the resistance value of resistor R2 is designed to satisfy (resistance value of resistor R11) × (capacitance of capacitor C1) / (capacitance of capacitor C1 + capacitance of capacitor Cref), the voltage V2 of node N5 can be made the same as the second reference voltage.

[0080] Thus, when the control circuit 3 switches from the first reference voltage to the second reference voltage, it turns on switches SW1, SW3, and SW4, then turns off switch SW3, then turns off switches SW1 and SW4, and turns on switches SW2 and SW5, and then turns on switch SW3. After transitioning from the first reference voltage to the second reference voltage, by turning on switch SW3 and applying the voltage of node N5 to output terminal t1, it is possible to suppress a decrease in the second reference voltage and maintain the second reference voltage.

[0081] Next, we will explain the case where the voltage can be switched from the second reference voltage to the first reference voltage.

[0082] The control circuit 3 turns on switches SW2, SW3, and SW5, and turns off switches SW1 and SW4. As a result, a voltage V2 corresponding to the product of the sum of the resistance values ​​of resistors R11, R12, and R2 and the bias current of power supply 1 is supplied to one end (Vrefp) of capacitor C1, and a voltage V4 corresponding to the product of the resistance value of resistor R11 and the bias current of power supply 1 is supplied to the other end (Vrefn) of capacitor C1. In other words, a voltage V2 is generated as a second reference voltage, and a potential difference of voltage V2 - voltage V4 is created across capacitor C1.

[0083] Next, the control circuit 3 turns off switch SW3. At this time, capacitor C1 holds a charge corresponding to the second reference voltage.

[0084] Next, the control circuit 3 turns off switches SW2 and SW5, and turns on switches SW1 and SW4. As a result, the ground voltage V3 is supplied to the other end (Vrefn) of capacitor C1. Since capacitor C1 holds a charge of (capacitance of capacitor C1) × (voltage V2 - voltage V4), a first reference voltage of voltage V2 - (voltage V4 - voltage V3) is generated.

[0085] After transitioning from the second reference voltage to the first reference voltage, there is a risk that the first reference voltage may decrease due to leakage current from switch SW3, etc. Therefore, the control circuit 3 turns on switch SW3 after transitioning from the second reference voltage to the first reference voltage and applies the voltage of node N3 to output terminal t1.

[0086] Thus, the control circuit 3 turns on switches SW2 and SW5, then turns on switch SW3, then turns off switch SW3, then turns off switches SW2 and SW5, and turns on switches SW1 and SW4, and then turns on switch SW3. After transitioning from the second reference voltage to the first reference voltage, by turning on switch SW3 and applying the voltage of node N3 to output terminal t1, it is possible to suppress a decrease in the first reference voltage and maintain the first reference voltage.

[0087] (Other Embodiments) Embodiments have been described above as examples of the technology relating to this disclosure. However, the technology relating to this disclosure is not limited thereto and can be applied to embodiments that are modified, replaced, added to, or omitted as appropriate. For example, the following modified examples are also included in one embodiment of this disclosure.

[0088] For example, the above embodiment describes an example in which the reference voltage generation circuit switches between two reference voltages, but it is not limited to this. For example, the reference voltage generation circuit may include one or more resistors connected between node N1 and ground, and each of the one or more resistors may be provided with one or more switches connected between it and capacitor C1. In this way, the reference voltage generation circuit can switch between three or more reference voltages.

[0089] For example, this disclosure can be implemented not only as a reference voltage generation circuit and an LDO circuit, but also as a control method that includes steps (processes) performed by a control circuit.

[0090] Figure 8 is a flowchart showing a first example of a control method according to another embodiment.

[0091] Figure 9 is a flowchart showing a second example of a control method according to another embodiment.

[0092] The control method is a control method for a reference voltage generation circuit, the reference voltage generation circuit comprising a first resistor, a second resistor, a first switch, a second switch, a third switch, a first capacitor, and a second capacitor, the first resistor and the second resistor being connected in series with each other between the power supply and ground, from ground to power supply in the order of the first resistor and the second resistor, one end of the first switch being connected to a first node between ground and the first resistor, one end of the second switch being connected to a second node between the first resistor and the second resistor, and one end of the third switch being connected to a third node between the second resistor and the power supply, The other end of the 3 switch is connected to the output terminal, one end of the first capacitor is connected to the fourth node between the other end of the third switch and the output terminal, the other end of the first capacitor is connected to the other end of the first switch and the other end of the second switch, one end of the second capacitor is connected to the fourth node, and the other end of the second capacitor is connected to ground. In the control method, as shown in Figure 8, the first and third switches are turned on (step S11), then the third switch is turned off (step S12), then the first switch is turned off and the second switch is turned on (step S13). Alternatively, as shown in Figure 9, the second and third switches are turned on (step S21), then the third switch is turned off (step S22), then the second switch is turned off and the first switch is turned on (step S23).

[0093] For example, this disclosure can be implemented as a program that causes a computer (processor) to execute the steps included in the control method. Furthermore, this disclosure can be implemented as a non-temporary computer-readable recording medium, such as a CD-ROM, on which the program is recorded.

[0094] For example, if this disclosure is implemented in a program (software), each step is executed by the program using hardware resources such as the computer's CPU, memory, and input / output circuits. In other words, each step is executed by the CPU obtaining data from memory or input / output circuits, performing calculations, and outputting the calculation results to memory or input / output circuits.

[0095] In the above embodiment, each component included in the reference voltage generation circuit or LDO circuit may be implemented by dedicated hardware or by executing a software program suitable for each component. Each component may also be implemented by a program execution unit such as a CPU or processor reading and executing a software program recorded on a recording medium such as a hard disk or semiconductor memory.

[0096] Some or all of the functions of the reference voltage generation circuit or LDO circuit according to the above embodiment are typically implemented as an integrated circuit (LSI). These may be individually integrated on a single chip, or some or all of them may be integrated on a single chip. Furthermore, the implementation is not limited to an LSI, but may also be implemented using a dedicated circuit or a general-purpose processor. An FPGA (Field Programmable Gate Array) that can be programmed after LSI manufacturing, or a reconfigurable processor that can reconfigure the connections and settings of circuit cells inside the LSI may also be used.

[0097] Furthermore, if advances in semiconductor technology or other derived technologies lead to the emergence of integrated circuit technologies that can replace LSIs, then naturally, these technologies may be used to integrate each component included in the reference voltage generation circuit or LDO circuit into an integrated circuit.

[0098] Furthermore, this disclosure also includes forms obtained by applying various modifications to the embodiments that a person skilled in the art could conceive, and forms realized by arbitrarily combining the components and functions of each embodiment without departing from the spirit of this disclosure.

[0099] (Note) The above description of embodiments discloses the following technology.

[0100] (Technical 1) The device comprises a first resistor, a second resistor, a first switch, a second switch, a third switch, a first capacitor, and a second capacitor, wherein the first resistor and the second resistor are connected in series with each other between the power supply and ground, from ground to the power supply in the order of the first resistor and the second resistor, one end of the first switch is connected to a first node between ground and the first resistor, one end of the second switch is connected to a second node between the first resistor and the second resistor, and one end of the third switch is connected to a third node between the second resistor and the power supply. A reference voltage generation circuit in which the other end of the third switch is connected to an output terminal, one end of the first capacitor is connected to a fourth node between the other end of the third switch and the output terminal, the other end of the first capacitor is connected to the other end of the first switch and the other end of the second switch, one end of the second capacitor is connected to the fourth node, and the other end of the second capacitor is connected to ground, and the first switch and the third switch are turned on, then the third switch is turned off, then the first switch is turned off, and the second switch is turned on.

[0101] (Technology 2) The reference voltage generation circuit according to Technology 1, wherein the first switch is turned off and the second switch is turned on, and then the second switch is turned off and the first switch is turned on.

[0102] The resistance value of the power supply side resistor in the comparative reference voltage generation circuit is the same as the (resistance value of the first resistor) × (capacitance of the first capacitor) / (capacitance of the first capacitor + capacitance of the second capacitor) in the embodiment. Also, the resistance value of the ground side resistor in the comparative reference voltage generation circuit is the same as the combined resistance value of the first and second resistors in the reference voltage generation circuit of the embodiment. Furthermore, the capacitance of the capacitor connected to the output terminal of the reference voltage generation circuit in the comparative reference circuit is the same as the capacitance of the second capacitor connected to the output terminal of the reference voltage generation circuit of the embodiment.

[0103] In the first example of Embodiment 1, the transition time from the first reference voltage generated when the first and third switches are ON and the second switch is OFF to the second reference voltage generated when the first and third switches are OFF and the second switch is ON is the product of the resistance value of the first resistor and the combined capacitance of the first and second capacitors connected in series. Similarly, the transition time from the second reference voltage generated when the second switch is ON and the first and third switches are OFF to the first reference voltage generated when the second and third switches are OFF and the first switch is ON is the product of the resistance value of the first resistor and the combined capacitance of the first and second capacitors connected in series. On the other hand, the transition time in the comparative example is the product of the sum of the resistance values ​​of the power supply side resistor and the ground side resistor and the capacitance of the capacitor connected to the output terminal. In this embodiment, the resistance value of the first resistor is smaller than the sum of the resistance values ​​of the power supply side resistor and the ground side resistor in the comparative example, and the combined capacitance of the first and second capacitors in this embodiment is smaller than the capacitance of the capacitor connected to the output terminal in the comparative example.

[0104] Therefore, the reference voltage generation circuit according to the embodiment enables faster transitions of the reference voltage. Furthermore, since the sum of the resistance values ​​of the ground-side resistor in the reference voltage generation circuit according to the comparative example and the resistance values ​​of each resistor in the reference voltage generation circuit according to the embodiment are the same, the current consumption does not increase in the embodiment compared to the comparative example. Also, since the capacitance of the capacitor connected to the output terminal of the reference voltage generation circuit according to the comparative example and the capacitance of the second capacitor in the reference voltage generation circuit according to the embodiment are the same, the noise characteristics do not deteriorate in the embodiment compared to the comparative example. Thus, it is possible to accelerate the transitions of the reference voltage while suppressing increases in current consumption and deterioration of noise characteristics.

[0105] (Technology 3) A reference voltage generation circuit according to Technology 1 or 2, further comprising a third resistor, a fourth switch, and a fifth switch, wherein the first resistor, the second resistor, and the third resistor are connected in series with each other between the power supply and ground, from ground to the power supply in the order of the first resistor, the second resistor, and the third resistor, the third node is the node between the second resistor and the third resistor, one end of the fourth switch is connected to the third node, one end of the fifth switch is connected to the fifth node between the third resistor and the power supply, and one end of the third switch is connected to the other end of the fourth switch and the other end of the fifth switch.

[0106] This circuit configuration helps to suppress the drop in the reference voltage.

[0107] (Technical 4) The reference voltage generation circuit according to Technical 3, wherein the first switch, the third switch and the fourth switch are turned on, then the third switch is turned off, then the first switch and the fourth switch are turned off, and the second switch and the fifth switch are turned on, and then the third switch is turned on.

[0108] After transitioning from the first reference voltage to the second reference voltage, there is a risk that the second reference voltage may drop due to leakage current from the third switch, etc. Therefore, after transitioning to the second reference voltage, the third switch is turned on and the voltage of the fifth node is applied to the output terminal. At this time, the resistance value of the third resistor is designed to satisfy (resistance value of the first resistor) × (capacitance of the first capacitor) / (capacitance of the first capacitor + capacitance of the second capacitor). This makes it possible to make the voltage of the fifth node the same as the second reference voltage. By turning on the third switch and applying the voltage of the fifth node to the output terminal after transitioning from the first reference voltage to the second reference voltage, it is possible to suppress the drop in the second reference voltage and maintain the second reference voltage.

[0109] (Technical 5) The reference voltage generation circuit according to Technical 4, wherein the second switch and the fifth switch are turned on, then the third switch is turned on, then the third switch is turned off, then the second switch and the fifth switch are turned off, and the first switch and the fourth switch are turned on, then the third switch is turned on.

[0110] After transitioning from the second reference voltage to the first reference voltage, there is a risk that the first reference voltage may decrease due to leakage current from the third switch, etc. Therefore, after transitioning to the first reference voltage, the third switch is turned on and the voltage of the third node is applied to the output terminal. By turning on the third switch and applying the voltage of the third node to the output terminal after transitioning from the second reference voltage to the first reference voltage, it is possible to suppress the decrease in the first reference voltage and maintain the first reference voltage.

[0111] (Technical 6) The device comprises a first resistor, a second resistor, a first switch, a second switch, a third switch, a first capacitor, and a second capacitor, wherein the first and second resistors are connected in series with each other between the power supply and ground, from ground to the power supply in the order of the first resistor and the second resistor, one end of the first switch is connected to a first node between ground and the first resistor, one end of the second switch is connected to a second node between the first and second resistors, and one end of the third switch is connected to a third node between the second resistor and the power supply. A reference voltage generation circuit in which the other end of the third switch is connected to an output terminal, one end of the first capacitor is connected to a fourth node between the other end of the third switch and the output terminal, the other end of the first capacitor is connected to the other end of the first switch and the other end of the second switch, one end of the second capacitor is connected to the fourth node, and the other end of the second capacitor is connected to ground, and the second switch and the third switch are turned on, then the third switch is turned off, then the second switch is turned off, and the first switch is turned on.

[0112] (Technical 7) The reference voltage generation circuit according to Technical 6, wherein the second switch is turned off and the first switch is turned on, and then the first switch is turned off and the second switch is turned on.

[0113] In the second example of Embodiment 1, the transition time from the first reference voltage generated when the second and third switches are ON and the first switch is OFF to the third reference voltage generated when the second and third switches are OFF and the first switch is ON is the product of the resistance value of the first resistor and the combined capacitance of the first and second capacitors connected in series. On the other hand, the transition time in the comparative example is the product of the sum of the resistance values ​​of the power supply side resistor and the ground side resistor and the capacitance of the capacitor connected to the output terminal. In the embodiment, the resistance value of the first resistor is smaller than the sum of the resistance values ​​of the power supply side resistor and the ground side resistor in the comparative example, and the combined capacitance of the first and second capacitors in the embodiment is smaller than the capacitance of the capacitor connected to the output terminal in the comparative example.

[0114] Therefore, the reference voltage generation circuit according to the embodiment enables faster transitions of the reference voltage. Furthermore, since the sum of the resistance values ​​of the ground-side resistor in the reference voltage generation circuit according to the comparative example and the resistance values ​​of each resistor in the reference voltage generation circuit according to the embodiment are the same, the current consumption does not increase in the embodiment compared to the comparative example. Also, since the capacitance of the capacitor connected to the output terminal of the reference voltage generation circuit according to the comparative example and the capacitance of the second capacitor in the reference voltage generation circuit according to the embodiment are the same, the noise characteristics do not deteriorate in the embodiment compared to the comparative example. Thus, it is possible to accelerate the transitions of the reference voltage while suppressing increases in current consumption and deterioration of noise characteristics.

[0115] (Technical 8) An LDO circuit comprising a reference voltage generation circuit as described in any of Technical 1 to 7, an error amplifier, an output driver, and a feedback resistor connected between the output driver and ground, wherein the error amplifier controls the output driver based on the difference between the reference voltage output from the output terminal and the voltage generated in the feedback resistor.

[0116] This makes it possible to provide an LDO circuit that can accelerate the transition of the reference voltage while suppressing an increase in current consumption and deterioration of noise characteristics.

[0117] (Technical 9) A control method for a reference voltage generation circuit, wherein the reference voltage generation circuit comprises a first resistor, a second resistor, a first switch, a second switch, a third switch, a first capacitor, and a second capacitor, wherein the first resistor and the second resistor are connected in series with each other between a power source and ground, from ground to the power source in the order of the first resistor and the second resistor, one end of the first switch is connected to a first node between ground and the first resistor, one end of the second switch is connected to a second node between the first resistor and the second resistor, and one end of the third switch is connected between the second resistor and the power source The control method involves turning on the first switch and the third switch, then turning off the third switch, then turning off the first switch, and then turning on the second switch.

[0118] This provides a control method that enables faster transitions of the reference voltage while suppressing increases in current consumption and deterioration of noise characteristics.

[0119] (Technical 10) A control method for a reference voltage generation circuit, wherein the reference voltage generation circuit comprises a first resistor, a second resistor, a first switch, a second switch, a third switch, a first capacitor, and a second capacitor, wherein the first resistor and the second resistor are connected in series with each other between a power source and ground, from ground to the power source in the order of the first resistor and the second resistor, one end of the first switch is connected to a first node between ground and the first resistor, one end of the second switch is connected to a second node between the first resistor and the second resistor, and one end of the third switch is connected between the second resistor and the power source The control method involves turning on the second and third switches, then turning off the third switch, then turning off the second switch, and then turning on the first switch.

[0120] This provides a control method that enables faster transitions of the reference voltage while suppressing increases in current consumption and deterioration of noise characteristics.

[0121] This disclosure can be applied to LDO circuits and the like.

[0122] 1 Power supply 2, 2a, 3 Control circuit 10, 10a, 11 Reference voltage generation circuit 20 Error amplifier 30 Output driver 100, 100a, 101 LDO circuit C1, Cref Capacitors N1, N2, N3, N4, N5 Nodes R1, R2, R11, R12, Rf, Rs Resistors SW1, SW2, SW3, SW4, SW5, SWA, SWB Switch t1 Output terminal

Claims

1. The device comprises a first resistor, a second resistor, a first switch, a second switch, a third switch, a first capacitor, and a second capacitor, wherein the first and second resistors are connected in series with each other between the power supply and ground, from ground to the power supply in the order of the first resistor and the second resistor, one end of the first switch is connected to a first node between ground and the first resistor, one end of the second switch is connected to a second node between the first and second resistors, one end of the third switch is connected to a third node between the second resistor and the power supply, the other end of the third switch is connected to an output terminal, one end of the first capacitor is connected to a fourth node between the other end of the third switch and the output terminal, the other end of the first capacitor is connected to the other end of the first switch and the other end of the second switch, one end of the second capacitor is connected to the fourth node, and the other end of the second capacitor is connected to ground. A reference voltage generation circuit in which the first switch and the third switch are turned on, then the third switch is turned off, then the first switch is turned off, and the second switch is turned on.

2. The reference voltage generation circuit according to claim 1, wherein the first switch is turned off and the second switch is turned on, and then the second switch is turned off and the first switch is turned on.

3. A reference voltage generating circuit according to claim 1 or 2, further comprising a third resistor, a fourth switch, and a fifth switch, wherein the first resistor, the second resistor, and the third resistor are connected in series with each other between the power supply and ground, from ground to the power supply in the order of the first resistor, the second resistor, and the third resistor; the third node is the node between the second resistor and the third resistor; one end of the fourth switch is connected to the third node; one end of the fifth switch is connected to the fifth node between the third resistor and the power supply; and one end of the third switch is connected to the other end of the fourth switch and the other end of the fifth switch.

4. The reference voltage generation circuit according to claim 3, wherein the first switch, the third switch and the fourth switch are turned on, then the third switch is turned off, then the first switch and the fourth switch are turned off, and the second switch and the fifth switch are turned on, and then the third switch is turned on.

5. The reference voltage generation circuit according to claim 4, wherein the second switch and the fifth switch are turned on, then the third switch is turned on, then the third switch is turned off, then the second switch and the fifth switch are turned off, and the first switch and the fourth switch are turned on, then the third switch is turned on.

6. The device comprises a first resistor, a second resistor, a first switch, a second switch, a third switch, a first capacitor, and a second capacitor, wherein the first and second resistors are connected in series with each other between the power supply and ground, from ground to the power supply in the order of the first resistor and the second resistor, one end of the first switch is connected to a first node between ground and the first resistor, one end of the second switch is connected to a second node between the first and second resistors, one end of the third switch is connected to a third node between the second resistor and the power supply, the other end of the third switch is connected to an output terminal, one end of the first capacitor is connected to a fourth node between the other end of the third switch and the output terminal, the other end of the first capacitor is connected to the other end of the first switch and the other end of the second switch, one end of the second capacitor is connected to the fourth node, and the other end of the second capacitor is connected to ground. A reference voltage generation circuit in which the second switch and the third switch are turned on, then the third switch is turned off, then the second switch is turned off, and the first switch is turned on.

7. The reference voltage generation circuit according to claim 6, wherein the second switch is turned off and the first switch is turned on, and then the first switch is turned off and the second switch is turned on.

8. An LDO circuit comprising: a reference voltage generation circuit according to any one of claims 1 to 7; an error amplifier; an output driver; and a feedback resistor connected between the output driver and ground, wherein the error amplifier controls the output driver based on the difference between a reference voltage output from the output terminal and a voltage generated across the feedback resistor.

9. A control method for a reference voltage generation circuit, wherein the reference voltage generation circuit comprises a first resistor, a second resistor, a first switch, a second switch, a third switch, a first capacitor, and a second capacitor, the first resistor and the second resistor are connected in series with each other between a power supply and ground, from ground to the power supply in the order of the first resistor and the second resistor, one end of the first switch is connected to a first node between ground and the first resistor, one end of the second switch is connected to a second node between the first resistor and the second resistor, one end of the third switch is connected to a third node between the second resistor and the power supply, the other end of the third switch is connected to an output terminal, one end of the first capacitor is connected to a fourth node between the other end of the third switch and the output terminal, the other end of the first capacitor is connected to the other end of the first switch and the other end of the second switch, one end of the second capacitor is connected to the fourth node, and the other end of the second capacitor is connected to ground. The control method described above involves turning on the first switch and the third switch, then turning off the third switch, then turning off the first switch, and turning on the second switch.

10. A control method for a reference voltage generation circuit, wherein the reference voltage generation circuit comprises a first resistor, a second resistor, a first switch, a second switch, a third switch, a first capacitor, and a second capacitor, the first resistor and the second resistor are connected in series with each other between a power supply and ground, from ground to the power supply in the order of the first resistor and the second resistor, one end of the first switch is connected to a first node between ground and the first resistor, one end of the second switch is connected to a second node between the first resistor and the second resistor, one end of the third switch is connected to a third node between the second resistor and the power supply, the other end of the third switch is connected to an output terminal, one end of the first capacitor is connected to a fourth node between the other end of the third switch and the output terminal, the other end of the first capacitor is connected to the other end of the first switch and the other end of the second switch, one end of the second capacitor is connected to the fourth node, and the other end of the second capacitor is connected to ground. The control method described above involves turning on the second switch and the third switch, then turning off the third switch, then turning off the second switch, and turning on the first switch.

Images