Imaging element and imaging device

Abstract

The present invention simplifies a manufacturing process of an imaging element. This imaging element includes: a first pixel and a second pixel each including a photoelectric conversion unit formed in a semiconductor substrate and performing photoelectric conversion of incident light; a well connection region that is composed of a semiconductor region formed by ion implantation of impurities into the semiconductor substrate and to which a reference potential of a well region of the semiconductor substrate is transmitted, and that is disposed close to the first pixel and spaced apart from the second pixel; and a crystal defect adjustment region that is composed of a semiconductor region formed by ion implantation of impurities into the semiconductor substrate, that is disposed close to the second pixel and spaced apart from the first pixel, and that has a crystal defect adjusted according to a crystal defect of the well connection region.

Description

Image Sensor and Imaging Device

[0001] The present disclosure relates to an image sensor and an imaging device.

[0002] An image sensor configured by arranging a plurality of pixels each having a photoelectric conversion unit that performs photoelectric conversion on incident light and a charge retention unit that retains charges generated by photoelectric conversion is in use. A photodiode formed in a semiconductor substrate is used for this photoelectric conversion unit. Charges resulting from semiconductor crystal defects may flow into the charge retention unit or the like of the pixel. The current caused by this inflow of charges is a current that does not originate from incident light, and is therefore referred to as dark current. If this dark current varies from pixel to pixel, uneven brightness occurs, leading to degradation in image quality. Accordingly, image sensors that control this dark current have been proposed. For example, there has been proposed an image sensor including: a semiconductor in which a light receiving unit that photoelectrically converts incident light is formed; a conductor wiring; and a contact group including contacts of a plurality of sizes that connects the semiconductor and the wiring (see, for example, Patent Document 1). In this image sensor, dark current is controlled by adjusting the size of the contact.

[0003] Japanese Unexamined Patent Application Publication No. 2014-192273

[0004] However, the above-described conventional technique requires contacts of different sizes, which poses a problem that the manufacturing process becomes complicated.

[0005] Accordingly, the present disclosure proposes an image sensor and an imaging device that allow simplification of the manufacturing process.

[0006] The image sensor according to this disclosure includes a first pixel and a second pixel, each having a photoelectric conversion unit that performs photoelectric conversion of incident light formed on a semiconductor substrate; a well connection region, which is formed by ion implantation of impurities into the semiconductor substrate and to which a reference potential of the well region of the semiconductor substrate is transmitted, and is arranged in close proximity to the first pixel and spaced apart from the second pixel; and a crystal defect adjustment region, which is formed by ion implantation of impurities into the semiconductor substrate, and is arranged in close proximity to the second pixel and spaced apart from the first pixel, in which crystal defects are adjusted according to the crystal defects of the well connection region.

[0007] This figure shows an example of the configuration of an image sensor according to the embodiment of this disclosure. This figure shows an example of the circuit configuration of a pixel according to the first embodiment of this disclosure. This figure shows an example of the configuration of a pixel according to the first embodiment of this disclosure. This figure shows an example of the configuration of a pixel according to the first embodiment of this disclosure. This figure shows an example of the configuration of a pixel according to the first embodiment of this disclosure. This figure shows an example of the configuration of a pixel according to the first embodiment of this disclosure. This figure shows an example of the configuration of a pixel according to the first embodiment of this disclosure. This figure shows an example of the crystal defect adjustment region according to the first embodiment of this disclosure. This figure shows an example of the crystal defect adjustment region according to the first embodiment of this disclosure. This figure shows another example of the crystal defect adjustment region according to the first embodiment of this disclosure. This figure shows another example of the crystal defect adjustment region according to the first embodiment of this disclosure. This figure shows another example of the crystal defect adjustment region according to the first embodiment of this disclosure. This figure shows another example of the crystal defect adjustment region according to the first embodiment of this disclosure. This figure shows another example of the crystal defect adjustment region according to the first embodiment of this disclosure. This figure shows another example of the crystal defect adjustment region according to the first embodiment of this disclosure. This figure shows an example of the manufacturing method of an image sensor according to the first embodiment of this disclosure. This figure shows an example of the manufacturing method of an image sensor according to the first embodiment of this disclosure. This figure shows an example of the manufacturing method of an image sensor according to the first embodiment of this disclosure. This figure shows an example of the manufacturing method of an image sensor according to the first embodiment of this disclosure. This is a diagram showing an example of a method for manufacturing an image sensor according to the first embodiment of this disclosure. This is a diagram showing an example of a method for manufacturing an image sensor according to the first embodiment of this disclosure. This is a diagram showing an example of a method for manufacturing an image sensor according to the first embodiment of this disclosure. This is a diagram showing an example of a method for manufacturing an image sensor according to the first embodiment of this disclosure. This is a diagram showing another example of a pixel configuration according to the first embodiment of this disclosure. This is a diagram showing an example of a pixel configuration according to the second embodiment of this disclosure. This is a diagram showing an example of a pixel configuration according to the second embodiment of this disclosure. This is a diagram showing an example of a pixel configuration according to the second embodiment of this disclosure. This is a diagram showing an example of a pixel configuration according to the second embodiment of this disclosure. This is a diagram showing an example of a pixel configuration according to the second embodiment of this disclosure. This is a block diagram showing an example of a configuration of an imaging device mounted on an electronic device.

[0008] The embodiments of this disclosure will be described in detail below with reference to the drawings. The description will be in the following order. In each of the following embodiments, the same parts will be denoted by the same reference numerals, and redundant descriptions will be omitted. 1. First Embodiment 2. Second Embodiment 3. Configuration of the Electronic Device

[0009] (1. First Embodiment) <Configuration of Image Sensor> Figure 1 is a diagram showing an example configuration of an image sensor according to the present disclosure. The same figure is a block diagram showing an example configuration of the image sensor 1. The image sensor 1 is a semiconductor element that generates pixel signals that constitute an image of a subject. The image sensor 1 comprises a pixel array unit 10, a vertical drive unit 20, a column signal processing unit 30, and a control unit 40.

[0010] The pixel array section 10 is composed of multiple pixels 100 arranged together. The pixel array section 10 in Figure 1 shows an example in which multiple pixels 100 are arranged in the shape of a two-dimensional matrix. Here, each pixel 100 is equipped with a photoelectric conversion unit that performs photoelectric conversion of incident light and generates a pixel signal of the subject based on the irradiated incident light. For example, a photodiode can be used for this photoelectric conversion unit. Signal lines 11 and 12 are wired to each pixel 100. The pixel 100 generates a pixel signal controlled by a control signal transmitted by the signal line 12 and outputs the generated pixel signal via the signal line 12. The signal line 11 is arranged in each row of the two-dimensional matrix and is wired in common to multiple pixels 100 arranged in one row. The signal line 12 is arranged in each column of the two-dimensional matrix and is wired in common to multiple pixels 100 arranged in one column.

[0011] The vertical drive unit 22 generates the control signals for the pixels 100 described above. The vertical drive unit 22 in Figure 1 generates control signals for each row of the two-dimensional matrix of the pixel array unit 10 and outputs them sequentially via the signal line 11.

[0012] The column signal processing unit 30 processes the pixel signals generated by the pixels 100. The column signal processing unit 30 in Figure 1 simultaneously processes pixel signals from multiple pixels 100 arranged in one row of the pixel array unit 10, which are transmitted via the signal line 12. This processing can include, for example, analog-to-digital conversion, which converts the analog pixel signals generated by the pixels 100 into digital pixel signals, and correlated double sampling (CDS), which removes offset errors in the pixel signals. The processed pixel signals are output to external circuits, etc., of the image sensor 1.

[0013] The control unit 40 controls the vertical drive unit 20 and the column signal processing unit 30. The control unit 40 in Figure 1 generates control signals to control the vertical drive unit 20 and the column signal processing unit 30 based on data that commands the clock, operating mode, etc., input from an external circuit or the like. Next, the control unit 40 controls the vertical drive unit 20 and the column signal processing unit 30 by outputting control signals via signal lines 41 and 42, respectively.

[0014] <Pixel Circuit Configuration> Figure 2 is a diagram showing an example of the circuit configuration of a pixel according to the first embodiment of the present disclosure. The figure is a circuit diagram showing an example of the configuration of a pixel 100. The pixel 100 in the figure comprises a photoelectric conversion unit 101 and a charge transfer unit 102. The photoelectric conversion unit 101 generates charge by performing photoelectric conversion of incident light. This photoelectric conversion unit 101 can be configured with a photodiode. The charge transfer unit 102 transfers the charge from the photoelectric conversion unit 101 to a charge holding unit (charge holding unit 103). This charge transfer unit 102 can be configured with an n-channel MOS transistor. The charge holding unit 103 holds the charge generated by the photoelectric conversion unit 101. This charge holding unit 103 is arranged for each pixel group consisting of four pixels 100 (pixels 100a-100d). In the circuit of the figure, one pixel signal generation circuit 110 is arranged to generate an image signal for a pixel block consisting of a pixel group and a charge holding unit. The pixel signal generation circuit 110 generates a pixel signal, which is a signal based on the charge of the charge holding unit 103.

[0015] The pixel block comprises pixels 100a, 100b, 100c, 100d, and a charge holding unit 103.

[0016] Signal lines 11 and 12 are wired to the pixel block. Signal lines TG1, TG2, TG3, TG4, RST, and SEL in Figure 2 are included in signal line 11. In addition, a power line Vdd is wired to the pixel signal generation circuit 110. This power line Vdd is the wiring that supplies power to the pixel signal generation circuit 110.

[0017] The anode of the photoelectric conversion unit 101 is connected to a common ground wire, and its cathode is connected to the source of the charge transfer unit 102. These connections are the same for pixels 100a-100d. The drains of the charge transfer unit 102 for pixels 100a-100d are each connected to one end of the charge holding unit 103. The other end of the charge holding unit 103 is connected to a common ground wire.

[0018] Signal line TG1 is connected to the gate of the charge transfer unit 102 of pixel 100a. Signal line TG2 is connected to the gate of the charge transfer unit 102 of pixel 100b. Signal line TG3 is connected to the gate of the charge transfer unit 102 of pixel 100c. Signal line TG4 is connected to the gate of the charge transfer unit 102 of pixel 100d.

[0019] The pixel signal generation circuit 110 includes a reset transistor 111, an amplification transistor 112, and a selection transistor 113. These can be constructed using n-channel MOS transistors.

[0020] The reset transistor 111 resets the charge holding unit 103. This reset is performed by discharging the charge from the charge holding unit 103 by creating conductivity between the charge holding unit 103 and the power line Vdd. The control signal for the reset transistor 111 is transmitted via the signal line RST.

[0021] The amplifying transistor 112 amplifies the voltage of the charge holding unit 103. The gate of the amplifying transistor 112 is connected to the charge holding unit 103. Therefore, a pixel signal with a voltage corresponding to the charge held in the charge holding unit 103 is generated at the source of the amplifying transistor 112. Furthermore, by making the selection transistor 113 conduct, this pixel signal can be output to the signal line 16. The control signal of the selection transistor 113 is transmitted via the signal line 12.

[0022] <Pixel Configuration> Figure 3 is a diagram showing an example of the pixel configuration according to the first embodiment of the present disclosure. The figure shows an example of the configuration of a pixel block including a plurality of pixels 100. Pixels 100a to 100d are arranged in 2 rows and 2 columns. A photoelectric conversion unit 101 and a charge transfer unit 102 are shown in pixels 100a to 100d. The charge transfer unit 102 is shown as a gate electrode. A charge holding unit 103 is arranged in the center of pixels 100a to 100d. A reset transistor 111, an amplification transistor 112, and a selection transistor 113 are arranged adjacent to the pixel group 100. The amplification transistor 112 and the selection transistor 113 are arranged on the right side of the pixel group in the figure. The reset transistor 111 is arranged on the left side of the pixel group in the figure. A transistor 119 is arranged adjacent to the reset transistor 111. This transistor 119 is arranged to maintain the symmetry of the arrangement of transistors, etc., and is a transistor that does not participate in signal generation, etc.

[0023] As will be described later, the transistors of the pixel 100 and the pixel signal generation circuit 110 are arranged on the semiconductor substrate 120. In addition, contact plugs 153 for transmitting signals are arranged on the charge transfer unit 102 and the reset transistor 111. The hatched rectangles in Figure 3 represent the contact plugs 153.

[0024] A well connection region 130 is located above the pixel group in Figure 3. This well connection region 130 is a semiconductor region formed by ion implantation of impurities into the semiconductor substrate 120. The reference potential of the well region of the semiconductor substrate 120 is transmitted to the well connection region 130. The well connection region 130 is located in close proximity to pixels 100a and 100b of the pixel group. Pixels to which this well connection region 130 is located are referred to as first pixels. The well connection region 130 is located at a distance from pixels 100c and 100d of the pixel group. Pixels to which this well connection region 130 is located are referred to as second pixels. A well connection wiring 159 is connected to the well connection region 130. This well connection wiring 159 is a contact plug that transmits the reference potential.

[0025] A crystal defect adjustment region 131 is located below the pixel group in Figure 3. This crystal defect adjustment region 131 is a semiconductor region formed by ion implantation of impurities into the semiconductor substrate 120. The crystal defect adjustment region 131 is located close to the second pixels, i.e., pixels 100c and 100d, and spaced apart from the first pixels, i.e., pixels 100a and 100b. Furthermore, the crystal defect adjustment region 131 is constructed by adjusting the crystal defects in accordance with the crystal defects in the well connection region 130.

[0026] Figure 4 is a diagram showing an example of the configuration of a pixel according to the first embodiment of the present disclosure. The figure is a schematic cross-sectional view showing an example of the configuration of a pixel 100. Pixels 100a and 100c are shown in the figure. The pixel 100 comprises a semiconductor substrate 120, a wiring area 150, a protective film 180, a color filter 181, and an on-chip lens 182.

[0027] The semiconductor substrate 120 is a semiconductor substrate on which the diffusion layer of the semiconductor elements of the pixel 100 is formed. The semiconductor substrate 120 can be made of, for example, silicon (Si). The semiconductor elements are arranged in the well regions formed on the semiconductor substrate 120. For convenience, the semiconductor substrate 120 in Figure 4 is assumed to be composed of p-type well regions. Semiconductor elements can be formed by arranging n-type or p-type semiconductor regions in these p-type well regions. In the semiconductor substrate 120 in Figure 4, the photoelectric conversion units 101a and 101c, the charge transfer unit 102, and the charge holding unit 103 are shown as examples. Note that the photoelectric conversion unit 101a is included in the pixel 100a. The photoelectric conversion unit 101c is included in the pixel 100c.

[0028] The photoelectric conversion unit 101 is composed of an n-type semiconductor region 121. Specifically, the photodiode consisting of a pn junction at the interface between the n-type semiconductor region 121 and the surrounding p-type well region corresponds to the photoelectric conversion unit 101.

[0029] The charge-holding portion 103 is composed of an n-type semiconductor region 122. A charge-holding portion composed of such a semiconductor region is called a floating diffusion (FD).

[0030] The charge transfer section 102 is composed of semiconductor regions 121 and 122 and a gate electrode 142. The gate electrode 142 can be made of polycrystalline silicon containing impurities.

[0031] An insulating film 141 is placed on the surface of the semiconductor substrate 120. This insulating film 141 insulates the surface side of the semiconductor substrate 120. This insulating film 141 contains, for example, silicon oxide (SiO₂ ２ A film of the above can be applied. The insulating film 141 directly beneath the gate electrode 142 of the charge transfer unit 102 constitutes the gate insulating film.

[0032] The wiring region 150 is located on the surface side of the semiconductor substrate 120 and is a region where the wiring of the element is formed. This wiring region 150 comprises an insulating layer 151, wiring 152, a contact plug 153, and a via plug 154. The wiring 152 is a conductor that transmits signals to the element on the semiconductor substrate 120. The wiring 152 can be made of a metal such as copper (Cu) or tungsten (W). The contact plug 153 connects the element on the semiconductor substrate 120 to the wiring. This contact plug 153 can be made of a columnar metal, for example. The insulating layer 151 insulates the wiring 152, etc. This insulating layer 151 can be made of a metal such as SiO ２ It can be constructed as follows. The via plug 154 connects the wiring 152 which is arranged in different layers. The via plug 154 can be made of columnar metal.

[0033] The protective film 180 is a film that protects the back side of the semiconductor substrate 120. This protective film 180 is made of SiO ２ It can be constructed from insulating materials such as the following.

[0034] The color filter 181 is an optical filter that transmits incident light of a predetermined wavelength. For example, a color filter that transmits red light, green light, and blue light can be used for this color filter 181. In this case, one color filter 181 corresponding to red light, green light, or blue light is placed in the pixel 100. Such a pixel 100 generates a pixel signal of incident light of the wavelength corresponding to the color filter 181.

[0035] The on-chip lens 182 is a lens positioned on the pixel 100. The on-chip lens 182 in Figure 4 has a hemispherical cross-section and focuses incident light onto the photoelectric conversion unit 101 of the pixel 100. The on-chip lens 182 can be made of an organic material such as acrylic resin or an inorganic material such as silicon nitride (SiN).

[0036] The well connection region 130 is placed on the semiconductor substrate 120. The well connection region 130 is a semiconductor region configured with the same conductivity type as the well region and a relatively high impurity concentration. The well connection region 130 in Figure 4 shows an example where it is configured as p-type. Well connection wiring 159 is connected to the well connection region 130. The well connection wiring 159 can be configured using via plugs. By placing this well connection region 130 in between, the connection resistance between the well connection wiring 159 and the well region can be reduced.

[0037] The reference potential transmitted to the well connection wiring 159 is supplied, for example, from an external circuit connected to the image sensor 1. As shown in Figure 4, the reference potential is transmitted via wiring 152 connected to the well connection wiring 159.

[0038] Furthermore, the aforementioned crystal defect adjustment region 131 is further arranged on the semiconductor substrate 120. The crystal defect adjustment region 131 is a semiconductor region configured with a relatively high impurity concentration of the same conductivity type as the well region. The crystal defect adjustment region 131 in Figure 4 shows an example where it is configured as p-type. Unlike the well connection region 130, the contact plug 153 is not connected to the crystal defect adjustment region 131.

[0039] Figure 5A is a diagram showing an example of the pixel configuration according to the first embodiment of the present disclosure. The figure shows an example of the configuration of the well connection region. The figure shows pixels 100a and 100c, the well connection region 130, and the crystal defect adjustment region 131.

[0040] The well connection region 130 is positioned close to the first pixel, pixel 100a, and spaced apart from the second pixel, pixel 100c. The crystal defect adjustment region 131 is also positioned close to the second pixel, pixel 100c, and spaced apart from the first pixel, pixel 100a.

[0041] The well connection region 130 is necessary for transmitting a reference potential to the well region, and is arranged in the vicinity of the pixel group. The well connection region 130 is formed by ion implantation. During this ion implantation, crystal defects are formed in the well connection region 130. The "x" in the well connection region 130 of FIG. 5A represents a crystal defect. As described above, crystal defects cause dark current. A large amount of dark current flows into the pixel 100a adjacent to the well connection region 130. On the other hand, the pixel 100c arranged spaced apart from the well connection region 130 is less affected by dark current. The arrows in FIG. 5A represent dark current.

[0042] By arranging the well connection region 130 also in the vicinity of the pixel 100c, dark current in the pixel 100a and the pixel 100c can be made uniform. However, since the number of well connection wirings 159 increases, constraints are imposed on the arrangement of the wirings 152.

[0043] Therefore, a crystal defect adjustment region 131, which is a semiconductor region where no well connection wiring 159 is arranged, is provided. In the well connection region 130, in addition to crystal defects generated during ion implantation, additional crystal defects are formed when forming the well connection wiring 159. Therefore, by adjusting the crystal defects in the crystal defect adjustment region 131, balance can be achieved with the crystal defects in the well connection region 130.

[0044] FIG. 5B is a diagram showing a configuration example of a pixel according to the first embodiment of the present disclosure. This drawing shows an example in which the crystal defects in the well connection region 130 and the crystal defect adjustment region 131 are not uniform. The rectangles in the drawing represent pixels 100a to 100d. The pixels 100a and 100b adjacent to the well connection region 130 have a large amount of dark current flowing in, resulting in high dark portion luminance. On the other hand, the pixels 100c and 100d adjacent to the crystal defect adjustment region 131 have a small amount of flowing-in dark current, resulting in low dark portion luminance. In this way, the luminance changes for each row of the pixel array unit 10, leading to degradation of image quality.

[0045] As methods for adjusting the crystal defects in the crystal defect adjustment region 131, a method of adjusting ion implantation energy, a method of adjusting the implantation dose during ion implantation, and a method of adjusting the size of the crystal defect adjustment region 131 are conceivable.

[0046] <Crystal Defect Adjustment> Figures 6A-6C show an example of a crystal defect adjustment region according to the first embodiment of this disclosure. Figure 6A shows an example of a crystal defect adjustment region 131 formed by ion implantation with higher energy compared to the well connection region 130. Due to the high energy of the ion implantation, the bottom of the crystal defect adjustment region 131 reaches a deep region of the semiconductor substrate 120.

[0047] Figure 6B shows the relationship between ion implantation energy and dark current. The horizontal axis of the figure represents the ion implantation energy [keV]. The vertical axis represents the dark current [e- / s]. The solid line in the figure represents the graph of the crystal defect adjustment region 131. The dashed line in the figure represents the graph of the well connection region 130. The dark current a in the figure represents the target dark current. This target dark current is, for example, 4 [e- / s]. At this target dark current, if the ion implantation energy of the well connection region 130 is E in the figure, then the ion implantation energy of the crystal defect adjustment region 131 is approximately three times that, or 3E. The well connection region 130 has a relatively low ion implantation energy because it contains crystal defects associated with the formation of the well connection wiring 159.

[0048] Figure 6C shows the relationship between impurity concentration and depth from the surface of the semiconductor substrate 120. The horizontal axis of the figure represents depth [μm]. The vertical axis of the figure represents impurity concentration [cm]. －３ This represents [ ]. The solid line in the figure is the graph when the ion implantation energy is 3E in Figure 6B. The dashed line in the figure is the graph when the ion implantation energy is E in Figure 6B. Also, the impurity concentration b in the figure represents the target impurity concentration. This target impurity concentration is, for example, 1E18 [cm －３ This is the case. At the target impurity concentration, if the ion implantation energy is 3E, the depth will be approximately three times that of when the ion implantation energy is E. In this way, by adjusting the ion implantation energy, defects in the crystal defect adjustment region 131 can be adjusted.

[0049] Figures 7A-7C show other examples of crystal defect adjustment regions according to the first embodiment of the present disclosure. Figure 7A shows an example of a crystal defect adjustment region 131 formed by ion implantation with an increased implantation amount compared to the well connection region 130. Due to the increased implantation amount, it is possible to form a crystal defect adjustment region 131 containing approximately the same number of crystal defects as the well connection region 130 after the formation of the well connection wiring 159.

[0050] Figure 7B shows the relationship between injection volume and dark current. The horizontal axis of the figure represents the injection volume [cm²]. －２ This represents [ ]. The vertical axis of the figure represents the dark current [e- / s]. The solid line in the figure represents the graph of the crystal defect adjustment region 131. The dashed line in the figure represents the graph of the well connection region 130. Also, the dark current a in the figure represents the target dark current, as in Figure 6B. At this target dark current, if the injection amount in the well connection region 130 is I in the figure, the injection amount in the crystal defect adjustment region 131 becomes approximately three times that, 3I.

[0051] Figure 7C shows the relationship between impurity concentration and depth from the surface of the semiconductor substrate 120. The horizontal axis of the figure represents depth [μm]. The vertical axis of the figure represents impurity concentration [cm]. －３ This represents the case where the injection amount is 3I in Figure 7B. The dashed line in the same figure represents the case where the injection amount is I in Figure 7B. When the injection amount is 3I, the impurity concentration increases by 15% compared to when the injection amount is I. In this way, defects in the crystal defect adjustment region 131 can be adjusted by adjusting the injection amount.

[0052] Figures 8A and 8B show other examples of crystal defect adjustment regions according to the first embodiment of the present disclosure. Figure 8A shows an example of a crystal defect adjustment region 131 with increased size compared to the well connection region 130. Due to its larger size, the crystal defect adjustment region 131 can be formed containing approximately the same number of crystal defects as the well connection region 130 after the formation of the well connection wiring 159.

[0053] Figure 8B shows the relationship between size and dark current. The horizontal axis of the figure represents the width [nm] of the crystal defect adjustment region 131. Note that the width of the crystal defect adjustment region 131 in the figure represents the width when the crystal defect adjustment region 131 is configured in a square shape. The vertical axis of the figure represents the dark current [e- / s]. The solid line in the figure represents the graph of the crystal defect adjustment region 131. The dashed line in the figure represents the graph of the well connection region 130. Also, "a" in the figure represents the target dark current, as in Figure 6B. At this target dark current, the width of the well connection region 130 is width W1, and the width of the crystal defect adjustment region 131 is approximately 1.4 times that width, W2. Thus, the size (area) of the crystal defect adjustment region 131 can be made 2 to 3 times the size (area) of the well connection region 130. In this way, defects in the crystal defect adjustment region 131 can be adjusted by adjusting the size.

[0054] <Method for Manufacturing an Image Sensor> Figures 9A-9I show an example of a method for manufacturing an image sensor according to the first embodiment of this disclosure. First, an insulating film 141 is formed on the surface of a semiconductor substrate 120. Next, a gate electrode 142 such as a reset transistor 111 is placed (Figure 9A).

[0055] Next, a resist 400 is placed on the surface of the semiconductor substrate 120. In this resist 400, an opening 401 is placed in the region where the crystal defect adjustment region 131 is formed (Figure 9B).

[0056] Next, ion implantation is performed using the resist 400 as a mask (Figure 9C). The thick arrows in the figure represent ion implantation. This forms the crystal defect adjustment region 131 (Figure 9C). After that, the resist 400 is removed.

[0057] Next, a resist 402 is placed on the surface of the semiconductor substrate 120. Openings 403 are placed in the region that forms the well connection region 130 in this resist 402 (Figure 9D).

[0058] Next, ion implantation is performed using the resist 402 as a mask (Figure 9E). The arrows in the figure represent ion implantation. The energy of this ion implantation is lower than the energy of the ion implantation in Figure 9C. This forms the well connection region 130 (Figure 9E). After that, the resist 402 is removed.

[0059] Next, a sidewall 149 is formed on the side surface of the gate electrode 142 (Figure 9F). After that, heat treatment is performed (not shown).

[0060] Next, an insulating layer 151 is placed on the surface of the semiconductor substrate 120 (Figure 9G). Next, an opening 404 is formed in the region of the insulating layer 151 where the well connection wiring 159 will be formed (Figure 9H). Next, the well connection wiring 159 is formed in the opening 404 (Figure 9I).

[0061] Figure 10 shows another example of a pixel configuration according to the first embodiment of the present disclosure. The figure shows an example where two pixel blocks are connected. The crystal defect adjustment region 131 can be placed between the two pixel blocks. The wiring 152 in the figure represents wiring that connects the charge holding portions 103 of the two pixel blocks. Since no contact plugs are placed in the crystal defect adjustment region 131, the wiring 152 can be placed on top of each other. This makes it possible to create the shortest possible wiring distance.

[0062] Thus, the image sensor 1 of the first embodiment of this disclosure controls the dark current of the pixel 100 using a crystal defect adjustment region 131 that does not require a contact plug. This eliminates the need for special contact plugs and simplifies the manufacturing process.

[0063] (2. Second Embodiment) A variation of the image sensor 1 of the first embodiment described above will be explained.

[0064] <Pixel Configuration> Figures 11A to 11D are diagrams showing examples of pixel configurations according to the second embodiment of the present disclosure. Figures 11A to 11D show variations in the arrangement of the well connection region 130 and the crystal defect adjustment region 131 in two pixel blocks. The upward-sloping diagonal hatching represents the first pixel, and the downward-sloping diagonal hatching represents the second pixel.

[0065] Figures 12A and 12B show examples of pixel configurations according to a second embodiment of the present disclosure. Figures 12A and 12B show variations in the arrangement of the well connection region 130 and the crystal defect adjustment region 131 in a single pixel block.

[0066] The configuration of the image sensor 1 other than that described above is the same as that of the image sensor 1 in the first embodiment of this disclosure, so a description will be omitted.

[0067] (3. Configuration of Electronic Devices) The image sensor 1 described above can be applied to various electronic devices such as imaging systems like digital still cameras and digital video cameras, mobile phones equipped with imaging functions, or other devices equipped with imaging functions.

[0068] Figure 13 is a block diagram showing an example configuration of an imaging device mounted on an electronic device. As shown in Figure 13, the electronic device 701 includes an optical system 702, a light detection device 703, and a DSP (Digital Signal Processor) 704. The DSP 704, display device 705, operating system 706, memory 708, recording device 709, and power supply system 710 are connected via a bus 707, and the device is capable of capturing still and moving images.

[0069] The optical system 702 is composed of one or more lenses and guides the image light (incident light) from the subject to the light detection device 703, where it forms an image on the light-receiving surface (sensor part) of the light detection device 703.

[0070] The image sensor 1 of any of the above-described configuration examples is applied to the light detection device 703. Electrons are accumulated in the light detection device 703 for a certain period of time according to the image formed on the light-receiving surface via the optical system 702. Then, a signal corresponding to the electrons accumulated in the light detection device 703 is input to the DSP 704.

[0071] The DSP 704 performs various signal processing on the signal from the light detection device 703 to acquire an image, and temporarily stores the image data in the memory 708. The image data stored in the memory 708 is recorded in the recording device 709 or supplied to the display device 705 to display the image. The operation system 706 accepts various operations from the user and supplies operation signals to each block of the electronic equipment 701, and the power supply system 710 supplies the power necessary to drive each block of the electronic equipment 701.

[0072] Furthermore, the DSP 704 can process the image signal from the image sensor 1. This processing includes, for example, interpolation processing. Note that the DSP 704 is an example of a "processing circuit" in this disclosure. The electronic device in Figure 13 is an example of an "imaging device" in this disclosure.

[0073] Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also occur.

[0074] Furthermore, this technology can also take the following configurations: (1) An image sensor having a first pixel and a second pixel, each having a photoelectric conversion unit that performs photoelectric conversion of incident light formed on a semiconductor substrate; a well connection region, which is formed by ion implantation of impurities into the semiconductor substrate and to which a reference potential of the well region of the semiconductor substrate is transmitted, and which is arranged in close proximity to the first pixel and spaced apart from the second pixel; and a crystal defect adjustment region, which is formed by ion implantation of impurities into the semiconductor substrate and is arranged in close proximity to the second pixel and spaced apart from the first pixel, in which crystal defects are adjusted according to the crystal defects of the well connection region. (2) The image sensor according to (1), further having a well connection wiring that transmits the reference potential to the well connection region. (3) The image sensor according to (2), wherein the well connection wiring is composed of contact plugs. (4) The image sensor according to any one of (1) to (3), wherein the crystal defect adjustment region is adjusted by adjusting the energy during ion implantation. (5) The image sensor according to (4), wherein the crystal defect adjustment region is subjected to ion implantation with an energy approximately three times that of the ion implantation energy in the well connection region. (6) The image sensor according to any one of (1) to (3), wherein the crystal defect adjustment region is subjected to ion implantation with an energy approximately three times that of the ion implantation energy in the well connection region. (7) The image sensor according to (6), wherein the crystal defect adjustment region is subjected to ion implantation with an energy approximately three times that of the ion implantation amount in the well connection region. (8) The image sensor according to any one of (1) to (3), wherein the crystal defect adjustment region is subjected to ion implantation with an energy approximately three times that of the ion implantation energy in the well connection region. (9) The image sensor according to (8), wherein the crystal defect adjustment region is configured to be two to three times the size of the well connection region.(10) An imaging device comprising: a first pixel and a second pixel, each having a photoelectric conversion unit for performing photoelectric conversion of incident light formed on a semiconductor substrate; a well connection region, which is composed of a semiconductor region formed by ion implantation of impurities into the semiconductor substrate and to which a reference potential of the well region of the semiconductor substrate is transmitted, and is arranged in close proximity to the first pixel and spaced apart from the second pixel; a crystal defect adjustment region, which is composed of a semiconductor region formed by ion implantation of impurities into the semiconductor substrate, and is arranged in close proximity to the second pixel and spaced apart from the first pixel, and whose crystal defects are adjusted according to the crystal defects of the well connection region; and a processing circuit for processing a pixel signal, which is a signal based on the charge generated by the photoelectric conversion.

[0075] 1 Image sensor 10 Pixel array section 100, 100a, 100b, 100c, 100d Pixels 101, 101a, 101c Photoelectric conversion section 102 Charge transfer section 103 Charge holding section 130 Well connection area 701 Electronic equipment 703 Photodetector

Claims

1. An image sensor comprising: a first pixel and a second pixel, each having a photoelectric conversion unit for performing photoelectric conversion of incident light formed on a semiconductor substrate; a well connection region, which is formed by ion implantation of impurities into the semiconductor substrate and to which a reference potential of the well region of the semiconductor substrate is transmitted, and is positioned in close proximity to the first pixel and spaced apart from the second pixel; and a crystal defect adjustment region, which is formed by ion implantation of impurities into the semiconductor substrate, and is positioned in close proximity to the second pixel and spaced apart from the first pixel, in which crystal defects are adjusted according to the crystal defects of the well connection region.

2. The image sensor according to claim 1, further comprising well connection wiring for transmitting the reference potential to the well connection region.

3. The image sensor according to claim 2, wherein the well connection wiring is composed of a contact plug.

4. The image sensor according to claim 1, wherein the crystal defect adjustment region is adjusted by adjusting the energy during ion implantation.

5. The image sensor according to claim 4, wherein the crystal defect adjustment region is subjected to ion implantation with an energy approximately three times that of the ion implantation energy in the well connection region.

6. The image sensor according to claim 1, wherein the crystal defect adjustment region is adjusted by adjusting the amount of ion implantation during the ion implantation.

7. The image sensor according to claim 6, wherein the crystal defect adjustment region is subjected to ion implantation with an amount approximately three times the amount implanted in the well connection region.

8. The image sensor according to claim 1, wherein the crystal defect adjustment region is adjusted by adjusting its size.

9. The image sensor according to claim 8, wherein the crystal defect adjustment region is configured to be two to three times the size of the well connection region.

10. An imaging device comprising: a first pixel and a second pixel, each having a photoelectric conversion unit for performing photoelectric conversion of incident light formed on a semiconductor substrate; a well connection region, which is formed by ion implantation of impurities into the semiconductor substrate and to which a reference potential of the well region of the semiconductor substrate is transmitted, and is arranged in close proximity to the first pixel and spaced apart from the second pixel; a crystal defect adjustment region, which is formed by ion implantation of impurities into the semiconductor substrate and is arranged in close proximity to the second pixel and spaced apart from the first pixel, and whose crystal defects are adjusted according to the crystal defects of the well connection region; and a processing circuit for processing a pixel signal, which is a signal based on the charge generated by the photoelectric conversion.

Images