Light detection device

Abstract

[Problem] To ensure a sufficient area for a photoelectric conversion part even as miniaturization progresses. [Solution] A light detection device comprises: a plurality of pixels each having a photoelectric conversion part that performs photoelectric conversion of incident light and a floating diffusion region that holds charges obtained by the photoelectric conversion; and a plurality of pixel circuits shared, on a per-pixel-group basis, by a plurality of pixel groups each including two or more of the plurality of pixels. The plurality of pixel groups and the plurality of pixel circuits are disposed along a first direction and a second direction that intersect each other. The plurality of pixel circuits each have a plurality of pixel transistors that are disposed symmetrically with respect to the first direction and / or the second direction. The plurality of pixel transistors are disposed in at least two rows along the first direction or the second direction.

Description

Photodetection device

[0001] The present disclosure relates to a photodetection device.

[0002] Image sensors with expanded dynamic range achieved by varying photoelectric conversion efficiency are widely used. For imaging under low illuminance, a pixel circuit is shared by a plurality of pixels, thereby increasing the amount of charge in a floating diffusion region and performing photoelectric conversion with high conversion efficiency. On the other hand, when imaging is performed under high illuminance, it is desirable to provide a charge holding portion capable of holding charge in addition to the floating diffusion region and perform photoelectric conversion with low conversion efficiency.

[0003] Pixels tend to be miniaturized along with the progress of semiconductor process technology and the improvement of resolution of captured images. On the other hand, a pixel circuit capable of variably controlling photoelectric conversion efficiency has a complicated circuit configuration, which makes it difficult to sufficiently secure the area of the photoelectric conversion portion in the pixel. Against this background, a technique for securing the arrangement area of the photoelectric conversion portion by arranging a plurality of pixel transistors in a boundary region of pixels has been proposed (see Patent Document 1).

[0004] Japanese Unexamined Patent Application Publication No. 2007-115994

[0005] However, it is necessary to provide contacts for connecting to a power supply voltage wiring and a ground voltage wiring in the pixel boundary region, and there are cases where a space for arranging a plurality of pixel transistors in the pixel boundary region cannot necessarily be secured.

[0006] Accordingly, the present disclosure provides a photodetection device capable of securing a sufficient area for a photoelectric conversion portion even as pixel miniaturization progresses.

[0007] To solve the above problems, the present disclosure provides a photodetector comprising: a plurality of pixels each having a photoelectric conversion unit that performs photoelectric conversion of incident light and a floating diffusion region that holds the photoelectrically converted charge; a plurality of pixel circuits shared by each of a plurality of pixel groups each containing two or more of the plurality of pixels; the plurality of pixel groups and the plurality of pixel circuits are arranged along a first direction and a second direction that intersect each other; each of the plurality of pixel circuits has a plurality of pixel transistors arranged symmetrically with respect to at least one of the first direction or the second direction; and the plurality of pixel transistors are arranged in at least two rows along the first direction or the second direction.

[0008] The plurality of pixel transistors may be arranged symmetrically with respect to the boundary region of the pixel extending in at least one of the first or second directions.

[0009] Each of the plurality of pixels has a transfer transistor, and may further include an insulating layer or diffusion isolation layer disposed between the transfer transistor and the pixel transistor, or between at least one of the plurality of pixel transistors.

[0010] The insulating layer may be divided at the boundary regions of each of the two or more pixel groups arranged along the first direction.

[0011] The boundary of the pixel sharing range, which includes each of the plurality of pixel groups and the corresponding pixel circuit, and the boundary of the arrangement area of ​​the pixel circuit corresponding to each of the plurality of pixel groups may be offset.

[0012] Each of the aforementioned plurality of pixel groups may be arranged across two adjacent pixel sharing ranges in the first or second direction.

[0013] The plurality of pixel groups may include impurity diffusion regions arranged along the boundary regions of each of them.

[0014] The impurity diffusion region may be electrically connected to the well contact region.

[0015] The multiple well contact regions and the multiple floating diffusion regions, each set to a reference voltage, may be arranged alternately along the first or second direction of the pixel group.

[0016] The system may include a contact member connected to a well contact region among the plurality of well contact regions that does not overlap with the power supply voltage wiring in a plan view.

[0017] The system may also include power supply voltage wiring that is arranged along the boundary region of the pixels extending in the second direction and is divided into multiple sections to match the location of the contact members.

[0018] Each of the plurality of pixels has a transfer transistor, and the plurality of well contact regions and the plurality of floating diffusion regions may be arranged along the first direction, passing between two adjacent transfer transistors in the second direction.

[0019] Each of the plurality of pixel circuits has a conversion efficiency switching transistor, which is shared by two of the pixel circuits adjacent in the first direction, and may further include a charge holding unit that holds the charge generated by the photoelectric conversion of the two corresponding photoelectric conversion units when the two conversion efficiency switching transistors of the two pixel circuits are turned on.

[0020] The charge holding portion and the wiring connected to the charge holding portion may be arranged along the boundary region between two adjacent pixel circuits in the first direction.

[0021] The pixel group may include two or more pairs of pixels for phase difference detection, and phase difference detection may be performed for each pixel group.

[0022] According to this disclosure, a photodetector is provided, comprising: a plurality of pixels each having a photoelectric conversion unit that performs photoelectric conversion of incident light and a floating diffusion region that holds the photoelectrically converted charge; a plurality of pixel circuits shared by each of a plurality of pixel groups each containing two or more of the plurality of pixels; each of the plurality of pixel circuits having a plurality of pixel transistors including a conversion efficiency switching transistor; and a charge holding unit that holds the photoelectrically converted charge when the conversion efficiency switching transistor is on; the conversion efficiency switching transistor having, in a plan view, a first side facing the floating diffusion region and a second side facing the charge holding unit, the first side being shorter than the second side.

[0023] Each of the plurality of pixel circuits has a reset transistor, the reset transistor having, in a plan view, a third side facing the floating diffusion region and a fourth side electrically connected to the power supply voltage wiring, the third side may be shorter than the fourth side.

[0024] The reset transistor has a fifth side facing the photoelectric conversion unit in a plan view, and the fifth side may be longer than the third side.

[0025] Each of the plurality of pixel circuits has an amplifying transistor, and the width of the source region of the amplifying transistor may be narrower than the width of the drain region of the amplifying transistor.

[0026] The plurality of pixel groups and the plurality of pixel circuits are arranged along a first direction and a second direction that intersect each other, the plurality of pixel transistors are arranged in two rows along the first direction or the second direction, the plurality of pixel transistors have a trapezoidal shape in plan view, the orientation of the pixel transistors in each of the two rows is opposite to that of the others, and two or more of the pixel groups arranged in the first direction or the second direction may be arranged in a staggered pattern.

[0027] A block diagram of an electronic device equipped with a photodetector according to one embodiment of the present disclosure. A schematic perspective view showing an example of a two-layer stacked structure for the photodetector according to the present disclosure. A schematic perspective view showing an example of a three-layer structure for the photodetector according to the present disclosure. A block diagram showing the overall configuration of the photodetector according to the present disclosure. A circuit diagram showing the pixel configuration of the photodetector according to the first embodiment. A timing diagram when one of the two pixel circuits sharing the charge holding part in Figure 4 is driven by an HCG. A timing diagram when one of the two pixel circuits sharing the charge holding part is driven by an LCG. A layout diagram of the pixel group and pixel circuit of the photodetector according to the first embodiment. A cross-sectional view along line A-A' in Figure 7. A cross-sectional view along line B-B' in Figure 7. A cross-sectional view along line C-C' in Figure 7. A cross-sectional view along line D-D' in Figure 7. A circuit diagram of the pixel circuit in the photodetector according to the second embodiment. A timing diagram of HCG driving according to the second embodiment. A circuit diagram of the pixel circuit in the photodetector according to the third embodiment. A timing diagram of HCG driving of the pixel circuit according to the third embodiment. A timing diagram of the pixel circuit during LCG drive according to the third embodiment. A layout diagram of the pixel group and pixel circuit in the photodetector according to the third embodiment. A circuit diagram of a pixel circuit according to one modified example of the third embodiment. A diagram illustrating the readout order of four rows of pixel signals arranged adjacently in the second direction. A layout diagram of the pixel group and pixel circuit in the photodetector according to the fourth embodiment. A diagram showing the planar layout of the second wiring layer arranged on the silicon layer and first wiring layer of the first substrate. A cross-sectional view of line A-A' in Figure 18. A layout diagram of the pixel group and pixel circuit of the photodetector according to the fifth embodiment. A layout diagram of the pixel group and pixel circuit of the photodetector according to the sixth embodiment. A layout diagram of the pixel group and pixel circuit of the photodetector according to the seventh embodiment. A layout diagram of the pixel group and pixel circuit of the photodetector according to the eighth embodiment. A layout diagram of the pixel group and pixel circuit of the photodetector according to the ninth embodiment. A layout diagram of the pixel group and pixel circuit of the photodetector according to the tenth embodiment. A layout diagram of the pixel group and pixel circuit of the photodetector according to the eleventh embodiment. A layout diagram of the pixel group and pixel circuit of the photodetector according to the twelfth embodiment. Layout diagram of the pixel group and pixel circuit of the photodetector according to the thirteenth embodiment. Layout diagram of the pixel group and pixel circuit of the photodetector according to the fourteenth embodiment.Layout diagram of the pixel group and pixel circuit of the photodetector according to the 15th embodiment. Layout diagram of the pixel group and pixel circuit of the photodetector according to the 16th embodiment. Layout diagram of the pixel group and pixel circuit of the photodetector according to the 17th embodiment. Layout diagram of the pixel group and pixel circuit of the photodetector according to the 18th embodiment. Layout diagram of the pixel group and pixel circuit of the photodetector according to the 19th embodiment. Enlarged plan view of the area around the conversion efficiency switching transistor and reset transistor in Figure 34. Layout diagram of the pixel group and pixel circuit of the photodetector according to the 20th embodiment. Layout diagram of the pixel group and pixel circuit of the photodetector according to the 21st embodiment. Layout diagram of the pixel group and pixel circuit of the photodetector according to the 22nd embodiment. Layout diagram of the pixel group and pixel circuit of the photodetector according to the 23rd embodiment. Layout diagram of the pixel group and pixel circuit of the photodetector according to the 24th embodiment. Block diagram showing an example of the schematic configuration of a vehicle control system. Explanatory diagram showing an example of the installation position of the external information detection unit and the imaging unit.

[0028] The embodiments of the photodetector will be described below with reference to the drawings. While the main components of the photodetector will be described below, there may be components and functions not shown or described in the drawings. The following description does not exclude any components or functions not shown or described.

[0029] Figure 1 is a block diagram of an electronic device 30 equipped with a light detection device 1 according to one embodiment of the present disclosure. This electronic device 30 has a function to generate an image corresponding to the brightness of incident light. The electronic device 30 in Figure 1 comprises a light detection device 1, an imaging lens 31, an image processing unit 32, a recording unit 33, and a control unit 34. The electronic device 30 can be applied to various electronic devices such as surveillance cameras, cameras mounted on industrial robots, or cameras for general use, but the specific application and configuration of the electronic device 30 are arbitrary.

[0030] The imaging lens 31 focuses the incident light and guides it to the photodetector 1. The photodetector 1 images the incident light. The photodetector 1 causes light in a predetermined wavelength range, such as visible light or infrared light, to be incident on multiple pixels and performs photoelectric conversion, accumulating a charge in the floating diffusion region corresponding to the amount of incident light. The charge accumulated in the floating diffusion region is converted into a voltage, and a pixel signal with a voltage level corresponding to the amount of incident light is generated. The photodetector 1 generates image data on a frame-by-frame basis based on the pixel signal of each pixel.

[0031] The light detection device 1 according to this embodiment has a plurality of pixels for detecting grayscale information or brightness information. The light detection device 1 according to this embodiment may also include pixels for an EVS (Event Vision Sensor) that detect changes in the amount of incident light as events.

[0032] The image processing unit 32 performs predetermined image processing on the image data generated by the light detection device 1, such as color or brightness adjustment, image compression, image recognition, tracking, or analysis. The image data processed by the image processing unit 32 is recorded, for example, in the recording unit 33.

[0033] The recording unit 33 records image data output from the light detection device 1 or the image processing unit 32. The recording unit 33 may be located on a server connected via a network. In the electronic device 30 according to this embodiment, at least one of the image processing unit 32 and the recording unit 33 in Figure 1 can be omitted.

[0034] The control unit 34 controls the operation of the light detection device 1. Although not explicitly shown in Figure 1, the control unit 34 may also control the image processing unit 32 and the recording unit 33.

[0035] (Two-Layer Lamination) The photodetector 1 according to this disclosure can be realized as a stacked chip. Figure 2A is a schematic perspective view showing an example of a two-layer stacked structure for the photodetector 1 according to this disclosure. The photodetector 1 in Figure 2A comprises a first substrate SB1 arranged on the light incident surface side and a second substrate SB2 stacked on the first substrate SB1. For example, a photoelectric conversion unit for each pixel is arranged on the first substrate SB1. The photoelectric conversion unit is, for example, a photodiode. Circuits surrounding the photoelectric conversion unit (for example, a transfer transistor) may also be arranged on the first substrate SB1. Multiple transistors for generating event signals are arranged on the second substrate SB2. The first substrate SB1 and the second substrate SB2 are joined and signal transmitted by, for example, a CCC (Cupper-Cupper Connection). Alternatively, the first substrate SB1 and the second substrate SB2 may be joined by vias or bumps other than a CCC. In this specification, the first substrate SB1 may be referred to as a pixel chip, and the second substrate SB2 may be referred to as a logic chip.

[0036] (Three-Layer Lamination) The photodetector 1 according to this disclosure can be constructed by laminating three or more substrates. Figure 2B is a schematic perspective view showing an example of a three-layer structure for the photodetector 1 according to this disclosure. Figure 2B shows an example in which the photodetector 1 has a laminated structure of a first substrate SB1, a second substrate SB2, and a third substrate SB3. Photoelectric conversion elements for each pixel are arranged on the first substrate SB1. Pixel transistors, for example, are arranged on the second substrate SB2. Signal processing circuits, for example, are arranged on the third substrate SB3.

[0037] The circuit elements and other components placed on the first substrate SB1, the second substrate SB2, and the third substrate SB3 are arbitrary and can be in any combination.

[0038] Figure 3 is a block diagram showing the overall configuration of the photodetector 1 according to this disclosure. The photodetector 1 shown in Figure 3 shows the block configuration of a CMOS (Complementary Metal Oxide Semiconductor) image sensor.

[0039] The light detection device 1 in Figure 3 comprises a pixel array section 2 and a peripheral circuit section 3.

[0040] The pixel array section 2 includes a plurality of pixels 4 that are two-dimensionally arranged in a first direction (e.g., row direction) X and a second direction (e.g., column direction) Y. Each pixel 4 includes a photoelectric conversion element, a floating diffusion region, a transfer transistor, a pixel transistor, and the like. This embodiment is characterized in that two or more pixels 4 can share a floating diffusion region.

[0041] In the pixel array section 2, a plurality of row selection lines LS and a plurality of vertical signal lines VSL are arranged. Each pixel 4 is connected to one of the row selection lines LS and one of the vertical signal lines VSL. The plurality of row selection lines LS extend in the first direction X and are arranged at intervals in the second direction Y. The plurality of vertical signal lines VSL extend in the second direction Y and are arranged at intervals in the first direction X.

[0042] The peripheral circuit section 3 includes a row selection section 5, a constant current source section 6, an analog-digital conversion section 7, a horizontal transfer scanning section 8, a signal processing section 9, a timing control section 10, and a reference signal generation section 11.

[0043] The row selection section 5 sequentially drives the plurality of row selection lines LS. The row selection section 5 includes a shift register, an address decoder, and the like that are not shown. The row selection section 5 performs read scanning and sweep scanning. In read scanning, the plurality of row selection lines LS are sequentially driven. Pixel signals corresponding to charges photoelectrically converted by each pixel 4 on the driven row selection line LS are output to the corresponding vertical signal lines VSL. In sweep scanning, the row selection line LS of a read row is driven to discharge charges from each pixel 4 before the start of an exposure period that is performed before the start of read scanning.

[0044] The constant current source section 6 includes a plurality of current sources connected to the plurality of vertical signal lines VSL. Each current source includes, for example, a MOS transistor, and supplies a bias current to each vertical signal line VSL.

[0045] The analog-digital conversion section 7 converts a plurality of pixel signals on the plurality of vertical signal lines VSL into digital signals. For each of the plurality of vertical signal lines VSL, the analog-digital conversion section 7 includes a comparator, a counter, and a latch that are not shown in FIG. 3.

[0046] Each comparator compares the pixel signal on the corresponding vertical signal line VSL with the reference signal generated by the reference signal generation unit 11. Each counter stops counting when the pixel signal matches the reference signal at the corresponding comparator. Each latch holds the count value when the corresponding counter stops the counting operation. The count value held by the latch generates a digital signal obtained by analog-to-digital converting the pixel signal.

[0047] The horizontal transfer scanning unit 8 controls transfer of the digital signal that has been subjected to analog-to-digital conversion by the analog-to-digital conversion unit 7. The horizontal transfer scanning unit 8 includes a shift register, an address decoder, and the like.

[0048] The signal processing unit 9 generates image data in frame units based on the digital signals of the respective pixels 4 transferred by the horizontal transfer scanning unit 8. For example, the signal processing unit 9 performs digital signal processing such as correction of vertical line defects and point defects, and level adjustment of luminance and gradation.

[0049] The timing control unit 10 generates various timing signals, clock signals, control signals, and the like, and performs drive control on the row selection unit 5, the constant current source unit 6, the reference signal generation unit 11, the analog-to-digital conversion unit 7, the horizontal transfer scanning unit 8, the signal processing unit 9, and the like using these signals.

[0050] (First Embodiment) FIG. 4 is a circuit diagram showing a pixel configuration of the photodetection device 1 according to the first embodiment. In the photodetection device 1 according to the first embodiment, for example, four pixels PX share one pixel circuit 20. As will be described later, the number of pixels PX sharing one pixel circuit 20 is arbitrary.

[0051] Hereinafter, a plurality of pixels PX sharing one pixel circuit 20 is referred to as a pixel group PXG. FIG. 4 shows an example in which one pixel group PXG includes four pixels PX. As shown in FIG. 4, two pixel groups PXG adjacent to each other in a first direction X share the charge holding unit 21. In the present specification, this may be referred to as FD linking. Also, in the present specification, the charge holding unit 21 may be referred to as a sub FD, and one pixel group PXG sharing the charge holding unit 21 and one pixel circuit 20 may be referred to as a pixel sharing range SU.

[0052] In the example shown in Figure 4, each pixel group PXG has four photoelectric converters (e.g., photodiodes) PD and four transfer transistors TRG. The four transfer transistors TRG are connected to a common floating diffusion region FD. The pixel circuit 20 is connected to this floating diffusion region FD. The charge photoelectrically converted by each photoelectric converter PD is transferred to the floating diffusion region FD when the corresponding transfer transistor TRG is turned on.

[0053] The pixel circuit 20 includes an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and a conversion efficiency switching transistor FDG.

[0054] The source of the selection transistor SEL is connected to the same vertical signal line VSL, along with the source of the selection transistor SEL in the pixel circuit 20 connected to the adjacent pixel group PXG. Of the two pixel circuits 20 adjacent in the first direction X, the pixel circuit 20 in which the corresponding selection transistor SEL is turned on outputs the corresponding pixel signal to a single vertical signal line VSL.

[0055] Thus, in the first embodiment, since two adjacent pixel circuits 20 in the first direction X (for example, the horizontal direction) output pixel signals to the same vertical signal line VSL, it is not possible to output two pixel signals in parallel from two horizontally adjacent pixels PX.

[0056] When the conversion efficiency switching transistor FDG is turned on, photoelectric conversion is performed at low conversion efficiency (LCG: Low Conversion Gain), and when it is turned off, photoelectric conversion is performed at high conversion efficiency (HCG: High Conversion Gain).

[0057] When the conversion efficiency switching transistor FDG is turned on, it transfers the charge from the floating diffusion region FD to the charge holding unit 21. As described above, the charge holding unit 21 is shared by two adjacent pixel groups PXG (two pixel circuits 20) in the first direction X (for example, the horizontal direction).

[0058] The four pixels PX that make up the pixel group PXG (hereinafter referred to as the first to fourth pixels) can be used as phase difference detection pixels. For example, one of the first and second pixels adjacent in the first direction X (e.g., the horizontal direction) (e.g., the first pixel) is shielded from light, and the other of the third and fourth pixels adjacent in the same first direction X (e.g., the fourth pixel) is shielded from light. As a result, phase difference information can be detected by taking the difference between the pixel signals of the unshielded second and third pixels. Only a portion of the pixel group PXG in the pixel array unit 2 can be used as phase difference detection pixels. Alternatively, all of the pixel group PXG in the pixel array unit 2 can be used as phase difference detection pixels.

[0059] Figure 5 is a timing diagram for when one of the two pixel circuits 20 sharing the charge holding section 21 in Figure 4 is driven by HCG. In HCG driving, exposure and pixel signal reading are performed with the conversion efficiency switching transistor FDG turned off. Figure 5 illustrates the potentials of the following: gate SEL1 of one of the two pixel circuits 20 sharing the charge holding section 21, gate SEL2 of the other selection transistor SEL, gate RST of the reset transistor RST in one of the pixel circuits 20, gate FDG of the conversion efficiency switching transistor FDG in one of the pixel circuits 20, gates TRG1 to TRG4 of the four transfer transistors TRG in one of the pixel circuits 20, the floating diffusion region FD of one of the pixel circuits 20, and the vertical signal line VSL.

[0060] At time t1 in Figure 5, the reset transistor RST and the selection transistor SEL of one of the two pixel circuits 20 that share the charge holding unit 21 are turned on. As a result, a pixel signal in a reset state is output from the one pixel circuit 20.

[0061] At time t2, the four transfer transistors TRG of one of the pixel circuits 20 are turned on. As a result, a pixel signal corresponding to the charge generated by the photoelectric conversion in one of the pixel groups PXG is output from one of the pixel circuits 20. At time t3, the selection transistor SEL of one of the pixel circuits 20 is turned off, ending the readout operation of the pixel signal from one of the pixel circuits 20.

[0062] Figure 6 is a timing diagram for when one of two pixel circuits 20 sharing a charge holding unit 21 is driven by the LCG. When the LCG is driven, the two pixel circuits 20 sharing the charge holding unit 21 output pixel signals in parallel. More specifically, at time t1, the reset transistor RST and the conversion efficiency switching transistor FDG of both pixel circuits 20 are turned on. As a result, the reset level pixel signals of the two pixel circuits 20 are output.

[0063] At time t2, all transfer transistors TRG (TRG1 to TRG8) of the two pixel groups PXG are turned on. As a result, pixel signals are output in parallel from the two pixel circuits 20, and the vertical signal line VSL reaches a potential level corresponding to the two pixel signals.

[0064] Thus, when HCG is driven, two adjacent pixel groups PXG and two pixel circuits 20 in the first direction X (for example, the horizontal direction) perform exposure and output pixel signals at different timings, while when LCG is driven, the two pixel groups PXG and pixel circuits 20 perform photoelectric conversion in parallel and output the generated pixel signal. Therefore, when LCG is driven, a pixel signal is output which is a composite of the two pixel signals generated by the two pixel groups PXG and two pixel circuits 20, thereby reducing random noise.

[0065] Figure 7 is a layout diagram of the pixel group PXG and pixel circuit 20 of the photodetector 1 according to the first embodiment. Similar to Figure 4, Figure 7 shows an example in which one pixel group PXG contains 2 x 2 = 4 pixels PX, and one pixel circuit 20 is connected to one pixel group PXG. Each pixel PX has a photoelectric conversion unit PD and a transfer transistor TRG. Each pixel circuit 20 has an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and a conversion efficiency switching transistor FDG. In this specification, each transistor in the pixel circuit 20 is collectively referred to as a pixel transistor. As will be described later, the multiple pixel transistors in the pixel circuit 20 are arranged in at least two rows along the first direction X or the second direction Y.

[0066] Although the photoelectric conversion unit PD is not shown in Figure 7, it is located, for example, below the transfer transistor TRG (on the back side of the page in Figure 7).

[0067] In the pixel sharing area SU shown by the dashed line in Figure 7, the transfer transistor TRG of one pixel group PXG and each pixel transistor of one pixel circuit 20 are arranged in four rows along the second direction Y (for example, the vertical direction). More specifically, the pixel sharing area SU in Figure 7 is provided with a row in which the amplification transistor AMP and the selection transistor SEL are arranged, a row in which two transfer transistors TRG are arranged, a row in which the remaining two transfer transistors TRG are arranged, and a row in which the reset transistor RST and the conversion efficiency switching transistor FDG are arranged.

[0068] Of the two pixel sharing ranges SU adjacent in the second direction Y, the row in one pixel sharing range SU where the reset transistor RST and the conversion efficiency switching transistor FDG are located, and the row in the other pixel sharing range SU where the amplification transistor AMP and the selection transistor SEL are located, are adjacent in the second direction Y. If the reset transistor RST and the conversion efficiency switching transistor FDG in one pixel circuit 20 and the amplification transistor AMP and the selection transistor SEL in the other pixel circuit 20 are located adjacent in the second direction Y, crosstalk may occur. Therefore, it is desirable that these two rows, a total of four pixel transistors, be included in the same pixel circuit 20.

[0069] In the first embodiment, a pixel circuit 20, which includes a reset transistor RST and a conversion efficiency switching transistor FDG located inside the pixel sharing range SU, and an amplification transistor AMP and a selection transistor SEL located outside the pixel sharing range SU, is associated with the pixel group PXG of the pixel sharing range SU. That is, the reset transistor RST and the conversion efficiency switching transistor FDG of the pixel circuit 20, which are connected to a pixel group PXG different from the pixel group PXG of the pixel sharing range SU, are located inside the pixel sharing range SU.

[0070] Thus, the boundary of the pixel sharing range SU and the boundary of the pixel circuit 20 are offset in at least part. That is, each of the multiple pixel circuits 20 is arranged to span two adjacent pixel sharing range SUs in the first direction X or the second direction Y.

[0071] An insulating layer 22 is placed between the transfer transistor TRG and the pixel transistor in each row of the second direction Y of the pixel sharing range SU. This insulating layer 22 may be referred to herein as the STI (Shallow Trench Isolation) layer 22. Furthermore, by placing the STI layer 22 between multiple adjacent pixel transistors in the second direction Y, i.e., in the boundary region of the pixel sharing range SU, capacitive coupling between each pixel transistor can be reduced. Thus, the STI layer 22 has a size and shape that can reduce capacitive coupling between the transfer transistor TRG and the pixel transistor, or between multiple pixel transistors.

[0072] Between two adjacent pixel sharing ranges SU in the first direction X (for example, the horizontal direction), a sub-FD wiring WR1 connected to the charge holding unit 21, a contact member CT1 connected to the charge holding unit 21, a ground voltage wiring WR2, a contact member CT2 connected to the ground voltage wiring WR2, a vertical signal line VSL, and a contact member CT3 connected to the vertical signal line VSL are arranged.

[0073] The STI layer 22 in Figure 7 is a continuous line-shaped layer extending in the first direction X. A P-type impurity diffusion region 23 is arranged to surround the two pixel sharing areas SU in Figure 7. The P-type impurity diffusion region 23 is set to, for example, the ground voltage level by a contact member CT2 connected to a well contact region 24. The well contact region 24 is connected to a P-type well layer arranged around the photoelectric conversion unit PD.

[0074] In the region extending in the first direction X through approximately the center of the second direction Y of the pixel sharing range SU (between two adjacent transfer transistors TRG in the second direction), floating diffusion regions FD and well contact regions 24 are alternately arranged. A power supply voltage wiring WR4 is arranged along the boundary region of the pixel PX extending in the second direction Y of the pixel sharing range SU, and multiple contact members CT4 for supplying power voltage are connected to this power supply voltage wiring WR4. A part of the power supply voltage wiring WR4 and a part of the P-type impurity diffusion region 23 overlap in a plan view. In the P-type impurity diffusion region 23, a well contact region 24 cannot be provided in the region that overlaps with the power supply voltage wiring WR4, so the well contact region 24 and contact members CT2 are provided in the region of the P-type impurity diffusion region 23 that does not overlap with the power supply voltage wiring WR4. In addition, an FD wiring WR5 is provided which is electrically connected to the floating diffusion region FD via contact members CT5.

[0075] In this way, by arranging the well contact regions 24 alternately with the floating diffusion regions FD, the potential of the P-type impurity diffusion regions 23 formed by P-type impurity ion implantation around the photoelectric conversion unit PD can be made uniform, and potential fluctuations on the anode side of the photoelectric conversion unit PD can be suppressed.

[0076] Two pixel circuits 20 sharing a charge holding section 21 are arranged adjacent to each other along a first direction X. These two pixel circuits 20 are arranged symmetrically with respect to the pixel boundary region between them. That is, each pixel transistor in the two pixel circuits 20 is mirrored with respect to the pixel boundary region. This allows the two conversion efficiency switching transistors FDG to be placed close together in the first direction X, and the distance between the two conversion efficiency switching transistors FDG and the sub-FD wiring WR1 and charge holding section 21 can be shortened. Furthermore, the distance from each conversion efficiency switching transistor FDG to the sub-FD wiring WR1 can be made the same, and the distance from each conversion efficiency switching transistor FDG to the charge holding section 21 can also be made the same. In this way, by mirroring the two pixel groups PXG and the two pixel circuits 20 with respect to the pixel boundary region, an FD link can be easily realized.

[0077] Figure 8A is a cross-sectional view taken along the line A-A' in Figure 7. An STI layer 22 is placed between the conversion efficiency switching transistor FDG and the selection transistor SEL (not shown in Figure 8A). Similarly, an STI layer 22 is also placed between the conversion efficiency switching transistor FDG and the transfer transistor TRG.

[0078] Furthermore, a pixel isolation region 25 is arranged along the boundary of the pixel PX. In this specification, the pixel isolation region 25 may be referred to as the DTI (Deep Trench Isolation) region 25. The DTI region 25 is, for example, a laminated structure of a light-shielding layer 25a and an insulating layer 25b. The light-shielding layer 25a is formed of, for example, tungsten. The insulating layer 25b is formed of, for example, an SiO2 layer.

[0079] A photoelectric conversion unit PD is arranged around the DTI region 25. The photoelectric conversion unit PD is, for example, an N-type well layer 26. A P-type well layer 27 is arranged on top of the N-type well layer 26. An STI layer 22 and a floating diffusion region FD are arranged on the upper surface side of the P-type well layer 27.

[0080] Figure 8B is a cross-sectional view of the line B-B' in Figure 7. The line B-B' is the region between pixel transistors arranged in two rows along the second direction Y, and is located in the boundary region of the pixel PX. A DTI region 25 is located along the B-B' line, a P-type well layer 27 is located above it, and an STI layer 22 is located above that.

[0081] Figure 8C is a cross-sectional view of the line C-C' in Figure 7. The line C-C' is the region between the pixel transistor and the transfer transistor TRG, which are arranged along the second direction Y. This region is provided with a plurality of DTI regions 25 arranged along the boundary region of the pixel PX, an N-type well layer 26 arranged between each DTI region 25, and a P-type well layer 27 arranged on top of the DTI regions 25 and the N-type well layer 26.

[0082] Figure 8D is a cross-sectional view of the line D-D' in Figure 7. The line D-D' is the region between two transfer transistors TRG arranged in two rows along the second direction Y. In this region, floating diffusion regions FD and well contact regions 24 are arranged alternately. Among the multiple well contact regions 24, contact members CT2 are connected to well contact regions 24 that do not have a power supply voltage wiring WR4 above them. These contact members CT2 are connected to the upper ground voltage wiring WR2 via an interlayer insulating film 13.

[0083] Thus, in the first embodiment, two pixel groups PXG, each having four pixels PX and four transfer transistors TRG, and two pixel circuits 20 connected to the two pixel groups PXG are arranged symmetrically with respect to the pixel boundary region, and a charge holding unit 21 and its connection wiring are placed between the two pixel groups PXG, thereby easily realizing an FD link that shares the charge holding unit 21.

[0084] Furthermore, by alternately arranging the floating diffusion region FD and the well contact region 24 along the first direction X, and setting the multiple well contact regions 24 to ground voltage via the contact member CT2, potential fluctuations in the well contact region 24 and the P-type well layer 27 can be suppressed.

[0085] Furthermore, by arranging the multiple pixel transistors constituting the pixel circuit 20 in two rows along the second direction Y, and ensuring that each pixel transistor in the two consecutive rows is included in the same pixel circuit 20, crosstalk between the pixel transistors in two adjacent pixel circuits 20 can be suppressed.

[0086] (Second Embodiment) Figure 9 is a circuit diagram of the pixel circuit 20 in the light detection device 1 according to the second embodiment. In Figure 4, the same gate signal FDG is input to the gates of two conversion efficiency switching transistors FDG in two pixel circuits 20 that share a charge holding unit 21, and the same gate signal RST is input to the gates of two reset transistors RST. In contrast, in Figure 9, different gate signals FDG1 and FDG2 are input to the gates of two conversion efficiency switching transistors FDG, and different gate signals RST1 and RST2 are input to the gates of two reset transistors RST.

[0087] In the second embodiment, the timing of LCG drive is the same as in Figure 6, but the timing of HCG drive is different from that in Figure 5.

[0088] In the second embodiment, when one of the two pixel circuits 20 sharing the charge holding section 21 is driven by HCG, the conversion efficiency switching transistor FDG1 of one pixel circuit 20 is turned off, and the conversion efficiency switching transistor FDG2 of the other pixel circuit 20 is turned on. As a result, the charge of the charge holding section 21 is initialized via the conversion efficiency switching transistor FDG2 and reset transistor RST of the other pixel circuit 20, and the potential level of the charge holding section 21 is no longer indeterminate. If both of the two conversion efficiency switching transistors FDG1 and FDG2 in the two pixel circuits 20 sharing the charge holding section 21 are turned off, the potential of the charge holding section 21 becomes indeterminate, and the potential of the floating diffusion region FD may fluctuate. In this embodiment, when the conversion efficiency switching transistor FDG1 of either of the two pixel circuits 20 is off, the other conversion efficiency switching transistor FDG2 is turned on to initialize the charge of the charge holding unit 21. As a result, the potential of the charge holding unit 21 does not become undefined, and potential fluctuations in the floating diffusion region FD can be suppressed.

[0089] Figure 10 is a timing diagram of HCG drive according to the second embodiment. Figure 10 shows the timing when exposure and output of a pixel signal are performed by one of two pixel circuits 20 that share a charge holding unit 21. At time t1 in Figure 10, the conversion efficiency switching transistor FDG2 of the other pixel circuit 20 that shares a charge holding unit 21 is turned on, the reset transistor RST of both pixel circuits 20 is turned on, and the selection transistor SEL1 of one of the pixel circuits 20 is turned on. As a result, a pixel signal in a reset state is output from one of the pixel circuits 20. Also, since both the reset transistor RST and the conversion efficiency switching transistor FDG2 in the other pixel circuit 20 are turned on, the charge held in the charge holding unit 21 is initialized, and the charge holding unit 21 is set to its initial potential level. As a result, the potential of the charge holding unit 21 does not become undefined, and potential fluctuations in the floating diffusion region FD of one of the pixel circuits 20 can be suppressed.

[0090] Thus, in the second embodiment, when performing HCG driving, the conversion efficiency switching transistor FDG and reset transistor RST of the other pixel circuit 20, which is different from the one pixel circuit 20 that performs exposure and outputs the pixel signal, among the two pixel circuits 20 that share the charge holding unit 21, are turned on to prevent the potential of the charge holding unit 21 from becoming undefined. This makes it possible to suppress fluctuations in the potential of the floating diffusion region FD of the one pixel circuit 20 that is being read out.

[0091] (Third Embodiment) Figure 11 is a circuit diagram of the pixel circuit 20 in the photodetector 1 according to the third embodiment. The pixel circuit 20 according to the third embodiment shown in Figure 11 differs from Figure 4 in that separate vertical signal lines VSL are connected to the output nodes of two pixel circuits 20 that share a charge holding unit 21. As a result, the two pixel circuits 20 that share a charge holding unit 21 according to the third embodiment can output pixel signals in parallel. In addition, the pixel circuit 20 in Figure 11 differs from the pixel circuit 20 in Figure 9 in that a common gate signal FDG is input to the two conversion efficiency switching transistors FDG, and a common gate signal SEL is input to the two selection transistors SEL.

[0092] Figure 12 is a timing diagram of the pixel circuit 20 during HCG drive according to the third embodiment. In Figure 5, the selection transistors SEL of two adjacent pixel circuits 20 in the first direction X could not be turned on simultaneously during HCG drive. However, in Figure 12, the selection transistors SEL of two pixel circuits 20 can be turned on simultaneously, and pixel signals can be output in parallel to the two vertical signal lines VSL. Therefore, the same gate signal SEL can be input to the gates of the selection transistors SEL of the two pixel circuits 20.

[0093] As shown in Figure 12, each pixel circuit 20 sharing the charge holding unit 21 outputs a pixel signal in a reset state at the timing when the reset transistor RST is turned on (time t1), and outputs a pixel signal corresponding to the charge generated by photoelectric conversion at the timing when the transfer transistor TRG is turned on (time t2). When the HCG is driven, two pixel signals can be transmitted in parallel using two vertical signal lines VSL adjacent to the first direction X, thereby improving the transmission speed of the pixel signals.

[0094] Figure 13 is a timing diagram of the LCG drive of the pixel circuit 20 according to the third embodiment. The timing in Figure 13 is the same as the timing in Figure 6. By turning on both of the two selection transistors SEL in the two pixel circuits 20 that share the charge holding unit 21, the same pixel signal can be output from the two vertical signal lines VSL adjacent to each other in the first direction X, thereby reducing random noise.

[0095] Figure 14 is a layout diagram of the pixel group PXG and pixel circuit 20 in the light detection device 1 according to the third embodiment. Between two adjacent pixel groups PXG and two pixel circuits 20 in the first direction X, a sub-FD wiring WR1 connected to the charge holding unit 21, a ground voltage wiring WR2, and two vertical signal lines VSL are arranged. The two vertical signal lines VSL are arranged in close proximity in the first direction X.

[0096] The two pixel groups PXG and the two pixel circuits 20 are arranged symmetrically with respect to the pixel boundary region extending in the second direction Y. Therefore, the distances from the two conversion efficiency switching transistors FDG to the charge holding section 21 can be made equal, and the distances from the two selection transistors SEL to the corresponding vertical signal lines VSL can also be made equal.

[0097] Figure 15 is a circuit diagram of a pixel circuit 20 according to a modified example of the third embodiment. Figure 15 shows the circuit configuration of two pixel groups PXG for three rows and two pixel circuits 20 arranged adjacent to each other in the second direction Y. Figure 16 is a diagram illustrating the readout order of pixel signals for four rows arranged adjacent to each other in the second direction Y.

[0098] As shown in Figure 15, the output nodes of the two pixel circuits 20 that share the charge holding section 21 are connected to the same vertical signal line VSL. This eliminates the need to divide the diffusion layers of the two selection transistors SEL and connect each diffusion layer to separate vertical signal lines VSL via separate contact members, thereby simplifying the layout design of the pixel circuit 20.

[0099] As shown in Figure 16, two vertical signal lines VSL are provided for each row of pixels PX arranged in the first direction X. Hereafter, these two vertical signal lines VSL will be referred to as the first vertical signal line VSL1 and the second vertical signal line VSL2.

[0100] The first vertical signal line VSL1 transmits the pixel signals output from the first and second row pixel circuits 20. The second vertical signal line VSL2 transmits the pixel signals output from the third and fourth row pixel circuits 20. The first vertical signal line VSL1 and the second vertical signal line VSL2 simultaneously transmit the pixel signals of the first and third row, and simultaneously transmit the pixel signals of the second and fourth row. As a result, the pixel signals of odd-numbered rows can be read out simultaneously using the first vertical signal line VSL1 and the second vertical signal line VSL2, and the pixel signals of even-numbered rows can be read out simultaneously.

[0101] Figure 15 shows an example where different signals are input to the gates of the reset transistor RST and the conversion efficiency switching transistor FDG in each row. However, the same signal may be input to the gates of the reset transistor RST in each row. Similarly, the same signal may be input to the gates of the conversion efficiency switching transistor FDG in each row.

[0102] Thus, in the third embodiment, two pixel signals can be output in parallel from two adjacent pixel circuits 20 in the first direction X, thereby improving the data transmission speed. Furthermore, pixel signals can be output in parallel from odd-numbered rows of pixel circuits 20 arranged in the second direction Y, and pixel signals can also be output in parallel from even-numbered rows of pixel circuits 20.

[0103] (Fourth Embodiment) Figure 17 is a layout diagram of the pixel group PXG and the pixel circuit 20 in the light detection device 1 according to the fourth embodiment. Figure 17 shows the planar layout of the silicon layer of the first substrate SB1 and the first wiring layer on it, which are arranged on the light incident surface side, and Figure 18 shows the planar layout of the second wiring layer arranged on the silicon layer and the first wiring layer of the first substrate SB1.

[0104] As shown in Figure 17, in the first wiring layer, a first power supply voltage wiring WR6 and a first ground voltage wiring WR7 are provided on the same line, separated from each other, along the boundary region of the pixel group PXG, in the second direction Y. The first ground voltage wiring WR7 is used for connection with the well contact region 24.

[0105] As shown in Figure 18, the second wiring layer, which is provided above the first wiring layer, is provided with a second power supply voltage wiring WR8 and a second ground voltage wiring WR9 extending in the second direction Y along the boundary region of the pixel group PXG. In the first wiring layer, the first power supply voltage wiring WR6 is arranged in a divided manner, and since it is not possible to secure sufficient space for the first power supply voltage wiring WR6, a second power supply voltage wiring WR8, which has a larger arrangement area than the first power supply voltage wiring WR6, is provided at a position that overlaps with the first power supply voltage wiring WR6 in a plan view. In addition, the second ground voltage wiring WR9 is arranged in the second wiring layer at a position that overlaps with the ground voltage wiring WR2 in a plan view. Furthermore, the second wiring layer is provided with a ground voltage wiring WR10 extending in the first direction X and a wiring WR11 extending in the first direction X along the wiring WR1 connected to the charge holding unit 21.

[0106] Figure 19 is a cross-sectional view taken along the line B-B' in Figure 18. The first to third contact members CT11 to CT13 are connected to the floating diffusion region FD, the gate of the transfer transistor TRG, and the well contact region 24, respectively. The first to third contact members CT11 to CT13 are connected to three different wirings of the first wiring layer 28. These three wirings are connected to three different wirings of the second wiring layer 29 via the fourth to sixth contact members CT14 to CT16.

[0107] Thus, in the fourth embodiment, the first power supply voltage wiring WR6, which is arranged along the boundary region of the pixel group PXG of the first wiring layer 28, is divided into multiple sections, and the first ground voltage wiring WR7 is placed in between them to electrically connect with the well contact region 24. This suppresses potential fluctuations between the well contact region 24 and the P-type well layer 27. In addition, a second power supply voltage wiring WR8, which has a larger arrangement area than the first power supply voltage wiring WR6, is provided in the second wiring layer 29 to prevent fluctuations in the power supply voltage.

[0108] (Fifth Embodiment) Figure 20 is a layout diagram of the pixel group PXG and pixel circuit 20 of the light detection device 1 according to the fifth embodiment. In the fifth embodiment, the pixel group PXG is composed of 2 × 4 = 8 pixels PX, and one pixel circuit 20 is shared for each pixel group PXG. Phase difference detection may be performed for each pixel group PXG, or phase difference detection may be performed for two pixel groups PXG.

[0109] As shown in Figure 20, between two adjacent pixel groups PXG in the first direction X, a ground voltage wiring WR2 extending in the second direction Y, a vertical signal line VSL, and a sub-FD wiring WR1 connected to the charge holding unit 21 are arranged. In addition, STI layers 22 are arranged between adjacent pixel transistors and transfer transistors TRG in the second direction Y, and between multiple pixel transistors arranged in two rows in the second direction Y.

[0110] Two adjacent pixel groups PXG and two pixel circuits 20 in the first direction X are arranged symmetrically with respect to the boundary region of a pixel PX in the second direction Y. That is, two adjacent pixel groups PXG and two pixel circuits 20 in the first direction X are arranged in a mirror configuration.

[0111] The pixel transistors are arranged in two rows along the second direction Y, and these four pixel transistors arranged in two consecutive rows are used as a pixel circuit 20 of the same pixel group PXG.

[0112] Between the four transfer transistors TRG arranged in two rows in the second direction Y, contact members connected to the floating diffusion region FD and contact members connected to the well contact region 24 are alternately arranged along the first direction X.

[0113] Thus, in the fifth embodiment, a pixel group PXG is formed by 2 × 4 = 8 pixels PX, and one pixel circuit 20 is shared. Therefore, the arrangement ratio of pixel circuits 20 can be reduced compared to the first to fourth embodiments, enabling further miniaturization.

[0114] (Sixth Embodiment) Figure 21 is a layout diagram of the pixel group PXG and pixel circuit 20 of the photodetector 1 according to the sixth embodiment. The photodetector 1 according to the sixth embodiment differs from Figure 7 in that the well contact region 24 is not arranged between the floating diffusion regions FD which are spaced apart in the first direction X. Other features are the same as in Figure 7.

[0115] In the sixth embodiment, similar to the first embodiment, four pixel transistors arranged in two rows along the second direction Y are used as the pixel circuit 20 of the corresponding pixel group PXG, thereby suppressing coupling between pixel transistors.

[0116] Furthermore, since two adjacent pixel groups PXG and two pixel circuits 20 in the first direction X are arranged in a mirror configuration, a sub-FD wiring WR1 connected to the charge holding unit 21 can be placed between the two adjacent pixel groups PXG and two pixel circuits 20 in the first direction X, making it easy to realize an FD link.

[0117] Furthermore, by placing the STI layer 22 between pixel transistors arranged in two rows along the second direction Y, and between adjacent transfer transistors TRG and pixel transistors in the second direction Y, crosstalk between the transfer transistors TRG or pixel transistors can be suppressed, and potential fluctuations in the floating diffusion region FD can be eliminated. In the sixth embodiment, the STI layer 22 is a single continuous layer arranged along the first direction X.

[0118] Furthermore, when the LCG is driven and the conversion efficiency switching transistor FDG is turned on, the output nodes of two adjacent pixel circuits 20 in the first direction X are short-circuited and the pixel signal is output to a single vertical signal line VSL, thereby reducing random noise.

[0119] (Seventh Embodiment) Figure 22 is a layout diagram of the pixel group PXG and pixel circuit 20 of the light detection device 1 according to the seventh embodiment. In the seventh embodiment, the STI layer 22, which is arranged between pixel transistors that are divided into two rows along the second direction Y, is divided near the boundary of the pixel group PXG. Similarly, the STI layer 22, which is arranged between adjacent transfer transistors TRG and pixel transistors in the second direction Y, is divided near the boundary of the pixel group PXG.

[0120] In this way, by dividing the STI layer 22, stress concentration in the STI layer 22 can be alleviated compared to when the STI layer 22 is continuous, and defects such as cracks in the STI layer 22 can be prevented. For example, where four pixel PXs intersect, the DTI regions 25 intersect with each other. When the STI layer 22 is placed above the DTI regions 25, the STI layer 22 may experience greater stress near the intersection of the DTI regions 25. Therefore, the STI layer 22 is partially divided and placed away from the intersection of the DTI regions 25. This allows the stress on the STI layer 22 to be alleviated.

[0121] (Eighth Embodiment) Figure 23 is a layout diagram of the pixel group PXG and pixel circuit 20 of the light detection device 1 according to the eighth embodiment.

[0122] In the eighth embodiment, as shown in Figure 23, an STI layer 22 is placed between adjacent selection transistor SEL and transfer transistor TRG in the second direction Y, an STI layer 22 is placed between adjacent conversion efficiency switching transistor FDG and transfer transistor TRG in the second direction Y, and an STI layer 22 is placed between adjacent conversion efficiency switching transistor FDG and selection transistor SEL in the second direction Y.

[0123] In the eighth embodiment, the length of each STI layer 22 in the second direction Y is made as short as possible, and as described above, the STI layers 22 are placed only in the vicinity of the selection transistor SEL and the conversion efficiency switching transistor FDG. This makes it possible to avoid stress concentration in the STI layers 22.

[0124] Furthermore, in the eighth embodiment, since the STI layer 22 is placed near the conversion efficiency switching transistor FDG and the selection transistor SEL, the potential fluctuations of the floating diffusion region FD and the signal level fluctuations of the pixel signal can be suppressed.

[0125] (Ninth Embodiment) Figure 24 is a layout diagram of the pixel group PXG and pixel circuit 20 of the light detection device 1 according to the ninth embodiment.

[0126] In the ninth embodiment, as shown in Figure 24, a diffusion separation layer 14 is placed along the boundary region of two adjacent pixel sharing regions SU in the second direction Y, instead of an STI layer 22. The diffusion separation layer 14 is formed by implanting, for example, P-type impurity ions into an N-type well layer 26. At the location where the diffusion separation layer 14 is placed, there is a place where four pixels PX intersect, and at this location, DTI regions 25 intersect. Therefore, if the STI layer 22 is placed above the DTI regions 25, the STI layer 22 may be subjected to greater stress at the intersection of the DTI regions 25. By placing the diffusion separation layer 14 instead of the STI layer 22, stress concentration can be mitigated even at the intersection of the DTI regions 25.

[0127] (Tenth Embodiment) Figure 25 is a layout diagram of the pixel group PXG and pixel circuit 20 of the light detection device 1 according to the tenth embodiment.

[0128] In the tenth embodiment, a pixel group PXG is configured with 4 x 2 = 8 pixels PX, and one pixel circuit 20 is shared. The pixel circuit 20 according to the tenth embodiment has two amplification transistors AMP, two selection transistors SEL, one reset transistor RST, one conversion efficiency switching transistor FDG, and two dummy transistors DMY. The dummy transistors DMY simply have gates placed in empty spaces, and no valid signal is input to the gates, so they do not function as transistors.

[0129] Each pixel PX included in the pixel group PXG can be used as a phase difference detection pixel. Specifically, by shielding one of two adjacent pixels PX in the first direction X included in the pixel group PXG and outputting a pixel signal from the other, and by shielding the other of two other pixels PX included in the pixel group PXG and outputting a pixel signal from one, phase difference detection information can be obtained.

[0130] Between two adjacent pixel groups PXG and two pixel circuits 20 in the first direction X (for example, the horizontal direction), a sub-FD wiring WR1 connected to the charge holding unit 21 and a ground voltage wiring are arranged, and these two pixel circuits 20 are mirrored together.

[0131] An STI layer 22 is placed between adjacent transfer transistors TRG and pixel transistors in the second direction Y, and an STI layer 22 is also placed between two adjacent pixel transistors in the second direction Y.

[0132] In the tenth embodiment, the number of pixels PX included in one pixel group PXG is increased compared to the first embodiment, allowing for further miniaturization. Furthermore, since two amplification transistors AMP and two selection transistors SEL are provided for each pixel group PXG, the drive capability of the pixel signal can be improved.

[0133] (Eleventh Embodiment) Figure 26 is a layout diagram of the pixel group PXG and pixel circuit 20 of the light detection device 1 according to the eleventh embodiment.

[0134] The light detection device 1 according to the eleventh embodiment shown in Figure 26 shares one pixel circuit 20 with a pixel group PXG including 2 × 2 = 4 pixels PX, similar to the first embodiment. The arrangement of two pixel groups PXG and two pixel circuits 20, as well as the inclusion of an STI layer 22, are also the same as in the first embodiment.

[0135] The light detection device 1 according to the eleventh embodiment detects phase difference information in multiple pixel groups PXG, rather than detecting phase difference information for each pixel group PXG. The locations of the pair of pixel groups PXG for detecting phase difference information are arbitrary.

[0136] The photodetector 1 according to the eleventh embodiment is configured in the same way as the first embodiment, except that the unit for detecting phase difference information is different from that of the first embodiment. For example, two adjacent pixel groups PXG and two pixel circuits 20 in the first direction X are arranged in a mirror arrangement. A sub-FD wiring WR1 connected to a charge holding unit 21 is also arranged between two adjacent pixel groups PXG and two pixel circuits 20 in the first direction X. An STI layer 22 is also arranged between an adjacent transfer transistor TRG and a pixel transistor in the first direction X, and between a plurality of pixel transistors arranged in two rows in the first direction X. Furthermore, a P-type impurity region is arranged to surround two adjacent pixel groups PXG in the first direction X.

[0137] In the eleventh embodiment, the same effects as in the first embodiment can be obtained.

[0138] (Twelfth Embodiment) Figure 27 is a layout diagram of the pixel group PXG and pixel circuit 20 of the light detection device 1 according to the twelfth embodiment.

[0139] In the twelfth embodiment, similar to Figure 22, the STI layer 22, which is positioned between a plurality of pixel transistors arranged in two rows in the second direction Y, is separated between two adjacent reset transistors RST in the first direction X. This allows the stress on the STI layer 22 to be relieved.

[0140] (Third Embodiment) Figure 28 is a layout diagram of the pixel group PXG and pixel circuit 20 of the light detection device 1 according to the thirteenth embodiment.

[0141] In the 13th embodiment, similar to Figure 23, the STI layer 22 is placed between the transfer transistor TRG and the conversion efficiency switching transistor FDG, which are adjacent to each other in the second direction Y, and also between the selection transistor SEL and the transfer transistor TRG, which are adjacent to each other in the second direction Y, thereby making the length of the STI layer 22 extending in the first direction X as short as possible. This further relieves the stress on the STI layer 22.

[0142] (14th Embodiment) Figure 29 is a layout diagram of the pixel group PXG and pixel circuit 20 of the light detection device 1 according to the 14th embodiment.

[0143] In the 14th embodiment, similar to Figure 24, a diffusion isolation layer 14 is placed between multiple pixel transistors arranged in two rows in the second direction Y, instead of an STI layer 22. This makes it possible to alleviate stress concentration even at the points where the DTI regions 25 intersect.

[0144] (15th Embodiment) Figure 30 is a layout diagram of the pixel group PXG and pixel circuit 20 of the light detection device 1 according to the 15th embodiment.

[0145] In the 15th embodiment, a pixel group PXG is configured with 1 × 2 = 2 pixels PX, and one pixel circuit 20 is shared.

[0146] By reducing the number of pixels (PX) included in the pixel group (PXG), further improvements in conversion efficiency can be achieved.

[0147] (16th Embodiment) Figure 31 is a layout diagram of the pixel group PXG and pixel circuit 20 of the light detection device 1 according to the 16th embodiment.

[0148] In the sixteenth embodiment, similar to Figure 22, the STI layer 22, which is positioned between a plurality of pixel transistors arranged in two rows in the second direction Y, is separated between two adjacent reset transistors RST in the first direction X. This allows the stress on the STI layer 22 to be relieved.

[0149] (17th Embodiment) Figure 32 is a layout diagram of the pixel group PXG and pixel circuit 20 of the light detection device 1 according to the 17th embodiment.

[0150] In the 17th embodiment, similar to Figure 23, the STI layer 22 is placed between the transfer transistor TRG and the conversion efficiency switching transistor FDG, which are adjacent to each other in two directions, and between the selection transistor SEL and the transfer transistor TRG, which are adjacent to each other in the second direction Y, thereby making the length of the STI layer 22 extending in the first direction X as short as possible. This further relieves the stress on the STI layer 22.

[0151] (Eighteenth Embodiment) Figure 33 is a layout diagram of the pixel group PXG and pixel circuit 20 of the light detection device 1 according to the eighteenth embodiment.

[0152] In the 18th embodiment, similar to Figure 24, a diffusion isolation layer 14 is placed between multiple pixel transistors arranged in two rows in the second direction Y, instead of an STI layer 22. This makes it possible to alleviate stress concentration even at the points where the DTI regions 25 intersect.

[0153] (19th Embodiment) Figure 34 is a layout diagram of the pixel group PXG and pixel circuit 20 of the light detection device 1 according to the 19th embodiment. In the 19th embodiment, one pixel circuit 20 is shared by a pixel group PXG including four pixels PX, and a charge holding unit 21 is shared by two adjacent pixel groups PXG in the first direction X.

[0154] The pixel transistor of the pixel circuit 20 according to the 19th embodiment includes an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and a conversion efficiency switching transistor FDG.

[0155] On the pixel boundary region extending in the second direction Y through the center of the first direction X of the four shared pixels PX, FD wiring WR20, which connects to a floating diffusion region, is arranged.

[0156] The pixel group PXG and pixel circuit 20 according to the 19th embodiment have a configuration similar to the pixel group PXG and pixel circuit 20 according to the first to 18th embodiments. Although not explicitly shown in Figure 20, an STI layer 22 or a diffusion isolation layer 14 is disposed between adjacent transfer transistors TRG and pixel transistors in the second direction Y, and between a plurality of pixel transistors arranged in two rows in the second direction Y. The plurality of pixel groups PXG and the plurality of pixel circuits 20 according to the 19th embodiment are arranged along a first direction X and a second direction Y that intersect each other, and each of the plurality of pixel circuits 20 has a plurality of pixel transistors arranged symmetrically with respect to at least one of the first direction X or the second direction Y.

[0157] The planar shape of the pixel transistor in the pixel circuit 20 according to the 19th embodiment is different from the planar shape of the pixel transistor in the pixel circuit 20 according to the first to 18th embodiments described above.

[0158] Figure 35 is an enlarged plan view of the area around the conversion efficiency switching transistor FDG and reset transistor RST in Figure 34. In the 19th embodiment, the conversion efficiency switching transistor FDG has, in plan view, a first side SD1 facing the floating diffusion region FD and a second side SD2 facing the charge holding portion 21, wherein the first side SD1 is shorter than the second side SD2.

[0159] Furthermore, the reset transistor RST has, in a plan view, a third side SD3 facing the floating diffusion region FD and a fourth side SD4 electrically connected to the power supply voltage wiring WR4, and the third side SD3 is shorter than the fourth side SD4.

[0160] In this way, by shortening both the first side SD1 of the conversion efficiency switching transistor FDG and the third side SD3 of the reset transistor RST, which face the floating diffusion region FD, the FD capacitance can be reduced, and the conversion efficiency during HCG can be increased.

[0161] Furthermore, by lengthening the second side SD2 of the conversion efficiency switching transistor FDG facing the charge holding section 21, the capacitance of the charge holding section 21 can be increased, thereby increasing the amount of charge that can be held in the charge holding section 21, and thus further reducing the conversion efficiency during LCG operation. Therefore, in the 19th embodiment, the difference in charge holding capacitance between HCG operation and LCG operation can be further increased.

[0162] Furthermore, the reset transistor RST has a fifth side SD5 facing the photoelectric conversion unit PD in a plan view, and the fifth side SD5 is longer than the third side SD3 facing the floating diffusion region FD. In addition, the fifth side SD5 is arranged in a direction inclined with respect to the third side SD3 and the fourth side SD4. This allows for a larger size of the photoelectric conversion unit PD, making it easier to secure a transfer path for the charge generated by photoelectric conversion in the photoelectric conversion unit PD, and increasing the saturation charge amount.

[0163] Furthermore, in the 19th embodiment, the width of the source region of the amplification transistor AMP is made narrower than the width of the drain region. This reduces RTS (Random Telegraph Signal) noise.

[0164] Thus, in the 19th embodiment, a pixel group PXG including multiple pixels PX shares one pixel circuit 20, and two adjacent pixel groups PXG in the first direction X share a charge holding section 21. Various effects can be obtained by devising the planar shape of the pixel transistors. For example, in a plan view, by making the first side SD1 facing the floating diffusion region FD of the conversion efficiency switching transistor FDG shorter, and the third side SD3 facing the floating diffusion region FD of the reset transistor RST shorter, the FD capacitance can be reduced, and the conversion efficiency during HCG can be increased. Also, in a plan view, by making the second side SD2 facing the charge holding section 21 of the conversion efficiency switching transistor FDG longer, the capacitance of the charge holding section 21 can be increased, and the amount of charge that can be held in the charge holding section 21 can be increased. Also, in a plan view, by making the fifth side SD5 facing the photoelectric conversion section PD of the reset transistor RST longer, the size of the photoelectric conversion section PD can be increased, and the saturation charge amount can be increased. Furthermore, RTS noise can be reduced by narrowing the source region of the amplification transistor (AMP).

[0165] (20th Embodiment) Figure 36 is a layout diagram of the pixel group PXG and pixel circuit 20 of the light detection device 1 according to the 20th embodiment. In the 20th embodiment, pixel transistors having the same or similar planar shape as in the 19th embodiment are arranged in a line along the boundary region extending in the second direction Y of the pixel group PXG and the pixel circuit 20.

[0166] In addition to the effects of the 19th embodiment, by arranging multiple pixel transistors along the boundary region of the pixel group PXG and the pixel circuit 20, the arrangement area of ​​the photoelectric conversion unit PD of each pixel PX can be increased.

[0167] (21st Embodiment) Figure 37 is a layout diagram of the pixel group PXG and pixel circuit 20 of the light detection device 1 according to the 21st embodiment. In the 21st embodiment, the planar shape of the pixel transistor is trapezoidal. Furthermore, when arranging multiple pixel transistors in two rows in the second direction Y, each pixel transistor is arranged such that the distance between the sides connected to the upper and lower bases of each trapezoid is made as short as possible.

[0168] Furthermore, the orientation of the pixel transistors in each row is reversed. More specifically, the pixel transistors in each row are arranged so that, in a plan view, the edges connecting to the top and bottom bases face each other.

[0169] This allows the distance between pixel transistors in each row of the second direction Y to be reduced, and the area for arranging the photoelectric conversion unit PD within the pixel PX can be increased.

[0170] Furthermore, the pixel groups PXG in each row, which are positioned in the second direction Y, are arranged in a staggered pattern.

[0171] In the 21st embodiment, by making the first side SD1 facing the floating diffusion region FD of the conversion efficiency switching transistor FDG shorter, and the third side SD3 facing the floating diffusion region FD of the reset transistor RST shorter, the capacitance of FD can be reduced, and the conversion efficiency during HCG can be increased. Also, in a plan view, by making the side (second side SD2) facing the charge holding portion 21 of the conversion efficiency switching transistor FDG longer, the capacitance of the charge holding portion 21 can be increased, and the amount of charge that can be held in the charge holding portion 21 can be increased. Also, in a plan view, by making the side (fifth side SD5) facing the photoelectric conversion portion PD of the reset transistor RST longer, the size of the photoelectric conversion portion PD can be increased, and the saturation charge amount can be increased. In addition, by making the width of the source region of the amplification transistor AMP narrower, RTS noise can be reduced.

[0172] (22nd Embodiment) Figure 38 is a layout diagram of the pixel group PXG and pixel circuit 20 of the light detection device 1 according to the 22nd embodiment. The planar shape of the pixel transistor in the 22nd embodiment is the same as in the 19th embodiment.

[0173] In the 22nd embodiment, the STI layer 22 is placed between adjacent pixel transistors and transfer transistors TRG in the second direction Y. The STI layer 22 has a curved planar shape rather than a straight line shape in plan view. By bending the STI layer 22, the stress on the STI layer 22 can be relieved. A diffusion separation layer may be provided instead of the STI layer 22.

[0174] (23rd Embodiment) Figure 39 is a layout diagram of the pixel group PXG and pixel circuit 20 of the light detection device 1 according to the 23rd embodiment.

[0175] In the pixel groups PXG of the 19th to 23rd embodiments described above, phase difference information can be detected for each pixel group PXG. In contrast, in the 23rd embodiment, phase difference information is detected for any two pixel groups PXG within the pixel array unit 2.

[0176] In the 23rd embodiment, the planar shape of the pixel transistor is the same as in the 19th embodiment, and the same effects as in the 19th embodiment can be obtained.

[0177] (24th Embodiment) Figure 40 is a layout diagram of the pixel group PXG and pixel circuit 20 of the light detection device 1 according to the 24th embodiment. In the 24th embodiment, as in the 23rd embodiment, phase difference information is detected by any two pixel groups PXG in the pixel array section 2.

[0178] In the 24th embodiment, similar to the 20th embodiment, multiple pixel transistors are arranged along the boundary region of the pixel group PXG extending in the second direction Y. This allows for an increase in the arrangement area of ​​the photoelectric conversion unit PD of each pixel PX, thereby increasing the saturation charge capacitance.

[0179] <Examples of application to mobile devices> The technology disclosed herein (this technology) can be applied to various products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0180] Figure 41 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0181] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 41, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0182] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0183] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0184] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0185] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0186] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0187] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0188] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0189] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0190] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 41, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0191] Figure 42 shows an example of the installation position of the imaging unit 12031.

[0192] In Figure 42, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0193] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0194] Figure 42 shows an example of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0195] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0196] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0197] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0198] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0199] The above describes an example of a vehicle control system to which the technology described herein may be applied. The technology described herein may be applied to the imaging unit 12031, etc., among the configurations described above.

[0200] Furthermore, this technology can take the following configurations: (1) A light detection device comprising: a plurality of pixels each having a photoelectric conversion unit that performs photoelectric conversion of incident light and a floating diffusion region that holds the photoelectrically converted charge; and a plurality of pixel circuits shared by each of a plurality of pixel groups each containing two or more of the plurality of pixels, wherein the plurality of pixel groups and the plurality of pixel circuits are arranged along a first direction and a second direction that intersect each other; each of the plurality of pixel circuits has a plurality of pixel transistors arranged symmetrically with respect to at least one of the first direction or the second direction; and the plurality of pixel transistors are arranged in at least two rows along the first direction or the second direction. (2) The light detection device according to (1), wherein the plurality of pixel transistors are arranged symmetrically with respect to the boundary region of the pixels extending in at least one of the first direction or the second direction. (3) The photodetector according to (1) or (2), wherein each of the plurality of pixels has a transfer transistor, and further comprises an insulating layer or diffusion separation layer disposed between the transfer transistor and the pixel transistor, or between at least one of the plurality of pixel transistors. (4) The photodetector according to (3), wherein the transfer transistor and two or more pixel transistors among the plurality of pixel transistors are arranged in the second direction, and the insulating layer or diffusion separation layer is disposed between the transfer transistor and the pixel transistor arranged in the second direction, or between at least one of the two or more pixel transistors arranged in at least two rows along the second direction. (5) The photodetector according to (3) or (4), wherein the insulating layer or diffusion separation layer has a size and shape that reduces at least one of the capacitive coupling between the transfer transistor and the pixel transistor, or the capacitive coupling between the two or more pixel transistors. (6) The photodetector according to (3) or (5), wherein the insulating layer or diffusion separation layer is disposed along the boundary region of a pixel sharing range including each of the plurality of pixel groups and the corresponding pixel circuit.(7) The photodetector according to any one of (3) to (6), wherein the insulating layer or the diffusion separation layer is a continuous layer that passes through the regions of two or more pixel groups arranged along the first direction. (8) The photodetector according to any one of (3) to (6), wherein the insulating layer is divided at the boundary regions of two or more pixel groups arranged along the first direction. (9) The photodetector according to (8), wherein the plurality of insulating layers are arranged to avoid the intersections of the pixel separation regions. (10) The photodetector according to (8) or (9), wherein each of the plurality of pixel transistors has a conversion efficiency switching transistor, and each of the plurality of insulating layers is arranged in correspondence with the conversion efficiency switching transistor. (11) The photodetector according to any one of (8) to (10), wherein each of the plurality of pixel transistors has a selection transistor, and each of the plurality of insulating layers is arranged in correspondence with the selection transistor. (12) The photodetector according to any one of (1) to (11), wherein the boundary of the pixel sharing range, which includes each of the plurality of pixel groups and the corresponding pixel circuit, is offset from the boundary of the arrangement area of ​​the pixel circuit corresponding to each of the plurality of pixel groups. (13) The photodetector according to (12), wherein the pixel circuit corresponding to each of the plurality of pixel groups is arranged across two adjacent pixel sharing ranges in the first or second direction. (14) The photodetector according to any one of (1) to (13), further comprising an impurity diffusion range arranged along the boundary area of ​​each of the plurality of pixel groups. (15) The photodetector according to (14), wherein the impurity diffusion range is electrically connected to a well contact range. (16) The photodetector according to (15), wherein a plurality of well contact ranges and a plurality of floating diffusion ranges, each set to a reference voltage, are arranged alternately along the first or second direction of the pixel group. (17) The photodetector according to (16), further comprising a contact member connected to a well contact region among the plurality of well contact regions that does not overlap with the power supply voltage wiring in a plan view.(18) The photodetector according to (17), further comprising power supply voltage wiring arranged along the boundary region of the pixel extending in the second direction and divided into a plurality of sections to match the location of the contact members. (19) The photodetector according to any one of (16) to (18), wherein each of the plurality of pixels has a transfer transistor, and the plurality of well contact regions and the plurality of floating diffusion regions are arranged along the first direction passing between two adjacent transfer transistors in the second direction. (20) The photodetector according to any one of (1) to (19), wherein each of the plurality of pixel circuits has a conversion efficiency switching transistor, and further comprises a charge holding section shared by two adjacent pixel circuits in the first direction, which holds the charge generated by the photoelectric conversion of the corresponding two photoelectric conversion sections when the two conversion efficiency switching transistors of the two pixel circuits are turned on. (21) The light detection device according to (20), wherein the charge holding unit and the wiring connected to the charge holding unit are arranged along the boundary region between two adjacent pixel circuits in the first direction. (22) The light detection device according to any one of (1) to (21), comprising a signal line connected to the output node of each of the two adjacent pixel circuits in the first direction, wherein the signal line is arranged in the boundary region between the two pixel circuits. (23) The light detection device according to (22), wherein the signal line is connected to the output node of each of the two adjacent pixel circuits in the first direction, and of the two or more pixel circuits arranged in the second direction, the odd-numbered pixel circuits and the even-numbered pixel circuits are connected to different signal lines. (24) The light detection device according to (22) or (23), wherein the plurality of pixel transistors each have a selection transistor, and of the two adjacent pixel circuits in the first direction, the pixel circuit whose corresponding selection transistor is ON outputs the corresponding pixel signal to the signal line.(25) The photodetector according to (24), wherein the plurality of pixel transistors each have a reset transistor, a selection transistor and a conversion efficiency switching transistor, and of the two pixel circuits, the pixel circuit whose corresponding selection transistor is off turns on the corresponding reset transistor and the conversion efficiency switching transistor. (26) The photodetector according to any one of (1) to (21), wherein different signal lines are connected to the output nodes of each of the two pixel circuits adjacent in the first direction, and the two signal lines are arranged between the two pixel circuits adjacent in the first direction. (27) The photodetector according to (26), wherein the plurality of pixel transistors each have a conversion efficiency switching transistor, and the two pixel circuits output two pixel signals in parallel to the two signal lines when the conversion efficiency switching transistor is off. (28) The photodetector according to (26), wherein each of the plurality of pixel transistors has a conversion efficiency switching transistor, and the two pixel circuits output the same pixel signal in parallel to the two signal lines when the conversion efficiency switching transistor is on. (29) The photodetector according to any one of (1) to (28), wherein each of the plurality of pixel groups includes two of the pixels in the first direction and two in the second direction. (30) The photodetector according to any one of (1) to (28), wherein each of the plurality of pixel groups includes two of the pixels in one of the first or second directions and four in the other. (31) The photodetector according to any one of (1) to (28), wherein each of the plurality of pixel groups includes one of the pixels in one of the first or second directions and two in the other. (32) The optical detection device according to any one of (1) to (31), wherein the pixel group includes two or more pairs of pixels for phase difference detection, and phase difference detection is performed for each pixel group. (33) The optical detection device according to any one of (1) to (32), wherein each of two pairs of pixels includes a pixel for phase difference detection, and phase difference detection is performed using the two pairs of pixels.(34) A photodetector comprising: a plurality of pixels each having a photoelectric conversion unit that performs photoelectric conversion of incident light and a floating diffusion region that holds the photoelectrically converted charge; and a plurality of pixel circuits shared by each of a plurality of pixel groups each containing two or more of the plurality of pixels, wherein each of the plurality of pixel circuits comprises: a plurality of pixel transistors including a conversion efficiency switching transistor; and a charge holding unit that holds the photoelectrically converted charge when the conversion efficiency switching transistor is on; wherein the conversion efficiency switching transistor has, in a plan view, a first side facing the floating diffusion region and a second side facing the charge holding unit, and the first side is shorter than the second side; (35) The photodetector according to (34), wherein each of the plurality of pixel circuits has a reset transistor; wherein the reset transistor has, in a plan view, a third side facing the floating diffusion region and a fourth side electrically connected to a power supply voltage wiring, and the third side is shorter than the fourth side; (36) The photodetector according to (35), wherein the reset transistor has a fifth side facing the photoelectric conversion unit in a plan view, and the fifth side is longer than the third side. (37) The photodetector according to (36), wherein the fifth side is arranged in a direction inclined with respect to the third side and the fourth side. (38) The photodetector according to any one of (34) to (37), wherein each of the plurality of pixel circuits has an amplifying transistor, and the width of the source region of the amplifying transistor is narrower than the width of the drain region of the amplifying transistor. (39) The photodetector according to any one of (35) to (37), wherein the plurality of pixel groups and the plurality of pixel circuits are arranged along a first direction and a second direction that intersect each other, and each of the plurality of pixel circuits has a plurality of pixel transistors arranged symmetrically with respect to at least one of the first direction or the second direction. (40) The photodetector according to (39), wherein the plurality of pixel transistors are arranged in two rows along the first direction or the second direction.(41) The optical detection device according to (40), wherein the plurality of pixel transistors are trapezoidal in plan view, the orientation of the pixel transistors in each of the two rows is opposite to that of the others, and two or more pixel groups arranged in the first direction or the second direction are arranged in a staggered manner. (42) The optical detection device according to (41), wherein the pixel transistors in each of the two rows are arranged so that the sides connecting to the upper and lower bases face each other in plan view. (43) The optical detection device according to any one of (34) to (39), wherein the plurality of pixel groups and the plurality of pixel circuits are arranged along a first direction and a second direction that intersect each other, and the plurality of pixel transistors are arranged in a column or row along the boundary region of the pixel group extending in the first direction or the second direction. (44) The photodetector according to any one of (34) to (43), wherein each of the plurality of pixel circuits has a transfer transistor, and further comprises an insulating layer or a diffusion separation layer disposed between the transfer transistor and the pixel transistor, or between at least one of the plurality of pixel transistors. (45) The photodetector according to (44), wherein the insulating layer or the diffusion separation layer is bent.

[0201] The aspects of this disclosure are not limited to the individual embodiments described above, but include various modifications that a person skilled in the art could conceive, and the effects of this disclosure are not limited to those described above. In other words, various additions, modifications, and partial deletions are possible, as long as they do not depart from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents.

[0202] 1. Photodetector, 2. Pixel array section, 3. Peripheral circuit section, 5. Row selection section, 6. Constant current source section, 8. Horizontal transfer scanning section, 9. Signal processing section, 10. Timing control section, 11. Reference signal generation section, 13. Interlayer insulating film, 14. Diffusion separation layer, 20. Pixel circuit, 21. Charge holding section, 22. STI layer, 22. Insulating layer, 23. P-type impurity diffusion region, 24. Well contact region, 25. DTI region, 25. Pixel separation region, 25a. Light shielding layer, 25b. Insulating layer, 26. N-type well layer, 27. P-type well layer, 28. First wiring layer, 29. Second wiring layer, 30. Electronic equipment, 31. Imaging lens, 32. Image processing section, 33. Recording section, 34. Control section

Claims

1. A photodetector comprising: a plurality of pixels each having a photoelectric conversion unit that performs photoelectric conversion of incident light and a floating diffusion region that holds the photoelectrically converted charge; a plurality of pixel circuits shared by each of a plurality of pixel groups each containing two or more of the plurality of pixels; wherein the plurality of pixel groups and the plurality of pixel circuits are arranged along a first direction and a second direction that intersect each other; each of the plurality of pixel circuits has a plurality of pixel transistors arranged symmetrically with respect to at least one of the first direction or the second direction; and the plurality of pixel transistors are arranged in at least two rows along the first direction or the second direction.

2. The photodetector according to claim 1, wherein the plurality of pixel transistors are arranged symmetrically with respect to the boundary region of the pixel extending in at least one of the first direction or the second direction.

3. The photodetector according to claim 1, wherein each of the plurality of pixels has a transfer transistor, and further comprises an insulating layer or a diffusion separation layer disposed between the transfer transistor and the pixel transistor, or between at least one of the plurality of pixel transistors.

4. The photodetector according to claim 3, further comprising a plurality of insulating layers separated at the boundary regions of two or more pixel groups arranged along the first direction.

5. The photodetector according to claim 1, wherein the boundary of the pixel sharing range, which includes each of the plurality of pixel groups and the corresponding pixel circuit, is offset from the boundary of the arrangement area of ​​the pixel circuit corresponding to each of the plurality of pixel groups.

6. The photodetector according to claim 5, wherein the pixel circuit corresponding to each of the plurality of pixel groups is arranged across two adjacent pixel sharing ranges in the first or second direction.

7. The photodetector according to claim 1, further comprising impurity diffusion regions arranged along the boundary regions of each of the plurality of pixel groups.

8. The photodetector according to claim 7, wherein the impurity diffusion region is electrically connected to the well contact region.

9. The photodetector according to claim 8, wherein the plurality of well contact regions and the plurality of floating diffusion regions, each set to a reference voltage, are alternately arranged along the first or second direction of the pixel group.

10. The photodetector according to claim 9, further comprising a contact member connected to a well contact region among the plurality of well contact regions that does not overlap with the power supply voltage wiring in a plan view.

11. The photodetector according to claim 10, further comprising power supply voltage wiring arranged along the boundary region of the pixel extending in the second direction, and divided into multiple sections according to the location of the contact member.

12. The photodetector according to claim 9, wherein each of the plurality of pixels has a transfer transistor, and the plurality of well contact regions and the plurality of floating diffusion regions are arranged along the first direction through two adjacent transfer transistors in the second direction.

13. The photodetector according to claim 1, wherein each of the plurality of pixel circuits has a conversion efficiency switching transistor, which is shared by two of the pixel circuits adjacent in the first direction, and further comprises a charge holding unit that holds the charge generated by the photoelectric conversion of the two corresponding photoelectric conversion units when the two conversion efficiency switching transistors of the two pixel circuits are turned on.

14. The light detection device according to claim 13, wherein the charge holding portion and the wiring connected to the charge holding portion are arranged along the boundary region between two adjacent pixel circuits in the first direction.

15. The optical detection device according to claim 1, wherein the pixel group includes two or more pairs of pixels for phase difference detection, and phase difference detection is performed for each pixel group.

16. A photodetector comprising: a plurality of pixels, each having a photoelectric conversion unit that performs photoelectric conversion of incident light and a floating diffusion region that holds the photoelectrically converted charge; a plurality of pixel circuits shared by each of a plurality of pixel groups, each containing two or more of the plurality of pixels; each of the plurality of pixel circuits having a plurality of pixel transistors including a conversion efficiency switching transistor; and a charge holding unit that holds the photoelectrically converted charge when the conversion efficiency switching transistor is on; the conversion efficiency switching transistor having, in a plan view, a first side facing the floating diffusion region and a second side facing the charge holding unit, the first side being shorter than the second side; 17. Each of the plurality of pixel circuits has a reset transistor, the reset transistor having, in a plan view, a third side facing the floating diffusion region and a fourth side electrically connected to a power supply voltage wiring, the third side being shorter than the fourth side, the light detection device according to claim 16.

18. The photodetector according to claim 17, wherein the reset transistor has a fifth side facing the photoelectric conversion unit in a plan view, and the fifth side is longer than the third side.

19. The photodetector according to claim 16, wherein each of the plurality of pixel circuits has an amplifying transistor, and the width of the source region of the amplifying transistor is narrower than the width of the drain region of the amplifying transistor.

20. The photodetector according to claim 16, wherein the plurality of pixel groups and the plurality of pixel circuits are arranged along a first direction and a second direction that intersect each other, the plurality of pixel transistors are arranged in two rows along the first direction or the second direction, the plurality of pixel transistors are trapezoidal in plan view, the orientation of the pixel transistors in each of the two rows is opposite to that of the others, and the two or more pixel groups arranged in the first direction or the second direction are arranged in a staggered manner.

Images