Light detection device

Abstract

[Problem] To provide a light detection device that has high sensitivity and high image quality without complicating the manufacturing process therefor. [Solution] This light detection device comprises: a pixel that has a photoelectric conversion unit which performs photoelectric conversion of incident light and a floating diffusion region which holds a charge obtained by the photoelectric conversion; a pixel circuit that generates a pixel signal in accordance with the charge obtained by the photoelectric conversion by the pixel; a first conductive member that extends in the depth direction of a substrate on which the pixel and / or the pixel circuit is disposed; and a capacitor that has a length and a position in the depth direction of the substrate which are the same as those of the first conductive member. The capacitor has a first electrode layer that is disposed in the depth direction of the substrate, an insulation layer that is disposed in the depth direction of the substrate and that is laminated on the first electrode layer, and a second electrode layer that is disposed in the depth direction off the substrate and that is laminated on the insulation layer. The diameter of the capacitor is greater than the diameter of the first conductive member.

Description

Photodetection device

[0001] The present disclosure relates to a photodetection device.

[0002] Image sensors capable of providing captured images with high sensitivity and high image quality have been developed. To achieve both high sensitivity and high image quality, it is necessary to expand the dynamic range of photoelectric conversion. For example, in order to obtain a captured image without overexposure under high illumination, a structure that can hold as much charge generated by photoelectric conversion as possible in a pixel is required. For this reason, a structure in which a charge holding capacitor is provided for each pixel has been proposed (see Patent Document 1).

[0003] Furthermore, a technique has been proposed in which, in the step of forming a contact hole and a contact, an electrode layer and an insulating layer are stacked in the contact hole to form a contact hole capacitor (see Patent Document 2).

[0004] International Publication No. 2017 / 169882 Japanese Unexamined Patent Application Publication No. 2012-109577

[0005] In Patent Document 1, a new step of forming a capacitor in a pixel is added, which complicates the manufacturing process and may cause a decrease in yield.

[0006] Furthermore, Patent Document 2 relates to a technique for a contact hole capacitor for data storage used in semiconductor memories, and is not assumed to be applied to image sensors.

[0007] Therefore, the present disclosure provides a photodetection device with high sensitivity and high image quality without complicating the manufacturing process.

[0008] To solve the above problems, the present disclosure provides a photodetector comprising: a pixel having a photoelectric conversion unit that performs photoelectric conversion of incident light and a floating diffusion region that holds the photoelectrically converted charge; a pixel circuit that generates a pixel signal corresponding to the charge photoelectrically converted by the pixel; a first conductive member extending in the depth direction of a substrate on which at least one of the pixel or the pixel circuit is arranged; and a capacitor whose position and length in the depth direction of the substrate are the same as those of the first conductive member, wherein the capacitor comprises: a first electrode layer arranged in the depth direction of the substrate; an insulating layer arranged in the depth direction of the substrate and laminated on the first electrode layer; and a second electrode layer arranged in the depth direction of the substrate and laminated on the insulating layer, wherein the diameter of the capacitor is larger than the diameter of the first conductive member.

[0009] The substrate has a diffusion layer and a wiring layer arranged at different depths, and the first conductive member and the capacitor may each be connected to the diffusion layer and the wiring layer.

[0010] The substrate has a first diffusion layer and a second diffusion layer arranged at different depths, and the first conductive member and the capacitor may each be connected to the first diffusion layer and the second diffusion layer.

[0011] The substrate has a first wiring layer and a second wiring layer, and the first conductive member and the capacitor may each be connected to the first wiring layer and the second wiring layer.

[0012] The first wiring layer connected to the first electrode layer of the capacitor and the second wiring layer connected to the second electrode layer of the capacitor may be arranged on one end side of the capacitor that extends in the depth direction of the substrate.

[0013] The first wiring layer and the second wiring layer may be arranged at the same depth position on the substrate, or at different depth positions.

[0014] One of the first wiring layer or the second wiring layer may be in contact with the first electrode layer or the second electrode layer, and the other of the first wiring layer or the second wiring layer may be connected to the first electrode layer or the second electrode layer via a second conductive member extending in the depth direction of the substrate.

[0015] One of the first electrode layer or the second electrode layer may be connected to one of the first wiring layer or the second wiring layer, and the other of the first electrode layer or the second electrode layer may be connected to the other of the first wiring layer or the second wiring layer via a diffusion layer.

[0016] The device comprises a first layer on which the pixels are arranged, and a second layer stacked on the first layer on which at least a portion of the pixel circuit is arranged, wherein the first conductive member and the capacitor may be arranged in the first or second layer.

[0017] The first and second layers may be arranged at different heights on the same substrate.

[0018] The first and second layers may be arranged on different substrates.

[0019] The first layer includes a transfer transistor that transfers the charge photoelectrically converted in the photoelectric conversion unit to the floating diffusion region, and a first wiring layer located closer to the second layer than the location of the transfer transistor and the floating diffusion region; the second layer includes a second wiring layer located further from the first layer than the location of the pixel circuit; and the first conductive member and the capacitor may each be connected to the first wiring layer and the second wiring layer.

[0020] The device comprises a first layer on which the pixels are arranged, and a second layer stacked on the first layer on which at least a portion of the pixel circuit is arranged, wherein the first layer or the second layer has a first wiring layer and a second wiring layer arranged at different depths, and the first conductive member and the capacitor may each be connected to the first wiring layer and the second wiring layer.

[0021] The capacitor may also include a dielectric layer disposed so as to cover at least a portion of the first electrode layer, the insulating layer, or the second electrode layer on the upper surface of the capacitor.

[0022] The device may also include one or more wiring layers connected to the first conductive member and the capacitor, and a barrier metal film covering the outer surface of at least one of the first conductive member, the capacitor, or the wiring layers.

[0023] The device comprises a transistor having a gate and a diffusion layer, wherein one end of the first conductive member is connected to the diffusion layer, and the first electrode layer or the second electrode layer of the capacitor may be connected to the gate.

[0024] The first conductive member and at least one of the first electrode layer or the second electrode layer may be made of the same conductive material.

[0025] The conductive material may include copper (Cu), tungsten (W), polysilicon implanted with impurity ions, amorphous silicon implanted with impurity ions, N-type silicon, P-type silicon, transparent electrode material, titanium (Ti), or titanium nitride (TiN).

[0026] The capacitor has a filling portion located inside a trench placed on the substrate and a flange portion located outside the upper end of the trench, and both the filling portion and the flange portion may have a laminated structure including the first electrode layer, the insulating layer and the second electrode layer.

[0027] The pixel circuit may have a conversion efficiency switching transistor, and the capacitor may hold the charge photoelectrically converted in the photoelectric conversion unit when the conversion efficiency switching transistor is ON.

[0028] A block diagram of an electronic device equipped with a photodetector according to one embodiment of the present disclosure. A schematic perspective view showing an example of a two-layer stacked structure for the photodetector according to the present disclosure. A schematic perspective view showing an example of a three-layer structure for the photodetector according to the present disclosure. A block diagram showing the overall configuration of the photodetector according to the present disclosure. A circuit diagram of a pixel circuit connected to the second pixel group in the photodetector according to this embodiment. A partial cross-sectional view of the photodetector according to the first embodiment. An enlarged cross-sectional view of the area around the first contact shown by the dashed frame in Figure 5. A cross-sectional view showing the cross-sectional structure around the capacitor of the photodetector according to the first embodiment. A cross-sectional view showing the cross-sectional structure around the capacitor of the photodetector according to the second embodiment. A cross-sectional view showing the cross-sectional structure around the capacitor of the photodetector according to the third embodiment. A cross-sectional view showing the cross-sectional structure around the capacitor of the photodetector according to the fourth embodiment. A cross-sectional view showing the cross-sectional structure around the capacitor of the photodetector according to the fifth embodiment. A cross-sectional view showing the cross-sectional structure around the capacitor of the photodetector according to the sixth embodiment. A cross-sectional view showing the cross-sectional structure around the capacitor of the photodetector according to the seventh embodiment. A cross-sectional view showing the cross-sectional structure around a capacitor in the photodetector according to the eighth embodiment. A plan view of the capacitors according to the first to eighth embodiments, viewed from above. A cross-sectional view showing the cross-sectional structure around a capacitor in the photodetector according to the tenth embodiment. A partial cross-sectional view of the photodetector according to the eleventh embodiment. A cross-sectional view of the process showing an example of the first manufacturing process. A cross-sectional view of the process following Figure 18A. A cross-sectional view of the process following Figure 18B. A cross-sectional view of the process following Figure 18C. A cross-sectional view of the process following Figure 18D. A cross-sectional view of the process following Figure 18E. A cross-sectional view of the process following Figure 18F. A cross-sectional view of the process following Figure 18G. A cross-sectional view of the process following Figure 18H. A cross-sectional view of the process following Figure 18I. A cross-sectional view of the process following Figure 18J. A cross-sectional view of the process following Figure 18K. A cross-sectional view of the process showing an example of the second manufacturing process. A cross-sectional view of the process following Figure 19A. A cross-sectional view of the process following Figure 19B. A cross-sectional view of the process following Figure 19C. A cross-sectional view of the process following Figure 19D. A cross-sectional view of the process following Figure 19E. A cross-sectional view of the process following Figure 19F. Process cross-sectional view following Figure 19G. Process cross-sectional view following Figure 19H. Process cross-sectional view following Figure 19I. Process cross-sectional view following Figure 19J. Process cross-sectional view following Figure 19K. Process cross-sectional view showing a third example of the manufacturing process. Process cross-sectional view following Figure 20A. Process cross-sectional view following Figure 20B. Process cross-sectional view following Figure 20C.Process cross-sectional view following Figure 20D. Process cross-sectional view following Figure 20E. Process cross-sectional view following Figure 20F. Process cross-sectional view following Figure 20G. Process cross-sectional view following Figure 20H. Process cross-sectional view following Figure 20I. Process cross-sectional view following Figure 20J. Process cross-sectional view following Figure 20K. Process cross-sectional view following Figure 20L. Block diagram showing an example of the general configuration of a vehicle control system. Explanatory diagram showing an example of the installation location of the external information detection unit and imaging unit.

[0029] The embodiments of the photodetector will be described below with reference to the drawings. While the main components of the photodetector will be described below, there may be components and functions not shown or described in the drawings. The following description does not exclude any components or functions not shown or described.

[0030] Figure 1 is a block diagram of an electronic device 30 equipped with a light detection device 1 according to one embodiment of the present disclosure. This electronic device 30 has a function to generate an image corresponding to the brightness of incident light. The electronic device 30 in Figure 1 comprises a light detection device 1, an imaging lens 31, an image processing unit 32, a recording unit 33, and a control unit 34. The electronic device 30 can be applied to various electronic devices such as surveillance cameras, cameras mounted on industrial robots, or cameras for general use, but the specific application and configuration of the electronic device 30 are arbitrary.

[0031] The imaging lens 31 focuses the incident light and guides it to the photodetector 1. The photodetector 1 images the incident light. The photodetector 1 causes light in a predetermined wavelength range, such as visible light or infrared light, to be incident on multiple pixels and performs photoelectric conversion, accumulating a charge in the floating diffusion region corresponding to the amount of incident light. The charge accumulated in the floating diffusion region is converted into a voltage, and a pixel signal with a voltage level corresponding to the amount of incident light is generated. The photodetector 1 generates image data on a frame-by-frame basis based on the pixel signal of each pixel.

[0032] The light detection device 1 according to this embodiment has a plurality of pixels for detecting grayscale information or brightness information. The light detection device 1 according to this embodiment may also include pixels for an EVS (Event Vision Sensor) that detect changes in the amount of incident light as events.

[0033] The image processing unit 32 performs predetermined image processing on the image data generated by the light detection device 1, such as color or brightness adjustment, image compression, image recognition, tracking, or analysis. The image data processed by the image processing unit 32 is recorded, for example, in the recording unit 33.

[0034] The recording unit 33 records image data output from the light detection device 1 or the image processing unit 32. The recording unit 33 may be located on a server connected via a network. In the electronic device 30 according to this embodiment, at least one of the image processing unit 32 and the recording unit 33 in Figure 1 can be omitted.

[0035] The control unit 34 controls the operation of the light detection device 1. Although not explicitly shown in Figure 1, the control unit 34 may also control the image processing unit 32 and the recording unit 33.

[0036] (Two-Layer Stacking) The photodetector 1 according to this disclosure can be realized as a stacked chip. Figure 2A is a schematic perspective view showing an example of a two-layer stacked structure for the photodetector 1 according to this disclosure. The photodetector 1 in Figure 2A comprises a first layer SB1 arranged on the light incident surface side and a second layer SB2 stacked on the first layer SB1. For example, a photoelectric conversion element for each pixel is arranged in the first layer SB1. In this specification, an example in which the photoelectric conversion element is a photodiode will be mainly described. Circuits surrounding the photodiode (for example, a transfer transistor) may also be arranged in the first layer SB1. Multiple transistors for generating an event signal are arranged in the second layer SB2. The first layer SB1 and the second layer SB2 are joined and signal transmitted by, for example, a CCC (Cupper-Cupper Connection). Alternatively, the first layer SB1 and the second layer SB2 may be joined by vias or bumps other than a CCC. In this specification, the first layer SB1 may be referred to as the pixel chip, and the second layer SB2 as the logic chip.

[0037] (Three-Layer Lamination) The photodetector 1 according to this disclosure can be constructed by laminating multiple layers on one or more substrates. Figure 2B is a schematic perspective view showing an example of a three-layer structure for the photodetector 1 according to this disclosure. Figure 2B shows an example of a photodetector 1 having a laminated structure of a first layer SB1, a second layer SB2, and a third layer SB3. Photoelectric conversion elements for each pixel are arranged in the first layer SB1. For example, pixel transistors are arranged in the second layer SB2. For example, signal processing circuits are arranged in the third layer SB3. The first to third layers SB1 to SB3 may be physically different first to third substrates, or at least some of the layers may be arranged at different heights on the same substrate.

[0038] Furthermore, the circuit elements and other components placed in the first layer SB1, the second layer SB2, and the third layer SB3 are arbitrary and can be in any combination.

[0039] Figure 3 is a block diagram showing the overall configuration of the photodetector 1 according to this disclosure. The photodetector 1 shown in Figure 3 shows the block configuration of a CMOS (Complementary Metal Oxide Semiconductor) image sensor.

[0040] The light detection device 1 in Figure 3 comprises a pixel array section 2 and a peripheral circuit section 3.

[0041] The pixel array section 2 has a plurality of pixels 4 arranged in two dimensions in a first direction (e.g., row direction) X and a second direction (e.g., column direction) Y. Each pixel 4 has a photoelectric conversion element, a floating diffusion region, a transfer transistor, and a pixel transistor, etc. In this embodiment, a floating diffusion region can be shared by two or more pixels 4.

[0042] The pixel array section 2 is arranged with multiple row selection lines LS and multiple vertical signal lines VSL. Each pixel 4 is connected to either a row selection line LS or a vertical signal line VSL. The multiple row selection lines LS extend in a first direction X and are arranged at intervals in a second direction Y. The multiple vertical signal lines VSL extend in a second direction Y and are arranged at intervals in the first direction X.

[0043] The peripheral circuit section 3 includes a row selection section 5, a constant current source section 6, an analog-digital conversion section 7, a horizontal transfer scanning section 8, a signal processing section 9, a timing control section 10, and a reference signal generation section 11.

[0044] The row selection section 5 sequentially drives a plurality of row selection lines LS. The row selection section 5 includes a shift register, an address decoder, and the like that are not shown in the drawings. The row selection section 5 performs read scanning and sweep scanning. In read scanning, a plurality of row selection lines LS are sequentially driven. Pixel signals corresponding to charges photoelectrically converted by each pixel 4 on the driven row selection line LS are output to the corresponding vertical signal lines VSL. In sweep scanning, the row selection line LS of a read row is driven before the start of an exposure period that is performed before the start of read scanning, so that charges in each pixel 4 are discharged.

[0045] The constant current source section 6 includes a plurality of current sources connected to the plurality of vertical signal lines VSL. Each current source includes, for example, a MOS transistor, and supplies a bias current to each vertical signal line VSL.

[0046] The analog-digital conversion section 7 converts a plurality of pixel signals on the plurality of vertical signal lines VSL into digital signals. The analog-digital conversion section 7 includes a comparator, a counter, and a latch, which are not shown in FIG. 3, for each of the plurality of vertical signal lines VSL.

[0047] Each comparator compares the pixel signal on the corresponding vertical signal line VSL with the reference signal generated by the reference signal generation section 11. Each counter stops counting when the pixel signal matches the reference signal at the corresponding comparator. Each latch holds the count value obtained when the corresponding counter stops counting. A digital signal obtained by analog-digital converting the pixel signal is generated from the count value held by the latch.

[0048] The horizontal transfer scanning section 8 controls transfer of the digital signals that have been analog-digital converted by the analog-digital conversion section 7. The horizontal transfer scanning section 8 includes a shift register, an address decoder, and the like.

[0049] The signal processing unit 9 generates image data on a frame-by-frame basis based on the digital signals of each pixel 4 transmitted by the horizontal transfer scanning unit 8. For example, the signal processing unit 9 performs digital signal processing such as correcting vertical line defects and dot defects, and adjusting brightness and gradation levels.

[0050] The timing control unit 10 generates various timing signals, clock signals, and control signals, and uses these signals to drive and control the row selection unit 5, constant current source unit 6, reference signal generation unit 11, analog-to-digital conversion unit 7, horizontal transfer scanning unit 8, and signal processing unit 9, etc.

[0051] The light detection device 1 according to this embodiment is characterized in that a first pixel group IG1 containing two or more pixels 4 shares a floating diffusion region, and each second pixel group IG2 containing two or more first pixel groups IG1 also shares a floating diffusion region, and a single signal line provided for each second pixel group IG2 transmits the pixel signals of all or some of the pixels 4 included in the corresponding second pixel group IG2. Hereinafter, the signal line may be referred to as the vertical signal line VSL.

[0052] Thus, in the photodetector 1 according to this embodiment, when each of the multiple vertical signal lines VSLs shares the floating diffusion region of all pixels 4 included in the second pixel group IG2, a pixel signal is transmitted which is a composite of the charges photoelectrically converted in all pixels 4. When the floating diffusion regions of all pixels 4 included in the second pixel group IG2 are not shared, the pixel signals of each of the two or more first pixel groups IG1 included in the second pixel group IG2 are transmitted with a time delay.

[0053] Multiple vertical signal lines VSLs corresponding to multiple second pixel groups IG2 are arranged, for example, in one direction. Multiple second pixel groups IG2, multiple first pixel groups IG1 included in the second pixel groups IG2, and multiple pixel transistors connected to the multiple second pixel groups IG2 are arranged in accordance with the direction in which the multiple vertical signal lines VSLs extend.

[0054] Figure 4 is a circuit diagram of a pixel circuit 20 connected to the second pixel group IG2 in the photodetector 1 according to this embodiment. The pixel circuit 20 in Figure 4 shares a floating diffusion region FD with the first pixel group IG1 which includes four pixels 4, and also shares a floating diffusion region FD with the second pixel group IG2 which includes two first pixel groups IG1.

[0055] Of the two first pixel groups IG1 included in the second pixel group IG2, one first pixel group IG1 has four photodiodes PD0 to PD3 and four transfer transistors TRG0 to TRG3, while the other first pixel group IG1 has four photodiodes PD4 to PD7 and four transfer transistors TRG4 to TRG7.

[0056] The four floating diffusion regions FD0, connected to one end (e.g., source) of the four transfer transistors TRG0 to TRG3, are interconnected and shared with one another. Similarly, the four floating diffusion regions FD1, connected to one end (e.g., source) of the four transfer transistors TRG4 to TRG7, are interconnected and shared with one another.

[0057] In the pixel circuit 20 of Figure 4, one of the two first pixel groups IG1 is provided with a floating diffusion region FD0, a reset transistor RST0, a conversion efficiency switching transistor FDG0, an amplification transistor AMP0, and a selection transistor SEL0, while the other first pixel group IG1 is provided with a floating diffusion region FD1, a reset transistor RST1, a conversion efficiency switching transistor FDG1, an amplification transistor AMP1, and a selection transistor SEL1. The sources of the two selection transistors SEL0 and SEL1 are connected to a common vertical signal line VSL0. Thus, all selection transistors SEL0 and SEL1 included in the corresponding second pixel group IG2 are connected to the vertical signal line VSL0. When at least one of the conversion efficiency switching transistors FDG0 and FDG1 is turned on, at least a portion of the charge in at least one of the floating diffusion regions FD0 and FD1 is transferred to the capacitor C, allowing it to hold more of the charge generated by photoelectric conversion.

[0058] When FD linking is performed, both conversion efficiency switching transistors FDG0 and FDG1 are turned on. As a result, at least a portion of the charge in the floating diffusion regions FD0 and FD1 is transferred to capacitor C, allowing the floating diffusion regions FD0 and FD1 and capacitor C to share the charge.

[0059] The drain of reset transistor RST0 is connected to the power supply voltage VDD node, and its source is connected to the floating diffusion region FD0. The drain of reset transistor RST1 is connected to the power supply voltage VDD node, and its source is connected to the floating diffusion region FD1.

[0060] The gate of the amplification transistor AMP0 is connected to the floating diffusion region FD0. The drain of the amplification transistor AMP0 is connected to the power supply voltage node VDD, and its source is connected to the drain of the selection transistor SEL0. The source of the selection transistor SEL0 is connected to the vertical signal line VSL0.

[0061] The gate of the amplification transistor AMP1 is connected to the floating diffusion region FD1. The drain of the amplification transistor AMP1 is connected to the power supply voltage VDD node, and its source is connected to the drain of the selection transistor SEL1. The source of the selection transistor SEL1 is connected to the vertical signal line VSL0.

[0062] When performing FD linking in the pixel circuit 20 of Figure 4, both conversion efficiency switching transistors FDG0 and FDG1 are turned on. As a result, the two floating diffusion regions FD0 and FD1 and capacitor C of the two first pixel groups IG1 are connected, and the second pixel group IG2 shares the floating diffusion regions FD0 and FD1.

[0063] Furthermore, when performing FD linking in the pixel circuit 20 of Figure 4, both selection transistors SEL0 and SEL1 are turned on. This supplies a pixel signal with a voltage level corresponding to the combined charge of the two floating diffusion regions FD0 and FD1 to the vertical signal line VSL0. In this way, when all pixels in the second pixel group IG2 corresponding to the signal line share a floating diffusion region, all selection transistors SEL0 and SEL1 connected to the vertical signal line VSL0 are turned on.

[0064] Although only one vertical signal line VSL0 is shown in Figure 4, other vertical signal lines VSL have a similar configuration.

[0065] On the other hand, if FD linking is not performed in the pixel circuit 20 of Figure 4, the conversion efficiency switching transistors FDG0 and FDG1 are turned off. As a result, the two floating diffusion regions FD0 and FD1 are not connected. In this state, if either of the selection transistors SEL0 or SEL1 is turned on, a pixel signal with a voltage level corresponding to the charge of one of the floating diffusion regions FD0 or FD1 is supplied to the vertical signal line VSL0.

[0066] Thus, when FD linking is performed, both conversion efficiency switching transistors FDG0 and FDG1 are turned on, and both selection transistors SEL0 and SEL1 are turned on, supplying a pixel signal with a voltage level corresponding to the combined charge obtained by photoelectric conversion in the two first pixel groups IG1 to the vertical signal line VSL0. When FD linking is not performed, both conversion efficiency switching transistors FDG0 and FDG1 are turned off, and the two selection transistors SEL0 and SEL1 are turned on alternately. As a result, pixel signals with voltage levels corresponding to the charge obtained by photoelectric conversion in the two first pixel groups IG1 are supplied to the vertical signal line VSL0 with a time delay.

[0067] (First Embodiment) Figure 5 is a partial cross-sectional view of the light detection device 1 according to the first embodiment. Figure 5 shows the cross-sectional structure of two adjacent pixels 4. Figure 5 shows a first layer SB1 on which a plurality of pixels 4 are arranged, and a second layer SB2 on which at least a part of the pixel circuit is arranged. The light detection device 1 according to this embodiment may include a third layer SB3 stacked on the second layer SB2, as shown in Figure 2B, but the third layer SB3 is not shown in Figure 5. As described above, the first layer SB1 and the second layer SB2 are arranged at different heights on the same substrate. Alternatively, the first layer SB1 and the second layer SB2 may be arranged on different substrates and the substrates may be bonded together.

[0068] Each pixel 4 arranged in the first layer SB1 has a photoelectric conversion unit PD, a transfer transistor TRG, and a floating diffusion region FD. The photoelectric conversion unit PD has, for example, an N-type silicon layer. The N-type impurity concentration in the N-type silicon layer changes continuously or stepwise depending on the depth position.

[0069] The photoelectric conversion unit PD is divided into pixel-separated regions 41 for each pixel 4. The pixel-separated region 41 extends in the depth direction of the first layer SB1 along the boundary region of the pixel 4. The pixel-separated region 41 has a laminated structure in which a light-shielding member 42 such as tungsten, an insulating layer 43 laminated on the light-shielding member 42, and a fixed charge film 44 laminated on the insulating layer 43 are laminated. The pixel-separated region 41 may be arranged to penetrate the N-type silicon layer, or it may be arranged at a height position that is part of the pixel 4 boundary region of the N-type silicon layer.

[0070] The photoelectric conversion unit PD is arranged in the region of each pixel 4, which is separated by the pixel separation region 41. The photoelectric conversion unit PD has an N-type silicon layer 45 that performs photoelectric conversion and a P-type diffusion region 46 arranged around the N-type silicon layer 45. The photoelectric conversion unit PD is, for example, a photodiode.

[0071] The gate of the transfer transistor TRG (hereinafter referred to as the transfer gate) has a vertical electrode extending in the depth direction of the N-type silicon layer 45. The transfer transistor TRG turns on when the transfer gate reaches a high level and transfers the charge photoelectrically converted by the photoelectric conversion unit PD to the floating diffusion region FD. The floating diffusion region FD of each pixel 4 is arranged along the boundary region of the pixel 4. For example, when four pixels 4 share a pixel circuit, four floating diffusion regions FD are arranged near the intersection of the four pixels 4.

[0072] Four floating diffusion regions FD are connected by vias 47 extending in the depth direction of the first layer SB1. The four floating diffusion regions FD are connected to the upper wiring layer WL0 via the vias 47. In this specification, each wiring layer at the depth position where this wiring layer WL0 is located is collectively referred to as the M0 wiring layer WL0. The M0 wiring layer WL0 is provided in the first layer SB1.

[0073] A first contact (first conductive member) CT1 is connected to the M0 wiring layer WL0. The first contact CT1 is positioned from the first layer SB1 to the second layer SB2. Alternatively, the first contact CT1 is positioned in the second layer SB2. More specifically, the first contact CT1 is connected to the M0 wiring layer WL0 of the first layer SB1 and the M1 wiring layer WL1 of the second layer SB2. The first contact CT1 is provided to transmit the potential of the floating diffusion region FD of the first layer SB1 to the pixel transistor of the second layer SB2.

[0074] The second layer SB2 has a region where pixel transistors such as amplification transistors are arranged, an M1 wiring layer WL1 arranged above this region, and an M2 wiring layer WL2 arranged above the M1 wiring layer WL1. It is also possible that one or more wiring layers from M3 onwards are arranged above the M2 wiring layer WL2.

[0075] Well contact regions 48 are provided at corners different from the corners where the floating diffusion region FD is located within the region of each pixel 4 separated by the pixel separation region 41. The well contact regions 48 are located in the P-type diffusion region 46. A second contact CT2 is placed in the well contact region 48. The second contact CT2 is placed from the first layer SB1 to the second layer SB2. The second contact CT2 is used to set the well contact region 48 and the P-type diffusion region 46 to ground potential.

[0076] As shown in Figure 5, the second contact CT2 is longer than the first contact CT1. In addition, vias are provided inside the first layer SB1 and the second layer SB2 to connect diffusion layers arranged in different depth directions, vias to connect wiring layers arranged in different depth directions, and vias to connect diffusion layers and wiring layers arranged in different depth directions.

[0077] The first contact CT1, the second contact CT2, and the vias are made of a conductive material such as copper (Cu), tungsten (W), or aluminum (Al). The vias may also be referred to as contacts, and vice versa. In this specification, contacts and vias are sometimes collectively referred to as conductive members.

[0078] In the first embodiment, various conductive members are provided in the first layer SB1 or the second layer SB2, and a capacitor C of the same length is provided at the same depth. The conductive members may connect two diffusion layers located at different positions, connect a diffusion layer located at different positions to a wiring layer, or connect two wiring layers located at different positions to each other.

[0079] Figure 6 is an enlarged cross-sectional view of the area around the first contact CT1 shown by the dashed frame in Figure 5. As shown in Figure 6, the pixel 4 has a first contact CT1 and a capacitor C, both having the same length in the depth direction. The diameter of the capacitor C is larger than the diameter of the first contact CT1. Both the first contact CT1 and the capacitor C are connected to the M0 wiring layer WL0 and the M1 wiring layer WL1. As described above, the M0 wiring layer WL0 is located in the first layer SB1, and the M1 wiring layer WL1 is located in the second layer SB2. Therefore, the first contact CT1 and the capacitor C are located from the first layer SB1 to the second layer SB2. Alternatively, the first contact CT1 and the capacitor C are located in the second layer SB2.

[0080] Capacitor C has a MIM (Metal Insulator Metal) structure. More specifically, capacitor C has a first electrode layer 51 arranged in the depth direction of the second layer SB2, an insulating layer 52 arranged in the depth direction of the second layer SB2 and laminated on the first electrode layer 51, and a second electrode layer 53 arranged in the depth direction of the second layer SB2 and laminated on the insulating layer 52.

[0081] By using a MIM structure for the capacitor C, a large charge-holding capacity can be obtained with a small footprint. In particular, since the capacitor C has the same length as the first contact CT1 and can form a charge-holding region along the depth direction of the second layer SB2, a large-capacitance capacitor C can be obtained even with a small surface size. Moreover, since the depth position and length of the capacitor C are the same as those of the first contact CT1, the capacitor C can be formed in the process of forming the first contact CT1, and the manufacturing process does not become complicated even when a new capacitor C is added.

[0082] The first electrode layer 51 and the second electrode layer 53 of capacitor C are made of a conductive material such as copper (Cu) or tungsten (W). The insulating layer of capacitor C is made of an insulating material such as zirconium oxide. The insulating layer may also be a laminated structure in which multiple layers made of two or more types of insulating materials are stacked.

[0083] Capacitor C is used, for example, to hold the charge transferred from the floating diffusion region FD when at least one of the conversion efficiency switching transistors FDG0 and FDG1 in Figure 4 is turned on.

[0084] Figure 7 is a cross-sectional view showing the periphery of the capacitor C in the photodetector 1 according to the first embodiment.

[0085] As shown in Figure 7, the first electrode layer 51 of capacitor C is connected to the M0 wiring layer WL0. The M0 wiring layer WL0 is connected to the first contact CT1. The first contact CT1 is connected to both the M0 wiring layer WL0 and the M1 wiring layer WL1. As a result, the first electrode layer 51 of capacitor C is electrically connected to the M1 wiring layer WL1 via the M0 wiring layer WL0 and the first contact CT1.

[0086] The second electrode layer 53 of capacitor C is connected to the M1 wiring layer WL1. A via 54 extending in the depth direction is connected to the M1 wiring layer WL1. This via 54 is connected to both the M1 wiring layer WL1 and the M2 wiring layer WL2. As a result, the second electrode layer 53 of capacitor C is electrically connected to the M2 wiring layer WL2 via the M1 wiring layer WL1 and the via 54.

[0087] Various contacts and vias, including the first contact CT1 and the second contact CT2, and the first electrode layer 51 and the second electrode layer of the capacitor C may be formed from the same conductive material. In this case, the conductive material may be, for example, copper (Cu), tungsten (W), polysilicon implanted with impurity ions, amorphous silicon implanted with impurity ions, N-type silicon, P-type silicon, transparent electrode material, titanium (Ti), or titanium nitride (TiN).

[0088] Thus, the first electrode layer 51 and the second electrode layer 53 of the capacitor C according to the first embodiment are electrically connected to the M1 wiring layer WL1 and the M2 wiring layer WL2, which are located at different depths. This makes it easier to route the two wiring layers connected to the first electrode layer 51 and the second electrode layer 53 of the capacitor C.

[0089] Furthermore, in the first embodiment, since a capacitor C of the same length is provided at the same depth as the first contact CT1 located in the second layer SB2, the capacitor C can be formed in the same process as the formation of the first contact CT1, eliminating the need for a separate process for forming the capacitor C. Therefore, the capacitor C can be formed without complicating the manufacturing process.

[0090] The first contact CT1 and capacitor C may be connected to a first wiring layer located closer to the second layer SB2 than the location of the transfer transistor and the floating diffusion region FD, and to a second wiring layer of the second layer SB2 located further from the first layer SB1 than the location of the pixel circuit.

[0091] Alternatively, the via and capacitor C may be connected to the first and second wiring layers in the first layer SB1 or the second layer SB2.

[0092] Figure 7 shows an example where a capacitor C of the same length as the first contact CT1 is provided, but a capacitor C of the same length as the second contact CT2 shown in Figure 5 may also be provided. In this case, the capacitor C can be formed in the process of forming the second contact CT2. Since the second contact CT2 is longer than the first contact CT1, the charge holding capacity of the capacitor C can be increased further.

[0093] Furthermore, as will be described later, a capacitor C having the same length as the via provided inside the first layer SB1 or the second layer SB2 may be provided, and the capacitor C may be formed in the via formation process.

[0094] (Second Embodiment) Figure 8 is a cross-sectional view showing the surrounding structure of the capacitor C in the photodetector 1 according to the second embodiment.

[0095] As shown in Figure 8, a first electrode layer 51, an insulating layer 52, and a second electrode layer 53 are arranged radially on the upper surface of the capacitor C, and these three layers are in contact with the insulating layer 55 of the second layer SB2 on the upper surface of the capacitor C. Near the upper surface of the capacitor C, the M1 wiring layer WL1 and the M2 wiring layer WL2 are arranged, and there is a risk of time-dependent dielectric breakdown (TDDB) of the capacitor C. Therefore, as shown in Figure 8, a dielectric layer 56 with high resistance to voltage or current stress may be arranged on the upper surface of the capacitor C. This dielectric layer 56 may be, for example, a layer containing zirconium oxide, or other dielectric materials may be used. Alternatively, the dielectric layer 56 may be a layer formed by stacking multiple dielectric layers 56. The dielectric layer 56 is arranged around the vias connected to the second electrode layer 53 on the upper surface of the capacitor C.

[0096] Thus, in the second embodiment, since at least a portion of the upper surface of the capacitor C, which is the same depth and length as the first contact CT1, is covered with the dielectric layer 56, TDDB is less likely to occur, and reliability is improved.

[0097] (Third Embodiment) Figure 9 is a cross-sectional view showing the surrounding structure of the capacitor C in the photodetector 1 according to the third embodiment.

[0098] In the third embodiment, at least one surface of the capacitor C, contact, via, M0 wiring layer WL0, M1 wiring layer WL1, and M2 wiring layer WL2 in the pixel 4 or pixel circuit is covered with a barrier metal layer 57.

[0099] Figure 9 shows an example in which a barrier metal layer 57 is laminated on the side of the first electrode layer 51 of the capacitor C opposite to the contact surface with the insulating layer 52. For example, if the first electrode layer 51 is made of copper (Cu), there is a risk that copper (Cu) may leak into the surroundings due to migration, causing problems such as fluctuations in the capacitance of the capacitor C. Therefore, migration can be prevented by covering the first electrode layer 51 with a barrier metal layer 57. The barrier metal layer 57 is, for example, tantalum (Ta) or tantalum nitride (TaN).

[0100] Although not shown in Figure 9, the surfaces of each contact, via, and wiring layer may be covered with a barrier metal layer 57.

[0101] Thus, in the third embodiment, the surface of the conductive member in the pixel 4 (for example, at least one of the capacitor C, contact, via, M0 wiring layer WL0, M1 wiring layer WL1, and M2 wiring layer WL2) is covered with a barrier metal layer 57, eliminating the risk of migration of the conductive material of the conductive member and preventing fluctuations in electrical characteristics.

[0102] (Fourth Embodiment) Figure 10 is a cross-sectional view showing the surrounding structure of a capacitor C in the photodetector 1 according to the fourth embodiment.

[0103] In the fourth embodiment, a capacitor C of the same length is placed at the same depth as the third contact CT3 connected to the diffusion layer 58 and the M1 wiring layer WL1. The diffusion layer 58 is, for example, the gate, drain, or source diffusion layer of a pixel transistor located in the second layer SB2. The wiring layer is, for example, the M1 wiring layer WL1 of the second layer SB2.

[0104] The capacitor C according to the fourth embodiment is connected to the diffusion layer 58 and the M1 wiring layer WL1, similar to the third contact CT3. For example, the first electrode layer 51 of the capacitor C is connected to the diffusion layer 58 of the gate, drain, or source of a pixel transistor located in the second layer SB2. The second electrode layer 53 of the capacitor C is connected to the M1 wiring layer WL1 of the second layer SB2, for example. Vias 54 extending in the depth direction are connected to the M1 wiring layer WL1. The vias 54 are connected to the M1 wiring layer WL1 and the M2 wiring layer WL2. Thus, the second electrode layer 53 of the capacitor C is electrically connected to the M2 wiring layer WL2.

[0105] In the fourth embodiment, the third contact CT3 and capacitor C may be provided in the first layer SB1.

[0106] Thus, in the fourth embodiment, the capacitor C can be formed in the step of forming the third contact CT3 which is connected to the diffusion layer 58 and the M1 wiring layer WL1.

[0107] (Fifth Embodiment) Figure 11 is a cross-sectional view showing the surrounding structure of a capacitor C in the photodetector 1 according to the fifth embodiment.

[0108] In the fifth embodiment, similar to the fourth embodiment, a capacitor C of the same length and depth as the third contact CT3 connected to the diffusion layer 58 and the M1 wiring layer WL1 is provided. The first electrode layer 51 of the capacitor C according to the fifth embodiment is connected, for example, to the gate G of a pixel transistor located in the second layer SB2. A fourth contact CT4 extending in the depth direction of the second layer SB2 is connected to the gate G. The fourth contact CT4 is connected to the gate G and the M1 wiring layer WL1. As a result, the first electrode layer 51 of the capacitor C is electrically connected to the M1 wiring layer WL1 via the gate G and the fourth contact CT4. The second electrode layer 53 of the capacitor C is electrically connected to the M2 wiring layer WL2 via a via 54 with respect to the M1 wiring layer WL1, similar to the fourth embodiment.

[0109] Thus, in the fifth embodiment, the first electrode layer 51 of the capacitor C can be directly connected to the gate G of the pixel transistor, and electrically connected from the gate G to the M1 wiring layer WL1 via the fourth contact CT4.

[0110] (Sixth Embodiment) Figure 12 is a cross-sectional view showing the surrounding structure of a capacitor C in the photodetector 1 according to the sixth embodiment.

[0111] In the first to fifth embodiments, the first electrode layer 51 of the capacitor C is electrically connected to the M1 wiring layer WL1 via a contact extending in the depth direction with respect to the wiring layer or diffusion layer on the first layer SB1 side. In contrast, in the sixth embodiment, as shown in Figure 12, the first electrode layer 51 is directly connected to the M1 wiring layer WL1. The second electrode of the capacitor C is connected to the M1 wiring layer WL1, and the M1 wiring layer WL1 is connected to the M2 wiring layer WL2 via a via 54.

[0112] Thus, in the sixth embodiment, both the first electrode layer 51 and the second electrode layer 53 of the capacitor C are connected to either the M1 wiring layer WL1 or the M2 wiring layer WL2 on the upper surface side of the capacitor C. This eliminates the need to provide a contact connecting the M0 wiring layer WL0 and the M1 wiring layer WL1 in order to connect the first electrode layer 51 to the M1 wiring layer WL1, thereby simplifying the structure.

[0113] (Seventh Embodiment) Figure 13 is a cross-sectional view showing the surrounding structure of a capacitor C in the photodetector 1 according to the seventh embodiment.

[0114] As shown in Figure 13, the capacitor C according to the seventh embodiment includes a capacitor C that is at the same depth and has the same length as the first contact CT1 connected to the M0 wiring layer WL0 and the M1 wiring layer WL1.

[0115] The capacitor C according to the seventh embodiment comprises a filling portion Ca that is filled into a trench and a flange portion Cb that is positioned outside the upper end of the trench. Both the filling portion Ca and the flange portion Cb have a laminated structure of a first electrode layer 51, an insulating layer 52, and a second electrode layer 53.

[0116] The flange portion Cb is positioned at the same depth as the M1 wiring layer WL1. The first electrode layer 51 and the insulating layer 52 are positioned on the outside of the flange portion Cb.

[0117] The first electrode layer 51 is electrically connected to the M2 wiring layer WL2 via via 61. The second electrode layer 53 is also electrically connected to the M2 wiring layer WL2 via via 54.

[0118] Thus, in the seventh embodiment, since the capacitor C has a flange portion Cb, the charge holding capacity can be increased compared to the first to sixth embodiments. Furthermore, since the first electrode layer 51, which is part of the capacitor C, is positioned at the same depth as the M1 wiring layer WL1, the first electrode layer 51 can be formed in the process of forming the M1 wiring layer WL1.

[0119] (Eighth Embodiment) Figure 14 is a cross-sectional view showing the surrounding structure of the capacitor C in the photodetector 1 according to the eighth embodiment.

[0120] The photodetector 1 according to the eighth embodiment consists only of the first layer SB1. The contact CT is connected to the diffusion layer 63 and the M1 wiring layer WL1, which are arranged on the substrate 70. The first electrode layer 51 of the capacitor C is connected to the diffusion layer 63, which are arranged on the substrate 70. This diffusion layer 63 is connected to the M1 wiring layer WL1 via the contact CT. Therefore, the first electrode layer 51 of the capacitor C is electrically connected to the M1 wiring layer WL1. The second electrode layer 53 of the capacitor C is connected to the M1 wiring layer WL1. The M1 wiring layer WL1 is electrically connected to the M2 wiring layer WL2 via the via 54. As a result, the second electrode layer 53 of the capacitor C is electrically connected to the M2 wiring layer WL2.

[0121] Thus, in the eighth embodiment, when the photodetector 1 is constructed using only the first layer SB1, a capacitor C is provided at the same depth and length as the contact CT connected to the diffusion layer 63 of the substrate 70 and the M1 wiring layer WL1. Therefore, the capacitor C can be formed in the process of forming the contact CT.

[0122] (Ninth Embodiment) Figure 15 is a plan view of the capacitor C according to the first to eighth embodiments, viewed from above. As shown in Figure 15, the planar shape of the capacitor C viewed from above is arbitrary and can take on various shapes. For example, Figure 15 shows examples of capacitor C having an L-shape, a circular shape, an elliptical shape, and a non-uniform curved surface shape. In addition, the capacitor C can also take on any planar shape such as an annular shape, an uneven shape, or a polyline shape.

[0123] (Tenth Embodiment) Figure 16 is a cross-sectional view showing the surrounding structure of a capacitor C in the light detection device 1 according to the tenth embodiment.

[0124] In the tenth embodiment, a capacitor C of the same length is placed at the same depth as the via 64 connecting the M1 wiring layer WL1 and the M2 wiring layer WL2, which are shown by the dashed frame F1 in Figure 16. Note that the capacitor C is not shown in Figure 16.

[0125] Thus, the capacitor C can be placed not only at contacts that bridge different substrates, but also at the same depth and with the same length as vias placed at any depth in the first layer SB1 or the second layer SB2. Therefore, for example, multiple capacitors C can be provided in association with multiple vias within the pixel 4, further increasing the charge retention capacity.

[0126] (Eleventh Embodiment) In the first to tenth embodiments, an example was shown in which an FtoB junction is performed in which the upper surface of the first layer SB1 and the lower surface of the second layer SB2 are facing each other. However, the photodetector 1 according to the present disclosure is also applicable in the case of an FtoF junction in which the upper surface of the first layer SB1 and the upper surface of the second layer SB2 are facing each other.

[0127] Figure 17 is a partial cross-sectional view of the light detection device 1 according to the eleventh embodiment. The light detection device 1 according to the eleventh embodiment shows an example in which cupper-to-cupper connection (CCC) is performed by facing the upper surface of the first layer SB1 and the upper surface of the second layer SB2.

[0128] Although Figure 17 omits the illustration of contacts, vias, and capacitor C, the same effects as in the first to tenth embodiments can be obtained by placing capacitor C at the same depth and length as the contacts or vias located in the first layer SB1 and the second layer SB2.

[0129] (Example of the first manufacturing process) Figures 18A to 18L are cross-sectional views showing an example of the first manufacturing process. The first example of the manufacturing process shows the process for manufacturing the photodetector 1 according to the first embodiment shown in Figure 7. Hereinafter, contact CTs or vias formed at the same depth and length as the capacitor C will be collectively referred to as contact CTs.

[0130] First, as shown in Figure 18A, a plurality of trenches 72 are formed in the oxide layer (e.g., SiO2 layer) 71 formed on the substrate 70 of the first layer SB1. These trenches 72 are formed to match the locations where the contact CT and capacitor C are formed. In addition, an M0 wiring layer WL0 is formed on the bottom surface of the trenches 72. The M0 wiring layer WL0 is formed of, for example, copper (Cu), tungsten (W), or aluminum (Al). The substrate 70 is, for example, a silicon substrate.

[0131] Next, as shown in Figure 18B, a conductive material is filled into the trench 72 corresponding to the contact CT, and a first electrode layer 51 made of the conductive material is formed on the upper surface of the oxide layer 71 and on the inner wall of the trench 72 for the capacitor C. The conductive material is, for example, copper (Cu) or tungsten (W).

[0132] Next, as shown in Figure 18C, an insulating layer 52 is formed on the first electrode layer 51. The insulating layer 52 is, for example, zirconia oxide.

[0133] Next, as shown in Figure 18D, a second electrode layer 53 is formed on the insulating layer 52. The material of the second electrode layer 53 may be the same as or different from that of the first electrode layer 51. By forming the second electrode layer 53, the inside of the trench 72 for the capacitor C is filled with the second electrode layer 53, and the upper surface of the substrate 70 becomes flat.

[0134] Next, as shown in Figure 18E, the second electrode layer 53, insulating layer 52, and first electrode layer 51 formed on the upper surface of the oxide layer 71 are removed. As a result, a capacitor C is formed with the first electrode layer 51, insulating layer 52, and second electrode layer 53 filled only inside the trench 72.

[0135] Next, as shown in Figure 18F, an oxide layer 73 is formed on the oxide layer 71. The oxide layer 73 is, for example, an SiO2 layer.

[0136] Next, as shown in Figure 18G, the oxide layer 73 formed in Figure 18F is patterned to expose the upper surface of the first contact CT1 and the upper surface of the second electrode layer 53 of the capacitor C.

[0137] Next, as shown in Figure 18H, a conductive layer 74, which is the material for the M1 wiring layer WL1, is formed on the upper surface of the oxide layer 73. The material for the conductive layer 74 is, for example, copper (Cu), tungsten, or aluminum (Al).

[0138] Next, as shown in Figure 18I, the conductive layer 74 is thinned to form the M1 wiring layer WL1.

[0139] Next, as shown in Figure 18J, an oxide layer 75 is formed on the upper surface of the M1 wiring layer WL1 and the oxide layer 73. The oxide layer 75 is, for example, an SiO2 layer. The formed oxide layer 75 is patterned to match the formation location of the M2 wiring layer WL2, and trenches 76 are formed in the oxide layer 75 to match the position of the second electrode of the capacitor C.

[0140] Next, as shown in Figure 18K, a conductive layer 77, which is the material for the M2 wiring layer WL2, is formed on the upper surface of the oxide layer 75. The material for the conductive layer 77 is, for example, copper (Cu), tungsten, or aluminum (Al).

[0141] Next, as shown in Figure 18L, the conductive layer 77 is thinned to form the M2 wiring layer WL2.

[0142] In the first manufacturing process shown in Figures 18A to 18L, if the MIM structure capacitor C is not formed, the two steps shown in Figures 18C and 18D can be eliminated. In other words, the MIM structure capacitor C can be formed by adding just two steps to the manufacturing process in which capacitor C is not formed.

[0143] (Example of a second manufacturing process) Figures 19A to 19L are cross-sectional views showing an example of a second manufacturing process. The second example of a manufacturing process shows the process for manufacturing the photodetector 1 according to the second embodiment shown in Figure 8. The following explanation will focus on the differences from the first manufacturing process.

[0144] The manufacturing process shown in Figures 19A to 19E is the same as that shown in Figures 18A to 18E. Next, as shown in Figure 19F, a dielectric layer 56 is formed on the upper surface of the substrate 70, and an oxide layer 81 is formed on top of it. The material of the dielectric layer 56 is, for example, zirconium oxide. Alternatively, the dielectric layer 56 may be a laminated structure consisting of multiple dielectric materials.

[0145] Next, as shown in Figure 19G, the oxide layer 81 and the dielectric layer 56 are patterned, leaving the dielectric layer 56 and oxide layer 81 only around the trench 76.

[0146] Next, as shown in Figure 19H, a conductive layer 74, which is the material for the M1 wiring layer WL1, is formed on the oxide layer 81.

[0147] Next, as shown in Figure 19I, the conductive layer 74 is thinned to expose the oxide layer 81 around the trench 76.

[0148] Next, as shown in Figure 19J, an oxide layer 75 is formed on the conductive layer 74 and the oxide layer 81, and a trench 76 is formed in the oxide layer 75 in accordance with the position of the second electrode layer 53 of the capacitor C.

[0149] Next, as shown in Figure 19K, a conductive layer 77, which is the material for the M2 wiring layer WL2, is formed on the upper surface of the oxide layer 75 to fill the inside of the trench 76.

[0150] Next, as shown in Figure 19L, the conductive layer 77 is thinned to form the M2 wiring layer WL2.

[0151] In the second manufacturing process shown in Figures 19A to 19L, if a capacitor C with an MIM structure is not formed, the three steps shown in Figures 19C to 19E can be omitted. In other words, by adding just three steps to the manufacturing process in which capacitor C is not formed, a capacitor C with an MIM structure whose upper surface is covered with a dielectric layer 56 can be formed.

[0152] (Example of the third manufacturing process) Figures 20A to 20M are cross-sectional views showing an example of the third manufacturing process. The example of the third manufacturing process shows the process for manufacturing the photodetector 1 according to the seventh embodiment shown in Figure 13. The following explanation will focus on the differences from the first manufacturing process.

[0153] The manufacturing process shown in Figures 20A to 20D is the same as that shown in Figures 18A to 18D, except that a trench for the contact CT for connecting the first electrode layer 51 of the capacitor C to the M1 wiring layer WL1 is not formed.

[0154] Next, as shown in Figure 20E, the second electrode layer 53 is removed. At this time, the second electrode layer 53 is left in the portion corresponding to the flange portion Cb of the capacitor C.

[0155] Next, as shown in Figure 20F, the first electrode layer 51 and the insulating layer between the capacitor C and the first contact CT1 are removed.

[0156] Next, as shown in Figure 20G, an oxide layer (for example, an SiO2 layer) 82 is formed on the upper surface of the substrate 70.

[0157] Next, as shown in Figure 20H, the oxide layer 82 is thinned and flattened to expose the second electrode layer 53.

[0158] Next, as shown in Figure 20I, an oxide layer (for example, an SiO2 layer) 83 is formed on the upper surface of the substrate 70.

[0159] Next, as shown in Figure 20J, trenches 84 are formed in the oxide layer 83 to match the positions of the vias connected to the second electrode layer 53 of the capacitor C and the vias connected to the first electrode.

[0160] Next, as shown in Figure 20K, the oxide layer 83 is processed to match the shape of the M2 wiring layer WL2.

[0161] Next, as shown in Figure 20L, a conductive layer 77, which is the material for the M2 wiring layer WL2, is formed on the oxide layer 83.

[0162] Next, as shown in Figure 20M, the conductive layer 77 is thinned and flattened to form the M2 wiring layer WL2.

[0163] In the third manufacturing process shown in Figures 20A to 20M, if a capacitor C with an MIM structure is not formed, the four steps shown in Figures 20C to 20F can be omitted. In other words, by adding just four steps to the manufacturing process in which capacitor C is not formed, a capacitor C with an MIM structure having a flange portion Cb can be formed. Furthermore, since the step in Figure 20F also serves as the step for the M1 wiring layer WL1, by including the step in Figure 20F, a part of the step for the M1 wiring layer WL1 can be omitted.

[0164] <Examples of application to mobile devices> The technology disclosed herein (this technology) can be applied to various products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0165] Figure 21 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0166] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 21, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0167] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0168] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0169] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0170] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0171] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0172] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0173] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0174] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0175] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 21, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0176] Figure 22 shows an example of the installation position of the imaging unit 12031.

[0177] In Figure 22, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0178] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0179] Figure 22 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0180] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0181] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0182] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0183] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0184] The above describes an example of a vehicle control system to which the technology described herein may be applied. The technology described herein may be applied to the imaging unit 12031, etc., among the configurations described above.

[0185] Furthermore, this technology can take the following configurations: (1) A photodetector comprising: a pixel having a photoelectric conversion unit that performs photoelectric conversion of incident light and a floating diffusion region that holds the photoelectrically converted charge; a pixel circuit that generates a pixel signal corresponding to the charge photoelectrically converted by the pixel; a first conductive member extending in the depth direction of a substrate on which at least one of the pixel or the pixel circuit is arranged; and a capacitor whose position and length in the depth direction of the substrate are the same as that of the first conductive member, wherein the capacitor comprises: a first electrode layer arranged in the depth direction of the substrate; an insulating layer arranged in the depth direction of the substrate and laminated on the first electrode layer; and a second electrode layer arranged in the depth direction of the substrate and laminated on the insulating layer, wherein the diameter of the capacitor is larger than the diameter of the first conductive member. (2) The photodetector according to (1), comprising a diffusion layer and a wiring layer arranged at mutually different depth positions of the substrate, wherein the first conductive member and the capacitor are each connected to the diffusion layer and the wiring layer. (3) The photodetector according to (1), further comprising a first diffusion layer and a second diffusion layer arranged at different depth positions on the substrate, wherein the first conductive member and the capacitor are each connected to the first diffusion layer and the second diffusion layer. (4) The photodetector according to (1), further comprising a first wiring layer and a second wiring layer arranged on the substrate, wherein the first conductive member and the capacitor are each connected to the first wiring layer and the second wiring layer. (5) The photodetector according to (4), wherein the first wiring layer connected to the first electrode layer of the capacitor and the second wiring layer connected to the second electrode layer of the capacitor are arranged on one end side of the capacitor extending in the depth direction of the substrate. (6) The photodetector according to (5), wherein the first wiring layer and the second wiring layer are arranged at the same depth position or at different depth positions on the substrate. (7) The photodetector according to (5) or (6), wherein one of the first wiring layer or the second wiring layer is in contact with the first electrode layer or the second electrode layer, and the other of the first wiring layer or the second wiring layer is connected to the first electrode layer or the second electrode layer via a second conductive member extending in the depth direction of the substrate.(8) The photodetector according to (5) or (6), wherein one of the first electrode layer or the second electrode layer is connected to one of the first wiring layer or the second wiring layer, and the other of the first electrode layer or the second electrode layer is connected to the other of the first wiring layer or the second wiring layer via a diffusion layer. (9) The photodetector according to any one of (1) to (8), comprising a first layer on which the pixels are arranged, and a second layer stacked on the first layer on which at least a portion of the pixel circuit is arranged, wherein the first conductive member and the capacitor are arranged in the first layer or the second layer. (10) The photodetector according to (9), wherein the first layer and the second layer are arranged at different heights on the same substrate. (11) The photodetector according to (9), wherein the first layer and the second layer are arranged on different substrates. (12) The photodetector according to any one of (9) to (11), wherein the first layer comprises a transfer transistor that transfers the charge photoelectrically converted in the photoelectric conversion unit to the floating diffusion region, and a first wiring layer located closer to the second layer than the location of the transfer transistor and the floating diffusion region, and the second layer comprises a second wiring layer located further from the first layer than the location of the pixel circuit, and the first conductive member and the capacitor are each connected to the first wiring layer and the second wiring layer. (13) The photodetector according to any one of (1) to (8), comprising a first layer on which the pixels are arranged, and a second layer stacked on the first layer on which at least a part of the pixel circuit is arranged, wherein the first layer or the second layer comprises a first wiring layer and a second wiring layer located at different depths from each other, and the first conductive member and the capacitor are each connected to the first wiring layer and the second wiring layer. (14) The photodetector according to any one of (1) to (13), further comprising a dielectric layer disposed so as to cover at least a portion of the first electrode layer, the insulating layer, or the second electrode layer on the upper surface of the capacitor.(15) A photodetector according to any one of (1) to (14), comprising: (15) one or more wiring layers connected to the first conductive member and the capacitor; and a barrier metal film covering the outer surface of at least one of the first conductive member, the capacitor, or the wiring layer. (16) A photodetector according to any one of (1) to (15), comprising: a transistor having a gate and a diffusion layer, wherein one end of the first conductive member is connected to the diffusion layer, and the first electrode layer or the second electrode layer of the capacitor is connected to the gate. (17) A photodetector according to any one of (1) to (16), wherein the first conductive member and at least one of the first electrode layer or the second electrode layer are made of the same conductive material. (18) A photodetector according to (17), wherein the conductive material includes copper (Cu), tungsten (W), polysilicon implanted with impurity ions, amorphous silicon implanted with impurity ions, N-type silicon, P-type silicon, transparent electrode material, titanium (Ti), or titanium nitride (TiN). (19) The photodetector according to any one of (1) to (18), wherein the capacitor has a filling portion located inside a trench placed on the substrate and a flange portion located outside the upper end of the trench, and both the filling portion and the flange portion have a laminated structure including the first electrode layer, the insulating layer and the second electrode layer. (20) The photodetector according to any one of (1) to (19), wherein the pixel circuit has a conversion efficiency switching transistor, and the capacitor holds the charge photoelectrically converted in the photoelectric conversion unit when the conversion efficiency switching transistor is ON.

[0186] The aspects of this disclosure are not limited to the individual embodiments described above, but include various modifications that a person skilled in the art could conceive, and the effects of this disclosure are not limited to those described above. In other words, various additions, modifications, and partial deletions are possible, as long as they do not depart from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents.

[0187] 1. Photodetector, 2. Pixel array section, 3. Peripheral circuit section, 4. Pixel, 5. Row selection section, 6. Constant current source section, 8. Horizontal transfer scanning section, 9. Signal processing section, 10. Timing control section, 11. Reference signal generation section, 20. Pixel circuit, 30. Electronic equipment, 31. Imaging lens, 32. Image processing section, 33. Recording section, 34. Control section, 41. Pixel separation area, 42. Light shielding member, 43. Insulating layer, 44. Fixed charge film, 45. N-type silicon layer, 46. P-type diffusion area, 47. Via, 48. Well contact area, 51. First electrode layer, 52. Insulating layer, 53. Second electrode layer, 54. Via, 55. Insulating layer, 56. Dielectric layer, 57. Barrier metal layer, 58. Diffusion layer, 61. Via, 63. Diffusion layer, 64. Via, 70. Substrate, 71. Oxide layer, 72. Trench, 73. Oxide layer, 74. Conductive layer, 75; Oxide layer, 76; Trench, 77; Conductive layer, 81; Oxide layer, 82; Oxide layer, 83; Oxide layer, 84; Trench

Claims

1. A photodetector comprising: a photoelectric conversion unit that performs photoelectric conversion of incident light and a pixel having a floating diffusion region that holds the photoelectrically converted charge; a pixel circuit that generates a pixel signal corresponding to the charge photoelectrically converted by the pixel; a first conductive member extending in the depth direction of a substrate on which at least one of the pixel or the pixel circuit is arranged; and a capacitor whose position and length in the depth direction of the substrate are the same as that of the first conductive member, wherein the capacitor comprises: a first electrode layer arranged in the depth direction of the substrate; an insulating layer arranged in the depth direction of the substrate and laminated on the first electrode layer; and a second electrode layer arranged in the depth direction of the substrate and laminated on the insulating layer, wherein the diameter of the capacitor is larger than the diameter of the first conductive member.

2. The photodetector according to claim 1, further comprising a diffusion layer and a wiring layer arranged at different depth positions on the substrate, wherein the first conductive member and the capacitor are each connected to the diffusion layer and the wiring layer.

3. The photodetector according to claim 1, comprising a first diffusion layer and a second diffusion layer arranged at different depth positions on the substrate, wherein the first conductive member and the capacitor are each connected to the first diffusion layer and the second diffusion layer, respectively.

4. The photodetector according to claim 1, having a first wiring layer and a second wiring layer disposed on the substrate, wherein the first conductive member and the capacitor are each connected to the first wiring layer and the second wiring layer, respectively.

5. The photodetector according to claim 4, wherein the first wiring layer connected to the first electrode layer of the capacitor and the second wiring layer connected to the second electrode layer of the capacitor are arranged on one end side of the capacitor extending in the depth direction of the substrate.

6. The photodetector according to claim 5, wherein the first wiring layer and the second wiring layer are arranged at the same depth position or at different depth positions on the substrate.

7. The photodetector according to claim 5, wherein one of the first wiring layer or the second wiring layer is in contact with the first electrode layer or the second electrode layer, and the other of the first wiring layer or the second wiring layer is connected to the first electrode layer or the second electrode layer via a second conductive member extending in the depth direction of the substrate.

8. The photodetector according to claim 5, wherein one of the first electrode layer or the second electrode layer is connected to one of the first wiring layer or the second wiring layer, and the other of the first electrode layer or the second electrode layer is connected to the other of the first wiring layer or the second wiring layer via a diffusion layer.

9. The photodetector according to claim 1, comprising: a first layer on which the pixels are arranged; and a second layer stacked on the first layer on which at least a portion of the pixel circuit is arranged, wherein the first conductive member and the capacitor are arranged in the first layer or the second layer.

10. The photodetector according to claim 9, wherein the first layer and the second layer are arranged at different heights on the same substrate.

11. The photodetector according to claim 9, wherein the first layer and the second layer are arranged on different substrates.

12. The photodetector according to claim 9, wherein the first layer comprises a transfer transistor that transfers the charge photoelectrically converted in the photoelectric conversion unit to the floating diffusion region, and a first wiring layer located closer to the second layer than the location of the transfer transistor and the floating diffusion region, and the second layer comprises a second wiring layer located further from the first layer than the location of the pixel circuit, and the first conductive member and the capacitor are connected to the first wiring layer and the second wiring layer, respectively.

13. The photodetector according to claim 1, comprising: a first layer on which the pixels are arranged; and a second layer stacked on the first layer on which at least a portion of the pixel circuit is arranged, wherein the first layer or the second layer has a first wiring layer and a second wiring layer arranged at different depth positions from each other, and the first conductive member and the capacitor are each connected to the first wiring layer and the second wiring layer, respectively.

14. The photodetector according to claim 1, further comprising a dielectric layer disposed so as to cover at least a portion of the first electrode layer, the insulating layer, or the second electrode layer on the upper surface of the capacitor.

15. The photodetector according to claim 1, comprising: one or more wiring layers connected to the first conductive member and the capacitor; and a barrier metal film covering the outer surface of at least one of the first conductive member, the capacitor, or the wiring layers.

16. The photodetector according to claim 1, comprising a transistor having a gate and a diffusion layer, wherein one end of the first conductive member is connected to the diffusion layer, and the first electrode layer or the second electrode layer of the capacitor is connected to the gate.

17. The photodetector according to claim 1, wherein the first conductive member and at least one of the first electrode layer or the second electrode layer are made of the same conductive material.

18. The photodetector according to claim 17, wherein the conductive material includes copper (Cu), tungsten (W), polysilicon implanted with impurity ions, amorphous silicon implanted with impurity ions, N-type silicon, P-type silicon, transparent electrode material, titanium (Ti), or titanium nitride (TiN).

19. The photodetector according to claim 1, wherein the capacitor has a filling portion disposed inside a trench disposed on the substrate and a flange portion disposed outside from the upper end of the trench, and both the filling portion and the flange portion have a laminated structure including the first electrode layer, the insulating layer and the second electrode layer.

20. The photodetector according to claim 1, wherein the pixel circuit has a conversion efficiency switching transistor, and the capacitor holds the charge photoelectrically converted in the photoelectric conversion unit when the conversion efficiency switching transistor is ON.

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