Light detection device

Abstract

A first light detection device according to an embodiment of the present disclosure comprises: a first semiconductor layer in which formed are a plurality of sensor pixels that perform photoelectric conversion and a separation part that separates the adjacent plurality of sensor pixels from each other; a second semiconductor layer that is laminated on the first semiconductor layer and has a first surface facing the first semiconductor layer, a second surface on the side opposite from the first surface, and an impurity diffusion region extending between the first surface and the second surface; and a first connection part that is electrically connected to the impurity diffusion region from the first surface side of the second semiconductor layer, extends between the first semiconductor layer and the second semiconductor layer, and is positioned on the separation part when observed in plan view.

Description

Photodetector device

[0001] The present disclosure relates to a photodetector device in which a plurality of semiconductor layers are stacked.

[0002] For example, Patent Document 1 discloses an imaging device in which a first semiconductor substrate and a second semiconductor substrate stacked on each other are electrically connected by a connection portion that penetrates an insulating layer provided therebetween and connects the first semiconductor substrate and the back surface of the second semiconductor substrate.

[0003] Japanese Patent Laid-Open No.2022-147587

[0004] By the way, improvement of characteristics is required for photodetector devices.

[0005] It is desirable to provide a photodetector device capable of improving characteristics.

[0006] A first photodetector device according to an embodiment of the present disclosure includes: a first semiconductor layer in which a plurality of sensor pixels that perform photoelectric conversion and a separation portion that separates adjacent plurality of sensor pixels from each other are formed; a second semiconductor layer stacked on the first semiconductor layer, the second semiconductor layer having a first surface facing the first semiconductor layer, a second surface opposite to the first surface, and an impurity diffusion region extending between the first surface and the second surface; and a first connection portion electrically connected to the impurity diffusion region from the first surface side of the second semiconductor layer, extending between the first semiconductor layer and the second semiconductor layer, and positioned on the separation portion in a plan view.

[0007] In the first photodetector device according to an embodiment of the present disclosure, a connection portion (first connection portion) extending between the first semiconductor layer and the second semiconductor layer stacked on each other is provided. The first semiconductor layer is formed with a plurality of sensor pixels that perform photoelectric conversion and a separation portion that separates adjacent plurality of sensor pixels from each other, and the second semiconductor layer has an impurity diffusion region extending between the first surface and the second surface. The first connection portion is electrically connected to the impurity diffusion region from the side of the surface (first surface) facing the first semiconductor layer with respect to the second semiconductor layer, and is positioned on the separation portion in a plan view. This reduces capacitive coupling between adjacent sensor pixels.

[0008] A second photodetector according to one embodiment of the present disclosure comprises: a first semiconductor layer on which a plurality of sensor pixels that perform photoelectric conversion and a third transistor that constitutes a pixel circuit that outputs a pixel signal based on the charge output from the sensor pixels are formed; a semiconductor active layer laminated above the first semiconductor layer so as to overlap with at least a portion of the source or drain of the third transistor in a plan view; a third connection portion extending between the first semiconductor layer and the semiconductor active layer and electrically connecting the semiconductor active layer and the source or drain of the third transistor that overlaps with the semiconductor active layer; and a first laminate in which the semiconductor active layer, a first insulating film, and a first electrode film are laminated in this order.

[0009] In a second photodetector according to one embodiment of the present disclosure, a first laminate is provided above a first semiconductor layer, in which a semiconductor active layer, a first insulating film, and a first electrode film are stacked in that order. The first semiconductor layer has a plurality of sensor pixels that perform photoelectric conversion, and a transistor (third transistor) that constitutes a pixel circuit that outputs a pixel signal based on the charge output from the sensor pixels. In a plan view, the first laminate is arranged to overlap at least a portion of the source or drain of the third transistor, and is electrically connected to the source or drain of the third transistor via a connection (third connection). This adds capacitance to the pixel circuit.

[0010] A third photodetector according to one embodiment of the present disclosure comprises: a first semiconductor layer on which a plurality of sensor pixels for photoelectric conversion are formed; a second semiconductor layer laminated on the first semiconductor layer and having a first surface facing the first semiconductor layer, a second surface opposite to the first surface, and a first impurity diffusion region extending between the first surface and the second surface; a sixth transistor provided on the first surface side of the second semiconductor layer and having the first impurity diffusion region as its source and drain; and an electrode portion provided on the second surface side of the second semiconductor layer and electrically connected to at least one of the source and drain of the sixth transistor.

[0011] In a third photodetector according to one embodiment of the present disclosure, an electrode portion is provided that is electrically connected to at least one of the source and drain of a transistor (sixth transistor) which is stacked on a first semiconductor layer on which a plurality of sensor pixels that perform photoelectric conversion are formed, and which is located on the side of the second semiconductor layer opposite to the surface facing the first semiconductor layer. This adds capacitance to the sixth transistor.

[0012] Figure 1 is a block diagram showing an example of the functional configuration of a photodetector according to a first embodiment of the present disclosure. Figure 2 is a schematic plan view showing the general configuration of the photodetector shown in Figure 1. Figure 3 is a schematic diagram showing the cross-sectional configuration along the line A-A' shown in Figure 2. Figure 4 is an equivalent circuit diagram of the pixel circuit shown in Figure 1. Figure 5 is a schematic cross-sectional view showing an example of the configuration of the photodetector shown in Figure 3. Figure 6 is a schematic plan view showing a specific example of the configuration of the photodetector shown in Figure 3. Figure 7 is a schematic cross-sectional view corresponding to the line I-I' shown in Figure 6. Figure 8 is an enlarged view of the connection portion between the connection portion shown in Figure 7 and the contact region of the semiconductor layer. Figure 9A is a schematic cross-sectional view illustrating an example of a method for manufacturing the photodetector shown in Figure 6. Figure 9B is a schematic cross-sectional view showing the process following Figure 9A. Figure 9C is a schematic cross-sectional view showing the process following Figure 9B. Figure 9D is a schematic cross-sectional view showing the process following Figure 9C. Figure 9E is a schematic cross-sectional view showing the process following Figure 9D. Figure 9F is a schematic cross-sectional diagram showing the process following Figure 9E. Figure 9G is a schematic cross-sectional diagram showing the process following Figure 9F. Figure 9H is a schematic cross-sectional diagram showing the process following Figure 9G. Figure 10A is a schematic cross-sectional diagram showing an example of a specific configuration of a photodetector according to Modification 1 of the present disclosure. Figure 10B is a schematic cross-sectional diagram showing another example of a specific configuration of a photodetector according to Modification 1 of the present disclosure. Figure 11 is a schematic plan view showing an example of a specific configuration of a photodetector according to Modification 2 of the present disclosure. Figure 12 is a schematic cross-sectional diagram corresponding to the line II-II' shown in Figure 11. Figure 13 is a schematic plan view showing an example of a specific configuration of a photodetector according to Modification 3 of the present disclosure. Figure 14 is a schematic cross-sectional diagram corresponding to the line III-III' shown in Figure 13. Figure 15 is a schematic cross-sectional diagram showing the cross-sectional configuration of a photodetector according to a second embodiment of the present disclosure. Figure 16 is an equivalent circuit diagram of the pixel circuit of the photodetector shown in Figure 15. Figure 17 is a schematic cross-sectional diagram showing an example of a specific configuration of the photodetector shown in Figure 15. Figure 18 is a schematic plan view showing an example of the gate electrode structure shown in Figure 17. Figure 19A is a schematic cross-sectional diagram illustrating an example of a method for manufacturing the photodetector shown in Figure 17. Figure 19B is a schematic cross-sectional diagram showing the process following Figure 19A. Figure 19C is a schematic cross-sectional diagram showing the process following Figure 19B. Figure 19D is a schematic cross-sectional diagram showing the process following Figure 19C.Figure 19E is a schematic cross-sectional diagram showing the process following Figure 19D. Figure 19F is a schematic cross-sectional diagram showing the process following Figure 19E. Figure 19G is a schematic cross-sectional diagram showing the process following Figure 19F. Figure 20 is a schematic cross-sectional diagram showing an example of a specific configuration of a photodetector according to Modification 4 of this disclosure. Figure 21 is a schematic cross-sectional diagram showing another example of a specific configuration of a photodetector according to Modification 4 of this disclosure. Figure 22A is a schematic cross-sectional diagram illustrating an example of a method for manufacturing the photodetector shown in Figure 17. Figure 22B is a schematic cross-sectional diagram showing the process following Figure 22A. Figure 22C is a schematic cross-sectional diagram showing the process following Figure 22B. Figure 22D is a schematic cross-sectional diagram showing the process following Figure 22C. Figure 22E is a schematic cross-sectional diagram showing the process following Figure 22D. Figure 23 is a schematic cross-sectional diagram showing an example of a specific configuration of a photodetector according to Modification 5 of this disclosure. Figure 24 is a schematic cross-sectional diagram showing another example of a specific configuration of a photodetector according to Modification 5 of this disclosure. Figure 25 is a schematic diagram showing a cross-sectional configuration of a photodetector according to a third embodiment of the present disclosure. Figure 26 is a schematic plan view showing an example of a specific configuration of the photodetector shown in Figure 25. Figure 27 is a schematic cross-sectional view corresponding to the IV-IV' line shown in Figure 26. Figure 28A is a schematic cross-sectional view illustrating an example of a method for manufacturing the photodetector shown in Figure 25. Figure 28B is a schematic cross-sectional view showing the process following Figure 28A. Figure 28C is a schematic cross-sectional view showing the process following Figure 28B. Figure 28D is a schematic cross-sectional view showing the process following Figure 28C. Figure 28E is a schematic cross-sectional view showing the process following Figure 28D. Figure 28F is a schematic cross-sectional view showing the process following Figure 28E. Figure 28G is a schematic cross-sectional view showing the process following Figure 28F. Figure 28H is a schematic cross-sectional view showing the process following Figure 28G. Figure 28I is a schematic cross-sectional view showing the process following Figure 28H. Figure 28J is a schematic cross-sectional diagram showing the process following Figure 28I. Figure 29 is a schematic cross-sectional diagram showing an example of a specific configuration of a photodetector according to Modification 6 of the present disclosure. Figure 30 is a schematic cross-sectional diagram showing an example of a specific configuration of a photodetector according to Modification 7 of the present disclosure. Figure 31 is a schematic cross-sectional diagram showing an example of a specific configuration of a photodetector according to Modification 8 of the present disclosure. Figure 32A is a schematic cross-sectional diagram illustrating an example of a method for manufacturing the electrode shown in Figure 25. Figure 32B is a schematic cross-sectional diagram showing the process following Figure 32A.Figure 32C is a schematic cross-sectional view showing the process following Figure 32B. Figure 32D is a schematic cross-sectional view showing the process following Figure 32C. Figure 33 is a schematic plan view showing an example of a specific configuration of a photodetector according to Modification 9 of this disclosure. Figure 34 is a schematic cross-sectional view corresponding to the line V-V' shown in Figure 33. Figure 35 is a block diagram showing an example of the configuration of an electronic device having the photodetector shown in Figure 1. Figure 36A is a schematic diagram showing an example of the overall configuration of a photodetector system using the photodetector shown in Figure 1, etc. Figure 36B is a diagram showing an example of the circuit configuration of the photodetector system shown in Figure 36A. Figure 37 is a diagram showing an example of the schematic configuration of an endoscopic surgery system. Figure 38 is a block diagram showing an example of the functional configuration of a camera head and a CCU. Figure 39 is a block diagram showing an example of the schematic configuration of a vehicle control system. Figure 40 is an explanatory diagram showing an example of the installation position of an external information detection unit and an imaging unit. Figure 41 is a schematic cross-sectional view showing an example of a specific configuration of a photodetector according to Modification 10 of this disclosure. Figure 42 is a schematic cross-sectional view showing an example of a specific configuration of a photodetector according to Modification 11 of the present disclosure. Figure 43 is a schematic cross-sectional view showing an example of a specific configuration of a photodetector according to Modification 12 of the present disclosure.

[0013] The embodiments of this disclosure will be described in detail below with reference to the drawings. The following description is one specific example of this disclosure, and this disclosure is not limited to the following embodiments. Furthermore, this disclosure is not limited to the arrangement, dimensions, dimensional ratios, etc., of each component shown in each figure. The order of description is as follows: 1. First Embodiment (An example of a photodetector in which a connection portion to which a fixed potential is applied is extended between the semiconductor layers of the first substrate and the second substrate and is placed on the separation portion of the first substrate) 2. Modifications 2-1. Modification 1 (Another example of the configuration of the photodetector) 2-2. Modification 2 (Another example of the configuration of the photodetector) 2-3. Modification 3 (Another example of the configuration of the photodetector) 3. Second Embodiment (An example of a photodetector in which a capacitive element including an active region provided on the semiconductor layer of the second substrate is provided on a connection portion electrically connected to a transistor provided on the first substrate) 4. Modifications 4-1. Modification 4 (Another example of the configuration of the photodetector) 4-2. Modification 5 (Another example of the configuration of the photodetector) 4-3. Modification 10 (Another example of the configuration of the photodetector) 4-4. Modification 11 (Another example of the configuration of the photodetector) 4-5. Modification 12 (Another example of the configuration of the photodetector) 5. Third Embodiment (Example of a photodetector in which electrodes are arranged on the drain of a transistor provided on a second substrate) 6. Modification 2-1. Modification 6 (Another example of the configuration of the photodetector) 6-2. Modification 7 (Another example of the configuration of the photodetector) 6-3. Modification 8 (Another example of the configuration of the photodetector) 6-4. Modification 9 (Another example of the configuration of the photodetector) 7. Application Examples 8. Application Examples

[0014] <1. First Embodiment> The light detection device (light detection device 1) according to the first embodiment of the present disclosure is used, for example, as a CMOS (Complementary Metal Oxide Semiconductor) image sensor used in electronic devices such as digital still cameras and video cameras.

[0015] [Functional Configuration of the Light Detection Device] Figure 1 is a block diagram showing an example of the functional configuration of the light detection device 1.

[0016] The light detection device 1 in Figure 1 includes, for example, an input unit 510A, a row drive unit 520, a timing control unit 530, a pixel array unit 540, a column signal processing unit 550, an image signal processing unit 560, and an output unit 510B.

[0017] In the pixel array section 540, multiple pixels 541 are repeatedly arranged in an array. More specifically, a pixel sharing unit 539 containing multiple pixels 541 serves as the repeating unit, and these are repeatedly arranged in an array consisting of row and column directions. For convenience, in this specification, the row direction may be referred to as the H direction or X-axis direction, and the column direction perpendicular to the row direction may be referred to as the V direction or Y-axis direction. In the example in Figure 1, one pixel sharing unit 539 contains four pixels (pixels 541A to 541D). Each of the pixels 541A to 541D has a photodiode PD (illustrated in Figure 5, etc., described later). The pixel sharing unit 539 is a unit that shares one pixel circuit (pixel circuit 210 in Figure 4, described later). In other words, there is one pixel circuit (pixel circuit 210 described later) for every four pixels (pixels 541A to 541D). By operating this pixel circuit in a time-division multiplexing manner, the pixel signals of each of the pixels 541A to 541D are read out sequentially. The pixels 541A to 541D are arranged, for example, in a 2x2 grid. The pixel array section 540 is provided with the pixels 541A to 541D, as well as a plurality of row drive signal lines 542 and a plurality of vertical signal lines (column read lines) 543. The row drive signal lines 542 drive the pixels 541 included in each of the plurality of pixel sharing units 539 that are arranged in the row direction in the pixel array section 540. The row drive signal lines 542 drive each pixel of the pixel sharing unit 539 that is arranged in the row direction. As will be explained in detail later with reference to Figure 4, the pixel sharing unit 539 is provided with a plurality of transistors. To drive each of these plurality of transistors, a plurality of row drive signal lines 542 are connected to one pixel sharing unit 539. The pixel sharing unit 539 is connected to the vertical signal lines (column read lines) 543. Pixel signals are read out from each of the pixels 541A to 541D included in the pixel sharing unit 539 via vertical signal lines (column readout lines) 543.

[0018] The row drive unit 520 includes, for example, a row address control unit that determines the position of a row for driving pixels, in other words, a row decoder unit, and a row drive circuit unit that generates signals for driving pixels 541A to 541D.

[0019] The timing control unit 530 supplies timing control signals to the row drive unit 520 and the column signal processing unit 550 based on the reference clock signal and timing control signal input to the device.

[0020] The column signal processing unit 550 includes, for example, a load circuit section connected to the vertical signal line 543 and forming a source follower circuit with the pixels 541A to 541D (pixel sharing unit 539). The column signal processing unit 550 may also have an amplification circuit section that amplifies the signal read from the pixel sharing unit 539 via the vertical signal line 543. The column signal processing unit 550 may also have a noise processing unit. In the noise processing unit, for example, the noise level of the system is removed from the signal read from the pixel sharing unit 539 as a result of photoelectric conversion.

[0021] The column signal processing unit 550 includes, for example, an analog-to-digital converter (ADC). In the analog-to-digital converter, the signal read from the pixel sharing unit 539 or the noise-processed analog signal is converted into a digital signal. The ADC includes, for example, a comparator unit and a counter unit. In the comparator unit, the analog signal to be converted is compared with a reference signal to be compared with it. In the counter unit, the time until the comparison result in the comparator unit is reversed is measured. The column signal processing unit 550 may also include a horizontal scanning circuit unit that controls scanning of the readout column.

[0022] The image signal processing unit 560 is a circuit that performs various signal processing on the data obtained as a result of photoelectric conversion, in other words, the data obtained as a result of the imaging operation in the photodetector 1. The image signal processing unit 560 includes, for example, an image signal processing circuit unit and a data holding unit. The image signal processing unit 560 may also include a processor unit.

[0023] One example of signal processing performed in the image signal processing unit 560 is tone curve correction processing, which increases the tonal range of AD-converted imaging data if it is data of a dark subject, and decreases the tonal range if it is data of a bright subject. In this case, it is desirable to store in advance the characteristic data of the tone curve on which the tonal range of the imaging data will be corrected in the data storage unit of the image signal processing unit 560.

[0024] The input unit 510A is for inputting, for example, the above-mentioned reference clock signal, timing control signal, and characteristic data from outside the device to the light detection device 1. The timing control signal is, for example, a vertical synchronization signal and a horizontal synchronization signal. The characteristic data is, for example, stored in the data holding unit of the image signal processing unit 560. The input unit 510A includes, for example, an input terminal 511, an input circuit unit 512, an input amplitude changing unit 513, an input data conversion circuit unit 514, and a power supply unit (not shown).

[0025] The input terminal 511 is an external terminal for inputting data. The input circuit section 512 is for taking the signal input to the input terminal 511 into the photodetector 1. The input amplitude changing section 513 changes the amplitude of the signal taken in by the input circuit section 512 to an amplitude that is easy to use inside the photodetector 1. The input data conversion circuit section 514 changes the order of the data sequence of the input data. The input data conversion circuit section 514 is configured, for example, by a serial-to-parallel conversion circuit. In this serial-to-parallel conversion circuit, the serial signal received as input data is converted into a parallel signal. Note that in the input section 510A, the input amplitude changing section 513 and the input data conversion circuit section 514 may be omitted. The power supply section supplies power set to various voltages required inside the photodetector 1, based on the power supply supplied to the photodetector 1 from the outside.

[0026] When the light detection device 1 is connected to an external memory device, the input unit 510A may be provided with a memory interface circuit for receiving data from the external memory device. The external memory device may be, for example, flash memory, SRAM, or DRAM.

[0027] The output unit 510B outputs image data to the outside of the device. This image data includes, for example, image data captured by the light detection device 1 and image data processed by the image signal processing unit 560. The output unit 510B includes, for example, an output data conversion circuit unit 515, an output amplitude changing unit 516, an output circuit unit 517, and an output terminal 518.

[0028] The output data conversion circuit 515 is configured, for example, by a parallel-to-serial conversion circuit, in which the parallel signal used inside the photodetector 1 is converted into a serial signal. The output amplitude modification unit 516 modifies the amplitude of the signal used inside the photodetector 1. The signal with the modified amplitude is made easier to use by external devices connected outside the photodetector 1. The output circuit 517 is a circuit that outputs data from inside the photodetector 1 to outside the device, and the output circuit 517 drives the wiring outside the photodetector 1 connected to the output terminal 518. At the output terminal 518, data is output from the photodetector 1 to outside the device. In the output unit 510B, the output data conversion circuit 515 and the output amplitude modification unit 516 may be omitted.

[0029] When the light detection device 1 is connected to an external memory device, the output unit 510B may be provided with a memory interface circuit for outputting data to the external memory device. The external memory device may be, for example, flash memory, SRAM, or DRAM.

[0030] [Schematic Configuration of the Photodetector] Figures 2 and 3 show an example of the schematic configuration of the photodetector 1. The photodetector 1 comprises three substrates (first substrate 100, second substrate 200, and third substrate 300). Figure 2 schematically shows the planar configuration of each of the first substrate 100, second substrate 200, and third substrate 300, and Figure 3 schematically shows the cross-sectional configuration of the first substrate 100, second substrate 200, and third substrate 300 stacked on top of each other. Figure 3 corresponds to the cross-sectional configuration along the line A-A' shown in Figure 2. The photodetector 1 is a three-dimensional photodetector constructed by bonding together three substrates (first substrate 100, second substrate 200, and third substrate 300). The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. Here, the wiring contained in each of the first substrate 100, the second substrate 200, and the third substrate 300, along with the interlayer insulating film surrounding it, are conveniently referred to as the wiring layers (100T, 200T, 300T) provided on each substrate (first substrate 100, second substrate 200, and third substrate 300). The first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order, and are arranged in the order of semiconductor layer 100S, wiring layer 100T, semiconductor layer 200S, wiring layer 200T, wiring layer 300T, and semiconductor layer 300S along the stacking direction. The specific configurations of the first substrate 100, the second substrate 200, and the third substrate 300 will be described later. The arrows shown in Figure 3 indicate the direction of incidence of light L to the photodetector 1. In this specification, for convenience, the side on which light is incident in the photodetector 1 may be referred to as "bottom," "lower side," or "downward," and the side opposite to the side on which light is incident may be referred to as "top," "upper side," or "upward" in the following cross-sectional diagrams. Also, in this specification, for convenience, with respect to a substrate having a semiconductor layer and a wiring layer, the side with the wiring layer may be referred to as the front surface and the side with the semiconductor layer as the back surface. However, the description in this specification is not limited to the above terminology. The photodetector 1 is, for example, a back-illuminated photodetector in which light is incident from the back surface of a first substrate 100 having a photodiode.

[0031] The pixel array section 540 and the pixel sharing unit 539 included in the pixel array section 540 are both constructed using both the first substrate 100 and the second substrate 200. The first substrate 100 is provided with a plurality of pixels 541A to 541D of the pixel sharing unit 539. Each of these pixels 541 has a photodiode (photodiode PD described later) and a transfer transistor (transfer transistor TR described later). The second substrate 200 is provided with a pixel circuit (pixel circuit 210 described later) of the pixel sharing unit 539. The pixel circuit reads out the pixel signal transferred from the photodiode of each of the pixels 541A to 541D via the transfer transistor, or resets the photodiode. In addition to such a pixel circuit, the second substrate 200 has a plurality of row drive signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction. The second substrate 200 further has power lines 544 (power lines VDD, etc., described later) extending in the row direction. The third substrate 300 has, for example, an input unit 510A, a row drive unit 520, a timing control unit 530, a column signal processing unit 550, an image signal processing unit 560, and an output unit 510B. The row drive unit 520 is provided, for example, in a region that partially overlaps the pixel array unit 540 in the stacking direction of the first substrate 100, the second substrate 200, and the third substrate 300 (hereinafter simply referred to as the stacking direction). More specifically, the row drive unit 520 is provided in a region that overlaps near the H-direction end of the pixel array unit 540 in the stacking direction. The column signal processing unit 550 is provided, for example, in a region that partially overlaps the pixel array unit 540 in the stacking direction. More specifically, the column signal processing unit 550 is located in a region that overlaps with the vicinity of the V-direction end of the pixel array section 540 in the stacking direction. Although not shown in the figures, the input section 510A and the output section 510B may be located in a part other than the third substrate 300, for example, on the second substrate 200. Alternatively, the input section 510A and the output section 510B may be located on the back surface (light incident surface) of the first substrate 100. The pixel circuit located on the second substrate 200 may also be referred to as a pixel transistor circuit, a group of pixel transistors, a pixel transistor, a pixel readout circuit, or a readout circuit.In this specification, the term "pixel circuit" is used.

[0032] The first substrate 100 and the second substrate 200 are electrically connected, for example, by through electrodes (through electrodes 252, 253 in Figure 5, described later). The second substrate 200 and the third substrate 300 are electrically connected, for example, by contact portions 201, 202, 301, 302. Contact portions 201, 202 are provided on the second substrate 200, and contact portions 301, 302 are provided on the third substrate 300. Contact portion 201 of the second substrate 200 is in contact with contact portion 301 of the third substrate 300, and contact portion 202 of the second substrate 200 is in contact with contact portion 302 of the third substrate 300. The second substrate 200 has a contact region 201R provided with a plurality of contact portions 201, and a contact region 202R provided with a plurality of contact portions 202. The third substrate 300 has a contact region 301R provided with a plurality of contact portions 301 and a contact region 302R provided with a plurality of contact portions 302. The contact regions 201R and 301R are provided between the pixel array portion 540 and the row drive portion 520 in the stacking direction, as shown in Figure 3, for example. In other words, the contact regions 201R and 301R are provided in the region where the row drive portion 520 (third substrate 300) and the pixel array portion 540 (second substrate 200) overlap in the stacking direction, or in a nearby region. The contact regions 201R and 301R are provided, for example, at the ends in the H direction of such a region. In the third substrate 300, for example, the contact region 301R is provided at a position that overlaps with a part of the row drive portion 520, specifically the end of the row drive portion 520 in the H direction. The contact sections 201 and 301 connect, for example, the row drive unit 520 provided on the third substrate 300 to the row drive signal line 542 provided on the second substrate 200. The contact sections 201 and 301 may also connect, for example, the input unit 510A provided on the third substrate 300 to the power line 544 and the reference potential line (for example, ground GND). The contact regions 202R and 302R are provided between the pixel array unit 540 and the column signal processing unit 550 in the stacking direction.In other words, the contact areas 202R and 302R are provided, for example, in the region where the column signal processing unit 550 (third substrate 300) and the pixel array unit 540 (second substrate 200) overlap in the stacking direction, or in a nearby region. The contact areas 202R and 302R are located, for example, at the V-direction end of such a region. On the third substrate 300, for example, the contact area 301R is provided at a position overlapping with a part of the column signal processing unit 550, specifically the V-direction end of the column signal processing unit 550. The contact areas 202 and 302 are for connecting, for example, the pixel signals (signals corresponding to the amount of charge generated as a result of photoelectric conversion by a photodiode) output from each of the multiple pixel sharing units 539 of the pixel array unit 540 to the column signal processing unit 550 provided on the third substrate 300. The pixel signals are sent from the second substrate 200 to the third substrate 300.

[0033] Figure 3 is an example of a cross-sectional view of the photodetector 1, as described above. The first substrate 100, the second substrate 200, and the third substrate 300 are electrically connected via wiring layers 100T, 200T, and 300T. For example, the photodetector 1 has an electrical connection section that electrically connects the second substrate 200 and the third substrate 300. Specifically, contact sections 201, 202, 301, and 302 are formed with electrodes made of a conductive material. The conductive material is made of a metallic material such as copper (Cu), aluminum (Al), or gold (Au). The contact regions 201R, 202R, 301R, and 302R electrically connect the second substrate 200 and the third substrate 300 by directly joining wirings formed as electrodes, for example, enabling signal input and / or output between the second substrate 200 and the third substrate 300.

[0034] The electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 can be provided at any desired location. For example, as described in Figure 3 as contact regions 201R, 202R, 301R, and 302R, it may be provided in a region that overlaps with the pixel array portion 540 in the stacking direction. Alternatively, the electrical connection portion may be provided in a region that does not overlap with the pixel array portion 540 in the stacking direction. Specifically, it may be provided in a region that overlaps with the peripheral portion located outside the pixel array portion 540 in the stacking direction.

[0035] The first substrate 100 and the second substrate 200 are provided with, for example, connection holes H1 and H2. The connection holes H1 and H2 penetrate the first substrate 100 and the second substrate 200 (Figure 3). The connection holes H1 and H2 are located outside the pixel array section 540 (or the portion overlapping the pixel array section 540) (Figure 2). For example, connection hole H1 is located outside the pixel array section 540 in the H direction, and connection hole H2 is located outside the pixel array section 540 in the V direction. For example, connection hole H1 reaches the input section 510A provided on the third substrate 300, and connection hole H2 reaches the output section 510B provided on the third substrate 300. The connection holes H1 and H2 may be cavities, or they may contain conductive material in at least part of them. For example, there is a configuration in which bonding wires are connected to electrodes formed as the input section 510A and / or the output section 510B. Alternatively, there is a configuration in which electrodes formed as input section 510A and / or output section 510B are connected to conductive material provided in connection holes H1 and H2. The conductive material provided in connection holes H1 and H2 may be embedded in part or all of connection holes H1 and H2, or the conductive material may be formed on the sides of connection holes H1 and H2.

[0036] In Figure 3, the input section 510A and output section 510B are provided on the third board 300, but the design is not limited to this. For example, the input section 510A and / or output section 510B can be provided on the second board 200 by sending the signals from the third board 300 to the second board 200 via wiring layers 200T and 300T. Similarly, the input section 510A and / or output section 510B can be provided on the first board 100 by sending the signals from the second board 200 to the first board 100 via wiring layers 100T and 200T.

[0037] Figure 4 is an equivalent circuit diagram showing an example of the configuration of a pixel sharing unit 539. The pixel sharing unit 539 includes a plurality of pixels 541 (in Figure 4, four pixels 541A to 541D are represented), a single pixel circuit 210 connected to these plurality of pixels 541, and a vertical signal line 543 connected to the pixel circuit 210. The pixel circuit 210 is composed of a plurality of transistors (pixel transistors 211). For example, the pixel transistor 211 includes four transistors, specifically an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG. As described above, the pixel sharing unit 539 operates the single pixel circuit 210 in a time-division manner, thereby sequentially outputting the pixel signals of each of the four pixels 541 (pixels 541A to 541D) included in the pixel sharing unit 539 to the vertical signal line 543. In a configuration where multiple pixels 541 are connected to a single pixel circuit 210, and the pixel signals of these multiple pixels 541 are output by the single pixel circuit 210 in a time-division manner, this is referred to as "multiple pixels 541 sharing a single pixel circuit 210."

[0038] Pixels 541A to 541D share common components. Hereafter, in order to distinguish the components of pixels 541A to 541D from one another, identification number 1 is added to the end of the code of the component of pixel 541A, identification number 2 to the end of the code of the component of pixel 541B, identification number 3 to the end of the code of the component of pixel 541C, and identification number 4 to the end of the code of the component of pixel 541D. If it is not necessary to distinguish the components of pixels 541A to 541D from one another, the identification number at the end of the code of the component of pixels 541A to 541D is omitted.

[0039] Each pixel 541A to 541D includes, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD electrically connected to the transfer transistor TR. In the photodiode PD (PD1 to PD4), the cathode is electrically connected to the source of the transfer transistor TR, and the anode is electrically connected to a reference potential line (e.g., ground GND). The photodiode PD converts incident light into photoelectric energy and generates a charge corresponding to the amount of light received. The transfer transistors TR (transfer transistors TR1 to TR4) are, for example, N-type MOS (Metal Oxide Semiconductor) transistors. The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to a drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 (see Figure 1) connected to one pixel sharing unit 539. The transfer transistor TR transfers the charge generated by the photodiode PD to the floating diffusion FD. The floating diffusion FD (floating diffusion FD1 to FD4) is an n-type diffusion layer region formed in a p-type semiconductor layer. The floating diffusion FD is a charge holding means that temporarily holds the charge transferred from the photodiode PD, and is also a charge-voltage conversion means that generates a voltage corresponding to the amount of charge due to the FD capacitance C of the floating diffusion FD.

[0040] The four floating diffusion FDs (floating diffusion FD1 to FD4) included in the pixel sharing unit 539 are electrically connected to each other, as well as to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to a drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 connected to the pixel sharing unit 539. The drain of the reset transistor RST is connected to the power line VDD, and the gate of the reset transistor RST is connected to a drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 connected to the pixel sharing unit 539. The gate of the amplification transistor AMP is connected to the floating diffusion FD, the drain of the amplification transistor AMP is connected to the power line VDD, and the source of the amplification transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to the vertical signal line 543, and the gate of the selection transistor SEL is connected to the drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 connected to one pixel sharing unit 539.

[0041] When the transfer transistor TR is turned ON, it transfers the charge from the photodiode PD to the floating diffusion FD. The gate (gate electrode 131) of the transfer transistor TR includes, for example, a so-called vertical electrode and extends from the surface of the semiconductor layer (semiconductor layer 100S in Figure 5) to a depth that reaches the photodiode PD, as shown in Figure 5 below. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned ON, it resets the potential of the floating diffusion FD to the potential of the power line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 210. The amplification transistor AMP generates a signal with a voltage corresponding to the level of charge held in the floating diffusion FD as the pixel signal. The amplification transistor AMP is connected to the vertical signal line 543 via the selection transistor SEL. This amplification transistor AMP forms a source follower in the column signal processing unit 550 together with the load circuit connected to the vertical signal line 543. When the selection transistor SEL is turned ON, the amplification transistor AMP outputs the voltage of the floating diffusion FD to the column signal processing unit 550 via the vertical signal line 543. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, N-type MOS transistors.

[0042] The FD conversion gain switching transistor FDG is used to change the gain of charge-to-voltage conversion in a floating diffusion FD. Generally, when shooting in dark places, the pixel signal is small. Based on Q=CV, when performing charge-to-voltage conversion, if the capacitance of the floating diffusion FD (FD capacitance C) is large, the voltage V when converted by the amplification transistor AMP will be small. On the other hand, in bright places, the pixel signal is large, so if the FD capacitance C is not large enough, the floating diffusion FD will not be able to accept the charge of the photodiode PD. Furthermore, the FD capacitance C needs to be large so that the voltage V when converted by the amplification transistor AMP does not become too large (in other words, to keep it small). Considering these points, when the FD conversion gain switching transistor FDG is turned on, the gate capacitance of the FD conversion gain switching transistor FDG increases, so the overall FD capacitance C becomes large. On the other hand, when the FD conversion gain switching transistor FDG is turned off, the overall FD capacitance C becomes small. In this way, by switching the FD conversion gain switching transistor FDG on and off, the FD capacitance C can be varied, and the conversion efficiency can be switched. The FD conversion gain switching transistor FDG is, for example, an N-type MOS transistor.

[0043] It is also possible to omit the FD conversion gain switching transistor FDG. In this case, for example, the pixel circuit 210 is composed of three transistors, for example, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. The pixel circuit 210 has at least one of the pixel transistors 211, such as an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG.

[0044] The selection transistor SEL may be provided between the power supply line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically connected to the row drive signal line 542. The source of the amplification transistor AMP (the output end of the pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. Although not shown in the drawings, the number of pixels 541 sharing one pixel circuit 210 may be other than four. For example, two or eight pixels 541 may share one pixel circuit 210.

[0045] [Cross-Sectional Configuration of Photodetection Device] FIG. 5 schematically illustrates an example of a cross-sectional configuration of the photodetection device 1. Note that FIG. 5 is schematically illustrated to facilitate understanding of the positional relationship of the constituent elements, and may differ from an actual cross-section. The photodetection device 1 is, for example, a back-illuminated photodetection device. In the photodetection device 1, three substrates, namely a first substrate 100, a second substrate 200, and a third substrate 300, are stacked in this order from the light incident side. The photodetection device 1 further includes an insulating film 181, a color filter 182, and an on-chip lens 401 on the light incident side (back side) of the first substrate 100. The on-chip lens 410 is provided, for example, for each of the plurality of pixels 541.

[0046] The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The semiconductor layer 100S has a pair of opposing surfaces (a front surface 100S1 and a back surface 100S2), and the wiring layer 100T is provided on the front surface 100S1 side. The back surface 100S2 of the semiconductor layer 100S serves as a light receiving surface, and an on-chip lens 410 is arranged for each pixel 541 on the back surface 100S2 side. An insulating film 181 and a color filter 182 are provided between the semiconductor layer 100S and the on-chip lens 410 in this order from the on-chip lens 410 side. The first substrate 100 is provided with a photodiode PD, a floating diffusion FD, a well contact WC, and a transfer transistor TR. The photodiode PD, the floating diffusion FD, the well contact WC, and the transfer transistor TR are provided for each pixel 541.

[0047] The semiconductor layer 100S is formed of, for example, a silicon substrate. The semiconductor layer 100S has a p-well layer 120, and includes an n-type semiconductor region 121 inside the p-well layer 120. For example, the n-type semiconductor region 121 and the p-well layer 120 constitute a pn-junction photodiode PD. The p-well layer 120 is a p-type semiconductor region.

[0048] On the front surface 100S1 of the semiconductor layer 100S, the floating diffusion FD and the well contact WC are provided spaced apart from each other.

[0049] The floating diffusion FD is constituted by an n-type semiconductor region 122 provided in the p-well layer 120. The floating diffusion FD is electrically connected from the first substrate 100 to the second substrate 200 via an electrical means. For example, the floating diffusion FD is electrically connected to the gate of an amplifying transistor AMP and the source of an FD conversion gain switching transistor FDG via a pad portion 132 and a through electrode 252 penetrating the semiconductor layer 200S constituting the second substrate 200.

[0050] The well contact WC is a region electrically connected to a reference potential line (e.g., ground GND) and is composed of a p-type semiconductor region 123 provided within the p-well layer 120. The well contact WC is connected to a semiconductor region 221 provided in the semiconductor layer 200S constituting the second substrate 200 via a pad portion 133 and a connection portion 251 from the surface 200S1 side of the semiconductor layer 200S. The well contact WC may also be connected to the ground potential or a fixed potential via a through-electrode that penetrates the semiconductor layer 200S constituting the second substrate 200. This supplies a reference potential to the semiconductor layer 100S.

[0051] The transfer transistor TR is provided on the surface 100S1 side of the semiconductor layer 100S. The transfer transistor TR has a gate electrode 131. The gate electrode 131 includes, for example, a horizontal portion 131b facing the surface of the semiconductor layer 100S and a vertical portion 131a provided within the semiconductor layer 100S. The vertical portion 131a extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion 131a is in contact with the horizontal portion 131b, and the other end is provided within the n-type semiconductor region 121. By configuring the transfer transistor TR as such a vertical transistor, the occurrence of pixel signal transfer failures becomes less likely, and the readout efficiency of the pixel signal can be improved.

[0052] As described above, the gate electrode 131 is electrically connected to the drive signal line. The gate electrode 131 and the drive signal line are electrically connected, for example, via a through-electrode 253 that penetrates the semiconductor layer 200S constituting the second substrate 200. The gate electrode 131 is formed using, for example, polysilicon with impurities implanted in it.

[0053] The transfer transistor TR may be composed of a planar transistor. In this case, a gate electrode 131 is provided on the surface of the semiconductor layer 100S. For example, the side surface of the gate electrode 131 is covered by a side wall 135 (see, for example, Figure 7). The side wall 135 is formed including, for example, silicon nitride (SiN). An insulating film 129 is provided between the semiconductor layer 100S and the gate electrode 131.

[0054] The semiconductor layer 100S is further provided with a pixel separation section 171.

[0055] The pixel separation section 171 separates adjacent pixels 541 from each other and extends between the front surface 100S1 and the back surface 100S2 of the semiconductor layer 100S. The pixel separation section 171 is provided, for example, in a grid pattern to partition adjacent pixels 541 from each other. The pixel separation section 171 separates adjacent pixels 541 from each other electrically and optically. The pixel separation section 171 can be formed, for example, by embedding an insulating film in a groove provided between the front surface 100S1 and the back surface 100S2 of the semiconductor layer 100S. A light-shielding film may be further embedded in the groove with the insulating film in between. The insulating film is formed by including, for example, silicon oxide (SiO). For the light-shielding film, for example, tungsten (W) can be used. The groove constituting the pixel separation section 171 has, for example, an FTI (Full Trench Isolation) structure and penetrates the semiconductor layer 100S. Although not shown in the figures, the pixel separation portion 171 is not limited to an FTI structure that penetrates the semiconductor layer 100S. For example, it may be a DTI (Deep Trench Isolation) structure that does not penetrate the semiconductor layer 100S.

[0056] The insulating film 181 is for insulating and protecting the back surface 100S2 of the semiconductor layer 100S. The insulating film 181 is formed of, for example, silicon oxide (SiO). In addition, the insulating film 181 may be formed using hafnium oxide (HfO), zircon oxide (ZrO), aluminum oxide (AlO), titanium oxide (TiO), or tantalum oxide (TaO), etc. The color filter 182 is an optical filter placed for each pixel 541 that transmits light of a predetermined wavelength from the incident light. The on-chip lens 401 is a lens placed for each pixel 541 that focuses the incident light onto the photodiode PD.

[0057] The wiring layer 100T has, from the semiconductor layer 100S side, an insulating film 129, the gate electrode 131 described above, pad portions 132 and 133, an interlayer insulating layer 141, and a connection portion 251.

[0058] The insulating film 129 is for insulating the surface 100S1 side of the semiconductor layer 100S. The insulating film 129 includes a gate insulating film 129A provided between the semiconductor layer 100S and the gate electrode 131, and a passivation film 129B extending to the surface 100S1 of the semiconductor layer 100S and the surface of the gate electrode 131 (see, for example, Figure 7). The insulating film 129 is formed of a single layer film made of one of the following: silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or a multilayer film made of two or more of these.

[0059] The pad portions 132 and 133 are electrodes connected to semiconductor regions (n-type semiconductor region 122 and p-type semiconductor region 123) provided in the semiconductor layer 100S. Pad portion 132 is connected to the floating diffusion FD. A through electrode 252 is further connected to pad portion 132. Pad portion 133 is connected to the well contact WC. A connection portion 251 is further connected to pad portion 133. The pad portions 132 and 133 are formed using, for example, polysilicon with impurities implanted.

[0060] The interlayer insulating layer 141 is for insulating the gate electrode 131 and pad portions 132, 133, etc., which are located on the surface 100S1 side of the semiconductor layer 100S. The interlayer insulating layer 141 is formed of a single layer film made of one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or a laminated film made of two or more of these.

[0061] The connection portion 251 is one of the connection means for electrically connecting the first substrate 100 and the second substrate 200. Figure 5 shows an example in which the connection portion 251 connects a well contact WC provided on the semiconductor layer 100S and a semiconductor region 221 provided on the semiconductor layer 200S via a pad portion 133 in order to supply a reference potential to the semiconductor layer 100S. The reference potential can be the ground potential. Alternatively, a fixed potential other than the ground potential can be applied as the reference potential. The connection portion 251 can be formed using, for example, polysilicon, polysilicon with impurities implanted, or a conductive metal material.

[0062] The second substrate 200 has a semiconductor layer 200S and a wiring layer 200T. The semiconductor layer 200S has a pair of opposing surfaces (front surface 200S1 and back surface 200S2), and the wiring layer 200T is provided on the front surface 200S1 side of the semiconductor layer 200S. The front surface 200S1 of the semiconductor layer 200S is the element formation surface. In the photodetector 1, the first substrate 100 and the second substrate 200 are stacked such that the front surface 100S1 of the semiconductor layer 100S and the back surface 200S2 of the semiconductor layer 200S face each other. In other words, the first substrate 100 and the second substrate 200 are joined so that the front surface of the first substrate 100 and the back surface of the second substrate 200 face each other. This joining method is called face-to-back joining. The second substrate 200 is provided with a plurality of pixel transistors 211 and through electrodes 252, 253 that constitute a pixel circuit 210. Although specific examples will be described later, the multiple pixel transistors 211 constituting the pixel circuit 210 may be provided separately on the first substrate 100 and the second substrate 200. The through electrodes 252 and 253 each penetrate the semiconductor layer 200S.

[0063] The semiconductor layer 200S is made of, for example, a silicon substrate. The semiconductor layer 200S has a p-well layer 220. The p-well layer 220 is, for example, a p-type semiconductor region. The semiconductor layer 200S is further provided with a plurality of semiconductor regions 221 corresponding to the "impurity diffusion region" of this disclosure.

[0064] The pixel transistor 211 is composed of an n-type semiconductor region 221 and a gate electrode 231. The n-type semiconductor region 221 consists of a source region 221S and a drain region 221D. A channel is formed in the p-well layer 220 below the gate electrode 231 between the source region 221S and the drain region 221D. The gate electrode 231 is formed using, for example, polysilicon with impurities implanted.

[0065] The semiconductor layer 200S is further provided with an insulating region 260.

[0066] The insulating region 260 is a region for providing multiple through electrodes 252, 253 for electrically connecting the first substrate 100 and the second substrate 200, insulated from the semiconductor layer 200S. The insulating region 260 also serves to isolate elements between multiple pixel transistors 211 constituting the pixel circuit 210, according to the layout of the pixel circuit 210. The insulating region 213 has approximately the same thickness as the semiconductor layer 200S and divides the semiconductor layer 200S into multiple sections. The through electrodes 252, 253 are arranged in this insulating region 213. For example, silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON) are embedded in the insulating region 213.

[0067] The wiring layer 200T has an insulating film 229 and an interlayer insulating layer 241 from the semiconductor layer 200S side. Multiple wirings (for example, a first wiring layer W1 and a second wiring layer W2), contact plugs 242, 243, through electrodes 252, 253 and contact portions 201, 202 are provided within the interlayer insulating layer 241. The interlayer insulating layer 241 forms a bonding surface with the third substrate 300, and the contact portions 201, 202 are exposed on the bonding surface.

[0068] The insulating film 229 is for insulating the surface 200S1 side of the semiconductor layer 200S. Similar to the insulating film 129, the insulating film 229 includes a gate insulating film provided between the semiconductor layer 200S and the gate electrode 231, and a passivation film extending across the surface 200S1 of the semiconductor layer 200S and the surface of the gate electrode 231. The insulating film 229 is formed from, for example, a single layer film made of one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or a multilayer film made of two or more of these.

[0069] The first wiring layer W1 and the second wiring layer W2 are for transmitting electrical signals to elements provided on the semiconductor layer 200S. The first wiring layer W1 and the second wiring layer W2 include, for example, the row drive signal line 542 and vertical signal line 543, and a reference potential line (e.g., ground GND) as described above. The first wiring layer W1 and the second wiring layer W2 are formed from, for example, aluminum (Al), copper (Cu), tungsten (W), polysilicon (Poly-Si), etc. The first wiring layer W1 and the second wiring layer W2 are insulated from each other by an interlayer insulating layer 241. Wiring provided on different layers can be connected by vias made of columnar metal, for example, columnar Cu. The interlayer insulating layer 241 is formed from a single layer film made of one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), etc., or from a multilayer film made of two or more of these.

[0070] The contact plugs 242 and 243 are for connecting the first wiring layer W1 to elements provided in the semiconductor layer 200S. Contact plug 242 connects the first wiring layer W1 to the source region 221S or drain region 221D of the pixel transistor 211 provided in the semiconductor layer 200S, or to the contact region 221A provided in the semiconductor layer 200S. Contact plug 243 connects the first wiring layer W1 to the gate electrode 231 of the pixel transistor 211 provided in the semiconductor layer 200S. The contact plugs 242 and 243 can be made of a columnar metal, for example, columnar tungsten (W).

[0071] As described above, the through electrodes 252 and 253 are arranged in the insulating region 260 and penetrate the semiconductor layer 200S in the thickness direction. The upper ends of the through electrodes 252 and 253 are connected to the wiring of the wiring layer 200T (for example, the first wiring layer W). The lower end of the through electrode 252 is connected to a pad portion 132 provided on the surface 100S1 side of the semiconductor layer 100S. The lower end of the through electrode 253 is connected to the gate electrode 131 of the transfer transistor TR. The through electrodes 252 and 253 can be made of a columnar metal, for example, columnar tungsten (W).

[0072] As described above, the contact portions 201 and 202 are connected to the contact portions 301 and 302 of the third substrate 300, respectively. Contact portion 201 is connected to the semiconductor region 221 of the semiconductor layer 200S via, for example, a contact plug 242, and transmits a reference potential. Contact portion 202 is used, for example, to transmit signals. The contact portions 201 and 202 are formed using, for example, copper (Cu).

[0073] The third substrate 300 has a semiconductor layer 300S and a wiring layer 300T. The semiconductor layer 300S has a pair of opposing surfaces, and the wiring layer 300T is provided on one of these surfaces (surface 300S1). In the photodetector 1, the second substrate 200 and the third substrate 300 are laminated together by bonding between electrodes, such that the surface 200S1 of the semiconductor layer 200S and the surface of the semiconductor layer 300S face each other. In other words, the second substrate 200 and the third substrate 300 are bonded together such that the surface of the second substrate 200 and the surface of the third substrate 300 face each other. This bonding method is called face-to-face bonding. The second substrate 200 and the third substrate 300 may also be bonded together by a so-called hybrid bonding. Specifically, electrodes (contact portions 201, 202) exposed on the bonding surface of the second substrate 200 and electrodes (contact portions 301, 302) exposed on the bonding surface of the third substrate 300 are bonded together, and the interlayer insulating layer 241 forming the bonding surface of the second substrate 200 and the interlayer insulating layer 341 forming the bonding surface of the third substrate 300 are bonded together. When both contact portions 201, 202 and contact portions 301, 302 are made of copper (Cu), the bonding between contact portions 201, 202 and contact portions 301, 302 is sometimes called a Cu-Cu bond.

[0074] The semiconductor layer 300S is made of, for example, a silicon substrate. Circuits are provided on the surface 300S1 side of the semiconductor layer 300S. Specifically, at least a portion of the following are provided on the surface side of the semiconductor layer 300S: the input unit 510A, the row drive unit 520, the timing control unit 530, the column signal processing unit 550, the image signal processing unit 560, and the output unit 510B.

[0075] The wiring layer 300T has an interlayer insulating layer 341. Multiple wiring layers and contact portions 301 and 302 are provided within the interlayer insulating layer 341. The interlayer insulating layer 341 forms a bonding surface with the second substrate 200, and the contact portions 301 and 302 are exposed on the bonding surface. The contact portions 301 and 302 are electrically connected to at least one of the input portion 510A, row drive portion 520, timing control portion 530, column signal processing portion 550, image signal processing portion 560, and output portion 510B formed on the semiconductor layer 300S, for example.

[0076] The interlayer insulating layer 341 is formed of a single layer film made of one of the following materials: silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or a laminated layer made of two or more of these materials. The contact portions 301 and 302 are formed using, for example, copper (Cu).

[0077] [Specific Configuration of the Photodetector] Figure 6 schematically shows an example of a specific planar configuration of the photodetector 1 shown in Figure 3. Figure 7 schematically shows a cross-sectional configuration of the photodetector 1 corresponding to the line I-I' shown in Figure 6.

[0078] In this embodiment, the photodetector 1 is provided with a connection portion 251, which is one of the connection means for electrically connecting the first substrate 100 and the second substrate 200. This connection portion 251B is provided to a plurality of semiconductor regions 221 (contact regions 221A) that extend between the surface 200S1 and the back surface 200S2 of the semiconductor layer 200S, and is electrically connected from the back surface 200S2 side of the semiconductor layer 200S facing the semiconductor layer 100S. As shown in Figure 6, for example, in a plan view, the connection portion 251B is located on an element isolation portion 124 provided on the semiconductor layer 100S and extends between the semiconductor layer 100S and the semiconductor layer 200S, similar to other connection portions 251.

[0079] Here, the semiconductor layer 100S corresponds to a specific example of the "first semiconductor layer" as one embodiment of the present disclosure. The pixel 541 corresponds to a specific example of the "sensor pixel" as one embodiment of the present disclosure, and the element isolation section 124 corresponds to a specific example of the "isolation section" as one embodiment of the present disclosure. The semiconductor layer 200S corresponds to a specific example of the "second semiconductor layer" as one embodiment of the present disclosure. The surface 200S1 corresponds to a specific example of the "second surface" as one embodiment of the present disclosure, and the back surface 200S2 corresponds to a specific example of the "first surface" as one embodiment of the present disclosure. The contact area 221A corresponds to a specific example of the "impurity diffusion area" as one embodiment of the present disclosure. The connection section 251B corresponds to a specific example of the "connection section" as one embodiment of the present disclosure.

[0080] In the light detection device 1 shown in Figures 6 and 7, the multiple pixel transistors 211 constituting the pixel circuit 210 are provided separately on the first substrate 100 and the second substrate 200. Specifically, the amplification transistor AMP, the selection transistor SEL, and the reset transistor RST are provided on the first substrate 100, and the FD conversion gain switching transistor FDG is provided on the second substrate 200. The gate electrode 131 of the amplification transistor AMP and the source region 221S of the FD conversion gain switching transistor FDG are electrically connected via a connection portion 251A. Here, the amplification transistor AMP corresponds to one specific example of the "first transistor" as an embodiment of the present disclosure, and the FD conversion gain switching transistor FDG corresponds to one specific example of the "second transistor" as an embodiment of the present disclosure.

[0081] In addition to the floating diffusion FD and well contact WC described above, an element isolation section 124 is further provided on the surface 100S1 of the semiconductor layer 100S.

[0082] The element isolation section 124 is for separating elements between a plurality of pixel transistors 211 constituting the pixel circuit 210 according to the layout of the pixel circuit 210. The element isolation section 124 can be formed, for example, by embedding an insulating film in a groove provided from the surface 100S1 side of the semiconductor layer 100S. The insulating film is formed by including, for example, silicon oxide (SiO). The groove constituting the element isolation section 124 has an STI (Shallow Trench Isolation) structure. A part of the element isolation section 124 is provided between adjacent pixels 541, and for example, it is in contact with a pixel isolation section 171 extending from the back surface 100S2 toward the front surface 100S1 of the semiconductor layer 100S within the semiconductor layer 100S. In other words, the element isolation section 124, together with the pixel isolation section 171, optically and electrically separates adjacent pixels 541 from each other between adjacent pixels 541.

[0083] The connection portion 251B is intended to reduce capacitive coupling between adjacent pixels 541. In a plan view, the connection portion 251B is located on an element isolation portion 124 provided between adjacent pixels 541. Specifically, as shown in Figure 6, it is located, for example, on an element isolation portion 124 between gate electrodes 131 of adjacent amplification transistors AMP in the Y-axis direction.

[0084] A first wiring layer W1 may be connected to the contact area 221A, for example, via a contact plug 242. This first wiring layer W1 is, for example, a reference potential line (e.g., ground GND). As a result, a fixed potential is applied to the connection portion 251B via the contact area 221A, further reducing capacitive coupling between adjacent pixels 541.

[0085] Furthermore, the connection portion 251B and the contact region 221A of the semiconductor layer 200S may be electrically connected via a conductive layer 221X, for example, as shown in Figure 8.

[0086] The conductive layer 221X is formed, for example, from single-crystal silicon epitaxially grown from the side surface of the semiconductor layer 200S. Alternatively, the conductive layer 221X may be formed using polysilicon or a conductive metal material.

[0087] [Manufacturing Method for Photodetector] Figures 9A to 9H show an example of a manufacturing method for the photodetector 1.

[0088] First, as shown in Figure 9A, pixel transistors 211 such as amplification transistors AMP are formed on the surface 100S1 side of the semiconductor layer 100S, and then a passivation film 129B and an interlayer insulating layer 141 are deposited in sequence.

[0089] Next, the interlayer insulating layer 141 and the passivation film 129B are processed by photolithography and etching (e.g., dry etching) to form contact holes. Subsequently, a conductive film is embedded in the contact holes by, for example, chemical vapor deposition (CVD), and then the conductive film deposited on the interlayer insulating layer 141 is removed and the surface is flattened by, for example, chemical mechanical polishing (CMP). As a result, connection portions 251A and 251B are formed, as shown in Figure 9B.

[0090] Next, as shown in Figure 9C, after bonding the semiconductor layers 200S, the semiconductor layers 200S are thinned to a predetermined thickness, for example, by CMP.

[0091] Next, as shown in Figure 9D, impurities are diffused into the semiconductor layer 200S by means of ion implantation, for example, to form semiconductor regions 221 such as the source region 221S, drain region 221D, and contact region 221A. Then, as shown in Figure 9D, the gate insulating film (insulating film 229), gate electrode 231, and side wall 232 are formed. This forms the FD conversion gain switching transistor FDG.

[0092] Next, as shown in Figure 9E, an insulating film 241A is formed to cover the semiconductor layer 200S and the FD conversion gain switching transistor FDG.

[0093] Next, as shown in Figure 9F, the insulating film 241A and the semiconductor layer 200S are patterned by photolithography and etching.

[0094] Next, as shown in Figure 9G, an interlayer insulating layer 241 is further formed, for example by CVD, to fill the gaps between the separated semiconductor layers 200S.

[0095] Next, the interlayer insulating layer 241 is processed by photolithography and etching (e.g., dry etching) to form contact holes. Then, a conductive film is embedded in the contact holes by, for example, CVD, and the conductive film deposited on the interlayer insulating layer 241 is removed and the surface is planarized by, for example, CMP. As a result, the contact plug 242 is formed as shown in Figure 9H.

[0096] Subsequently, the first wiring layer W1, the second wiring layer W2, and contact portions 201, 202, etc., are formed inside the interlayer insulating layer 241 by the BEOL process. Then, the contact portions 201, 202 are exposed on the surface of the interlayer insulating layer 241 and bonded to a separately prepared third substrate. With these steps completed, the photodetector 1 shown in Figure 5 is completed.

[0097] [Function and Effects] In the photodetector 1 of this embodiment, a connection portion 251B, which is electrically connected from the back surface 200S2 side of the semiconductor layer 200S facing the semiconductor layer 100S, is provided on the element isolation portion 124 in a plan view to the contact region 221A that extends between the front surface 200S1 and the back surface 200S2 of the semiconductor layer 200S, and is used as a shield between adjacent pixels 541. This reduces capacitive coupling between adjacent pixels 541. This will be explained below.

[0098] Traditionally, miniaturization of the area per pixel in two-dimensional imaging devices has been achieved through the introduction of microprocessing and improvements in mounting density. In recent years, three-dimensional imaging devices have been developed to achieve further miniaturization and miniaturization of the area per pixel.

[0099] In three-dimensional imaging devices, as a method to reduce the area of ​​the elements while facilitating the connection between stacked semiconductor substrates, an imaging device has been reported in which, for example, a first semiconductor substrate and a second semiconductor substrate are connected to each other by a connection portion that penetrates an insulating layer provided between them, thereby connecting the back surfaces of the first and second semiconductor substrates.

[0100] However, in imaging devices with the three-dimensional structure described above, it was difficult to reduce the FD-FD coupling rate between adjacent pixels due to the overall decrease in FD capacity resulting from the miniaturization of pixels.

[0101] In contrast, in this embodiment, as described above, a connection portion 251B is electrically connected from the back surface 200S2 side of the semiconductor layer 200S facing the semiconductor layer 100S to the contact region 221A that extends between the front surface 200S1 and the back surface 200S2 of the semiconductor layer 200S. This connection portion 251B is provided on the element isolation portion 124 in a plan view and used as a shield between adjacent pixels 541. As a result, capacitive coupling between adjacent pixels 541 is reduced.

[0102] As described above, in the optical detection device 1 of this embodiment, the FD-FD coupling rate between adjacent pixels is reduced, and FD-FD crosstalk between adjacent pixels 541 can be suppressed. Therefore, it is possible to improve the characteristics.

[0103] Furthermore, in the optical detection device 1 of this embodiment, a reference potential line (for example, ground GND) is connected to the contact region 221A to which the connection portion 251B is connected, and a fixed potential is applied to the connection portion 251B. This further reduces capacitive coupling between adjacent pixels 541. Therefore, it is possible to further improve the characteristics.

[0104] The following describes the second and third embodiments of this disclosure, as well as modifications 1 to 12, application examples, and application examples. In the following modifications, components common to the first embodiment are denoted by the same reference numerals.

[0105] <2. Modifications> (2-1. Modification 1) Figure 10A schematically shows an example of the cross-sectional configuration of the photodetector 1A according to Modification 1 of the present disclosure. Figure 10B schematically shows another example of the cross-sectional configuration of the photodetector 1A according to Modification 1 of the present disclosure.

[0106] In the first embodiment described above, an example was shown in which the end of the connection portion 251B on the semiconductor layer 100S side is in contact with the upper surface of the element isolation portion 124, but the embodiment is not limited to this. The connection portion 251B may be partially embedded in the element isolation portion 124, for example, as shown in Figure 10A. Alternatively, as shown in Figure 10B, for example, the end of the connection portion 251B on the semiconductor layer 100S side may be located within the interlayer insulating layer 141 above the element isolation portion 124. Except for this point, the photodetector 1A has substantially the same configuration as the photodetector 1 of the first embodiment described above.

[0107] Even with this configuration, the modified photodetector 1A can achieve the same effects as the photodetector 1 of the first embodiment described above.

[0108] (2-2. Modification 2) Figure 11 schematically shows an example of the cross-sectional configuration of the photodetector 1B according to Modification 2 of the present disclosure. Figure 12 schematically shows the cross-sectional configuration of the photodetector 1B corresponding to the line II-II' shown in Figure 11.

[0109] In addition to having a symmetrical shape, the connecting portion 251B may also have a ratio of 1.2 or more between the widths in mutually orthogonal directions (for example, the width W1 in the X-axis direction and the width W2 in the Y-axis direction). In this modified example, the photodetector 1B, as shown in Figure 11, for example, has the connecting portion 25B extended in the X-axis direction between adjacent pixels 541 in the Y-axis direction in a plan view. Specifically, the connecting portion 25B in this modified example extends in the X-axis direction between the gate electrodes 131 of adjacent amplification transistors AMP in the Y-axis direction. Except for this point, the photodetector 1B has substantially the same configuration as the photodetector 1 of the first embodiment described above.

[0110] Thus, in this modified optical detection device 1B, the connection portion 251B is extended in the X-axis direction between the gate electrodes 131 of the amplification transistors AMP provided on each of the adjacent pixels 541 in the Y-axis direction. As a result, capacitive coupling between adjacent pixels 541 is further reduced compared to the first embodiment. Therefore, it is possible to further improve the characteristics.

[0111] (2-3. Modification 3) Figure 13 schematically shows an example of the cross-sectional configuration of the photodetector 1C according to Modification 3 of the present disclosure. Figure 14 schematically shows the cross-sectional configuration of the photodetector 1C corresponding to the line III-III' shown in Figure 13.

[0112] In this modified photodetector 1C, for example, a portion of the contact region 221A of the semiconductor layer 200S extending in the X-axis direction is extended in the Y-axis direction, and a connection portion 25B is provided near the FD conversion gain switching transistor FDG. Except for this point, the photodetector 1C has substantially the same configuration as the photodetector 1 of the first embodiment described above.

[0113] Thus, in this modified photodetector 1C, a connection section 25B is provided near the FD conversion gain switching transistor FDG. This makes it possible to increase the FD capacitance C and thus the saturation electron count in, for example, the Low Conversion Gain (LCG) mode when performing photoelectric conversion with low conversion efficiency.

[0114] <2. Second Embodiment> The light detection device (light detection device 2) according to the second embodiment of the present disclosure is used, similar to the light detection device 2 of the first embodiment, as a CMOS image sensor used in electronic devices such as digital still cameras and video cameras.

[0115] [Cross-sectional configuration of the photodetector] Figure 15 schematically shows an example of the cross-sectional configuration of the photodetector 2 of the present disclosure. Note that Figure 15, like Figure 5 used in the first embodiment above, is schematically represented to make the positional relationships of the components easier to understand, and may differ from the actual cross-section. The photodetector 2 is, for example, a back-illuminated type photodetector. Similar to the photodetector 1 of the first embodiment above, the photodetector 2 has three substrates, namely a first substrate 100, a second substrate 200, and a third substrate 300, stacked in this order from the light incident side.

[0116] The first substrate 100 has a semiconductor layer 100S and a wiring layer 100T. The semiconductor layer 100S has a pair of opposing surfaces (front surface 100S1 and back surface 100S2), and the wiring layer 100T is provided on the front surface 100S1 side. The back surface 100S2 of the semiconductor layer 100S is a light-receiving surface, and an on-chip lens 410 is arranged on the back surface 100S2 side for each pixel 541. Between the semiconductor layer 100S and the on-chip lens 410, an insulating film 181 and a color filter 182 are provided in order from the on-chip lens 410 side. The first substrate 100 is provided with a photodiode PD, a floating diffusion FD, a well contact WC, and a transfer transistor TR. The photodiode PD, floating diffusion FD, well contact WC, and transfer transistor TR are provided for each pixel 541.

[0117] The semiconductor layer 100S is made of, for example, a silicon substrate. The semiconductor layer 100S has a p-well layer 120, which contains an n-type semiconductor region 121. For example, this n-type semiconductor region 121 and the p-well layer 120 constitute a pn-junction type photodiode PD. The p-well layer 120 is a p-type semiconductor region.

[0118] Floating diffusion FDs and well contacts WCs are provided on the surface 100S1 of the semiconductor layer 100S, spaced apart from each other.

[0119] The floating diffusion FD is composed of an n-type semiconductor region 122 provided within a p-well layer 120. The floating diffusion FD is connected to the second substrate 200 from the first substrate 100 via electrical means. For example, the floating diffusion FD is electrically connected to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG via a through electrode 252 that penetrates the pad portion 132 and the semiconductor layer 200S constituting the second substrate 200.

[0120] The well contact WC is a region electrically connected to a reference potential line (e.g., ground GND) and is composed of a p-type semiconductor region 123 provided within the p-well layer 120. The well contact WC is connected to a semiconductor region 221 provided in the semiconductor layer 200S constituting the second substrate 200 via a pad portion 133 and a connection portion 251 from the surface 200S1 side of the semiconductor layer 200S. The well contact WC may also be connected to the ground potential or a fixed potential via a through-electrode that penetrates the semiconductor layer 200S constituting the second substrate 200. This supplies a reference potential to the semiconductor layer 100S.

[0121] The transfer transistor TR is provided on the surface 100S1 side of the semiconductor layer 100S. The transfer transistor TR has a gate electrode 131. The gate electrode 131 includes, for example, a horizontal portion 131b facing the surface of the semiconductor layer 100S and a vertical portion 131a provided within the semiconductor layer 100S. The vertical portion 131a extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion 131a is in contact with the horizontal portion 131b, and the other end is provided within the n-type semiconductor region 121. By configuring the transfer transistor TR as such a vertical transistor, the occurrence of pixel signal transfer failures becomes less likely, and the readout efficiency of the pixel signal can be improved.

[0122] As described above, the gate electrode 131 is electrically connected to the drive signal line. The gate electrode 131 and the drive signal line are electrically connected, for example, via a through-electrode 253 that penetrates the semiconductor layer 200S constituting the second substrate 200. The gate electrode 131 is formed using, for example, polysilicon with impurities implanted in it.

[0123] The transfer transistor TR may be composed of a planar transistor. In this case, a gate electrode 131 is provided on the surface of the semiconductor layer 100S. For example, the side surface of the gate electrode 131 is covered by a side wall 135 (see, for example, Figure 7). The side wall 135 is formed including, for example, silicon nitride (SiN). An insulating film 129 is provided between the semiconductor layer 100S and the gate electrode 131.

[0124] The semiconductor layer 100S is further provided with a pixel separation section 171.

[0125] The pixel separation section 171 separates adjacent pixels 541 from each other and extends between the front surface 100S1 and the back surface 100S2 of the semiconductor layer 100S. The pixel separation section 171 is provided, for example, in a grid pattern to partition adjacent pixels 541 from each other. The pixel separation section 171 separates adjacent pixels 541 from each other electrically and optically. The pixel separation section 171 can be formed, for example, by embedding an insulating film in a groove provided between the front surface 100S1 and the back surface 100S2 of the semiconductor layer 100S. A light-shielding film may be further embedded in the groove with the insulating film in between. The insulating film is formed, for example, containing silicon oxide (SiO). For the light-shielding film, for example, tungsten (W) can be used. The groove constituting the pixel separation section 171 has, for example, an FTI structure and penetrates the semiconductor layer 100S. Although not shown in the figures, the pixel separation portion 171 is not limited to an FTI structure that penetrates the semiconductor layer 100S. For example, it may be a DTI structure that does not penetrate the semiconductor layer 100S.

[0126] The insulating film 181 is for insulating and protecting the back surface 100S2 of the semiconductor layer 100S. The insulating film 181 is formed of, for example, silicon oxide (SiO). In addition, the insulating film 181 may be formed using hafnium oxide (HfO), zircon oxide (ZrO), aluminum oxide (AlO), titanium oxide (TiO), or tantalum oxide (TaO), etc. The color filter 182 is an optical filter placed for each pixel 541 that transmits light of a predetermined wavelength from the incident light. The on-chip lens 401 is a lens placed for each pixel 541 that focuses the incident light onto the photodiode PD.

[0127] The wiring layer 100T has, from the semiconductor layer 100S side, an insulating film 129, the gate electrode 131 described above, pad portions 132 and 133, an interlayer insulating layer 141, and a connection portion 251.

[0128] The insulating film 129 is for insulating the surface 100S1 side of the semiconductor layer 100S. The insulating film 129 includes a gate insulating film 129A provided between the semiconductor layer 100S and the gate electrode 131, and a passivation film 129B extending to the surface 100S1 of the semiconductor layer 100S and the surface of the gate electrode 131 (see, for example, Figure 7). The insulating film 129 is formed of a single layer film made of one of the following: silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or a multilayer film made of two or more of these.

[0129] The pad portions 132 and 133 are electrodes connected to semiconductor regions (n-type semiconductor region 122 and p-type semiconductor region 123) provided in the semiconductor layer 100S. Pad portion 132 is connected to the floating diffusion FD. A through electrode 252 is further connected to pad portion 132. Pad portion 133 is connected to the well contact WC. A connection portion 251 is further connected to pad portion 133. The pad portions 132 and 133 are formed using, for example, polysilicon with impurities implanted.

[0130] The interlayer insulating layer 141 is for insulating the gate electrode 131 and pad portions 132, 133, etc., which are located on the surface 100S1 side of the semiconductor layer 100S. The interlayer insulating layer 141 is formed of a single layer film made of one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or a laminated film made of two or more of these.

[0131] The connection portion 251 is one of the connection means for electrically connecting the first substrate 100 and the second substrate 200. Figure 15 shows an example in which the connection portion 251 connects a well contact WC provided on the semiconductor layer 100S and a semiconductor region 221 provided on the semiconductor layer 200S via a pad portion 133 in order to supply a reference potential to the semiconductor layer 100S. The reference potential can be the ground potential. Alternatively, a fixed potential other than the ground potential can be applied as the reference potential. The connection portion 251 can be formed using, for example, polysilicon, polysilicon with impurities implanted, or a conductive metal material.

[0132] The second substrate 200 has a semiconductor layer 200S and a wiring layer 200T. The semiconductor layer 200S has a pair of opposing surfaces (front surface 200S1 and back surface 200S2), and the wiring layer 200T is provided on the front surface 200S1 side of the semiconductor layer 200S. The front surface 200S1 of the semiconductor layer 200S is the element formation surface. In the photodetector 2, the first substrate 100 and the second substrate 200 are stacked such that the front surface 100S1 of the semiconductor layer 100S and the back surface 200S2 of the semiconductor layer 200S face each other. In other words, the first substrate 100 and the second substrate 200 are joined so that the front surface of the first substrate 100 and the back surface of the second substrate 200 face each other. This joining method is called face-to-back joining. The second substrate 200 is provided with a plurality of pixel transistors 211 and through electrodes 252, 253 that constitute a pixel circuit 210. Although specific examples will be described later, the multiple pixel transistors 211 constituting the pixel circuit 210 may be provided separately on the first substrate 100 and the second substrate 200. The through electrodes 252 and 253 each penetrate the semiconductor layer 200S.

[0133] The semiconductor layer 200S is made of, for example, a silicon substrate. The semiconductor layer 200S has a p-well layer 220. The p-well layer 220 is, for example, a p-type semiconductor region. The semiconductor layer 200S is further provided with a plurality of semiconductor regions 221.

[0134] The pixel transistor 211 is composed of an n-type semiconductor region 221 and a gate electrode 231. The n-type semiconductor region 221 consists of a source region 221S and a drain region 221D. A channel is formed in the p-well layer 220 below the gate electrode 231 between the source region 221S and the drain region 221D. The gate electrode 231 is formed using, for example, polysilicon with impurities implanted.

[0135] The semiconductor layer 200S is further provided with an insulating region 260.

[0136] The insulating region 260 is a region for providing multiple through electrodes 252, 253 for electrically connecting the first substrate 100 and the second substrate 200, insulated from the semiconductor layer 200S. The insulating region 260 also serves to isolate elements between multiple pixel transistors 211 constituting the pixel circuit 210, according to the layout of the pixel circuit 210. The insulating region 213 has approximately the same thickness as the semiconductor layer 200S and divides the semiconductor layer 200S into multiple sections. The through electrodes 252, 253 are arranged in this insulating region 213. For example, silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON) are embedded in the insulating region 213.

[0137] The wiring layer 200T has an insulating film 229 and an interlayer insulating layer 241 from the semiconductor layer 200S side. Multiple wirings (for example, a first wiring layer W1 and a second wiring layer W2), contact plugs 242, 243, through electrodes 252, 253 and contact portions 201, 202 are provided within the interlayer insulating layer 241. The interlayer insulating layer 241 forms a bonding surface with the third substrate 300, and the contact portions 201, 202 are exposed on the bonding surface.

[0138] The insulating film 229 is for insulating the surface 200S1 side of the semiconductor layer 200S. Similar to the insulating film 129, the insulating film 229 includes a gate insulating film provided between the semiconductor layer 200S and the gate electrode 231, and a passivation film extending across the surface 200S1 of the semiconductor layer 200S and the surface of the gate electrode 231. The insulating film 229 is formed from, for example, a single layer film made of one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or a multilayer film made of two or more of these.

[0139] The first wiring layer W1 and the second wiring layer W2 are for transmitting electrical signals to elements provided on the semiconductor layer 200S. The first wiring layer W1 and the second wiring layer W2 include, for example, the row drive signal line 542 and vertical signal line 543, and a reference potential line (e.g., ground GND) as described above. The first wiring layer W1 and the second wiring layer W2 are formed from, for example, aluminum (Al), copper (Cu), tungsten (W), polysilicon (Poly-Si), etc. The first wiring layer W1 and the second wiring layer W2 are insulated from each other by an interlayer insulating layer 241. Wiring provided on different layers can be connected by vias made of columnar metal, for example, columnar Cu. The interlayer insulating layer 241 is formed from a single layer film made of one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), etc., or from a multilayer film made of two or more of these.

[0140] The contact plugs 242 and 243 are for connecting the first wiring layer W1 to elements provided in the semiconductor layer 200S. Contact plug 242 connects the first wiring layer W1 to the source region 221S or drain region 221D of the pixel transistor 211 provided in the semiconductor layer 200S, or to the contact region 221A provided in the semiconductor layer 200S. Contact plug 243 connects the first wiring layer W1 to the gate electrode 231 of the pixel transistor 211 provided in the semiconductor layer 200S. The contact plugs 242 and 243 can be made of a columnar metal, for example, columnar tungsten (W).

[0141] As described above, the through electrodes 252 and 253 are arranged in the insulating region 260 and penetrate the semiconductor layer 200S in the thickness direction. The upper ends of the through electrodes 252 and 253 are connected to the wiring of the wiring layer 200T (for example, the first wiring layer W). The lower end of the through electrode 252 is connected to a pad portion 132 provided on the surface 100S1 side of the semiconductor layer 100S. The lower end of the through electrode 253 is connected to the gate electrode 131 of the transfer transistor TR. The through electrodes 252 and 253 can be made of a columnar metal, for example, columnar tungsten (W).

[0142] As described above, the contact portions 201 and 202 are connected to the contact portions 301 and 302 of the third substrate 300, respectively. Contact portion 201 is connected to the semiconductor region 221 of the semiconductor layer 200S via, for example, a contact plug 242, and transmits a reference potential. Contact portion 202 is used, for example, to transmit signals. The contact portions 201 and 202 are formed using, for example, copper (Cu).

[0143] The third substrate 300 has a semiconductor layer 300S and a wiring layer 300T. The semiconductor layer 300S has a pair of opposing surfaces, and the wiring layer 300T is provided on one of these surfaces (surface 300S1). In the photodetector 2, the second substrate 200 and the third substrate 300 are laminated by electrode bonding such that the surface 200S1 of the semiconductor layer 200S and the surface of the semiconductor layer 300S face each other. In other words, the second substrate 200 and the third substrate 300 are bonded so that the surface of the second substrate 200 and the surface of the third substrate 300 face each other. This bonding method is called face-to-face bonding. The second substrate 200 and the third substrate 300 may also be bonded to each other by so-called hybrid bonding. Specifically, electrodes (contact portions 201, 202) exposed on the bonding surface of the second substrate 200 and electrodes (contact portions 301, 302) exposed on the bonding surface of the third substrate 300 are bonded together, and the interlayer insulating layer 241 forming the bonding surface of the second substrate 200 and the interlayer insulating layer 341 forming the bonding surface of the third substrate 300 are bonded together. When both contact portions 201, 202 and contact portions 301, 302 are made of copper (Cu), the bonding between contact portions 201, 202 and contact portions 301, 302 is sometimes called a Cu-Cu bond.

[0144] The semiconductor layer 300S is made of, for example, a silicon substrate. Circuits are provided on the surface 300S1 side of the semiconductor layer 300S. Specifically, at least a portion of the following are provided on the surface side of the semiconductor layer 300S: the input unit 510A, the row drive unit 520, the timing control unit 530, the column signal processing unit 550, the image signal processing unit 560, and the output unit 510B.

[0145] The wiring layer 300T has an interlayer insulating layer 341. Multiple wiring layers and contact portions 301 and 302 are provided within the interlayer insulating layer 341. The interlayer insulating layer 341 forms a bonding surface with the second substrate 200, and the contact portions 301 and 302 are exposed on the bonding surface. The contact portions 301 and 302 are electrically connected to at least one of the input portion 510A, row drive portion 520, timing control portion 530, column signal processing portion 550, image signal processing portion 560, and output portion 510B formed on the semiconductor layer 300S, for example.

[0146] The interlayer insulating layer 341 is formed of a single layer film made of one of the following materials: silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or a laminated layer made of two or more of these materials. The contact portions 301 and 302 are formed using, for example, copper (Cu).

[0147] [Specific Configuration of the Photodetector] Figure 16 is an equivalent circuit diagram showing an example of the configuration of the pixel circuit 210A of the photodetector 2 shown in Figure 15. In this embodiment, the photodetector 2 has two pixels 541A and 541B that share one pixel circuit 210A. The pixel circuit 210A includes, for example, four transistors, specifically an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG, and a capacitive element 271. The capacitive element 271 is for storing the charge overflowing from the photodiode PD and is connected between the FD conversion gain switching transistor FDG and the reset transistor RST.

[0148] Figure 17 schematically shows the specific cross-sectional configuration of the light detection device 2 shown in Figure 15.

[0149] In this embodiment, the photodetector 2 has a connection portion 251D as an example of a connection portion 251, which is one of the connection means for electrically connecting the first substrate 100 and the second substrate 200. The connection portion 251D is located on an n-type semiconductor region 122 (SFD) shared by an FD conversion gain switching transistor FDG and a reset transistor RST, which are provided on the surface 100S1 of the semiconductor layer 100S. A capacitive element 271 is provided on the connection portion 251D. The capacitive element 271 has a configuration in which an active layer 272, an insulating film 273, and an electrode film 274 are stacked in this order. In a plan view, the active layer 272 is arranged to overlap with the SFD, and the connection portion 251D extends between the semiconductor layer 100S and the active layer 272, electrically connecting the SFD and the active layer 272.

[0150] Here, the semiconductor layer 100S corresponds to a specific example of the "first semiconductor layer" as one embodiment of the present disclosure. The pixel 541 corresponds to a specific example of the "sensor pixel" as one embodiment of the present disclosure, and one or both of the FD conversion gain switching transistor FDG and the reset transistor RST correspond to a specific example of the "third transistor" as one embodiment of the present disclosure. The semiconductor layer 200S corresponds to a specific example of the "second semiconductor layer" as one embodiment of the present disclosure. The surface 200S1 corresponds to a specific example of the "second surface" as one embodiment of the present disclosure, and the back surface 200S2 corresponds to a specific example of the "first surface" as one embodiment of the present disclosure. The capacitive element 271 corresponds to a specific example of the "first laminate" as one embodiment of the present disclosure. The active layer 272 corresponds to a specific example of the "semiconductor active layer" as one embodiment of the present disclosure, the insulating film 273 corresponds to a specific example of the "insulating film" as one embodiment, and the electrode film 274 corresponds to a specific example of the "first electrode film" as one embodiment of the present disclosure. The connecting portion 521D corresponds to one specific example of the "third connecting portion" as one embodiment of the present disclosure.

[0151] In the light detection device 2, of the multiple pixel transistors 211 that constitute the pixel circuit 210A, at least the FD conversion gain switching transistor FDG and the reset transistor RST are provided on the first substrate 100.

[0152] The connection portion 251D is for connecting a capacitive element 271 to an n-type semiconductor region 122 (SFD) shared by an FD conversion gain switching transistor FDG and a reset transistor RST, which are provided on the surface 100S1 of the semiconductor layer 100S. The connection portion 251D can be formed using, for example, polysilicon, impurity-impregnated polysilicon, or a conductive metal material, similar to the connection portion 251 of the first embodiment described above.

[0153] As described above, the capacitive element 271 is for accumulating the charge overflowing from the photodiode PD, and has a configuration in which the active layer 272, the insulating film 273, and the electrode film 274 are stacked in this order.

[0154] As described above, the active layer 272 is positioned in a location where, in a plan view, it overlaps with the n-type semiconductor region 122 (SFD), which serves as both the drain of the FD conversion gain switching transistor FDG and the source of the reset transistor RST. The active layer 272 is composed of a semiconductor region 221 formed by, for example, a high concentration of n-type impurities implanted into the semiconductor layer 200S, and this semiconductor region 221 extends between the front surface 200S1 and the back surface 200S2 of the semiconductor layer 200S. The active layer 272 may be processed into multiple fin shapes, for example, as shown in Figure 18, to increase its effective surface area.

[0155] The insulating film 273 is formed by a single layer made of one of the following materials: silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or by a multilayer film made of two or more of these materials.

[0156] The electrode film 274 is formed using, for example, polysilicon with impurities implanted in it. Alternatively, the electrode film 274 may be formed using activated silicon.

[0157] A contact plug 244 is further connected to the capacitive element 271 from the electrode film 274 side. The contact plug 244 can be made of a columnar metal, for example, columnar tungsten (W).

[0158] [Manufacturing Method for Photodetector] Figures 19A to 19G show an example of a manufacturing method for the photodetector 2.

[0159] First, as shown in Figure 19A, pixel transistors 211 such as the FD conversion gain switching transistor FDG and the reset transistor RST are formed on the surface 100S1 side of the semiconductor layer 100S, and then the passivation film 129B and the interlayer insulating layer 141 are deposited in sequence.

[0160] Next, as shown in Figure 19B, the interlayer insulating layer 141 and the passivation film 129B are processed by photolithography and etching (e.g., dry etching) to form contact holes, and then a conductive film is embedded in the contact holes by, for example, CVD.

[0161] Next, as shown in Figure 19C, the conductive film formed on the interlayer insulating layer 141 is removed and the surface is flattened, for example by CMP. This forms the connection portion 251D.

[0162] Next, as shown in Figure 19D, after bonding the semiconductor layers 200S, the semiconductor layers 200S are thinned to a predetermined thickness, for example, by CMP.

[0163] Next, as shown in Figure 19E, the semiconductor layer 200S is processed by photolithography and etching (for example, dry etching).

[0164] Next, as shown in Figure 19F, an active layer 272 is formed by diffusing impurities into the semiconductor layer 200S, for example, by ion implantation. Subsequently, as shown in Figure 19F, after forming the insulating film 273 and the electrode film 274, a side wall 232 is formed on the side surface of the electrode film 274. This forms the capacitive element 271.

[0165] Next, as shown in Figure 19G, an interlayer insulating layer 241 is formed to cover the capacitive element 271. Then, the interlayer insulating layer 241 is processed by photolithography and etching (e.g., dry etching) to form contact holes. After that, a conductive film is embedded in the contact holes by, for example, CVD, and the conductive film formed on the interlayer insulating layer 241 is removed and the surface is planarized by, for example, CMP. This forms the contact plug 244. With the above steps, the photodetector 2 shown in Figure 17 is completed.

[0166] [Function and Effects] In the photodetector 2 of this embodiment, a capacitive element 271, which consists of an active layer 272, an insulating film 273, and an electrode film 274 stacked in that order, is placed in a position that overlaps with an n-type semiconductor region 122 (SFD) shared by an FD conversion gain switching transistor FDG and a reset transistor RST, which are provided on the surface 100S1 of the semiconductor layer 100S, and is electrically connected to each other via a connection portion 251D. This will be explained below.

[0167] Traditionally, miniaturization of the area per pixel in two-dimensional imaging devices has been achieved through the introduction of microprocessing and improvements in mounting density. In recent years, three-dimensional imaging devices have been developed to achieve further miniaturization and miniaturization of the area per pixel.

[0168] Incidentally, expanding the dynamic range in an imaging device can be achieved by switching the conversion efficiency using Dual / Triple Conversion Gain (DCG / TCG), etc. However, imaging devices with miniaturized pixels have a small FD capacity, making it difficult to form a sufficient capacity and thus difficult to expand the dynamic range on the low-light side.

[0169] In contrast, in this embodiment, as described above, a capacitive element 271, in which an active layer 272, an insulating film 273, and an electrode film 274 are stacked in this order, is provided at a position overlapping with an n-type semiconductor region 122 (SFD) shared by an FD conversion gain switching transistor FDG and a reset transistor RST, which are provided on the surface 100S1 of the semiconductor layer 100S, and is electrically connected to each other via a connection portion 251D. As a result, compared to, for example, the case in which a so-called planar type capacitive element having a source region and a drain region between the gate electrode is used, capacitance can be added to the pixel circuit 210A without reducing the capacitance density on the second substrate 200.

[0170] As a result, the light detection device 2 of this embodiment can, for example, expand the dynamic range on the low-light side and improve its characteristics.

[0171] Furthermore, in the photodetector 2 of this embodiment, the connection is made using the connection portion 251D to connect from the lower surface (back surface 200S2 of the semiconductor layer 200S) side of the capacitive element 271. This reduces the footprint compared to a typical capacitive element that has source and drain regions on both sides of the gate electrode.

[0172] <4. Modifications> (4-1. Modification 4) Figure 20 schematically shows an example of a cross-sectional configuration of a photodetector according to Modification 4 of this disclosure (photodetector 2A). Figure 21 schematically shows another example of a cross-sectional configuration of a photodetector according to Modification 4 of this disclosure (photodetector 2B).

[0173] In the second embodiment described above, an example was shown in which a capacitive element 271 was provided in which an active layer 272, activated by, for example, implanting a high concentration of n-type impurities into a semiconductor layer 200S, an insulating film 273, and an electrode film 274 were stacked in this order. However, the invention is not limited to this. In this modified example, the photodetector 2A is provided with a capacitive element 571A in which an oxide semiconductor layer 572, a high dielectric film 573, and a metal electrode 574 are stacked in this order. In this modified example, the photodetector 2B is provided with a capacitive element 571B in which a metal electrode 575, an oxide semiconductor layer 572, a high dielectric film 573, and a metal electrode 574 are stacked in this order. In this modified example, the connection portion 521D is formed using a conductive metal material or the like. Except for this point, the photodetectors 2A and 2B have substantially the same configuration as the photodetector 2 of the second embodiment described above.

[0174] The oxide semiconductor layer 572 corresponds to a specific example of a "semiconductor active layer" as one embodiment of the present disclosure. Similar to the active layer 272 in the second embodiment described above, the oxide semiconductor layer 572 is arranged to superimpose on the SFD in a plan view.

[0175] The high dielectric film 573 corresponds to one specific example of the "first insulating film" as one embodiment of the present disclosure. The high dielectric film 573 is formed using, for example, hafnium oxide (HfO), aluminum oxide (AlO), zirconium oxide (ZrO), tantalum oxide (TaO), titanium oxide (TiO), lanthanum oxide (LaO), praseodymium oxide (ProO), cerium oxide (CeO), neodymium oxide (NdO), promethium oxide (PmO), samarium oxide (SmO), europium oxide (EuO), gadolinium oxide (GdO), terbium oxide (TbO), dysprosium oxide (DyO), holmium oxide (HoO), thulium oxide (TmO), ytterbium oxide (YbO), lutetium oxide (LuO), yttrium oxide (YO), hafnium nitride (HfN), aluminum nitride (AlN), hafnium oxynitride (HfON), or aluminum oxynitride (AlON).

[0176] The metal electrode 531 corresponds to a specific example of the "first electrode film" as one embodiment of the present disclosure. The metal electrode 575 corresponds to a specific example of the "second electrode film" as one embodiment of the present disclosure.

[0177] Figures 22A to 22E show an example of a manufacturing method for the light detection device 2B shown in Figure 21.

[0178] First, the connection portion 251D is formed in the same manner as in the second embodiment described above, and then, as shown in Figure 22A, a metal film that will become a metal electrode 575 is formed on the interlayer insulating layer 141.

[0179] Next, as shown in Figure 22B, an oxide semiconductor layer 572 is formed on the metal film that will become the metal electrode 575, and then an annealing treatment is performed.

[0180] Next, as shown in Figure 22C, a high dielectric film 573 and a metal film that will become a metal electrode 574 are sequentially deposited on the oxide semiconductor layer 572.

[0181] Next, as shown in Figure 22D, a metal film to become the metal electrode 575, an oxide semiconductor layer 572, a high dielectric film 573, and a metal film to become the metal electrode 574 are processed by, for example, photolithography and etching (e.g., dry etching). This forms the capacitive element 22A.

[0182] Next, as shown in Figure 22E, an insulating film 229 is formed to cover the side and top surfaces of the capacitive element 571B.

[0183] Next, an interlayer insulating layer 241 is formed to cover the capacitive element 571B. Then, the interlayer insulating layer 241 is processed by photolithography and etching (e.g., dry etching) to form contact holes. After that, a conductive film is embedded in the contact holes by, for example, CVD, and the conductive film formed on the interlayer insulating layer 241 is removed and the surface is planarized by, for example, CMP. This forms the contact plug 244. With the above steps, the photodetector 2B shown in Figure 21 is completed.

[0184] Even with this configuration, the photodetectors 2A and 2B of this modified example can obtain the same effects as the photodetector 2 of the second embodiment described above.

[0185] (4-2. Modification 5) Figure 23 schematically shows an example of a cross-sectional configuration of a photodetector according to Modification 5 of the present disclosure (photodetector 2C). Figure 24 schematically shows an example of a cross-sectional configuration of a photodetector according to Modification 5 of the present disclosure (photodetector 2D).

[0186] In the modified photodetector devices 2C and 2D, the multiple pixel transistors 211 constituting the pixel circuit 210A are provided separately on the first substrate 100 and the second substrate 200. Specifically, the amplification transistor AMP, the selection transistor SEL, and the reset transistor RST are provided on the first substrate 100, and the FD conversion gain switching transistor FDG is provided on the second substrate 200. The gate electrode 131 of the amplification transistor AMP and the source region 221S of the FD conversion gain switching transistor FDG are electrically connected via a connection portion 251A. Here, the reset transistor RST corresponds to a specific example of the "third transistor" as one embodiment of the present disclosure, the FD conversion gain switching transistor FDG corresponds to a specific example of the "fourth transistor" as one embodiment of the present disclosure, and the amplification transistor AMP corresponds to a specific example of the "fifth transistor" as one embodiment of the present disclosure. The connection portion 251A corresponds to a specific example of the "fourth connection portion" as one embodiment of the present disclosure.

[0187] In the modified photodetectors 2C and 2D, each component constituting the capacitive elements 271 and 571 is formed on the same layer as each component constituting the FD conversion gain switching transistor FDG. Specifically, in the photodetector 2C, the active layer 272 constituting the capacitive element 271 and the source region 221S and drain region 221D constituting the FD conversion gain switching transistor FDG are formed on the same layer. The insulating film 273 constituting the capacitive element 271 and the gate insulating film 229 constituting the FD conversion gain switching transistor FDG are formed on the same layer. The electrode film 274 constituting the capacitive element 271 and the gate electrode 231 constituting the FD conversion gain switching transistor FDG are formed on the same layer. In the photodetector 2D, the FD conversion gain switching transistor FDG is composed of an oxide semiconductor layer 572 constituting the capacitive element 571, a high dielectric film 573, and a metal electrode 574, each formed on the same layer.

[0188] As described above, in the photodetectors 2, 2A, and 2B described in the second embodiment and modification 4, the capacitive elements 271 and 571 can be formed on the same layer as the components constituting the pixel transistors (for example, FD conversion gain switching transistors FDG) provided on the second substrate 200. In other words, capacitance can be added to the pixel circuit 210A without increasing the number of manufacturing steps.

[0189] (4-3. Modification 10) Figure 41 schematically shows an example of the cross-sectional configuration of the photodetector 2E according to Modification 10 of the present disclosure.

[0190] In this modified example, the photodetector 2E has the oxide semiconductor layer 572, high dielectric film 573, and metal electrode 574 constituting the capacitive element 571A provided in the modified example 4 extended, for example, above the FD conversion gain switching transistor FDG, and a capacitive element 571C is provided having a metal electrode 575 and a high dielectric film 576 below the oxide semiconductor layer 572 extending above the FD conversion gain switching transistor FDG, in order from a position close to the semiconductor layer 100S. The metal electrode 574 and the metal electrode 575 are electrically connected, for example, via contact plugs 244, 247 and the first wiring layer W1, as shown in Figure 41. Except for this point, the photodetector 2E has substantially the same configuration as the photodetector 2B in the modified example 4.

[0191] A laminated portion consisting of a metal electrode 575, a high dielectric film 576, an oxide semiconductor layer 572, a high dielectric film 573, and a metal electrode 574, which are stacked in order from a position close to the semiconductor layer 100S above the FD conversion gain switching transistor FDG, corresponds to one specific example of the "second laminate" as one embodiment of the present disclosure.

[0192] The high dielectric film 576 corresponds to one specific example of the "second insulating film" as one embodiment of the present disclosure. The high dielectric film 576 is formed, similar to the high dielectric film 573, using, for example, hafnium oxide (HfO), aluminum oxide (AlO), zirconium oxide (ZrO), tantalum oxide (TaO), titanium oxide (TiO), lanthanum oxide (LaO), praseodymium oxide (ProO), cerium oxide (CeO), neodymium oxide (NdO), promethium oxide (PmO), samarium oxide (SmO), europium oxide (EuO), gadolinium oxide (GdO), terbium oxide (TbO), dysprosium oxide (DyO), holmium oxide (HoO), thulium oxide (TmO), ytterbium oxide (YbO), lutetium oxide (LuO), yttrium oxide (YO), hafnium nitride (HfN), aluminum nitride (AlN), hafnium oxynitride (HfON), or aluminum oxynitride (AlON).

[0193] Even with this configuration, the modified photodetector 2E can obtain the same effects as the photodetector 2 of the second embodiment described above.

[0194] (4-4. Modification 11) Figure 42 schematically shows an example of the cross-sectional configuration of the photodetector 2F according to Modification 11 of the present disclosure.

[0195] The photodetector 2F in this modified example is equipped with a capacitive element 571D, which is formed by omitting the oxide semiconductor layer 572 from the metal electrode 575, oxide semiconductor layer 572, high dielectric film 573, and metal electrode 574 that constitute the capacitive element 571B provided in the modified example 4. Except for this point, the photodetector 2F has substantially the same configuration as the photodetector 2B in the modified example 4.

[0196] Even with this configuration, the modified photodetector 2F can achieve the same effects as the photodetector 2 of the second embodiment described above.

[0197] (4-5. Modification 12) Figure 43 schematically shows an example of the cross-sectional configuration of the photodetector 2G according to Modification 12 of the present disclosure.

[0198] In the above modified example 5, the FD conversion gain switching transistor FDG provided on the second substrate 200 is composed of an oxide semiconductor layer 572 constituting the capacitive element 571, a high dielectric film 573, and a metal electrode 574, each formed in the same layer, and the oxide semiconductor layer 572, high dielectric film 573, and metal electrode 574 each have the same film thickness in the FD conversion gain switching transistor FDG and the capacitive element 571, but the example is not limited to this. In the photodetector 2G of this modified example, the film thickness t1 of the high dielectric film 573 constituting the capacitive element 571 is thinner (t1 < t2) than the film thickness t2 of the high dielectric film 573 constituting the FD conversion gain switching transistor FDG. Except for this point, the photodetector 2G has substantially the same configuration as the photodetector 2D of the above modified example 5.

[0199] Even with this configuration, the modified photodetector 2G can obtain the same effects as the photodetector 2 of the second embodiment described above. Furthermore, in the modified photodetector 2G, the thickness of the high dielectric film 573 constituting the capacitive element 571 is made thinner than the thickness of the high dielectric film 573 constituting the FD conversion gain switching transistor FDG. By making the thickness of the high dielectric film 573 constituting the FD conversion gain switching transistor FDG thinner in this way, the capacitance of the capacitive element 571 can be increased compared to the photodetector 2D of the modified example 5 described above. This improves the degree of freedom in selecting the conversion efficiency.

[0200] <5. Third Embodiment> The light detection device (light detection device 3) according to the third embodiment of the present disclosure is used, similar to the light detection device 1 of the first embodiment, as a CMOS image sensor used in electronic devices such as digital still cameras and video cameras.

[0201] [Cross-sectional configuration of the photodetector] Figure 25 schematically shows an example of the cross-sectional configuration of the photodetector 3 of the present disclosure. Note that Figure 25, like Figure 5 used in the first embodiment above, is schematically shown to make the positional relationships of the components easier to understand, and may differ from the actual cross-section. The photodetector 3 is, for example, a back-illuminated type photodetector. Similar to the photodetector 1 of the first embodiment above, the photodetector 3 has three substrates, namely a first substrate 100, a second substrate 200, and a third substrate 300, stacked in this order from the light incident side.

[0202] The first substrate 100 has a semiconductor layer 100S and a wiring layer 100T. The semiconductor layer 100S has a pair of opposing surfaces (front surface 100S1 and back surface 100S2), and the wiring layer 100T is provided on the front surface 100S1 side. The back surface 100S2 of the semiconductor layer 100S is a light-receiving surface, and an on-chip lens 410 is arranged on the back surface 100S2 side for each pixel 541. Between the semiconductor layer 100S and the on-chip lens 410, an insulating film 181 and a color filter 182 are provided in order from the on-chip lens 410 side. The first substrate 100 is provided with a photodiode PD, a floating diffusion FD, a well contact WC, and a transfer transistor TR. The photodiode PD, floating diffusion FD, well contact WC, and transfer transistor TR are provided for each pixel 541.

[0203] The semiconductor layer 100S is made of, for example, a silicon substrate. The semiconductor layer 100S has a p-well layer 120, which contains an n-type semiconductor region 121. For example, this n-type semiconductor region 121 and the p-well layer 120 constitute a pn-junction type photodiode PD. The p-well layer 120 is a p-type semiconductor region.

[0204] Floating diffusion FDs and well contacts WCs are provided on the surface 100S1 of the semiconductor layer 100S, spaced apart from each other.

[0205] The floating diffusion FD is composed of an n-type semiconductor region 122 provided within a p-well layer 120. The floating diffusion FD is connected to the second substrate 200 from the first substrate 100 via electrical means. For example, the floating diffusion FD is electrically connected to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG via a through electrode 252 that penetrates the pad portion 132 and the semiconductor layer 200S constituting the second substrate 200.

[0206] The well contact WC is a region electrically connected to a reference potential line (e.g., ground GND) and is composed of a p-type semiconductor region 123 provided within the p-well layer 120. The well contact WC is connected to a semiconductor region 221 provided in the semiconductor layer 200S constituting the second substrate 200 via a pad portion 133 and a connection portion 251 from the surface 200S1 side of the semiconductor layer 200S. The well contact WC may also be connected to the ground potential or a fixed potential via a through-electrode that penetrates the semiconductor layer 200S constituting the second substrate 200. This supplies a reference potential to the semiconductor layer 100S.

[0207] The transfer transistor TR is provided on the surface 100S1 side of the semiconductor layer 100S. The transfer transistor TR has a gate electrode 131. The gate electrode 131 includes, for example, a horizontal portion 131b facing the surface of the semiconductor layer 100S and a vertical portion 131a provided within the semiconductor layer 100S. The vertical portion 131a extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion 131a is in contact with the horizontal portion 131b, and the other end is provided within the n-type semiconductor region 121. By configuring the transfer transistor TR as such a vertical transistor, the occurrence of pixel signal transfer failures becomes less likely, and the readout efficiency of the pixel signal can be improved.

[0208] As described above, the gate electrode 131 is electrically connected to the drive signal line. The gate electrode 131 and the drive signal line are electrically connected, for example, via a through-electrode 253 that penetrates the semiconductor layer 200S constituting the second substrate 200. The gate electrode 131 is formed using, for example, polysilicon with impurities implanted in it.

[0209] The transfer transistor TR may be composed of a planar transistor. In this case, a gate electrode 131 is provided on the surface of the semiconductor layer 100S. For example, the side surface of the gate electrode 131 is covered by a side wall 135 (see, for example, Figure 7). The side wall 135 is formed including, for example, silicon nitride (SiN). An insulating film 129 is provided between the semiconductor layer 100S and the gate electrode 131.

[0210] The semiconductor layer 100S is further provided with a pixel separation section 171.

[0211] The pixel separation section 171 separates adjacent pixels 541 from each other and extends between the front surface 100S1 and the back surface 100S2 of the semiconductor layer 100S. The pixel separation section 171 is provided, for example, in a grid pattern to partition adjacent pixels 541 from each other. The pixel separation section 171 separates adjacent pixels 541 from each other electrically and optically. The pixel separation section 171 can be formed, for example, by embedding an insulating film in a groove provided between the front surface 100S1 and the back surface 100S2 of the semiconductor layer 100S. A light-shielding film may be further embedded in the groove with the insulating film in between. The insulating film is formed by including, for example, silicon oxide (SiO). For the light-shielding film, for example, tungsten (W) can be used. The groove constituting the pixel separation section 171 has, for example, an FTI (Full Trench Isolation) structure and penetrates the semiconductor layer 100S. Although not shown in the figures, the pixel separation portion 171 is not limited to an FTI structure that penetrates the semiconductor layer 100S. For example, it may be a DTI (Deep Trench Isolation) structure that does not penetrate the semiconductor layer 100S.

[0212] The insulating film 181 is for insulating and protecting the back surface 100S2 of the semiconductor layer 100S. The insulating film 181 is formed of, for example, silicon oxide (SiO). In addition, the insulating film 181 may be formed using hafnium oxide (HfO), zircon oxide (ZrO), aluminum oxide (AlO), titanium oxide (TiO), or tantalum oxide (TaO), etc. The color filter 182 is an optical filter placed for each pixel 541 that transmits light of a predetermined wavelength from the incident light. The on-chip lens 401 is a lens placed for each pixel 541 that focuses the incident light onto the photodiode PD.

[0213] The wiring layer 100T has, from the semiconductor layer 100S side, an insulating film 129, the gate electrode 131 described above, pad portions 132 and 133, an interlayer insulating layer 141, and a connection portion 251.

[0214] The insulating film 129 is for insulating the surface 100S1 side of the semiconductor layer 100S. The insulating film 129 includes a gate insulating film 129A provided between the semiconductor layer 100S and the gate electrode 131, and a passivation film 129B extending to the surface 100S1 of the semiconductor layer 100S and the surface of the gate electrode 131 (see, for example, Figure 7). The insulating film 129 is formed of a single layer film made of one of the following: silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or a multilayer film made of two or more of these.

[0215] The pad portions 132 and 133 are electrodes connected to semiconductor regions (n-type semiconductor region 122 and p-type semiconductor region 123) provided in the semiconductor layer 100S. Pad portion 132 is connected to the floating diffusion FD. A through electrode 252 is further connected to pad portion 132. Pad portion 133 is connected to the well contact WC. A connection portion 251 is further connected to pad portion 133. The pad portions 132 and 133 are formed using, for example, polysilicon with impurities implanted.

[0216] The interlayer insulating layer 141 is for insulating the gate electrode 131 and pad portions 132, 133, etc., which are located on the surface 100S1 side of the semiconductor layer 100S. The interlayer insulating layer 141 is formed of a single layer film made of one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or a laminated film made of two or more of these.

[0217] The connection portion 251 is one of the connection means for electrically connecting the first substrate 100 and the second substrate 200. Figure 5 shows an example in which the connection portion 251 connects a well contact WC provided on the semiconductor layer 100S and a semiconductor region 221 provided on the semiconductor layer 200S via a pad portion 133 in order to supply a reference potential to the semiconductor layer 100S. The reference potential can be the ground potential. Alternatively, a fixed potential other than the ground potential can be applied as the reference potential. The connection portion 251 can be formed using, for example, polysilicon, polysilicon with impurities implanted, or a conductive metal material.

[0218] The second substrate 200 has a semiconductor layer 200S and a wiring layer 200T. The semiconductor layer 200S has a pair of opposing surfaces (front surface 200S1 and back surface 200S2), and the wiring layer 200T is provided on the front surface 200S1 side of the semiconductor layer 200S. The front surface 200S1 of the semiconductor layer 200S is the element formation surface. In the photodetector 1, the first substrate 100 and the second substrate 200 are stacked such that the front surface 100S1 of the semiconductor layer 100S and the back surface 200S2 of the semiconductor layer 200S face each other. In other words, the first substrate 100 and the second substrate 200 are joined so that the front surface of the first substrate 100 and the back surface of the second substrate 200 face each other. This joining method is called face-to-back joining. The second substrate 200 is provided with a plurality of pixel transistors 211 and through electrodes 252, 253 that constitute a pixel circuit 210. Although specific examples will be described later, the multiple pixel transistors 211 constituting the pixel circuit 210 may be provided separately on the first substrate 100 and the second substrate 200. The through electrodes 252 and 253 each penetrate the semiconductor layer 200S.

[0219] The semiconductor layer 200S is made of, for example, a silicon substrate. The semiconductor layer 200S has a p-well layer 220. The p-well layer 220 is, for example, a p-type semiconductor region. The semiconductor layer 200S is further provided with a plurality of semiconductor regions 221.

[0220] The pixel transistor 211 is composed of an n-type semiconductor region 221 and a gate electrode 231. The n-type semiconductor region 221 consists of a source region 221S and a drain region 221D. A channel is formed in the p-well layer 220 below the gate electrode 231 between the source region 221S and the drain region 221D. The gate electrode 231 is formed using, for example, polysilicon with impurities implanted.

[0221] The semiconductor layer 200S is further provided with an insulating region 260.

[0222] The insulating region 260 is a region for providing multiple through electrodes 252, 253 for electrically connecting the first substrate 100 and the second substrate 200, insulated from the semiconductor layer 200S. The insulating region 260 also serves to isolate elements between multiple pixel transistors 211 constituting the pixel circuit 210, according to the layout of the pixel circuit 210. The insulating region 213 has approximately the same thickness as the semiconductor layer 200S and divides the semiconductor layer 200S into multiple sections. The through electrodes 252, 253 are arranged in this insulating region 213. For example, silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON) are embedded in the insulating region 213.

[0223] The wiring layer 200T has an insulating film 229 and an interlayer insulating layer 241 from the semiconductor layer 200S side. Multiple wirings (for example, a first wiring layer W1 and a second wiring layer W2), contact plugs 242, 243, through electrodes 252, 253 and contact portions 201, 202 are provided within the interlayer insulating layer 241. The interlayer insulating layer 241 forms a bonding surface with the third substrate 300, and the contact portions 201, 202 are exposed on the bonding surface.

[0224] The insulating film 229 is for insulating the surface 200S1 side of the semiconductor layer 200S. Similar to the insulating film 129, the insulating film 229 includes a gate insulating film provided between the semiconductor layer 200S and the gate electrode 231, and a passivation film extending across the surface 200S1 of the semiconductor layer 200S and the surface of the gate electrode 231. The insulating film 229 is formed from, for example, a single layer film made of one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or a multilayer film made of two or more of these.

[0225] The first wiring layer W1 and the second wiring layer W2 are for transmitting electrical signals to elements provided on the semiconductor layer 200S. The first wiring layer W1 and the second wiring layer W2 include, for example, the row drive signal line 542 and vertical signal line 543, and a reference potential line (e.g., ground GND) as described above. The first wiring layer W1 and the second wiring layer W2 are formed from, for example, aluminum (Al), copper (Cu), tungsten (W), polysilicon (Poly-Si), etc. The first wiring layer W1 and the second wiring layer W2 are insulated from each other by an interlayer insulating layer 241. Wiring provided on different layers can be connected by vias made of columnar metal, for example, columnar Cu. The interlayer insulating layer 241 is formed from a single layer film made of one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), etc., or from a multilayer film made of two or more of these.

[0226] The contact plugs 242 and 243 are for connecting the first wiring layer W1 to elements provided in the semiconductor layer 200S. Contact plug 242 connects the first wiring layer W1 to the source region 221S or drain region 221D of the pixel transistor 211 provided in the semiconductor layer 200S, or to the contact region 221A provided in the semiconductor layer 200S. Contact plug 243 connects the first wiring layer W1 to the gate electrode 231 of the pixel transistor 211 provided in the semiconductor layer 200S. The contact plugs 242 and 243 can be made of a columnar metal, for example, columnar tungsten (W).

[0227] As described above, the through electrodes 252 and 253 are arranged in the insulating region 260 and penetrate the semiconductor layer 200S in the thickness direction. The upper ends of the through electrodes 252 and 253 are connected to the wiring of the wiring layer 200T (for example, the first wiring layer W). The lower end of the through electrode 252 is connected to a pad portion 132 provided on the surface 100S1 side of the semiconductor layer 100S. The lower end of the through electrode 253 is connected to the gate electrode 131 of the transfer transistor TR. The through electrodes 252 and 253 can be made of a columnar metal, for example, columnar tungsten (W).

[0228] As described above, the contact portions 201 and 202 are connected to the contact portions 301 and 302 of the third substrate 300, respectively. Contact portion 201 is connected to the semiconductor region 221 of the semiconductor layer 200S via, for example, a contact plug 242, and transmits a reference potential. Contact portion 202 is used, for example, to transmit signals. The contact portions 201 and 202 are formed using, for example, copper (Cu).

[0229] The third substrate 300 has a semiconductor layer 300S and a wiring layer 300T. The semiconductor layer 300S has a pair of opposing surfaces, and the wiring layer 300T is provided on one of these surfaces (surface 300S1). In the photodetector 3, the second substrate 200 and the third substrate 300 are laminated together by electrode bonding so that the surface 200S1 of the semiconductor layer 200S and the surface of the semiconductor layer 300S face each other. In other words, the second substrate 200 and the third substrate 300 are bonded together so that the surface of the second substrate 200 and the surface of the third substrate 300 face each other. This bonding method is called face-to-face bonding. The second substrate 200 and the third substrate 300 may also be bonded together by so-called hybrid bonding. Specifically, electrodes (contact portions 201, 202) exposed on the bonding surface of the second substrate 200 and electrodes (contact portions 301, 302) exposed on the bonding surface of the third substrate 300 are bonded together, and the interlayer insulating layer 241 forming the bonding surface of the second substrate 200 and the interlayer insulating layer 341 forming the bonding surface of the third substrate 300 are bonded together. When both contact portions 201, 202 and contact portions 301, 302 are made of copper (Cu), the bonding between contact portions 201, 202 and contact portions 301, 302 is sometimes called a Cu-Cu bond.

[0230] The semiconductor layer 300S is made of, for example, a silicon substrate. Circuits are provided on the surface 300S1 side of the semiconductor layer 300S. Specifically, at least a portion of the following are provided on the surface side of the semiconductor layer 300S: the input unit 510A, the row drive unit 520, the timing control unit 530, the column signal processing unit 550, the image signal processing unit 560, and the output unit 510B.

[0231] The wiring layer 300T has an interlayer insulating layer 341. Multiple wiring layers and contact portions 301 and 302 are provided within the interlayer insulating layer 341. The interlayer insulating layer 341 forms a bonding surface with the second substrate 200, and the contact portions 301 and 302 are exposed on the bonding surface. The contact portions 301 and 302 are electrically connected to at least one of the input portion 510A, row drive portion 520, timing control portion 530, column signal processing portion 550, image signal processing portion 560, and output portion 510B formed on the semiconductor layer 300S, for example.

[0232] The interlayer insulating layer 341 is formed of a single layer film made of one of the following materials: silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or a laminated layer made of two or more of these materials. The contact portions 301 and 302 are formed using, for example, copper (Cu).

[0233] [Specific Configuration of the Photodetector] Figure 26 schematically shows an example of a specific planar configuration of the photodetector 3 shown in Figure 25. Figure 27 schematically shows a cross-sectional configuration of the photodetector 3 corresponding to the IV-IV' line shown in Figure 26.

[0234] In this embodiment, the photodetector 3 is provided on the surface 200S1 side of the semiconductor layer 200S, and an electrode 233 is provided on the drain region 221D of a pixel transistor 211 (for example, an FD conversion gain switching transistor FDG) which has multiple semiconductor regions 221 extending between the surface 200S1 and the back surface 200S2 as a source region 221S and a drain region 221D.

[0235] Here, the semiconductor layer 100S corresponds to a specific example of the "first semiconductor layer" as one embodiment of the present disclosure. The pixel 541 corresponds to a specific example of the "sensor pixel" as one embodiment of the present disclosure, and the element isolation section 124 corresponds to a specific example of the "isolation section" as one embodiment of the present disclosure. The semiconductor layer 200S corresponds to a specific example of the "second semiconductor layer" as one embodiment of the present disclosure. The surface 200S1 corresponds to a specific example of the "second surface" as one embodiment of the present disclosure, and the back surface 200S2 corresponds to a specific example of the "first surface" as one embodiment of the present disclosure. The semiconductor region 221 corresponds to a specific example of the "impurity diffusion region" as one embodiment of the present disclosure. The FD conversion gain switching transistor FDG corresponds to a specific example of the "sixth transistor" as one embodiment of the present disclosure. The electrode 233 corresponds to a specific example of the "electrode section" as one embodiment of the present disclosure.

[0236] In the light detection device 3, the multiple pixel transistors 211 constituting the pixel circuit 210 are provided separately on the first substrate 100 and the second substrate 200. Specifically, the amplification transistor AMP, the selection transistor SEL, and the reset transistor RST are provided on the first substrate 100, and the FD conversion gain switching transistor FDG is provided on the second substrate 200. The gate electrode 131 of the amplification transistor AMP and the source region 221S of the FD conversion gain switching transistor FDG are electrically connected via a connection portion 251A. The drain region 221D of the FD conversion gain switching transistor FDG and the source region 122S of the reset transistor RST are electrically connected by a connection portion 251E. Here, the reset transistor RST corresponds to a specific example of the "seventh transistor" as one embodiment of the present disclosure, and the connection portion 251E corresponds to a specific example of the "fifth connection portion" as one embodiment of the present disclosure.

[0237] Electrode 233 is an electrode that is not connected to any wiring or other electrical connections to other elements other than the FD conversion gain switching transistor FDG, and is intended to add capacitance to the FD conversion gain switching transistor FDG. Electrode 233 is formed using, for example, polysilicon with impurities implanted in it.

[0238] The FD conversion gain switching transistor FDG is composed of a gate electrode 231, a source region 221S and a drain region 221D, a channel region 221C located below the gate electrode 231, an LDD (Lightly Doped Drain) region 223 located between the channel region 221C and the drain region 221D, a gate insulating film 229, and a side wall 232.

[0239] The gate electrode 231 is formed using, for example, polysilicon with impurities implanted. A contact plug 245 is connected to the gate electrode 231. The contact plug 245 can be made of a columnar metal, for example, columnar tungsten (W).

[0240] The source region 221S, drain region 221D, channel region 221C, and channel region 221C and LDD region 223 are composed of n-type semiconductor regions 221 provided in the semiconductor layer 200S. The impurity concentrations of each semiconductor region 221 constituting the source region 221S, drain region 221D, channel region 221C, and channel region 221C and LDD region 223 are highest in the source region 221S and drain region 221D, lowest in the channel region 221C, and the LDD region 223 has an impurity concentration between that of the source region 221S and drain region 221D and the channel region 221C.

[0241] The side wall 232 is formed to cover the side surface of the gate electrode 231 and the side surface of the electrode 233 provided on the drain region 221D, and to fill the space between the gate electrode 231 and the electrode 233.

[0242] [Manufacturing Method for the Light Detection Device] Figures 28A to 28J show an example of a manufacturing method for the light detection device 3.

[0243] First, as shown in Figure 28A, pixel transistors 211 such as amplification transistors AMP are formed on the surface 100S1 side of the semiconductor layer 100S, and then a passivation film 129B and an interlayer insulating layer 141 are deposited in sequence. Next, as shown in Figure 28A, the interlayer insulating layer 141 and the passivation film 129B are processed by photolithography and etching (e.g., dry etching) to form contact holes. Subsequently, a conductive film is embedded in the contact holes by, for example, CVD, and then the conductive film deposited on the interlayer insulating layer 141 is removed and the surface is flattened by, for example, CMP. This forms the connection portions 251A and 251E.

[0244] Next, as shown in Figure 28B, after bonding the semiconductor layers 200S, the semiconductor layers 200S are thinned to a predetermined thickness, for example, by CMP.

[0245] Next, as shown in Figure 28C, impurities are diffused into the semiconductor layer 200S by, for example, ion implantation to form a channel region 221C. Then, as shown in Figure 28C, after forming a gate insulating film (insulating film 229), the insulating film 229 at the position where the drain region 221D is formed is removed.

[0246] Next, as shown in Figure 28D, a polysilicon film 231X is formed on the insulating film 229 and the semiconductor layer 200S exposed from the insulating film 229.

[0247] Next, as shown in Figure 28E, a resist film 601 is patterned on the polysilicon film 231X.

[0248] Next, as shown in Figure 28F, the polysilicon film 231X exposed from the resist film 601 is removed by etching. This forms the gate electrode 231 and the electrode 233.

[0249] Next, as shown in Figure 28G, the resist film 602 is patterned to surround the electrode 233, and then, for example, ion implantation is performed. As a result, LDD regions 223 are formed in the semiconductor layer 200S exposed from the resist film 602 below and around the electrode 233.

[0250] Next, as shown in Figure 28H, a side wall 232 is formed to cover the sides of the gate electrode 231 and the side of the electrode 233, and to fill the gap between the gate electrode 231 and the electrode 233.

[0251] Next, as shown in Figure 28I, the resist film 603 is patterned to cover the gate electrode 231 and the outside of the electrode 233, and then ion implantation is performed. As a result, a source region 221S and a drain region 22D are formed in the semiconductor layer 200S exposed from the resist film 603 and in the semiconductor layer 200S below the electrode 233, respectively.

[0252] Next, as shown in Figure 28J, after removing the resist film 603, an interlayer insulating layer 241 is formed to cover the semiconductor layer 200S, the FD conversion gain switching transistor FDG, and the electrode 233.

[0253] Subsequently, the interlayer insulating layer 241 is processed by photolithography and etching (e.g., dry etching) to form contact holes. Then, a conductive film is embedded in the contact holes by, for example, CVD, and the conductive film deposited on the interlayer insulating layer 241 is removed and the surface is planarized by, for example, CMP. This forms the contact plug 245. With the above steps, the photodetector 3 shown in Figure 27 is completed.

[0254] [Function and Effects] In the photodetector 3 of this embodiment, an electrode 233 is provided on the drain region 221D of a pixel transistor 211 (for example, an FD conversion gain switching transistor FDG) which is provided on the surface 200S1 side of the semiconductor layer 200S and has multiple semiconductor regions 221 extending between the surface 200S1 and the back surface 200S2 as a source region 221S and a drain region 221D. This adds capacitance to the FD conversion gain switching transistor FDG. This will be explained below.

[0255] Traditionally, miniaturization of the area per pixel in two-dimensional imaging devices has been achieved through the introduction of microprocessing and improvements in mounting density. In recent years, three-dimensional imaging devices have been developed to achieve further miniaturization and miniaturization of the area per pixel.

[0256] Incidentally, in imaging devices with miniaturized pixels, when readout operations are performed with low conversion efficiency, it is difficult to sufficiently reduce the conversion efficiency due to insufficient floppy disk capacity. As a result, when converting the photoelectrically converted charge into voltage at high illumination, the voltage exceeds the maximum voltage, leading to the problem of not being able to obtain the desired characteristics.

[0257] In contrast, in this embodiment, as described above, an electrode 233 is provided on the drain region 221D of a pixel transistor 211 (for example, an FD conversion gain switching transistor FDG) which is provided on the surface 200S1 side of the semiconductor layer 200S and has multiple semiconductor regions 221 extending between the surface 200S1 and the back surface 200S2 as a source region 221S and a drain region 221D. This adds capacitance to the FD conversion gain switching transistor FDG. As a result, the overall FD capacitance C can be increased.

[0258] As described above, in the optical detection device 3 of this embodiment, the conversion efficiency can be reduced by increasing the overall FD capacity C, so that the desired characteristics can be obtained during readout operation with low conversion efficiency. Therefore, it is possible to improve the characteristics.

[0259] <6. Modifications> (6-1. Modification 6) Figure 29 schematically shows an example of the cross-sectional configuration of the photodetector 3A according to Modification 6 of the present disclosure.

[0260] In the third embodiment described above, an example was shown in which the electrode 233 is provided only on the drain region 221D of the FD conversion gain switching transistor FDG provided on the second substrate 200, but the invention is not limited to this. In this modified example, the photodetector 3A has electrodes 233 provided on the drain region 221D and the source region 221S of the FD conversion gain switching transistor FDG provided on the second substrate 200. Except for this point, the photodetector 3A has substantially the same configuration as the photodetector 3 of the third embodiment described above.

[0261] Thus, in this modified photodetector 3A, electrodes 233 are provided on the drain region 221D and source region 221S of the FD conversion gain switching transistor FDG provided on the second substrate 200, respectively, so that the overall FD capacitance C can be further increased. Therefore, it is possible to further improve the characteristics.

[0262] (6-2. Modification 7) Figure 30 schematically shows an example of the cross-sectional configuration of the photodetector 3B according to Modification 7 of the present disclosure.

[0263] In this modified example, the photodetector 3B has an electrode 233 provided on the drain region 221D of the FD conversion gain switching transistor FDG provided on the second substrate 200, to which a contact plug 246 is further connected from the surface 200S1 side of the semiconductor layer 200S. Except for this point, the photodetector 3B has substantially the same configuration as the photodetector 3 of the third embodiment described above.

[0264] The plug 246 corresponds to a specific example of the "sixth connection part" as one embodiment of the present disclosure. The plug 246, together with the electrode 233, is for adding capacitance to the FD conversion gain switching transistor FDG, and is not connected to any wiring or other elements that are electrically connected to other elements other than the FD conversion gain switching transistor FDG. The plug 246 is formed using, for example, polysilicon with impurities implanted in it.

[0265] Thus, in this modified photodetector 3B, a contact plug 246 is further connected from the surface 200S1 side of the semiconductor layer 200S to an electrode 233 provided on the drain region 221D of the FD conversion gain switching transistor FDG provided on the second substrate 200, thereby further increasing the overall FD capacitance C. Therefore, it is possible to further improve the characteristics.

[0266] (6-3. Modification 8) Figure 31 schematically shows an example of the cross-sectional configuration of the photodetector 3C according to Modification 8 of the present disclosure.

[0267] In the third embodiment described above, an example was shown in which the gate electrode 231 of the FD conversion gain switching transistor FDG provided on the second substrate 200 and the electrode 233 provided on the drain region 221D are formed using the same material, but the invention is not limited to this. In this modified photodetector 3C, an electrode 234 made of a different material from the gate electrode 231 of the FD conversion gain switching transistor FDG provided on the second substrate 200 is provided on the drain region 221D of the FD conversion gain switching transistor FDG. In addition, in this modified photodetector 3C, the LDD region 223 is omitted. Except for this point, the photodetector 3C has substantially the same configuration as the photodetector 3 of the third embodiment described above.

[0268] Electrode 234 corresponds to one specific example of the "electrode section" as one embodiment of the present disclosure. Similar to electrode 233 in the third embodiment described above, electrode 234 is an electrode that is not connected to any wiring or other elements that are electrically connected to other elements other than the FD conversion gain switching transistor FDG, and is intended to add capacitance to the FD conversion gain switching transistor FDG. Electrode 234 is formed using, for example, polysilicon or amorphous silicon.

[0269] Figures 32A to 32D show an example of a method for manufacturing the electrode 234.

[0270] First, as shown in Figure 32A, an FD conversion gain switching transistor FDG is formed on the surface 200S1 side of the semiconductor layer 200S.

[0271] Next, as shown in Figure 32B, an interlayer insulating layer 241 is formed on the FD conversion gain switching transistor FDG, and then an opening H is formed on the drain region 221D.

[0272] Next, as shown in Figure 32C, a polysilicon film 234X is formed to fill the opening H.

[0273] Next, as shown in Figure 32D, the polysilicon film 234X deposited on the interlayer insulating layer 241 is removed by, for example, CMP, and the surface is planarized. As a result, an electrode 234 is formed on the drain region 211D of the FD conversion gain switching transistor FDG.

[0274] Thus, in this modified photodetector 3C, an electrode 234 made of a different material from the gate electrode 231 is provided on the drain region 221D of the FD conversion gain switching transistor FDG provided on the second substrate 200. Even with this configuration, the photodetector 3C of this modified example can obtain the same effects as the photodetector 3 of the third embodiment described above.

[0275] (6-4. Modification 9) Figure 33 schematically shows an example of the planar configuration of the photodetector 3D according to Modification 9 of the disclosure. Figure 34 schematically shows the cross-sectional configuration of the photodetector 3D corresponding to the V-V' line shown in Figure 33.

[0276] In this modified photodetector 3D, a through electrode 255 is positioned near an electrode 233 located on the drain region 221D of an FD conversion gain switching transistor FDG provided on the second substrate 200. The upper end of the through electrode 255 is electrically connected to a reference potential line (e.g., ground GND), and a fixed potential is applied to the through electrode 255. The lower end on the first substrate 100 side is in contact with an element isolation portion 124 formed on the surface 100S1 of the semiconductor layer 100S, for example, as in the connection portion 251B of the first embodiment described above. Except for this point, the photodetector 3D has substantially the same configuration as the photodetector 3 of the third embodiment described above.

[0277] Thus, in this modified example, a through electrode 255 to which a fixed potential is applied is placed near the electrode 233 located on the drain region 221D of the FD conversion gain switching transistor FDG provided on the second substrate 200. As a result, the overall FD capacitance C can be further increased. Therefore, it is possible to further improve the characteristics.

[0278] <7. Application Examples> (Application Example 1) The above-mentioned light detection device 1 can be applied to any type of electronic device equipped with an imaging function, such as camera systems like digital still cameras and video cameras, or mobile phones with imaging capabilities. Figure 35 shows a schematic configuration of the electronic device 1000.

[0279] The electronic device 1000 includes, for example, a lens group 1001, a light detection device 1, a DSP (Digital Signal Processor) circuit 1002, a frame memory 1003, a display unit 1004, a recording unit 1005, an operation unit 1006, and a power supply unit 1007, all of which are interconnected via a bus line 1008.

[0280] The lens group 1001 captures incident light (image light) from the subject and forms an image on the imaging surface of the light detection device 1. The light detection device 1 converts the amount of incident light formed on the imaging surface by the lens group 1001 into an electrical signal on a pixel-by-pixel basis and supplies it as a pixel signal to the DSP circuit 1002.

[0281] The DSP circuit 1002 is a signal processing circuit that processes signals supplied from the light detection device 1. The DSP circuit 1002 outputs image data obtained by processing the signals from the light detection device 1. The frame memory 1003 temporarily holds the image data processed by the DSP circuit 1002 in frame units.

[0282] The display unit 1004 consists of a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and records the video or still image data captured by the light detection device 1 onto a recording medium such as a semiconductor memory or a hard disk.

[0283] The operation unit 1006 outputs operation signals for various functions possessed by the electronic device 1000 in accordance with user operations. The power supply unit 1007 appropriately supplies various power sources to the DSP circuit 1002, frame memory 1003, display unit 1004, recording unit 1005, and operation unit 1006.

[0284] (Application Example 2) Figure 36A schematically shows an example of the overall configuration of a photodetection system 2000 equipped with a photodetector 1. Figure 36B shows an example of the circuit configuration of the photodetection system 2000. The photodetection system 2000 includes a light-emitting device 2001 as a light source that emits infrared light L2, and a photodetector 2002 as a light-receiving unit having a photoelectric conversion element. The photodetector 1 described above can be used as the photodetector 2002. The photodetection system 2000 may further include a system control unit 2003, a light source drive unit 2004, a sensor control unit 2005, a light source side optical system 2006, and a camera side optical system 2007.

[0285] The photodetector 2002 can detect light L1 and light L2. Light L1 is light reflected from ambient light from the outside by the subject (object to be measured) 2100 (Figure 36A). Light L2 is light that has been emitted by the light-emitting device 2001 and then reflected by the subject 2100. Light L1 is, for example, visible light, and light L2 is, for example, infrared light. Light L1 is detectable in the photoelectric conversion unit of the photodetector 2002, and light L2 is detectable in the photoelectric conversion region of the photodetector 2002. Image information of the subject 2100 can be obtained from light L1, and distance information between the subject 2100 and the photodetector system 2000 can be obtained from light L2. The photodetector system 2000 can be mounted on, for example, electronic devices such as smartphones or mobile devices such as cars. The light-emitting device 2001 can be, for example, a semiconductor laser, a surface-emitting semiconductor laser, or a vertical-cavity surface-emitting laser (VCSEL). As a detection method for the light L2 emitted from the light-emitting device 2001 by the photodetector 2002, for example, the iTOF method can be used, but is not limited to this. In the iTOF method, the photoelectric conversion unit can measure the distance to the subject 2100 by, for example, the time-of-flight (TOF). As a detection method for the light L2 emitted from the light-emitting device 2001 by the photodetector 2002, for example, the structured light method or the stereo vision method can also be used. For example, in the structured light method, the distance between the photodetector 2000 and the subject 2100 can be measured by projecting a predetermined pattern of light onto the subject 2100 and analyzing the degree of distortion of the pattern. In the stereo vision method, for example, the distance between the photodetector 2000 and the subject can be measured by using two or more cameras to acquire two or more images of the subject 2100 from two or more different viewpoints. Furthermore, the light-emitting device 2001 and the light-detecting device 2002 can be synchronously controlled by the system control unit 2003.

[0286] <8. Application Examples> (Application to Endoscopic Surgical Systems) The technology disclosed herein (this technology) can be applied to various products. For example, the technology disclosed herein may be applied to an endoscopic surgical system.

[0287] Figure 37 is a diagram showing an example of a schematic configuration of an endoscopic surgical system to which the technology described herein (the technology) may be applied.

[0288] Figure 37 illustrates a surgeon (physician) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgical system 11000. As shown in the figure, the endoscopic surgical system 11000 consists of an endoscope 11100, other surgical instruments 11110 such as an insufflation tube 11111 and an energy treatment device 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 equipped with various devices for endoscopic surgery.

[0289] The endoscope 11100 consists of a barrel 11101, the tip of which is inserted into the body cavity of the patient 11132 for a predetermined length, and a camera head 11102 connected to the base end of the barrel 11101. In the illustrated example, the endoscope 11100 is shown as a so-called rigid endoscope having a rigid barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible endoscope having a flexible barrel.

[0290] An opening into which an objective lens is fitted is provided at the tip of the microscope tube 11101. A light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the tip of the microscope tube by a light guide extending inside the microscope tube 11101, and is irradiated through the objective lens towards the object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a straight-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0291] The camera head 11102 contains an optical system and an image sensor. Reflected light from the object being observed (observation light) is focused onto the image sensor by the optical system. The image sensor converts the observation light into electrical signals, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0292] The CCU 11201 is composed of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and other components, and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various image processing operations on that image signal, such as development processing (demosaic processing), to display an image based on that image signal.

[0293] The display device 11202 displays an image based on an image signal that has been processed by the CCU 11201, under control from the CCU 11201.

[0294] The light source device 11203 is composed of a light source such as an LED (light-emitting diode) and supplies illumination light to the endoscope 11100 when photographing the surgical area, etc.

[0295] The input device 11204 is an input interface for the endoscopic surgical system 11000. The user can input various types of information and instructions to the endoscopic surgical system 11000 via the input device 11204. For example, the user can input instructions to change the imaging conditions (type of light, magnification, focal length, etc.) of the endoscope 11100.

[0296] The treatment instrument control device 11205 controls the drive of the energy treatment instrument 11112 for purposes such as tissue cauterization, incision, or blood vessel sealing. The insufflation device 11206 injects gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity for the purpose of securing a field of view by the endoscope 11100 and securing the operator's workspace. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, images, or graphs.

[0297] The light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical area can be configured as a white light source consisting of, for example, an LED, a laser light source, or a combination thereof. When the white light source is configured as a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to capture images corresponding to each of the RGB colors in time-division by irradiating the observation target with laser light from each of the RGB laser light sources in time-division and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter on the image sensor.

[0298] Furthermore, the light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the drive of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity, images can be acquired in time-division order, and these images can be combined to generate high dynamic range images without so-called black crushing and white clipping.

[0299] Furthermore, the light source device 11203 may be configured to supply light in a predetermined wavelength range corresponding to special light observation. In special light observation, for example, so-called narrow-band imaging is performed, in which a predetermined tissue such as blood vessels on the surface of the mucosa is imaged with high contrast by irradiating with narrow-band light compared to the irradiation light used in normal observation (i.e., white light), utilizing the wavelength dependence of light absorption in body tissue. Alternatively, fluorescence observation may be performed in special light observation, in which an image is obtained from fluorescence generated by irradiation with excitation light. In fluorescence observation, fluorescence can be obtained by irradiating body tissue with excitation light and observing the fluorescence from the body tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into body tissue and irradiating the body tissue with excitation light corresponding to the fluorescence wavelength of the reagent to obtain a fluorescence image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0300] Figure 38 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in Figure 37.

[0301] The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0302] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and then incident on the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses, including a zoom lens and a focus lens.

[0303] The imaging unit 11402 may consist of one image sensor (a so-called single-chip type) or multiple image sensors (a so-called multi-chip type). If the imaging unit 11402 is configured as a multi-chip type, for example, each image sensor may generate image signals corresponding to RGB, and these may be combined to obtain a color image. Alternatively, the imaging unit 11402 may be configured to have a pair of image sensors for acquiring image signals for the right eye and left eye, respectively, corresponding to 3D (dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical area. In addition, if the imaging unit 11402 is configured as a multi-chip type, multiple lens units 11401 may be provided corresponding to each image sensor.

[0304] Furthermore, the imaging unit 11402 does not necessarily have to be located on the camera head 11102. For example, the imaging unit 11402 may be located inside the lens barrel 11101, directly behind the objective lens.

[0305] The drive unit 11403 is composed of actuators and, under control from the camera head control unit 11405, moves the zoom lens and focus lens of the lens unit 11401 along the optical axis by a predetermined distance. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted as appropriate.

[0306] The communication unit 11404 is composed of communication devices for sending and receiving various types of information with the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0307] Furthermore, the communication unit 11404 receives a control signal from the CCU 11201 to control the drive of the camera head 11102 and supplies it to the camera head control unit 11405. The control signal includes information about imaging conditions, such as information to specify the frame rate of the captured image, information to specify the exposure value at the time of imaging, and / or information to specify the magnification and focus of the captured image.

[0308] The imaging conditions such as frame rate, exposure value, magnification, and focus may be specified by the user as appropriate, or they may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with so-called AE (Auto Exposure), AF (Auto Focus), and AWB (Auto White Balance) functions.

[0309] The camera head control unit 11405 controls the drive of the camera head 11102 based on the control signal received from the CCU 11201 via the communication unit 11404.

[0310] The communication unit 11411 is comprised of a communication device for sending and receiving various types of information with the camera head 11102. The communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400.

[0311] Furthermore, the communication unit 11411 transmits control signals to the camera head 11102 to control the driving of the camera head 11102. Image signals and control signals can be transmitted by telecommunications, optical communications, etc.

[0312] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102.

[0313] The control unit 11413 performs various controls related to imaging the surgical area, etc., by the endoscope 11100, and the display of the images obtained from imaging the surgical area, etc. For example, the control unit 11413 generates a control signal to control the driving of the camera head 11102.

[0314] Furthermore, the control unit 11413 displays the captured image showing the surgical area, etc., on the display device 11202 based on the image signal processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical instruments such as forceps, specific biological sites, bleeding, mist when using the energy treatment device 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When the control unit 11413 displays the captured image on the display device 11202, it may use the recognition results to superimpose various surgical support information onto the image of the surgical area. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can proceed with the surgery reliably.

[0315] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable thereof.

[0316] In the illustrated example, communication was performed via a wired connection using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.

[0317] The above describes an example of an endoscopic surgical system to which the technology described herein may be applied. The technology described herein can be applied to the imaging unit 11402 of the configuration described above. By applying the technology described herein to the imaging unit 11402, the detection accuracy is improved.

[0318] While an endoscopic surgical system has been described here as an example, the technology described herein may also be applied to other systems, such as microsurgical systems.

[0319] (Examples of application to mobile devices) The technology disclosed herein can be applied to a variety of products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile device, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, robots, construction machinery, or agricultural machinery (tractors).

[0320] Figure 39 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0321] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 39, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0322] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0323] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0324] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0325] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0326] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0327] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0328] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0329] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0330] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 39, the output devices are exemplified as an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0331] Figure 40 shows an example of the installation position of the imaging unit 12031.

[0332] In Figure 40, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0333] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0334] Figure 40 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0335] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0336] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained in front of the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, etc., that drives autonomously without driver operation, can be performed.

[0337] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0338] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0339] The above describes an example of a mobile object control system to which the technology of this disclosure may be applied. The technology of this disclosure can be applied to the imaging unit 12031 of the configuration described above. Specifically, the light detection device according to the above embodiment and its modified example 1 can be applied to the imaging unit 12031. By applying the technology of this disclosure to the imaging unit 12031, high-resolution images with low noise can be obtained, so that high-precision control using the captured images can be performed in the mobile object control system.

[0340] The present disclosure has been described above with reference to the first to third embodiments and their modifications 1 to 12, as well as application examples and examples of applications. However, the present disclosure is not limited to the above embodiments, and various modifications are possible. For example, the first to third embodiments and their modifications 1 to 12 can be combined with each other.

[0341] The effects described herein are illustrative only. The effects of this disclosure are not limited to those described herein. This disclosure may have effects other than those described herein.

[0342] Furthermore, for example, the present disclosure can take the following configurations. In a photodetector having the following configuration, the capacitance of the through-wiring (FD capacitance) is reduced, and pixel miniaturization is made possible. (1) A photodetector comprising: a first semiconductor layer having a plurality of sensor pixels that perform photoelectric conversion and a separation portion that separates adjacent plurality of sensor pixels; a second semiconductor layer laminated on the first semiconductor layer and having a first surface facing the first semiconductor layer, a second surface opposite to the first surface, and an impurity diffusion region extending between the first surface and the second surface; and a first connection portion electrically connected to the impurity diffusion region from the first surface side of the second semiconductor layer and extending between the first semiconductor layer and the second semiconductor layer, and located on the separation portion in a plan view. (2) The photodetector according to (1), wherein a fixed potential is applied to the first connection portion. (3) The photodetector according to (2), wherein the second semiconductor layer further has a fixed potential wiring on the second surface side, and the impurity diffusion region is electrically connected to the fixed potential wiring. (4) The light detection device according to any one of (1) to (3), wherein the first connection portion is arranged between adjacent sensor pixels in a plan view. (5) The light detection device according to any one of (1) to (4), wherein when the direction perpendicular to the stacking direction of the first semiconductor layer and the second semiconductor layer is defined as the first direction, and the direction perpendicular to the stacking direction and the first direction is defined as the second direction, the ratio of the first width of the first connection portion in the first direction to the second width in the second direction is 1.2 or more. (6) The light detection device according to any one of (1) to (5), wherein the first connection portion extends in one direction between adjacent sensor pixels in a plan view. (7) The photodetector according to any one of (1) to (6), further comprising a pixel circuit that outputs a pixel signal based on the charge output from the sensor pixel, wherein the pixel circuit includes a first transistor and a second transistor, the first transistor being provided in the first semiconductor layer and the second transistor being provided in the second semiconductor layer.(8) The photodetector according to (7), wherein a portion of the impurity diffusion region is used as the source and drain of the second transistor. (9) The photodetector according to (7) or (8), wherein the pixel circuit includes a reset transistor that resets the potential of a charge holding section that temporarily holds the charge generated by photoelectric conversion to a predetermined potential, an amplification transistor that generates a signal of voltage corresponding to the level of the charge held in the charge holding section as the pixel signal, a selection transistor that controls the output timing of the pixel signal from the amplification transistor, and a conversion efficiency switching transistor that switches the conversion efficiency between the charge and the electrical voltage, wherein at least the amplification transistor is provided in the first semiconductor layer as the first transistor, and at least the conversion efficiency switching transistor is provided in the second semiconductor layer as the second transistor. (10) The photodetector according to (9), further having a second connection section that is electrically connected to the drain of the conversion efficiency switching transistor from the first surface side of the second semiconductor layer and extends between the first semiconductor layer and the second semiconductor layer, wherein the second connection section is arranged in parallel with the first connection section. (11) The photodetector according to any one of (1) to (10), wherein the first connection portion is in contact with the separation portion. (12) The photodetector according to any one of (1) to (11), wherein a portion of the first connection portion is embedded in the separation portion. (13) The photodetector according to any one of (1) to (12), wherein the first connection portion is formed comprising polysilicon, polysilicon containing impurities, or a conductive metal material. (14) The photodetector according to any one of (1) to (13), further comprising a conductive layer between the second semiconductor layer and the first connection portion, wherein the second semiconductor layer and the first connection portion are electrically connected via the conductive layer. (15) The photodetector according to (14), wherein the conductive layer comprises epitaxially grown single-crystal silicon, polysilicon, or a conductive metal material.(16) A photodetector comprising: a first semiconductor layer on which a plurality of sensor pixels that perform photoelectric conversion and a third transistor that constitutes a pixel circuit that outputs a pixel signal based on the charge output from the sensor pixels are formed; a semiconductor active layer laminated above the first semiconductor layer so as to overlap with at least a portion of the source or drain of the third transistor in a plan view; a third connection portion that extends between the first semiconductor layer and the semiconductor active layer and electrically connects the semiconductor active layer and the source or drain of the third transistor that overlaps with the semiconductor active layer; and a first laminate in which the semiconductor active layer, a first insulating film and a first electrode film are laminated in this order. (17) The photodetector according to (16), further comprising a second semiconductor layer laminated on the first semiconductor layer, having a first surface facing the first semiconductor layer and a second surface opposite to the first surface, and an impurity diffusion region extending between the first surface and the second surface, wherein the pixel circuit includes the third transistor and a fourth transistor provided on the second semiconductor layer, and the semiconductor active layer and the second semiconductor layer, the first insulating film and the gate insulating film of the fourth transistor, and the first electrode film and the gate electrode of the fourth transistor are each formed in the same layer. (18) The photodetector according to (17), wherein the thickness of the first insulating film is thinner than the thickness of the gate insulating film of the fourth transistor. (19) The photodetector according to (17) or (18), wherein the pixel circuit further includes a fifth transistor provided on the first semiconductor layer, the source of the fourth transistor is connected to the gate of the fifth transistor via a fourth connection from the first surface side of the second semiconductor layer, and the first laminate is provided on a part of the drain of the fourth transistor. (20) The photodetector according to any one of (16) to (19), wherein the semiconductor active layer is processed into a plurality of fin shapes.(21) The photodetector according to any one of (16) to (20), wherein the photodetector further comprises a second semiconductor layer laminated on the first semiconductor layer, having a first surface facing the first semiconductor layer and a second surface opposite to the first surface, and an impurity diffusion region extending between the first surface and the second surface, the semiconductor active layer being the second semiconductor layer having the impurity diffusion region, and the third connection portion being formed containing polysilicon. (22) The photodetector according to any one of (16) to (21), wherein the semiconductor active layer is made of an oxide semiconductor, and the third connection portion is formed containing a conductive metal material. (23) The photodetector according to (22), wherein the first laminate further comprises a second electrode film between the third connection portion and the semiconductor active layer. (24) The photodetector according to any one of (16) to (23), further comprising a second laminate in which a second electrode film, a second insulating film, the semiconductor active layer, the first insulating film, and the first electrode film are stacked in order from a position close to the first semiconductor layer, wherein the semiconductor active layer, the first insulating film, and the first electrode film are provided as a common layer between the first laminate and the second laminate, and the first electrode film and the second electrode film are electrically connected via wiring. (25) The photodetector according to any one of (16) to (23), comprising: a first semiconductor layer on which a plurality of sensor pixels for photoelectric conversion are formed; a second semiconductor layer stacked on the first semiconductor layer and having a first surface facing the first semiconductor layer, a second surface opposite to the first surface, and a first impurity diffusion region extending between the first surface and the second surface; a sixth transistor provided on the first surface side of the second semiconductor layer and having the first impurity diffusion region as its source and drain; and an electrode portion provided on the second surface side of the second semiconductor layer and electrically connected to at least one of the source and the drain of the sixth transistor. (26) The photodetector according to (25), wherein the electrode portion is not connected to any wiring that is electrically connected to any element other than the sixth transistor. (27) The photodetector according to (26), wherein the electrode portion is provided on the first impurity diffusion region that constitutes at least one of the source and the drain of the sixth transistor.(28) The photodetector according to (27), further comprising a fifth connection portion, the fifth connection portion extending between the first semiconductor layer and the second semiconductor layer, electrically connecting the first semiconductor layer and the first impurity diffusion region where the electrode portion is provided. (29) The photodetector according to (28), further comprising a sixth connection portion, the sixth connection portion being provided on the second surface side of the second semiconductor layer, extending in the stacking direction of the first semiconductor layer and the second semiconductor layer, and connected to the electrode portion. (30) The photodetector according to any one of (26) to (29), wherein the electrode portion is formed comprising polysilicon or amorphous silicon. (31) The photodetector according to any one of (27) to (30), further comprising a through-wiring extending in the stacking direction of the first semiconductor layer and the second semiconductor layer and penetrating the second semiconductor layer, the through-wiring being located near the electrode portion and having a fixed potential applied to it. (32) The photodetector according to any one of (28) to (31), further comprising a pixel circuit that outputs a pixel signal based on the charge output from the sensor pixel, wherein the pixel circuit includes the sixth transistor and a seventh transistor provided in the first semiconductor layer, one end of the fifth connection is electrically connected to a second impurity diffusion region constituting the drain of the sixth transistor, and the other end of the fifth connection is electrically connected to the source of the seventh transistor.

[0343] This application claims priority based on Japanese Patent Application No. 2025-054258, filed with the Japan Patent Office on 27 March 2025, and all contents of that application are incorporated herein by reference.

[0344] Those skilled in the art will understand that various modifications, combinations, subcombinations, and changes can be conceived depending on design requirements and other factors, and that these fall within the scope of the attached claims and their equivalents.

Claims

1. A photodetector comprising: a first semiconductor layer having a plurality of sensor pixels that perform photoelectric conversion and a separation portion that separates adjacent plurality of sensor pixels; a second semiconductor layer laminated on the first semiconductor layer and having a first surface facing the first semiconductor layer, a second surface opposite to the first surface, and an impurity diffusion region extending between the first surface and the second surface; and a first connection portion electrically connected to the impurity diffusion region from the first surface side of the second semiconductor layer and extending between the first semiconductor layer and the second semiconductor layer, and located on the separation portion in a plan view.

2. The photodetector according to claim 1, wherein a fixed potential is applied to the first connection portion.

3. The photodetector according to claim 2, further comprising a fixed potential wiring on the second surface side of the second semiconductor layer, wherein the impurity diffusion region is electrically connected to the fixed potential wiring.

4. The light detection device according to claim 1, wherein the first connection portion is arranged between adjacent sensor pixels in a plan view.

5. When the direction perpendicular to the stacking direction of the first semiconductor layer and the second semiconductor layer is defined as the first direction, and the direction perpendicular to the stacking direction and the first direction is defined as the second direction, the ratio of the first width of the first connection portion in the first direction to the second width in the second direction is 1.2 or more, as described in claim 1.

6. The light detection device according to claim 1, wherein the first connection portion extends in one direction between adjacent sensor pixels in a plan view.

7. The photodetector according to claim 1, further comprising a pixel circuit that outputs a pixel signal based on the charge output from the sensor pixel, wherein the pixel circuit includes a first transistor and a second transistor, the first transistor being provided in the first semiconductor layer and the second transistor being provided in the second semiconductor layer.

8. The photodetector according to claim 7, wherein a portion of the impurity diffusion region is used as the source and drain of the second transistor.

9. The photodetector according to claim 7, wherein the pixel circuit includes a reset transistor that resets the potential of a charge holding section that temporarily holds the charge generated by photoelectric conversion to a predetermined potential, an amplification transistor that generates a signal of voltage corresponding to the level of the charge held in the charge holding section as the pixel signal, a selection transistor that controls the output timing of the pixel signal from the amplification transistor, and a conversion efficiency switching transistor that switches the conversion efficiency between the charge and electrical voltage, wherein at least the amplification transistor is provided as the first transistor in the first semiconductor layer, and at least the conversion efficiency switching transistor is provided as the second transistor in the second semiconductor layer.

10. The photodetector according to claim 9, further comprising a second connection portion that is electrically connected to the drain of the conversion efficiency switching transistor from the first surface side of the second semiconductor layer and extends between the first semiconductor layer and the second semiconductor layer, wherein the second connection portion is arranged in parallel with the first connection portion.

11. The photodetector according to claim 1, wherein the first connection portion is in contact with the separation portion.

12. The photodetector according to claim 1, wherein a portion of the first connecting portion is embedded in the separating portion.

13. The photodetector according to claim 1, wherein the first connecting portion is formed of polysilicon, polysilicon containing impurities, or a conductive metal material.

14. The photodetector according to claim 1, further comprising a conductive layer between the second semiconductor layer and the first connection portion, wherein the second semiconductor layer and the first connection portion are electrically connected via the conductive layer.

15. The photodetector according to claim 14, wherein the conductive layer comprises epitaxially grown single-crystal silicon, polysilicon, or a conductive metal material.

16. A photodetector comprising: a first semiconductor layer on which a plurality of sensor pixels that perform photoelectric conversion and a third transistor that constitutes a pixel circuit that outputs a pixel signal based on the charge output from the sensor pixels are formed; a semiconductor active layer laminated above the first semiconductor layer so as to overlap with at least a portion of the source or drain of the third transistor in a plan view; a third connection portion extending between the first semiconductor layer and the semiconductor active layer and electrically connecting the semiconductor active layer and the source or drain of the third transistor that overlaps with the semiconductor active layer; and a first laminate in which the semiconductor active layer, a first insulating film and a first electrode film are laminated in this order.

17. The photodetector according to claim 16, further comprising a second semiconductor layer laminated on the first semiconductor layer, having a first surface facing the first semiconductor layer, a second surface opposite to the first surface, and an impurity diffusion region extending between the first surface and the second surface, wherein the pixel circuit includes the third transistor and a fourth transistor provided on the second semiconductor layer, and the semiconductor active layer and the second semiconductor layer, the first insulating film and the gate insulating film of the fourth transistor, and the first electrode film and the gate electrode of the fourth transistor are each formed in the same layer.

18. The photodetector according to claim 17, wherein the thickness of the first insulating film is thinner than the thickness of the gate insulating film of the fourth transistor.

19. The photodetector according to claim 17, wherein the pixel circuit further includes a fifth transistor provided on the first semiconductor layer, the source of the fourth transistor is connected to the gate of the fifth transistor via a fourth connection portion from the first surface side of the second semiconductor layer, and the first laminate is provided on a part of the drain of the fourth transistor.

20. The photodetector according to claim 16, wherein the semiconductor active layer is processed into a plurality of fin shapes.

21. The photodetector according to claim 16, further comprising a second semiconductor layer laminated on the first semiconductor layer, having a first surface facing the first semiconductor layer, a second surface opposite to the first surface, and an impurity diffusion region extending between the first surface and the second surface, wherein the semiconductor active layer is the second semiconductor layer having the impurity diffusion region, and the third connection portion is formed containing polysilicon.

22. The photodetector according to claim 16, wherein the semiconductor active layer is made of an oxide semiconductor, and the third connecting portion is formed including a conductive metal material.

23. The photodetector according to claim 22, wherein the first laminate further includes a second electrode film between the third connecting portion and the semiconductor active layer.

24. The photodetector according to claim 16, further comprising a second laminate in which a second electrode film, a second insulating film, the semiconductor active layer, the first insulating film, and the first electrode film are stacked in order from a position close to the first semiconductor layer, wherein the semiconductor active layer, the first insulating film, and the first electrode film are provided as a common layer between the first laminate and the second laminate, and the first electrode film and the second electrode film are electrically connected via wiring.

25. A photodetector comprising: a first semiconductor layer on which a plurality of sensor pixels for photoelectric conversion are formed; a second semiconductor layer stacked on the first semiconductor layer and having a first surface facing the first semiconductor layer, a second surface opposite to the first surface, and a first impurity diffusion region extending between the first surface and the second surface; a sixth transistor provided on the first surface side of the second semiconductor layer and having the first impurity diffusion region as its source and drain; and an electrode portion provided on the second surface side of the second semiconductor layer and electrically connected to at least one of the source and the drain of the sixth transistor.

26. The photodetector according to claim 25, wherein no wiring electrically connected to elements other than the sixth transistor is connected to the electrode portion.

27. The photodetector according to claim 26, wherein the electrode portions are provided on the first impurity diffusion region which constitutes at least one of the source and the drain of the sixth transistor.

28. The photodetector according to claim 27, further comprising a fifth connecting portion, the fifth connecting portion extending between the first semiconductor layer and the second semiconductor layer, and electrically connecting the first semiconductor layer and the first impurity diffusion region on which the electrode portion is provided.

29. The photodetector according to claim 28, further comprising a sixth connecting portion, the sixth connecting portion being provided on the second surface side of the second semiconductor layer, extending in the stacking direction of the first semiconductor layer and the second semiconductor layer, and connected to the electrode portion.

30. The photodetector according to claim 26, wherein the electrode portion is formed by including polysilicon or amorphous silicon.

31. The photodetector according to claim 27, further comprising through-wirings that are extended in the stacking direction of the first semiconductor layer and the second semiconductor layer and penetrate the second semiconductor layer, wherein the through-wirings are arranged near the electrode portion and a fixed potential is applied to them.

32. The photodetector according to claim 28, further comprising a pixel circuit that outputs a pixel signal based on the charge output from the sensor pixel, wherein the pixel circuit includes the sixth transistor and a seventh transistor provided in the first semiconductor layer, one end of the fifth connection is electrically connected to a second impurity diffusion region constituting the drain of the sixth transistor, and the other end of the fifth connection is electrically connected to the source of the seventh transistor.

Images