Light detection device

Abstract

A light detection device includes a photoelectric conversion element, a first circuit, first capacitors holding a reset level of the voltage signal for each photoelectric conversion efficiency, second capacitors holding a signal level of a voltage signal for each photoelectric conversion efficiency, a second circuit outputting, to a signal line, a pixel signal generated by selecting the first or second capacitors, a first substrate where at least a part of the photoelectric conversion element and the first circuit are mounted, and a second substrate where the first and second capacitors and the second circuit are mounted.

Description

LIGHT DETECTION DEVICECROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of Japanese Priority Patent Application JP 2025-054508 filed on March 27, 2025, the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a light detection device.

[0003] There has been known a voltage domain global shutter type (hereinafter, referred to as VDGS method) light detection device that simultaneously exposes all pixels, converts charges accumulated by the exposure of the pixels into a voltage, holds the voltage in a capacitor, and reads the held voltage in the capacitor for each pixel row (see PTL 1).

[0004] WO 2023 / 062962 ASummary

[0005] In order to widen a dynamic range, the light detection device of PTL 1 reads a signal level and a reset level separately for a plurality of photoelectric conversion efficiencies. More specifically, after the reset level corresponding to low conversion efficiency is stored in the corresponding capacitor, a discharge (overflow) transistor is turned on to discharge charges to overflow from the photodiode. However, when the discharge transistor is turned on, the overflowing charges may fail to discharge to the power supply voltage node and instead may bloom into the floating diffusion region. This can result in deterioration of image quality.

[0006] Therefore, the present disclosure provides a light detection device capable of preventing deterioration in image quality due to blooming.

[0007] According to the present disclosure, there is provided a light detection device including: a photoelectric conversion element that accumulates charges corresponding to a light amount of incident light; a pre-stage circuit capable of switching a plurality of photoelectric conversion efficiencies, the pre-stage circuit performing control of transferring the accumulated charges of the photoelectric conversion element to a floating diffusion region, control of initializing the accumulated charges of the photoelectric conversion element and retained charges of the floating diffusion region, and control of generating a voltage signal according to the retained charges of the floating diffusion region; a plurality of first capacitors that holds a reset level of the voltage signal for each of the plurality of photoelectric conversion efficiencies; a plurality of second capacitors holds a signal level of the voltage signal for each of the plurality of photoelectric conversion efficiencies; a post-stage circuit that selects one of the plurality of first capacitors and the plurality of second capacitors and outputs a generated pixel signal to a signal line; a first substrate on which the photoelectric conversion element and at least a part of the pre-stage circuit are mounted; and a second substrate laminated on the first substrate and on which the plurality of first capacitors, the plurality of second capacitors, and the post-stage circuit are mounted, in which the pre-stage circuit includes: a third capacitor that stores a part of the accumulated charges of the photoelectric conversion element at a time of selecting the first photoelectric conversion efficiency; a first transistor that transfers the accumulated charges of the photoelectric conversion element to the floating diffusion region; a second transistor that discharges the accumulated charges in the photoelectric conversion element; a third transistor that discharges the accumulated charges of the photoelectric conversion element to a predetermined reference voltage node via the second transistor; a fourth transistor that switches whether or not to block a charge transfer path between the third capacitor and the floating diffusion region; and a fifth transistor that switches whether or not to block a connection node between the second transistor and the third transistor and a connection node between the third capacitor and the fourth transistor.

[0008] The second transistor, the third transistor, and the fifth transistor may be connected to the same first diffusion region.

[0009] The third capacitor, the fourth transistor, and the fifth transistor may be connected to the same second diffusion region.

[0010] The pre-stage circuit may include a sixth transistor that switches whether or not to block a charge transfer path between the fourth transistor and the floating diffusion region, and a third diffusion region may be provided which is disposed in a region surrounded by each gate of the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor and is set to a predetermined reference voltage level.

[0011] The second transistor and the first transistor may be disposed adjacent to the vicinity of the substantially center of the pixel region and substantially parallel to each other.

[0012] One electrode of the third capacitor may be disposed in the same layer as that of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor in the first substrate.

[0013] A pixel isolation region is disposed in a boundary region of a pixel region, and the third capacitor is disposed along the pixel isolation region.

[0014] The third capacitor may be a metal-oxide-semiconductor (MOS) capacitor having a polysilicon gate set to a predetermined reference voltage level.

[0015] The third capacitor may include: a fifth diffusion region of a predetermined conductivity type; an insulating layer disposed along an inner wall of a trench extending in a depth direction from the fifth diffusion region; and a conductive layer disposed inside the trench to cover the insulating layer.

[0016] The third capacitor may have a metal-insulator-metal (MIM) structure.

[0017] A fifth diffusion region connected to the second transistor, the third transistor, and the fifth transistor and a gate region of the second transistor may be disposed at a distance causing capacitive coupling.

[0018] A first wiring layer set to a first reference voltage and a second wiring layer set to a second reference voltage may be disposed between the floating diffusion region and a gate region of the third transistor.

[0019] The pre-stage circuit may include a seventh transistor that converts the charges held in the floating diffusion region into the voltage signal, the post-stage circuit may include: a current source that causes a bias current to flow through the seventh transistor; a tenth transistor that generates the pixel signal according to an output voltage of the pre-stage circuit; an eleventh transistor that outputs the pixel signal to the signal line in synchronization with a selection signal; a plurality of twelfth transistors that switches whether or not to supply a voltage signal corresponding to the reset level held in any one of the plurality of first capacitors to a gate of the tenth transistor; and a plurality of thirteenth transistors that switches whether or not to supply a voltage signal corresponding to the signal level held in any one of the plurality of second capacitors to a gate of the tenth transistor, the current source may include an eighth transistor and a ninth transistor cascode-connected between an output node of the pre-stage circuit and a predetermined reference voltage node, the tenth transistor and the eleventh transistor may be disposed in a first direction with a common drain region,the twelfth transistor and the thirteenth transistor having the same conversion efficiency are disposed in the first direction with a common drain region, and the eighth transistor and the ninth transistor may be disposed in a second direction intersecting the first direction.

[0020] A plurality of pixels may be provided which is arranged in a first direction and a second direction intersecting each other, each of the plurality of pixels may include the photoelectric conversion element, the pre-stage circuit, the plurality of first capacitors, the plurality of second capacitors, and the post-stage circuit, and the two pixels adjacent to each other in at least one of the first direction and the second direction may share at least a part of the third capacitor.

[0021] The third capacitor may be a MOS capacitor having a gate formed of a polysilicon layer, and the polysilicon layer may be disposed along a boundary region between the two pixels adjacent to each other in at least one of the first direction and the second direction.

[0022] A third substrate may be provided which is laminated on the second substrate and on which a logic circuit is mounted.

[0023] According to the present disclosure, there is provided a light detection device including: a photoelectric conversion element that accumulates charges corresponding to a light amount of incident light; a pre-stage circuit capable of switching a plurality of photoelectric conversion efficiencies, the pre-stage circuit performing control of transferring the accumulated charges of the photoelectric conversion element to a floating diffusion region, control of initializing the accumulated charges of the photoelectric conversion element and retained charges of the floating diffusion region, and control of generating a voltage signal according to the retained charges of the floating diffusion region; a plurality of first capacitors that holds a reset level of the voltage signal for each of the plurality of photoelectric conversion efficiencies; a plurality of second capacitors holds a signal level of the voltage signal for each of the plurality of photoelectric conversion efficiencies; a post-stage circuit that selects one of the plurality of first capacitors and the plurality of second capacitors and outputs a generated pixel signal to a signal line; a first substrate on which the photoelectric conversion element, the pre-stage circuit, the plurality of first capacitors, the plurality of second capacitors, and the post-stage circuit are mounted; and a second substrate laminated on the first substrate and on which a logic circuit is mounted, in which the pre-stage circuit includes: a third capacitor that stores a part of the accumulated charges of the photoelectric conversion element at a time of selecting the first photoelectric conversion efficiency; a first transistor that transfers the accumulated charges of the photoelectric conversion element to the floating diffusion region; a second transistor that discharges the accumulated charges in the photoelectric conversion element; a third transistor that discharges the photoelectric conversion element to a predetermined reference voltage node through the second transistor; a fourth transistor that switches whether or not to block a charge transfer path between the third capacitor and the floating diffusion region; a fifth transistor that switches whether or not to block a charge transfer path between a connection node of the third capacitor and the first transistor, and the second transistor; a sixth transistor that switches whether or not to block a charge transfer path between the fourth transistor and the floating diffusion region; and a seventh transistor that converts the charges held in the floating diffusion region into the voltage signal, and the post-stage circuit includes: a current source that is cascode-connected between an output node of the pre-stage circuit and a predetermined reference voltage node and includes an eighth transistor and a ninth transistor that cause a bias current to flow in the seventh transistor; a tenth transistor that generates the pixel signal according to an output voltage of the pre-stage circuit; an eleventh transistor that outputs the pixel signal to the signal line in synchronization with a selection signal; a plurality of twelfth transistors that switches whether or not to supply a voltage signal corresponding to the reset level held in any one of the plurality of first capacitors to a gate of the tenth transistor; and a plurality of thirteenth transistors that switches whether or not to supply a voltage signal corresponding to the signal level held in any one of the plurality of second capacitors to a gate of the tenth transistor.

[0024] The third capacitor may be a metal-oxide-semiconductor (MOS) capacitor disposed on a same layer as that of an arrangement place of each transistor in the pre-stage circuit and the post-stage circuit on the first substrate.

[0025] The MOS capacitor may include a polysilicon gate set to a predetermined reference voltage, and the polysilicon gate may be disposed between an arrangement region of the pre-stage circuit and an arrangement region of the post-stage circuit.

[0026] Two pixels may be provided which are disposed adjacent to each other in a predetermined direction, each of the two pixels may include the photoelectric conversion element, the pre-stage circuit, the plurality of first capacitors, the plurality of second capacitors, and the post-stage circuit, and the polysilicon gate may be disposed along a boundary region between the two pixels.

[0027] Fig. 1 is a block diagram illustrating a configuration of a light detection device according to the present disclosure.Fig. 2 is a circuit diagram of a pixel according to a first example of the present disclosure.Fig. 3 is a block diagram of a load MOS circuit and a column signal processing circuit included in the light detection device of the present disclosure.Fig. 4 is a timing chart of exposure and sample hold of a pixel according to a first example.Fig. 5 is a timing chart of a pixel read operation according to the first example.Fig. 6 is a circuit diagram of a pixel according to a second example of the present disclosure.Fig. 7 is a timing chart of exposure and sample hold of a pixel according to a second example.Fig. 8 is a timing chart of a pixel read operation according to the second example.Fig. 9 is a cross-sectional view of a light detection device according to a first embodiment.Fig. 10 is a layout diagram of one pixel of the light detection device according to the first embodiment.Fig. 11A is a layout diagram of one pixel according to a first modification of the first embodiment.Fig. 11B is a layout diagram of one pixel according to a second modification of the first embodiment.Fig. 11C is a layout diagram of one pixel according to a third modification of the first embodiment.Fig. 11D is a layout diagram of one pixel according to a fourth modification of the first embodiment.Fig. 12A is a layout diagram in a case where MOS capacitors are disposed along two sides of a pixel isolation region.Fig. 12B is a cross-sectional view taken along line A-A' in Fig. 12A.Fig. 13A is a layout diagram illustrating a planar type pixel structure.Fig. 13B is a cross-sectional view taken along line A-A' in Fig. 13A.Fig. 14 is a layout diagram of a pixel region in which an OFG gate and an LCG-FD2 region are disposed close to each other.Fig. 15 is a layout diagram of the pixel region 34 on which measures against crosstalk between a floating diffusion region HCG-FD and an RST gate are taken.Fig. 16 is a layout diagram illustrating a pixel structure in a case where a third capacitor C3 for low conversion efficiency in a pre-stage circuit is configured by a trench capacitor 43.Fig. 17A is a cross-sectional view taken along line A-A' in Fig. 16.Fig. 17B is a cross-sectional view taken along line B-B' in Fig. 16.Fig. 18 is a layout diagram illustrating a pixel structure in which a conductive layer that is a first electrode of a trench capacitor is integrated with a pixel isolation region.Fig. 19 is a cross-sectional view taken along line A-A' in Fig. 18.Fig. 20 is a layout diagram of one pixel in a case where each pixel of a light detection device includes a solid-phase diffusion region according to a second embodiment.Fig. 21 is a cross-sectional view taken along line A-A' in Fig. 20.Fig. 22 is a layout diagram of pixels having a planar structure in the light detection device according to the second embodiment.Fig. 23 is a layout diagram in which an LCG-FD2 region and an OFG gate in each pixel are disposed close to each other in the light detection device according to the second embodiment.Fig. 24 is a layout diagram illustrating a countermeasure against crosstalk between a floating diffusion region HCG-FD and an RST gate in each pixel of the light detection device according to the second embodiment.Fig. 25 is a cross-sectional view of a light detection device according to a third embodiment.Fig. 26 is a cross-sectional view of a light detection device according to a first modification of the third embodiment.Fig. 27 is a cross-sectional view of a light detection device according to a second modification of the third embodiment.Fig. 28 is a circuit diagram of a pixel of a light detection device according to a fourth embodiment.Fig. 29 is a layout diagram of each transistor disposed on a second substrate of the pixel in Fig. 28.Fig. 30 is a circuit diagram of a pixel of a light detection device according to a modification of the fourth embodiment.Fig. 31 is a layout diagram of each transistor disposed on a second substrate of the pixel in Fig. 30.Fig. 32 is a layout diagram of 2×2 pixels of a light detection device according to a fifth embodiment.Fig. 33 is a layout diagram of 2×2 pixels of a light detection device according to a first comparative example.Fig. 34A is a layout diagram illustrating an example in which a polysilicon gate of a MOS capacitor is shared by a plurality of pixels along one side of a pixel isolation region.Fig. 34B is a layout diagram illustrating an example in which the polysilicon gate of the MOS capacitor is shared by the plurality of pixels along one side of the pixel isolation region.Fig. 34C is a layout diagram illustrating an example in which the polysilicon gate of the MOS capacitor is shared by the plurality of pixels along two sides of the pixel isolation region.Fig. 34D is a layout diagram illustrating an example in which the polysilicon gate of the MOS capacitor is shared by the plurality of pixels along three sides of the pixel isolation region.Fig. 34E is a layout diagram illustrating an example in which the polysilicon gate of the MOS capacitor is shared by the plurality of pixels along four sides of the pixel isolation region.Fig. 35 is a layout diagram of one pixel in a case where a third capacitor C3 includes a trench capacitor 43.Fig. 36A is a cross-sectional view taken along line A-A' in Fig. 35.Fig. 36B is a cross-sectional view taken along line B-B' in Fig. 35.Fig. 37 is a layout diagram of a semiconductor chip according to a first modification of the fifth embodiment.Fig. 38 is a layout diagram of a semiconductor chip according to a second modification of the fifth embodiment.Fig. 39 is a layout diagram of a semiconductor chip according to a comparative example.Fig. 40 is a layout diagram of a semiconductor chip according to a third modification of the fifth embodiment.Fig. 41 is a layout diagram of a semiconductor chip according to a fourth modification of the fifth embodiment.Fig. 42 is a layout diagram of a semiconductor chip according to a fifth modification of the fifth embodiment.Fig. 43 is a layout diagram of 2×2 pixels according to a sixth modification of the fifth embodiment.Fig. 44 is a layout diagram of 2×2 pixels according to a seventh modification of the fifth embodiment.Fig. 45 is a layout diagram of 2×2 pixels according to an eighth modification of the fifth embodiment.Fig. 46 is a layout diagram of 2×2 pixels according to a ninth modification of the fifth embodiment.Fig. 47 is a layout diagram of 2×2 pixels according to a tenth modification of the fifth embodiment.Fig. 48 is a layout diagram of 2×2 pixels according to an eleventh modification of the fifth embodiment.Fig. 49A is a cross-sectional view taken along line A-A' in Fig. 48.Fig. 49B is a cross-sectional view taken along line B-B' in Fig. 48.Fig. 49C is a cross-sectional view of a modification of Fig. 49B.Fig. 50A is a layout diagram of 2×2 pixels according to a twelfth modification of the fifth embodiment.Fig. 50B is a layout diagram of 2×2 pixels according to a thirteenth modification of the fifth embodiment.Fig. 50C is a layout diagram of 2×2 pixels according to a fourteenth modification of the fifth embodiment.Fig. 51A is a layout diagram of 2×2 pixels according to a fifteenth modification of the fifth embodiment.Fig. 51B is a layout diagram of 2×2 pixels according to a comparative example of the fifteenth modification.Fig. 52A is a layout diagram of 2×2 pixels according to a sixteenth modification of the fifth embodiment.Fig. 52B is a layout diagram of 2×2 pixels according to a comparative example of the sixteenth modification.Fig. 53A is a layout diagram of 2×2 pixels according to a seventeenth modification of the fifth embodiment.Fig. 53B is a layout diagram of 2×2 pixels according to a comparative example of the seventeenth modification.Fig. 54 is a cross-sectional view of a light detection device according to a sixth embodiment.Fig. 55 is a layout diagram of one pixel of a light detection device according to the sixth embodiment.Fig. 56 is a layout diagram of one pixel of a light detection device according to a first modification of the sixth embodiment.Fig. 57 is a layout diagram of 2×1 pixels of a light detection device according to a second modification of the sixth embodiment.Fig. 58 is a layout diagram of 2×2 pixels of a light detection device according to a third modification of the sixth embodiment.Fig. 59 is a cross-sectional view of a light detection device according to a fourth modification of the sixth embodiment.Fig. 60 is a layout diagram of a wiring region 25 of a first substrate in Fig. 59.Fig. 61 is a layout diagram of one pixel of a light detection device according to a fifth modification of the sixth embodiment.Fig. 62 is a layout diagram of one pixel of a light detection device according to a sixth modification of the sixth embodiment.Fig. 63 is a diagram illustrating an appearance example of an information processing system according to the present disclosure.Fig. 64 is a diagram illustrating an appearance example of an information processing system according to a modification of the present disclosure.Fig. 65 is a block diagram illustrating a hardware configuration example of the information processing system.Fig. 66 is a block diagram illustrating an example of a schematic configuration of a vehicle control system.Fig. 67 is an explanatory diagram illustrating an example of installation positions of a vehicle exterior information detection unit and an imaging unit.

[0028] Hereinafter, embodiments of a light detection device will be described with reference to the drawings. In the following, main components of the light detection device will be described, but the light detection device may have components and functions that are not illustrated or described. The following description does not exclude the components and functions that are not illustrated or described.

[0029] Fig. 1 is a block diagram illustrating a configuration of a light detection device 1 according to the present disclosure. The light detection device 1 of Fig. 1 may be referred to as an image sensor. The light detection device 1 of Fig. 1 includes a vertical scanning circuit 2, a pixel array unit 3, a timing control circuit 4, a digital to analog converter (DAC) 5, a load metal-oxide-semiconductor (MOS) circuit 6, and a column signal processing circuit 7.

[0030] The pixel array unit 3 includes a plurality of pixels PX arranged in a first direction (for example, a row direction) X and a second direction (for example, a column direction) Y. Furthermore, the pixel array unit 3 includes a plurality of row selection lines 8 each extending in the first direction X and provided corresponding to a plurality of pixel rows arranged in the second direction Y, and a plurality of vertical signal lines VSL each extending in the second direction Y and provided corresponding to a plurality of pixel columns arranged in the first direction X.

[0031] The timing control circuit 4 controls operational timings of the vertical scanning circuit 2, the DAC 5, and the column signal processing circuit 7 in synchronization with a vertical synchronization signal.

[0032] The vertical scanning circuit 2 sequentially drives the plurality of row selection lines 8. Each pixel PX of each pixel row outputs a pixel signal to the corresponding vertical signal line VSL in synchronization with the timing at which the vertical scanning circuit 2 drives the corresponding row selection line 8.

[0033] The DAC 5 generates a sawtooth shaped ramp signal based on a digital signal from the timing control circuit 4. The ramp signal generated by the DAC 5 is supplied to the column signal processing circuit 7.

[0034] The load MOS circuit 6 includes a plurality of MOS transistors that supply a constant current to each of the plurality of vertical signal lines VSL.

[0035] The column signal processing circuit 7 performs signal processing such as analog to digital (AD) conversion processing and correlated double sampling (CDS) processing of a pixel signal for each pixel column (vertical signal line VSL) to generate image data in units of frames. The generated image data is supplied to a logic circuit (not illustrated in Fig. 1).

[0036] Fig. 2 is a circuit diagram of a pixel PX according to a first example of the present disclosure. The pixel PX according to the first example, has a configuration capable of switching between two photoelectric conversion efficiencies. The pixel PX according to the first example includes a pre-stage circuit 11, a plurality of first capacitors C1 and a plurality of second capacitors C2 for sample hold of a reset level and a signal level, and a post-stage circuit 12. Each of transistors in the pre-stage circuit 11 and the post-stage circuit 12 is, for example, an NMOS transistor.

[0037] The pre-stage circuit 11 includes a photoelectric conversion element PD, a TRG transistor (first transistor) Q1, an RST transistor (third transistor) Q2, a floating diffusion region HCG-FD, an SF1 transistor (seventh transistor) Q3, a CLP transistor Q4, an SW transistor Q5, a PC transistor (eighth transistor) Q6, a VB transistor (ninth transistor) Q7, an OFG transistor (second transistor) Q8, an FCG transistor (fourth transistor) Q9, a FLG transistor (fifth transistor) Q10, and a third capacitor C3.

[0038] The photoelectric conversion element PD generates charges by photoelectric conversion. The photoelectric conversion element PD is, for example, a photodiode. The TRG transistor Q1 transfers the accumulated charge of the photoelectric conversion element PD to the floating diffusion region HCG-FD in synchronization with a transfer signal TRG from the vertical scanning circuit 2. The floating diffusion region HCG-FD holds the charges transferred from the photoelectric conversion element PD via the TRG transistor Q1 and converts the charges into voltage.

[0039] The OFG transistor Q8 is connected to the photoelectric conversion element PD. The OFG transistor Q8 is provided to discharge charges overflowing from the photoelectric conversion element PD.

[0040] The RST transistor Q2 discharges the accumulated charges of the photoelectric conversion element PD and the retained charges of the floating diffusion region HCG-FD to the VDD node in synchronization with a reset signal RST from the vertical scanning circuit 2 and initializes the charges.

[0041] The FCG transistor Q9 is provided to switch photoelectric conversion efficiency. While the FCG transistor Q9 is off, the high conversion efficiency HCG is selected. At the time of high conversion efficiency, a pixel signal is generated based on the charges retained in the floating diffusion region HCG-FD. While the FCG transistor Q9 is on, a low conversion efficiency LCG is selected. At the time of low conversion efficiency, a pixel signal is generated based on the charges retained in the third capacitor C3 and the charges retained in the floating diffusion region HCG-FD. In the present specification, the third capacitor C3 may be referred to as an additional capacitance.

[0042] A gate of the SF1 transistor Q3 is connected to the floating diffusion region HCG-FD. The SF1 transistor Q3 configures a source follower circuit that outputs a voltage corresponding to the voltage of the floating diffusion region HCG-FD to a source side.

[0043] The CLP transistor Q4 is connected in parallel with the SF1 transistor Q3. The switching signal CLP from the vertical scanning circuit 2 is input to a gate of the CLP transistor Q4. In a case where the switching signal CLP becomes high, the CLP transistor Q4 is turned on, and a power supply voltage is supplied to one of the ends of the plurality of first capacitors C1 and the plurality of second capacitors C2. In a case where the switching signal CLP becomes a low level, a source voltage of the SF1 transistor Q3 is held in the plurality of first capacitors C1 and the plurality of second capacitors C2. The SW transistor Q5 performs similar operations as that of the CLP transistor Q4.

[0044] The PC transistor Q6 and the VB transistor Q7 configure a current source 13. The PC transistor Q6 causes a constant current corresponding to the bias voltage PC to flow between the drain and the source. The VB transistor Q7 causes a constant current corresponding to the bias voltage VB to flow between the drain and the source. The current source 13 includes the PC transistor Q6 and the VB transistor Q7, and separate bias voltages PC and VB are input to gates of the transistors, and thus noise can be reduced.

[0045] The plurality of first capacitors C1 holds a reset level of the voltage signal of the floating diffusion region HCG-FD for each of the plurality of photoelectric conversion efficiencies. The plurality of second capacitors C2 holds a signal level of the voltage signal of the floating diffusion region HCG-FD for each of the plurality of photoelectric conversion efficiencies.

[0046] In the pixel PX according to the first example, the pixel PX is configured to switch between two photoelectric conversion efficiencies and includes two first capacitors C1 and two second capacitors C2, with each pair corresponding to a respective one of the two photoelectric conversion efficiencies.

[0047] The power supply voltage VDD supplied to the pre-stage circuit 11 may be configured to switch, for example, power supply voltages of a plurality of voltage levels. Furthermore, the power supply voltage VDD is not necessarily at the same voltage level as the power supply voltage of the light detection device 1. For example, different voltages may be supplied to the pre-stage circuit 11 at the time of exposure (collective) and at the time of reading (sequential). Therefore, the circuit noise (for example, random noise) of the SF1 transistor Q3 can be reduced.

[0048] The post-stage circuit 12 includes a selection circuit 14 that selects any one of the plurality of first capacitors C1 and the plurality of second capacitors C2, an RB transistor Q11 that initializes a voltage level of an output node of the selection circuit 14, an SF2 transistor (tenth transistor) Q12 configuring a source follower circuit that outputs a pixel signal of a voltage corresponding to a voltage of the output node of the selection circuit 14 to a source side, and an SEL transistor (eleventh transistor) Q13 that outputs the pixel signal to a corresponding vertical signal line VSL in synchronization with a selection signal SEL of the row selection line 8 from the vertical scanning circuit 2.

[0049] The selection circuit 14 includes an SRH transistor (twelfth transistor) Q14 connected to a first capacitor CRH for high conversion efficiency, an SRL transistor Q15 connected to a first capacitor CRL for low conversion efficiency, an SDH transistor (thirteenth transistor) Q16 connected to a second capacitor CDH for high conversion efficiency, and an SDL transistor Q17 connected to a second capacitor CDL for low conversion efficiency. In the present specification, the first capacitors CRH and CRL may be collectively referred to as a first capacitor C1, and the second capacitors CDH and CDL may be collectively referred to as a second capacitor C2.

[0050] The high conversion efficiency HCG has higher photoelectric conversion efficiency than low conversion efficiency. The high conversion efficiency is conversion efficiency in a case where the pixel signal is generated based on the charges retained in the floating diffusion region HCG-FD while the FCG transistor Q9 is turned off. The low conversion efficiency is conversion efficiency in a case where the pixel signal is generated based on the charges retained at the connection node of the third capacitor C3, the FLG transistor Q10, and the FCG transistor Q9 and a connection node of the OFG transistor Q8 and the RST transistor Q2 while the FCG transistor Q9 is on. In the present specification, a connection node of the third capacitor C3, the FLG transistor Q10, and the FCG transistor Q9 may be referred to as LCG-FD1, and a connection node of the OFG transistor Q8 and the RST transistor Q2 may be referred to as LCG-FD2.

[0051] In the present specification, the capacitance values of the first capacitor CRH (CRH) and the second capacitor C2 (CDH) for high conversion efficiency are the same. Furthermore, capacitance values of the first capacitor CRL (CRL) and the second capacitor C2 (CDL) for low conversion efficiency are also the same. Furthermore, the total capacitance value of the first capacitor CRH (CRH) and the second capacitor C2 for high conversion efficiency is larger than a total capacitance value of the first capacitor CRL (CRL) and the second capacitor C2 (CDL) for low conversion efficiency. In a case where the low conversion efficiency is selected, an optical shot noise becomes dominant as compared with the case where the high conversion efficiency is set, and a kTC noise generated at the time of sample hold does not significantly affect the image quality. On the other hand, in a case where the high conversion efficiency is selected, an adverse effect due to the kTC noise becomes relatively large. Furthermore, normally, in a case where a signal is sampled and held in a capacitive element, as the capacitance value is increased, the kTC noise at the time of sample and hold can be reduced. Therefore, by relatively increasing the capacitance value of the capacitive element corresponding to the HCG more influenced by the kTC noise, the kTC noise can be suppressed, and the image quality can be improved.

[0052] The post-stage circuit 12 sequentially reads the reset level and the signal level with high conversion efficiency and the reset level and the signal level with low conversion efficiency after the exposure ends.

[0053] The column signal processing circuit 7 performs CGS processing for obtaining a difference between a reset level corresponding to a high conversion efficiency and a signal level corresponding to the high conversion efficiency and generates a digital signal corresponding to the high conversion efficiency. Furthermore, the column signal processing circuit 7 performs CGS processing for obtaining a difference between a reset level corresponding to the low conversion efficiency and a signal level corresponding to the low conversion efficiency and generates a digital pixel signal corresponding to the low conversion efficiency.

[0054] Furthermore, the column signal processing circuit 7 determines whether illuminance is higher than a predetermined value in units of frames or in units of pixels. Then, the column signal processing circuit 7 outputs a digital pixel signal corresponding to the low conversion efficiency LCG in a case where the illuminance is high, and outputs a digital pixel signal corresponding to the high conversion efficiency HCG in a case where the illuminance is low.

[0055] In a case where the photoelectric conversion efficiency is switched according to the illuminance in units of frames, it is possible to prevent an insufficient saturation charge amount and sensitivity, and to improve image quality. Furthermore, in a case where the photoelectric conversion efficiency is switched according to the illuminance in units of pixels, a dynamic range can be expanded, and it is not necessary to perform imaging with different photoelectric conversion efficiency for each frame, and thus a decrease in the frame rate can be suppressed, and the image quality can be improved.

[0056] Furthermore, the vertical scanning circuit 2 controls the TRG transistor to transfer the signal charge to the floating diffusion region HCG-FD at the end of the exposure, but in a case where the illuminance is relatively high, there is a possibility that the charge overflowing from the photoelectric conversion element PD leaks to the floating diffusion region HCG-FD via the discharge transistor. This phenomenon is referred to as blooming. In the light detection device 1 of the VDGS method, a period from a time of transferring the signal charges to a time of sampling the signal level is relatively long, and several microseconds to several hundred microseconds are needed. If the charges generated by blooming are leaked to the floating diffusion region HCG-FD within this period, the signal level changes, and the image quality may be deteriorated.

[0057] Therefore, immediately after the charge transfer, the vertical scanning circuit 2 causes the FLG transistor Q10 to transition from on to off and causes the RST transistor Q2 and the OFG transistor Q8 to transition from off to on. With this control, charges generated by blooming can be discharged to the power supply side via the OFG transistor Q8 and the RST transistor Q2 which are in the ON state. At this time, since the FLG transistor Q10 is off, there is no possibility that charges leak from the OFG transistor Q8 to the third capacitor C3 via the FCG transistor Q9. Therefore, contamination with charges leaked due to blooming can be prevented, and image quality can be improved.

[0058] (Configuration of column signal processing circuit 7) Fig. 3 is a block diagram of the load MOS circuit 6 and the column signal processing circuit 7 included in the light detection device 1 of the present disclosure. A plurality of vertical signal lines VSL corresponding to a plurality of pixel columns is connected to the load MOS circuit 6. The load MOS circuit 6 includes a plurality of load MOS transistors Q18 connected to the plurality of vertical signal lines VSL. Each load MOS transistor Q18 causes a constant current to flow through the corresponding vertical signal line VSL.

[0059] The column signal processing circuit 7 includes a plurality of analog to digital converters (ADCs) 15 connected to a plurality of vertical signal lines VSL, and a digital signal processing circuit 16. Each ADC 15 is provided for each vertical signal line VSL. Each ADC 15 performs AD conversion on the pixel signal by comparing the corresponding pixel signal on the vertical signal line VSL with the ramp signal from the DAC 5. In the present specification, the pixel signal AD-converted by the ADC 15 is referred to as a digital pixel signal. Each ADC 15 is, for example, a single-slope ADC 15 having a comparator and a counter (not illustrated).

[0060] The digital signal processing circuit 16 performs predetermined signal processing such as CDS processing on the digital pixel signal to generate image data for each frame.

[0061] (Timing of exposure and sample hold of pixel PX according to first example) Fig. 4 is a timing chart of exposure and sample hold of the pixel PX according to the first example. Fig. 4 illustrates voltage waveforms of the transfer signal TRG input to a gate of the TRG transistor Q1, the reset signal RST input to a gate of the RST transistor Q2, a control signal FCG input to a gate of the FCG transistor Q9, a discharge signal OFG input to a gate of the OFG transistor Q8, a control signal FLG input to a gate of the FLG transistor Q10, a selection signal SRH input to a gate of the SRH transistor Q14, a selection signal SDH input to a gate of the SDH transistor Q16, a selection signal SRM input to a gate of the SRM transistor, a selection signal SDM input to a gate of the SDM transistor, a switching signal CLP input to a gate of the CLP transistor Q4, a selection signal SEL input to a gate of the SEL transistor Q13, and a reset signal RB input to a gate of the RB transistor Q11, an on / off timing of the current source 13 including the PC transistor Q6 and the VB transistor Q7 and an on / off timing of the load MOS circuit 6.

[0062] The control signal FLG is set to the high level before the exposure is started. From time t0 immediately before the exposure is started, the vertical scanning circuit 2 sets the transfer signal TRG, the reset signal RST, the control signal FCG, and the discharge signal OFG to the high level for all the pixels PX in all the rows. Therefore, all the pixels PX are initialized, and exposure is simultaneously started in all the pixels PX.

[0063] Subsequently, the vertical scanning circuit 2 supplies a high-level reset signal RB to all the pixels PX in all the rows at time t1 immediately before the exposure ends. Furthermore, the vertical scanning circuit 2 supplies the high-level control signal FCG to all the pixels PX in all the rows during a predetermined pulse period from the time t1.

[0064] After time t1, the vertical scanning circuit 2 turns on the PC transistor Q6 and the VB transistor Q7 configuring the current sources 13 of all the pixels PX in all the rows and causes a current id1 to flow to the current source 13. If the current id1 becomes a large current, an IR drop becomes large, and thus the current id1 flowing through the current source 13 is controlled to be several nanoamperes to several tens of nanoamperes. At this time, each load MOS transistor Q18 in the load MOS circuit 6 is turned off, and no current flows through the vertical signal line VSL.

[0065] The vertical scanning circuit 2 supplies the high-level selection signal SRH to all the pixels PX in all the rows during a predetermined pulse period from the time t2. At this time, since the FCG transistor Q9 is off, the high conversion efficiency HCG is selected, and the first capacitor CRH for high conversion efficiency holds the reset level at the time of high conversion efficiency.

[0066] The vertical scanning circuit 2 supplies the high-level transfer signal TRG to all the pixels PX in all the rows during a predetermined pulse period from time t3 at the end of the exposure. Therefore, the signal charges in all the pixels PX are transferred from the photoelectric conversion element PD to the floating diffusion region HCG-FD via the TRG transistor Q1, and the exposure is terminated. In each pixel PX, it is necessary to separately sample the signal level at the time of high conversion efficiency and the signal level at the time of low conversion efficiency, but the TRG transistor is turned on only once. The potential in the pixel PX is adjusted, and thus the charges of the photoelectric conversion element PD can be transferred only by one transfer of the TRG transistor.

[0067] The vertical scanning circuit 2 supplies the low-level control signal FLG to all the pixels PX in all the rows at time t4 immediately after the time t3 and sets the reset signal RST and the discharge signal OFG of all the pixels PX in all the rows to the high level at time t5 immediately after time t4. Therefore, the FLG transistor Q10 is turned off, and the RST transistor Q2 and the OFG transistor Q8 are turned on. Therefore, the charge generated by blooming is discharged to the VDD node via the OFG transistor Q8 and the RST transistor Q2, and it is possible to prevent the charges from leaking to the third capacitor C3 and the floating diffusion region HCG-FD via the FLG transistor Q10.

[0068] The vertical scanning circuit 2 supplies the high-level selection signal SDH to all the pixels PX in all the rows during a predetermined pulse period from time t6. At this time, since the FCG transistor Q9 is turned off, the signal level generated by the high conversion efficiency HCG is held in the second capacitor CDH for high conversion efficiency.

[0069] The vertical scanning circuit 2 sets the control signal FCG of all the pixels PX in all the rows to the high level at time t7 and supplies the high-level selection signal SDM to all the pixels PX in all the rows during a predetermined pulse period from time t8 immediately after that. At this time, since the FCG transistor Q9 is on, the signal level generated by the low conversion efficiency LCG is held in the second capacitor CDL for low conversion efficiency.

[0070] The vertical scanning circuit 2 supplies the high-level control signal FLG to all the pixels PX in all the rows during a predetermined pulse period from time t9. Therefore, a floating diffusion region HCG-FD of all the pixels PX in all the rows is initialized.

[0071] The vertical scanning circuit 2 supplies the high-level selection signal SRM to all the pixels PX in all the rows during a predetermined pulse period from time t10. At this time, since the FCG transistor Q9 is on, a reset level generated with low conversion efficiency is held in the first capacitor CRL for low conversion efficiency.

[0072] At time t11, the vertical scanning circuit 2 sets the reset signals and the control signals FCG of all the pixels PX in all the rows to the low level and supplies the high-level switching signal CLP to all the pixels PX in all the rows. Furthermore, the vertical scanning circuit 2 stops the supply of the current id1 from the current source 13 in all the pixels PX in all the rows at time t11 and starts the supply of a current id2 from the load MOS circuit 6 to all the vertical signal lines VSL.

[0073] Fig. 5 is a timing chart of the read operation of the pixel PX according to the first example. The read operation is performed after the exposure and sampling operations in Fig. 4 are completed. The read operation is performed for each pixel row. Fig. 5 illustrates timing of the operation of reading the pixel signals of the nth (n is any integer from 1 to the total number of pixel rows) row. In a case of reading the pixel signals of the nth row, the vertical scanning circuit 2 sets the selection signal SEL of the nth row to the high level.

[0074] As illustrated in Fig. 5, at the time of reading the pixel signal, the logic of the transfer signal TRG, the reset signal RST, the control signal FCG, the discharge signal FG, and the control signal FLG is irrelevant.

[0075] The vertical scanning circuit 2 supplies a high-level reset signal RB to the nth row during a predetermined pulse period from time t20. Therefore, even if a parasitic capacitance exists in the gate wiring of the SF2 transistor Q12, a signal history of a previous frame held by the parasitic capacitance can be erased.

[0076] The vertical scanning circuit 2 supplies a high-level selection signal to the nth row during a predetermined pulse period from time t21. Therefore, the reset level generated by the high conversion efficiency HCG is read.

[0077] The vertical scanning circuit 2 supplies the high-level reset signal RB to the nth row during a predetermined pulse period from time t22 and supplies the high-level selection signal SDH to the nth row during a predetermined pulse period from time t23. Therefore, the signal level generated by the high conversion efficiency HCG is read.

[0078] The vertical scanning circuit 2 supplies the high-level reset signal RB to the nth row during a predetermined pulse period from time t24 and supplies the high-level selection signal SRM to the nth row during a predetermined pulse period from time t25. Therefore, the reset level generated by the low conversion efficiency LCG is read.

[0079] The vertical scanning circuit 2 supplies the high-level reset signal RB to the nth row during a predetermined pulse period from time t26 and supplies the high-level selection signal SDM to the nth row during a predetermined pulse period from time t27. Therefore, the signal level generated by the low conversion efficiency LCG is read.

[0080] The vertical scanning circuit 2 continuously sets the switching signal SW of all the pixels PX in all the rows to the high level during the read period (time t20 to t28), stops the current id1 from the current source 13 of all the pixels PX, and supplies the current id2 from the load MOS circuit 6 to all the vertical signal lines VSL.

[0081] Fig. 6 is a circuit diagram of a pixel PX according to a second example of the present disclosure. The pixel PX according to the second example illustrated in Fig. 6 includes, in addition to the configuration of the pixel PX according to the first example illustrated in Fig. 2, an FDG transistor (sixth transistor) Q20, a first capacitor CRM that holds a reset level of middle conversion efficiency, a second capacitor CDM that holds a signal level of middle conversion efficiency, an SRM transistor Q21 that switches whether or not to select the reset level held in the first capacitor CRM for middle conversion efficiency, and an SDM transistor Q22 that switches whether or not to select the signal level held in the second capacitor CDM for middle conversion efficiency. In the present specification, the first capacitors CRH, CRM, and CRL that hold reset levels for high conversion efficiency, medium conversion efficiency, and low conversion efficiency may be collectively referred to as a first capacitor C1, and the second capacitors CDH, CDM, and CDL that hold signal levels for high conversion efficiency, medium conversion efficiency, and low conversion efficiency may be collectively referred to as a second capacitor C2.

[0082] The FDG transistor Q20 is disposed between the floating diffusion region HCG-FD and the FCG transistor Q9. The FDG transistor Q20 is switched on or off based on a control signal FDG from the vertical scanning circuit 2. In the present specification, a connection node between the FDG transistor Q20 and the FCG transistor Q9 may be referred to as MCG-FD.

[0083] One end of each of the first capacitor CRM and the second capacitor CDM for medium conversion efficiency is connected to the source of the SW transistor Q5. The SRM transistor Q21 switches whether to supply the reset level held in the first capacitor CRM for medium conversion efficiency to a gate of the SF2 transistor Q12 based on the selection signal SRM from the vertical scanning circuit 2. The SDM transistor Q22 switches whether to supply the signal level held in the second capacitor CDM for medium conversion efficiency to the gate of the SF2 transistor Q12 based on the selection signal SDM from the vertical scanning circuit 2.

[0084] Among the FCG transistor Q9 and the FDG transistor Q20, in a case where only the FDG transistor Q20 is turned on, the photoelectric conversion efficiency is lower than that in a case where both the FCG transistor Q9 and the FDG transistor Q20 are turned off. Furthermore, in a case where both the FCG transistor Q9 and the FDG transistor Q20 are on, the photoelectric conversion efficiency is lower than that in a case where only the FDG transistor Q20 is on.

[0085] As described above, in the pixel PX according to the second example, the photoelectric conversion efficiency is switched into three stages of high conversion efficiency, medium conversion efficiency, and low conversion efficiency. By switching the photoelectric conversion efficiency into three stages, sensitivity can be further improved as compared with switching in two stages.

[0086] It is desirable that the first capacitor CRH and the second capacitor C2 for high conversion efficiency have larger capacitance values than the first capacitor CRL and the second capacitor C2 for medium conversion efficiency and low conversion efficiency. Furthermore, it is desirable that the first capacitor CRM and the second capacitor CDM for medium conversion efficiency have the same capacitance value as the first capacitor CRL and the second capacitor C2 for low conversion efficiency.

[0087] It should be noted the photoelectric conversion efficiency may be switched into four or more stages. In this case, it is necessary to increase the number of transistors for switching the conversion efficiency and the first capacitor C1 and the second capacitor C2 for sample hold.

[0088] Fig. 7 is a timing chart of exposure and sample hold of the pixel PX according to the second example. The control signal FLG is set to a high level before the exposure is started. The vertical scanning circuit 2 sets the transfer signal TRG, the reset signal RST, the control signal FCG, the control signal FDG, and the discharge signal OFG supplied to all the pixels PX in all the rows to the high level during a predetermined pulse period from time t0 immediately before the exposure is started. Therefore, all the pixels PX are initialized and exposure is simultaneously started.

[0089] The vertical scanning circuit 2 sets both the reset signal RB and the control signal FDG supplied to all the pixels PX in all the rows to the high level at time t1 before the exposure ends. Furthermore, the vertical scanning circuit 2 supplies the high-level control signal FCG to all the pixels PX in all the rows during a predetermined pulse period from the time t1.

[0090] The vertical scanning circuit 2 causes the current id1 to flow to the current sources 13 in all the pixels PX in all the rows after the time t1. On the other hand, the load MOS circuit 6 stops the supply of the current to each vertical signal line VSL.

[0091] The vertical scanning circuit 2 supplies the high-level selection signal SRM to all the pixels PX in all the rows during a predetermined pulse period from the time t2. At this time, since the FCG transistor Q9 is off and the FDG transistor Q20 is on, the first capacitor CRM for medium conversion efficiency holds the reset level generated by the medium conversion efficiency.

[0092] The vertical scanning circuit 2 supplies the low-level control signal FDG to all the pixels PX in all the rows at time t3 and supplies the high-level selection signal SRH to all the pixels PX in all the rows during a predetermined pulse period from time t4. At this time, since both the FCG transistor Q9 and the FDG transistor Q20 are off, the first capacitor CRH for high conversion efficiency holds the reset level generated by the high conversion efficiency.

[0093] The vertical scanning circuit 2 supplies the high-level transfer signal TRG to all the pixels PX in all the rows during a predetermined pulse period from time t5 at which the exposure ends. Therefore, the signal charges are transferred to the floating diffusion region HCG-FD in all the pixels PX, and the exposure of all the pixels PX ends.

[0094] The vertical scanning circuit 2 supplies the low-level control signal FLG to all the pixels PX in all the rows at time t6 immediately after time t5 and sets both the reset signal RST and the discharge signal OFG to the high level at time t7 immediately after that.

[0095] The vertical scanning circuit 2 supplies the high-level selection signal SDH to all the pixels PX in all the rows during a predetermined pulse period from time t8. At this time, since both the FCG transistor Q9 and the FDG transistor Q20 are off, the signal level generated with high conversion efficiency is held.

[0096] The vertical scanning circuit 2 supplies the high-level control signal FDG to all the pixels PX in all the rows at time t9 and supplies the high-level selection signal SDM to all the pixels PX in all the rows during a predetermined pulse period from time t10 immediately after that. At this time, since the FCG transistor Q9 is off and the FDG transistor Q20 is on, the second capacitor CDM for medium conversion efficiency holds the signal level generated by medium conversion efficiency.

[0097] The vertical scanning circuit 2 supplies the high-level control signal FCG to all the pixels PX in all the rows at time t11 and supplies the high-level selection signal SDL to all the pixels PX in all the rows during a predetermined pulse period from time t12 immediately after that. At this time, since both the FCG transistor Q9 and the FDG transistor Q20 are turned on, the second capacitor CDL for low conversion efficiency holds the signal level generated by the low conversion efficiency.

[0098] The vertical scanning circuit 2 supplies the high-level control signal FLG to all the pixels PX in all the rows during a predetermined pulse period from time t13 and supplies the high-level selection signal SRL to all the pixels PX in all the rows during a predetermined pulse period from time t14. At this time, since both the FCG transistor Q9 and the FDG transistor Q20 are on, the first capacitor CRL for low conversion efficiency holds the reset level generated by the low conversion efficiency.

[0099] At time t15, the vertical scanning circuit 2 sets both the reset signal RST and the control signal FCG supplied to all the pixels PX in all the rows to the low level and sets the switching signal CLP in all the rows to the high level. Furthermore, the vertical scanning circuit 2 stops the supply of the current id1 from the current sources 13 in all the pixels PX and starts the supply of the current id2 from the load MOS circuit 6 to each vertical signal line VSL at time t15.

[0100] Fig. 8 is a timing chart of the read operation of the pixel PX according to the second example. Fig. 8 illustrates timing of the operation of reading the pixel signals of the nth row. The vertical scanning circuit 2 sets the selection signal SEL to a high level during the read operation of the nth row performed in the period of time t20 to t32.

[0101] The vertical scanning circuit 2 supplies the high-level reset signal RB to the nth row during a predetermined pulse period from time t20 and supplies the high-level selection signal SRH to the nth row during a predetermined pulse period from time t21. Therefore, the SRH transistor Q14 is turned on, and the reset level held in the first capacitor CRH for high conversion efficiency is read.

[0102] The vertical scanning circuit 2 supplies the high-level reset signal RB to the nth row during a predetermined pulse period from time t22 and supplies the high-level selection signal SDH to the nth row during a predetermined pulse period from time t23. Therefore, the SDH transistor Q16 is turned on, and the signal level held in the second capacitor CDH for high conversion efficiency is read.

[0103] The vertical scanning circuit 2 supplies the high-level reset signal RB to the nth row during a predetermined pulse period from time t24 and supplies the high-level selection signal SRM to the nth row during a predetermined pulse period from time t25. Therefore, the SRM transistor Q21 is turned on, and the reset level held in the first capacitor CRM for medium conversion efficiency is read.

[0104] The vertical scanning circuit 2 supplies the high-level reset signal RB to the nth row during a predetermined pulse period from time t26 and supplies the high-level selection signal SDM to the nth row during a predetermined pulse period from time t27. Therefore, the SDM transistor Q22 is turned on, and the signal level held in the second capacitor CDM for medium conversion efficiency is read.

[0105] The vertical scanning circuit 2 supplies the high-level reset signal RB to the nth row during a predetermined pulse period from time t28 and supplies the high-level selection signal SRL to the nth row during a predetermined pulse period from time t29. Therefore, the SRL transistor Q15 is turned on, and the reset level held in the first capacitor CRL for low conversion efficiency is read.

[0106] The vertical scanning circuit 2 supplies the high-level reset signal RB to the nth row during a predetermined pulse period from time t30 and supplies the high-level selection signal SDL to the nth row during a predetermined pulse period from time t31. Therefore, the SDL transistor Q17 is turned on, and the signal level held in the second capacitor CDL for low conversion efficiency is read.

[0107] During the read operation period, the vertical scanning circuit 2 sets the switching signals CLP of all the rows to a high level, stops the supply of the current id1 from the current sources 13 in all the pixels PX, and the load MOS circuit 6 supplies the current id2 to each vertical signal line VSL.

[0108] (First embodiment) Fig. 9 is a cross-sectional view of a light detection device 1 according to a first embodiment. As illustrated in Fig. 9, the light detection device 1 according to the first embodiment has a laminated structure in which three substrates are laminated. Hereinafter, the three substrates are referred to as a first substrate 21, a second substrate 22, and a third substrate 23. The first substrate 21 is disposed on a light incident surface side, and the first substrate 21, the second substrate 22, and the third substrate 23 are laminated in this order.

[0109] A pre-stage circuit 11 is disposed on the first substrate 21. As illustrated in Fig. 2, the pre-stage circuit 11 includes a photoelectric conversion element PD, a TRG transistor Q1, an RST transistor Q2, a floating diffusion region HCG-FD, an SF1 transistor Q3, a CLP transistor Q4, a PC transistor Q6, a VB transistor Q7, an OFG transistor Q8, an FCG transistor Q9, an FLG transistor Q10, and a third capacitor C3. The pre-stage circuit 11 may include an FDG transistor Q20 illustrated in Fig. 6.

[0110] In the present specification, each transistor in the pre-stage circuit 11 may be collectively referred to as a pixel transistor 24. The third capacitor C3 is an additional capacitance for low conversion efficiency. In the first embodiment, an example in which the third capacitor C3 is a MOS capacitor will be described. The MOS capacitor according to the first embodiment includes a first electrode including a polysilicon gate, a second electrode that is a silicon diffusion region, and an insulating layer (oxide layer) disposed between the first electrode and the second electrode. The first electrode is connected to, for example, a VDD node.

[0111] The first substrate 21 includes a photoelectric conversion region 36 disposed on a silicon substrate, a pixel isolation region 35 that separates the photoelectric conversion region 36 for each pixel PX, a color filter layer 28 and an on-chip lens 29 disposed on the light incident surface side of the photoelectric conversion region 36, an arrangement region of a pixel transistor 24 disposed on a back surface (surface opposite to the light incident surface) side of the photoelectric conversion region 36, and a wiring region 25 disposed on a back surface side of the arrangement region of the pixel transistor 24.

[0112] The second substrate 22 includes a plurality of first capacitors C1 and a plurality of second capacitors C2 for sample hold, and a post-stage circuit 12. As illustrated in Fig. 2 or 6, the post-stage circuit 12 includes a selection circuit 14 that selects any one of the plurality of first capacitors C1 and the plurality of second capacitors C2, an RB transistor Q11 that initializes a voltage level of an output node of the selection circuit 14, an SF2 transistor Q12 that outputs a pixel signal of a voltage corresponding to a voltage of the output node of the selection circuit 14 to a source side, and a SEL transistor Q13 that outputs the pixel signal to a corresponding vertical signal line VSL in synchronization with a selection signal SEL of the row selection line 8 from the vertical scanning circuit 2.

[0113] The plurality of first capacitors C1 and the plurality of second capacitors C2 are capacitors (hereinafter, referred to as an MIM capacitor) having an MIM structure disposed in the wiring region 26 of the second substrate 22. The MIM capacitor has a structure in which comb-shaped electrodes face each other in a laminating direction, and a dielectric layer or an insulating layer is disposed between the two electrodes. By using the plurality of first capacitors C1 and the plurality of second capacitors C2 as MIM capacitors, a large-capacity capacitor can be formed with a small circuit area.

[0114] The third substrate 23 includes a logic circuit 27 that performs various types of image processing on the image data for each frame generated by the post-stage circuit 12.

[0115] Bonding and signal transmission between the first substrate 21 and the second substrate 22 are performed by a copper-to-copper connection (CCC), a via, a bump, or the like. Similarly, bonding and signal transmission between the second substrate 22 and the third substrate 23 are performed by CCC, via, bump, or the like.

[0116] It should be noted the logic circuit 27 can be mounted on a semiconductor chip different from the light detection device 1. Therefore, the light detection device 1 according to the first embodiment may have a two-layer structure in which the third substrate 23 is omitted and the first substrate 21 and the second substrate 22 are laminated. Furthermore, the light detection device 1 according to the first embodiment may have a laminated structure in which a total of four or more substrates are laminated, for example, by forming the first substrate 21 in Fig. 9 into a laminated structure of two or more substrates.

[0117] Fig. 10 is a layout diagram of one pixel of the light detection device 1 according to the first embodiment. As illustrated in Fig. 10, each pixel PX of the light detection device 1 according to the first embodiment has a circuit configuration similar to that of Fig. 6, and the MOS capacitor 30 and the pixel transistor 24 configuring the third capacitor C3 are disposed in the same layer to improve layout efficiency.

[0118] More specifically, the L-shaped MOS capacitor 30 is disposed along the pixel isolation region 35 disposed in a boundary region of the pixel PX. Near the center of the pixel region, the TRG transistor Q1 and the OFG transistor Q8 are disposed adjacent to and substantially parallel to each other. The FLG transistor Q10 is disposed between the OFG transistor Q8 and the FCG transistor Q9. Therefore, the charges having passed through the OFG transistor Q8 are prevented from flowing to the FCG transistor Q9 through the FLG transistor Q10, and blooming is suppressed.

[0119] The OFG transistor Q8, the FLG transistor Q10, and the RST transistor Q2 are disposed to share the same diffusion region (active region) 31. Thus, the efficiency of the layout can be improved. The FLG transistor Q10, the FCG transistor Q9, and the MOS capacitor 30 are disposed to share the same diffusion region (active region) 32. Thus, the efficiency of the layout can be improved.

[0120] Furthermore, a VSS wiring layer 33 is disposed in a region surrounded by an FDG gate of the FDG transistor Q20, an FCG gate of the FCG transistor Q9, an FLG gate of the FLG transistor Q10, and an RST gate of the RST transistor Q2. Therefore, a floating diffusion HLG-FD between the TRG transistor Q1 and the FDG transistor Q20, a floating diffusion MLG-FD between the FDG transistor Q20 and the FCG transistor Q9, and a floating diffusion LCG-FD between the FCG transistor Q9 and the FLG transistor Q10 can be separated by the VSS wiring layer 33, and crosstalk between the floating diffusion HLG-FD, the MLG-FD, and the LCG-FD can be suppressed. In the present specification, the VSS wiring layer 33 may be referred to as a well contact.

[0121] Furthermore, the TRG transistor Q1 and the OFG transistor Q8 are disposed adjacent to and substantially parallel to the vicinity of the center of the pixel PX, and thus layout efficiency can be improved.

[0122] The MOS capacitor 30 has a structure in which an insulating layer is disposed between a first electrode that is a polysilicon gate and a second electrode including a silicon diffusion region. The two electrodes of the MOS capacitor 30 are disposed, for example, in an L shape along the pixel isolation region 35. The first electrode which is a polysilicon gate is connected to, for example, a power supply voltage VDD node. By connecting the first electrode, which is a polysilicon gate, to the power supply voltage VDD node, the polysilicon gate can be used as a shield with an adjacent pixel PX. Therefore, by providing the polysilicon gate, crosstalk with the adjacent pixel PX can be suppressed.

[0123] A planar layout of the MOS capacitor 30 can take various modifications other than those illustrated in Fig. 10.

[0124] Fig. 11A is a layout diagram of one pixel according to a first modification of the first embodiment. In a first modification illustrated in Fig. 11A, a rectangular MOS capacitor 30 is disposed along one side of a pixel isolation region 35 provided in a boundary region of a rectangular pixel region 34.

[0125] Fig. 11B is a layout diagram of one pixel according to a second modification of the first embodiment. In the second modification illustrated in Fig. 11B, similarly to Fig. 10, the L-shaped MOS capacitor 30 is disposed along two sides of the pixel isolation region 35 provided in a boundary region of the rectangular pixel region 34. In the second modification, the crosstalk with the pixel PX adjacent in two directions can be suppressed by a polysilicon gate of the MOS capacitor 30.

[0126] Fig. 11C is a layout diagram of one pixel according to a third modification of the first embodiment. In the third modification illustrated in Fig. 11C, the MOS capacitor 30 is disposed along three sides of the pixel isolation region 35 provided in a boundary region of the rectangular pixel region 34. In the third modification, crosstalk with the pixels PX adjacent in three directions can be suppressed by the polysilicon gate of the MOS capacitor 30.

[0127] Fig. 11D is a layout diagram of one pixel according to a fourth modification of the first embodiment. In the fourth modification illustrated in Fig. 11D, the MOS capacitor 30 is disposed along the four sides of the pixel isolation region 35 provided in the boundary region of the rectangular pixel region 34. In the fourth modification, although the arrangement area of the pixel transistor 24 is reduced, crosstalk with the pixels PX adjacent in the four directions can be suppressed by the polysilicon gate of the MOS capacitor 30.

[0128] (Solid-phase diffusion structure of pixel isolation region 35) Fig. 12A is a layout diagram in a case where the MOS capacitor 30 is disposed along two sides of the pixel isolation region 35, and Fig. 12B is a cross-sectional view taken along line A-A' of Fig. 12A.

[0129] The pixel isolation region 35 is disposed along the boundary region of the pixel PX to penetrate the photoelectric conversion region 36. The photoelectric conversion region 36 is, for example, a region in which N-type impurity ions are diffused into a silicon layer. A P-type solid-phase diffusion region 37 is disposed to be in contact with the pixel isolation region 35. The photoelectric conversion region 36 is disposed inside the solid-phase diffusion region 37. A plug region 36a having a higher N-type impurity concentration than that of the photoelectric conversion region 36 is disposed between the photoelectric conversion region 36 and a transfer gate of the TRG transistor Q1. The plug region 36a is a region that performs photoelectric conversion similarly to the photoelectric conversion region 36 but has a narrower width than that of the photoelectric conversion region 36. The P-type diffusion layer 38 is disposed so as to surround the plug region 36a, and the N-type diffusion layer 39 is disposed on the P-type diffusion layer 38. Furthermore, an element isolation region 40 including an insulating layer is disposed between the transfer gate and the MOS capacitor 30.

[0130] (Planar structure) Each pixel PX of the light detection device 1 according to the first embodiment may have a planar pixel structure in which charge transfer from the photoelectric conversion region 36 to the TRG transistor Q1 is performed in the plane direction of the photoelectric conversion region 36.

[0131] Fig. 13A is a layout diagram illustrating a planar type pixel structure. Fig. 13B is a cross-sectional view taken along line A-A' in Fig. 13A.

[0132] As illustrated in Figs. 13A and 13B, in the planar type pixel structure, a width of the plug region 36a in contact with the photoelectric conversion region 36 is wide, and charges are transferred from the plug region 36a in the plane direction. In the planar type pixel structure, the shapes of the MOS capacitor 30, the TRG transistor Q1, and the OFG transistor Q8 are different from those in Fig. 12A.

[0133] (Coupling between OFG gate and LCG-FD2) As illustrated in Fig. 10, the OFG transistor Q8, the FLG transistor Q10, and the RST transistor Q2 share the same diffusion region (active region) 31. The diffusion region 31 is referred to as an LCG-FD2 region or a floating diffusion region in the present specification.

[0134] Fig. 14 is a layout diagram of the pixel region 34 in which the OFG gate and the LCG-FD2 region are disposed close to each other. In Fig. 14, the LCG-FD2 region and the OFG gate are disposed close to each other, and thus capacitive coupling occurs between the LCG-FD2 region and the OFG gate. Therefore, the OFG transistor Q8 is turned on, and then the potential of the above-described diffusion region increases, and the accumulated charges of the photoelectric conversion element PD are easily discharged to the above-described diffusion region. Furthermore, in a case where the OFG transistor Q8 is turned off, the potential of the above-described diffusion region decreases, and thus, it is possible to prevent backflow of charges from the above-described diffusion region to the photoelectric conversion element PD.

[0135] (Countermeasure against crosstalk between HCG-FD and RST gate) As described above, in the present specification, the connection node between the TRG transistor Q1 and the FDG transistor Q20 is referred to as a floating diffusion region HCG-FD. The floating diffusion region HCG-FD is an important node connected to the gate of the SF1 transistor Q3. The potential of the floating diffusion region HCG-FD fluctuates, and then a reset level and a signal level of the signal output from the pre-stage circuit 11 fluctuates, and the image quality deteriorates.

[0136] In a case where the floating diffusion region HCG-FD and the RST gate are disposed close to each other, capacitive coupling may occur between the floating diffusion region HCG-FD and the RST gate. In this case, the potential of the floating diffusion region HCG-FD may fluctuate due to the fluctuation of the potential of the RST gate.

[0137] Fig. 15 is a layout diagram of the pixel region 34 in which measures against crosstalk between the floating diffusion region HCG-FD and the RST gate are taken. As illustrated in Fig. 15, a VDD wiring region 41 and a VSS wiring region 42 are disposed between the floating diffusion region HCG-FD and the RST gate. Therefore, capacitive coupling between the RST gate and the floating diffusion region HCG-FD can be suppressed, and even if a potential of the RST gate changes, there is no possibility that the floating diffusion region HCG-FD fluctuates due to the influence.

[0138] The VDD wiring region 41 is connected to the polysilicon gate of the MOS capacitor 30 and a drain of the RST transistor Q2. Therefore, the VDD wiring region 41 can be disposed between the floating diffusion region HCG-FD and the RST gate without intentionally routing the VDD wiring region 41.

[0139] As described above, in the first embodiment, since the first substrate 21 having the pre-stage circuit 11 and the second substrate 22 having the plurality of first capacitors C1 and the plurality of second capacitors C2 for sample hold, and the post-stage circuit 12 are laminated on each other, the degree of freedom of the layout of the pre-stage circuit 11 in the first substrate 21 and the post-stage circuit 12 in the second substrate 22 can be expanded. Furthermore, by laminating the first substrate 21 and the second substrate 22, downsizing of the light detection device 1 can be realized.

[0140] Furthermore, in the first embodiment, since the MOS capacitor 30 for low conversion efficiency is disposed in the same layer as the pixel transistor 24, a manufacturing process of the first substrate 21 can be simplified.

[0141] Moreover, in the first embodiment, since the plurality of first capacitors C1 and the plurality of second capacitors C2 for sample hold are MIM capacitors and are disposed in the wiring region of the second substrate 22, the first capacitors C1 and the second capacitors C2 can be increased in capacitance.

[0142] Furthermore, in the first embodiment, since the FLG transistor Q10 is disposed between the OFG transistor Q8 and the FCG transistor Q9, there is no possibility that the charges having overflowed from the photoelectric conversion element PD leak to the floating diffusion region HCG-FD through the OFG transistor Q8 in a case where the OFG transistor Q8 is turned on, and blooming can be suppressed.

[0143] Moreover, in the first embodiment, since the VSS wiring layer is disposed in a region surrounded by the FDG transistor Q20, the FCG transistor Q9, the FLG transistor Q10, and the RST transistor Q2, crosstalk between these transistors can be suppressed.

[0144] Furthermore, in the first embodiment, since the TRG transistor and the OFG transistor Q8 are disposed near the center of the pixel PX, the efficiency of the layout can be improved.

[0145] Moreover, in the first embodiment, since the polysilicon gate of the MOS capacitor 30 is disposed close to the pixel isolation region 35 disposed in the boundary region of the pixel PX and the polysilicon gate is connected to the VDD node, the polysilicon gate of the MOS capacitor 30 can be used as a shield with the adjacent pixel PX, and crosstalk with the adjacent pixel PX can be suppressed.

[0146] (Second embodiment) In the first embodiment, the example in which the third capacitor C3 for low conversion efficiency provided in the pre-stage circuit 11 is configured by the MOS capacitor 30 has been described, but the third capacitor C3 may be configured by a trench capacitor.

[0147] Fig. 16 is a layout diagram illustrating a pixel structure in a case where a third capacitor C3 for low conversion efficiency in a pre-stage circuit 11 is configured by a trench capacitor 43. The trench capacitor 43 of Fig. 16 is disposed, for example, along one side of a pixel isolation region 35.

[0148] The trench capacitor 43 is disposed in the same layer as the pixel transistor 24. In Fig. 16, the OFG transistor Q8, the FLG transistor Q10, and the RST transistor Q2 share the same diffusion region (active region) 31, thereby improving layout efficiency. Furthermore, the FLG transistor Q10 and the FCG transistor Q9 share the same diffusion region (active region) 32, thereby improving layout efficiency.

[0149] Fig. 17A is a cross-sectional view taken along line A-A' of Fig. 16, and Fig. 17B is a cross-sectional view taken along line B-B' of Fig. 16. As illustrated in Figs. 17A and 17B, the trench capacitor 43 includes a P-type well region 44 disposed along one side of the pixel isolation region 35. A plurality of trenches 45 is disposed along a longitudinal direction of the P-type well region 44, and an oxide layer 46 and a conductive layer 47 are disposed inside each trench 45. As described above, the trench capacitor 43 has a laminated structure of the P-type well region 44, the oxide layer 46, and the conductive layer 47, and the P-type well region 44 and the conductive layer 47 are electrodes of the trench capacitor 43. The number, size, and interval of the trenches 45 provided in the P-type well region 44 are arbitrary. The conductive layer 47 of the trench capacitor 43 is connected to the VDD node. The conductive layer 47 may be a metal layer or a polysilicon layer. In the present specification, in a case where the conductive layer 47 of the trench capacitor 43 is a polysilicon layer, it is referred to as a polysilicon gate.

[0150] The light detection device 1 according to the second embodiment is different from the first embodiment in that the third capacitor C3 in the pre-stage circuit 11 of each pixel PX is the trench capacitor 43, but the features of the layout of each pixel PX described in the first embodiment are also applicable to the second embodiment. Hereinafter, features on the layout of the pixel PX according to the second embodiment will be sequentially described.

[0151] As illustrated in Fig. 16, each pixel PX according to the second embodiment includes a VSS wiring layer 33 disposed in a region surrounded by an FDG gate of an FDG transistor Q20, an FCG gate of an FCG transistor Q9, an FLG gate of an FLG transistor Q10, and an RST gate of an RST transistor Q2. Therefore, an HLG-FD between the TRG transistor Q1 and the FDG transistor Q20, an MLG-FD between the FDG transistor Q20 and the FCG transistor Q9, and an LCG-FD between the FCG transistor Q9 and the FLG transistor Q10 can be separated by a VSS wiring layer, and crosstalk among the HLG-FD, the MLG-FD, and the LCG-FD can be suppressed.

[0152] Furthermore, as illustrated in Fig. 16, each pixel PX according to the second embodiment includes a TRG transistor Q1 and an OFG transistor Q8 disposed in a substantially central portion of a pixel region 34. By arranging the TRG transistor Q1 and the OFG transistor Q8 substantially in parallel, it is possible to improve layout efficiency.

[0153] A part of the electrode of the trench capacitor 43 may be integrated with the pixel isolation region 35. Fig. 18 is a layout diagram illustrating a pixel structure in which a conductive layer 47, which is a first electrode of the trench capacitor 43, is integrated with the pixel isolation region 35. The pixel isolation region 35 in Fig. 18 includes a conductive layer 47. The conductive layer 47 may be made of a metal material or polysilicon.

[0154] Fig. 19 is a cross-sectional view taken along line A-A' in Fig. 18. A conductive layer 47 is disposed in the pixel isolation region 35. As illustrated in Fig. 19, the trench capacitor 43 has a laminated structure of a conductive layer 47, an oxide layer 46, and a P-type well region 44. More specifically, the trench capacitor 43 has a structure in which the conductive layer 47 integrated with the pixel isolation region 35 is a first electrode, the P-type well region 44 is a second electrode, and the oxide layer 46 is disposed between the first electrode and the second electrode.

[0155] As illustrated in Fig. 19, by integrating the first electrode of the trench capacitor 43 and the pixel isolation region 35, the trench capacitor 43 can be formed along the pixel isolation region 35, the arrangement area of the pixel transistor 24 can be widened, and the degree of freedom of layout is widened.

[0156] The material of the oxide layer 46 of the trench capacitor 43 is arbitrary, and may be, for example, a ZAZ structure in which a ZnO2layer, an Al2O3layer, and a ZnO2layer are sequentially laminated, or a dielectric layer such as HfO2. The material of the conductive layer 47 of the trench capacitor 43 is arbitrary, and may be, for example, TiN.

[0157] Each pixel PX of the light detection device 1 according to the second embodiment may include a solid-phase diffusion region 37 disposed along the pixel isolation region 35.

[0158] Fig. 20 is a layout diagram of one pixel in a case where each pixel PX of the light detection device 1 according to the second embodiment includes the solid-phase diffusion region 37, and Fig. 21 is a cross-sectional view taken along line A-A' of Fig. 20. A P-type solid-phase diffusion region 37 is disposed between the pixel isolation region 35 and a photoelectric conversion region 36 disposed along a boundary region of the pixel PX. A width of the photoelectric conversion region 36 on a side of the surface (hereinafter, referred to as a back surface) opposite to a light incident surface of the photoelectric conversion region 36 is narrowed, and a P-type diffusion region 38 and an N-type diffusion layer 39 are laminated around the photoelectric conversion region 36 having a small width. By providing the solid-phase diffusion region 37, dark current can be suppressed.

[0159] Each pixel PX in the light detection device 1 according to the second embodiment may have a planar structure similarly to Figs. 13A and 13B. Fig. 22 is a layout diagram of pixels PX having a planar structure in the light detection device 1 according to the second embodiment.

[0160] Similarly to Fig. 14, in each pixel PX in the light detection device 1 according to the second embodiment, capacitive coupling may be generated between the LCG-FD2 region and the OFG gate by arranging the LCG-FD2 region and the OFG gate close to each other.

[0161] Fig. 23 is a layout diagram in which the LCG-FD2 region of each pixel PX and the OFG gate are disposed close to each other in the light detection device 1 according to the second embodiment. Since capacitive coupling occurs between the LCG-FD2 region and the OFG gate, the similar effect to that in Fig. 14 can be obtained.

[0162] In each pixel PX of the light detection device 1 according to the second embodiment, measures against crosstalk between the HCG-FD and the RST gate may be taken as in Fig. 15.

[0163] Fig. 24 is a layout diagram illustrating a countermeasure against crosstalk between the floating diffusion region HCG-FD of each pixel PX and the RST gate of the light detection device 1 according to the second embodiment. By arranging the VDD wiring region 41 and the VSS wiring region 42 between the floating diffusion region HCG-FD and the RST gate, capacitive coupling between the RST gate and the floating diffusion region HCG-FD can be suppressed, and even if the potential of the RST gate changes, there is no possibility that the floating diffusion region HCG-FD fluctuates due to the influence.

[0164] As described above, in the second embodiment, since the third capacitor C3 for low conversion efficiency in the pre-stage circuit 11 is configured by the trench capacitor 43, the trench capacitor 43 and the pixel transistor 24 can be disposed in the same layer of the first substrate 21. Furthermore, the capacitance of the third capacitor C3 can be increased as necessary by adjusting the number and depth of the trenches 45. By integrating some electrodes configuring the trench capacitor 43 with the pixel isolation region 35, the trench capacitor 43 can be formed with a small circuit area. Furthermore, even if the third capacitor C3 is configured by the trench capacitor 43, the similar effects to those of the first embodiment can be obtained.

[0165] (Third embodiment) In a third embodiment, a third capacitor C3 for low conversion efficiency in a pre-stage circuit 11 has an MIM structure.

[0166] Fig. 25 is a cross-sectional view of a light detection device 1 according to the third embodiment. The light detection device 1 according to the third embodiment has a laminated structure in which a first substrate 21, a second substrate 22, and a third substrate 23 are laminated. The pre-stage circuit 11 is disposed on the first substrate 21. A third capacitor C3 for low conversion efficiency in the pre-stage circuit 11 is an MIM capacitor having an MIM structure and is disposed in a wiring region of the first substrate 21. A pixel transistor 24 in the pre-stage circuit 11 is disposed in a layer different from that of the third capacitor C3. Since it is not necessary to arrange the third capacitor C3 in the layer in which the pixel transistor 24 is disposed, the degree of freedom in layout design of the pixel transistor 24 is increased.

[0167] A plurality of first capacitors C1 and a plurality of second capacitors C2 for sample hold, and a post-stage circuit 12 are disposed on the second substrate 22. The plurality of first capacitors C1 and the plurality of second capacitors C2 are MIM capacitors and are disposed in a wiring region of the second substrate 22. Each transistor in the post-stage circuit 12 is disposed in a layer different from that of the plurality of first capacitors C1 and the plurality of second capacitors C2.

[0168] A logic circuit 27 is disposed on the third substrate 23. Since the logic circuit 27 may be provided separately from the light detection device 1, the third substrate 23 may be omitted and a laminated structure of the first substrate 21 and the second substrate 22 may be formed.

[0169] The first substrate 21 and the second substrate 22 are bonded by, for example, CCC, via, bump, or the like to perform signal transmission. Similarly, the second substrate 22 and the third substrate 23 are bonded by, for example, CCC, via, bump, or the like to perform signal transmission.

[0170] Fig. 26 is a cross-sectional view of a light detection device 1 according to a first modification of the third embodiment. The first modification illustrated in Fig. 26 is different from Fig. 25 in that a third capacitor C3 in the pre-stage circuit 11 is disposed in a wiring region of the second substrate 22. In the wiring region of the second substrate 22, the third capacitor C3 in the pre-stage circuit 11, and the plurality of first capacitors C1 and the plurality of second capacitors C2 for sample hold are disposed. Each of these capacitors is an MIM capacitor having an MIM structure.

[0171] The first modification shows an example in which the third capacitor C3 in the pre-stage circuit 11, the plurality of first capacitors C1 and the plurality of second capacitors C2 for sample hold are disposed on different layers of the wiring region of the second substrate 22.

[0172] According to the first modification, since it is not necessary to dispose the third capacitor C3 in the pre-stage circuit 11 on the first substrate 21, a degree of freedom in layout design of the first substrate 21 is widened, and layout design is facilitated. Furthermore, since the first to third capacitors C3 having the MIM structure are collectively formed on the second substrate 22, the manufacturing process is facilitated. In a case where a multilayer wiring is formed, plasma induced damage (PID) may occur, but the capacitors having the MIM structure are collectively formed on the second substrate 22, and thus the PID per capacitor can be reduced, and the MIM capacitor is not disposed on the first substrate 21, so that the PID can be suppressed.

[0173] Fig. 27 is a cross-sectional view of a light detection device 1 according to a second modification of the third embodiment. In the second modification, the third capacitor C3 in the pre-stage circuit 11, and the plurality of first capacitors C1 and the plurality of second capacitors C2 for sample hold are disposed on the same layer of the wiring region of the second substrate 22. Each of these capacitors is an MIM capacitor having an MIM structure.

[0174] By forming the capacitors of the MIM structure on the same layer of the wiring region of the second substrate 22, a manufacturing process can be simplified. Furthermore, it is possible to limit a place where a PID occurs in a case where the MIM structure is formed.

[0175] As described above, in the third embodiment, since the third capacitor C3 for low conversion efficiency in the pre-stage circuit 11 is formed in the wiring region of the second substrate 22 with the MIM structure, the degree of freedom in layout arrangement of the pixel transistors 24 of the first substrate 21 is increased. Furthermore, by forming the plurality of first capacitors C1 and the plurality of second capacitors C2 for sample hold in the wiring region of the second substrate 22 in the MIM structure, the MIM capacitors can be aggregated in the wiring region of the second substrate 22, the manufacturing process can be simplified, and a place where the PID occurs can be limited to the wiring region of the second substrate 22.

[0176] (Fourth embodiment) A light detection device 1 according to a fourth embodiment is different from the light detection devices 1 according to the first to third embodiments in a connection form between a plurality of first capacitors C1 and a plurality of second capacitors C2 for sample hold and a selection circuit 14.

[0177] Fig. 28 is a circuit diagram of a pixel PX of the light detection device 1 according to the fourth embodiment. The pixel PX according to the fourth embodiment includes a pre-stage circuit 11, a current source 13, a plurality of first capacitors C1 and a plurality of second capacitors C2 for sample hold, and a post-stage circuit 12.

[0178] The pre-stage circuit 11 according to the fourth embodiment is similar to Fig. 6, and includes a photoelectric conversion element PD, a TRG transistor Q1, an RST transistor Q2, a floating diffusion region HCG-FD, an SF1 transistor Q3, a CLP transistor Q4, an SW transistor Q5, an OFG transistor Q8, an FCG transistor Q9, a FLG transistor Q10, an FDG transistor Q20, and a third capacitor C3.

[0179] The post-stage circuit 12 according to the fourth embodiment includes a PC transistor Q6 and a VB transistor Q7 configuring a current source 13, an SF2 transistor Q12, a SEL transistor Q13, and a current source 13.

[0180] The selection circuit 14 includes an SRH transistor Q14, an SDH transistor Q16, an SRM transistor Q21, an SDM transistor Q22, an SRL transistor Q15, and an SDL transistor Q17.

[0181] The SRH transistor Q14 and the first capacitor C1 for high conversion efficiency are connected in series between a gate of the SF2 transistor Q12 and the ground voltage node. The SDH transistor Q16 and the second capacitor C2 for high conversion efficiency are connected in series between the gate of the SF2 transistor Q12 and the ground voltage node.

[0182] The SRM transistor Q21 and the first capacitor C1 for medium conversion efficiency are connected in series between the gate of the SF2 transistor Q12 and the ground voltage node. The SDM transistor Q22 and the second capacitor C2 for medium conversion efficiency are connected in series between the gate of the SF2 transistor Q12 and the ground voltage node.

[0183] The SRL transistor Q15 and the first capacitor C1 for low conversion efficiency are connected in series between the gate of the SF2 transistor Q12 and the ground voltage node. The SDL transistor Q17 for low conversion efficiency and the second capacitor C2 are connected in series between the gate of the SF2 transistor Q12 and the ground voltage node.

[0184] In a case where the selection signal SRH becomes the high level, the SRH transistor Q14 is turned on, and the gate of the SF2 transistor Q12 becomes a potential of a reset level held in the first capacitor CRH for high conversion efficiency. In a case where the selection signal SDH becomes the high level, the SDH transistor Q16 is turned on, and the gate of the SF2 transistor Q12 becomes a potential of a signal level held in the second capacitor CDH for high conversion efficiency.

[0185] In a case where the selection signal SRM becomes the high level, the SRM transistor Q21 is turned on, and the gate of the SF2 transistor Q12 becomes the potential of the reset level held in the first capacitor CRM for medium conversion efficiency. In a case where the selection signal SDM becomes the high level, the SDM transistor Q22 is turned on, and the gate of the SF2 transistor Q12 becomes the potential of the signal level held in the second capacitor CDM for medium conversion efficiency.

[0186] In a case where the selection signal SRL becomes the high level, the SRL transistor Q15 is turned on, and the gate of the SF2 transistor Q12 becomes the potential of the reset level held in the first capacitor CRL for low conversion efficiency. In a case where the selection signal SDL becomes the high level, the SDL transistor Q17 is turned on, and the gate of the SF2 transistor Q12 becomes the potential of the signal level held in the second capacitor CDL for low conversion efficiency.

[0187] In the post-stage circuit 12 of Fig. 28, the RB transistor Q11 connected to the gate of the SF2 transistor Q12 is omitted as compared with the post-stage circuit 12 of Fig. 6. For this reason, there is a possibility that fixed pattern noise increases, but characteristic fluctuation of the current source 13 can be suppressed by increasing the size of the VB transistor Q7, so that it is possible to miniaturize the pixel PX by omitting the RB transistor Q11 while suppressing the fixed pattern noise.

[0188] Fig. 29 is a layout diagram of each transistor disposed on the second substrate 22 of the pixel PX in Fig. 28. The SEL transistor Q13 and the SF2 transistor Q12 are disposed adjacent to each other in the first direction X. A drain region of the SEL transistor Q13 and a source region of the SF2 transistor Q12 share the same diffusion region 51. The SDH transistor Q16 and the SRH transistor Q14 are disposed adjacent to each other in the first direction X. The drain regions of the SDH transistor Q16 and the SRH transistor Q14 share the same diffusion region 52. The SDM transistor Q22 and the SRM transistor Q21 are disposed adjacent to each other in the first direction X. The drain regions of the SDM transistor Q22 and the SRM transistor Q21 share the same diffusion region 53. The SDL transistor Q17 and the SRL transistor Q15 are disposed adjacent to each other in the first direction X. The drain regions of the SDL transistor Q17 and the SRL transistor Q15 share the same diffusion region 54.

[0189] The arrangement row 55 of the SEL transistor Q13 and the SF2 transistor Q12, the arrangement row 56 of the SDH transistor Q16 and the SRH transistor Q14, the arrangement row 57 of the SDM transistor Q22 and the SRM transistor Q21, and the arrangement row 58 of the SDL transistor Q17 and the SRL transistor Q15 are disposed separately from each other in the second direction Y.

[0190] The PC transistor Q6 and the VB transistor Q7 configuring the current source 13 are disposed adjacent to each other in the second direction Y. The source region of the PC transistor Q6 and the drain region of the VB transistor Q7 share the same diffusion region 59.

[0191] The gate wiring 60 of the SF2 transistor Q12 is disposed to cross the drain regions of the SRH transistor Q14, the SDH transistor Q16, the SRM transistor Q21, the SDM transistor Q22, the SRL transistor Q15, the SDL transistor Q17, and the PC transistor Q6.

[0192] As illustrated in Fig. 29, by crossing the arrangement direction of each transistor for sampling hold and the arrangement direction of the PC transistor Q6 and the VB transistor Q7 configuring the current source 13, all the transistors in the post-stage circuit 12 can be disposed within a limited area of a rectangular shape.

[0193] Fig. 30 is a circuit diagram of a pixel PX of a light detection device 1 according to a modification of the fourth embodiment. The pixel PX according to the modification illustrated in Fig. 30 includes a CLP2 transistor (fourteenth transistor) Q23 in addition to the configuration of the pixel PX in Fig. 28. The CLP2 transistor Q23 is disposed between a drain of the PC transistor Q6 and the gate of the SF2 transistor Q12. Without the CLP2 transistor Q23, the gate of the SF2 transistor Q12 is affected by the parasitic capacitance of the drain of the PC transistor Q6, and the transmission gain may decrease. By providing the CLP2 transistor Q23, a gate voltage of the SF2 transistor Q12 is not affected by a parasitic capacitance of the drain of the PC transistor Q6, a reduction of the transmission gain can be suppressed, and a fixed pattern noise caused by the parasitic capacitance of the drain of the PC transistor Q6 can be reduced.

[0194] Fig. 31 is a layout diagram of each transistor disposed on the second substrate 22 of the pixel PX in Fig. 30. The PC transistor Q6 and the VB transistor Q7 configuring the current source 13, and the CLP2 transistor Q23 are disposed in the second direction Y. A source region of the PC transistor Q6 and a drain region of the VB transistor Q7 share the same diffusion region, and a source region of the CLP2 transistor Q23 and a drain region of the PC transistor Q6 share the same diffusion region. Other layout arrangements are the same as those in Fig. 29.

[0195] As described above, in the fourth embodiment, between the gate of the SF2 transistor Q12 and the ground voltage node, the selection circuit 14 and the plurality of first capacitors C1 for sample and hold are connected in parallel, and the selection circuit 14 and the plurality of second capacitors C2 for sample and hold are connected in parallel. Furthermore, in the second substrate 22, each of the plurality of first transistors in the selection circuit 14 and the corresponding second transistor are disposed substantially in parallel, and the PC transistor Q6 and the VB transistor Q7 configuring the current source 13 are disposed in a direction intersecting with the arrangement direction, so that each transistor can be efficiently disposed in a layout in a small circuit area.

[0196] (Fifth embodiment) In a light detection device 1 according to a fifth embodiment, a polysilicon gate of a third capacitor C3 in a pre-stage circuit 11 of each pixel PX is shared between adjacent pixels PX.

[0197] Fig. 32 is a layout diagram of 2×2 pixels PX of the light detection device 1 according to the fifth embodiment. Fig. 32 illustrates an example in which the third capacitor C3 in the pre-stage circuit 11 includes a MOS capacitor 30, and an L-shaped polysilicon gate 61 of the MOS capacitor 30 is disposed along a pixel isolation region 35 of each pixel PX. Two pixels PX adjacent to each other in the first direction X share the polysilicon gate 61 disposed along one side of the pixel isolation region 35. Therefore, it is not necessary to arrange the polysilicon gate 61 for each pixel PX, and the layout arrangement of the pixel PX can be simplified. The example of Fig. 32 illustrates an example in which two pixels PX adjacent to each other in the first direction X share the polysilicon gate 61 disposed along one side of the pixel isolation region 35. The polysilicon gate 61 is connected to the VDD node.

[0198] Fig. 33 is a layout diagram of 2×2 pixels PX of the light detection device 1 according to a first comparative example. In the first comparative example, it is necessary to arrange the L-shaped polysilicon gate 61 along two sides of the pixel isolation region 35 for each pixel PX and to provide a contact 63 for connecting to a VDD node for each polysilicon gate 61, and it takes time and effort to arrange the polysilicon gate 61 as compared with Fig. 32.

[0199] In the fifth embodiment, the polysilicon gate 61 of the MOS capacitor 30 may be shared by the plurality of pixels PX along one side, two sides, three sides, or four sides of the pixel isolation region 35.

[0200] Figs. 34A and 34B are layout diagrams illustrating an example in which the polysilicon gate 61 of the MOS capacitor 30 is shared by a plurality of pixels PX along one side of the pixel isolation region 35. In Figs 34A and 34B, an extending direction of the polysilicon gate 61 differs by about 90 degrees.

[0201] Fig. 34C is a layout diagram illustrating an example in which the polysilicon gate 61 of the MOS capacitor 30 is shared by the plurality of pixels PX along two sides of the pixel isolation region 35. Fig. 34D is a layout diagram illustrating an example in which the polysilicon gate 61 of the MOS capacitor 30 is shared by the plurality of pixels PX along three sides of the pixel isolation region 35. Fig. 34E is a layout diagram illustrating an example in which the polysilicon gate 61 of the MOS capacitor 30 is shared by the plurality of pixels PX along the four sides of the pixel isolation region 35.

[0202] The third capacitor C3 in the pre-stage circuit 11 may be configured by a trench capacitor 43 instead of the MOS capacitor 30. Fig. 35 is a layout diagram of one pixel in a case where the third capacitor C3 includes the trench capacitor 43. Fig. 36A is a cross-sectional view taken along line A-A' of Fig. 35, and Fig. 36B is a cross-sectional view taken along line B-B' of Fig. 35.

[0203] As illustrated in Fig. 36A, the trench capacitor 43 has a structure in which, for example, a plurality of trenches 45 is formed in a P-type well region 44 disposed along one side of the pixel isolation region 35, and an oxide layer 46 and a polysilicon layer 62 are disposed inside and on an upper surface of each trench 45. The number, size, and interval of the trenches 45 disposed in the P-type well region 44 are arbitrary.

[0204] In a case where the third capacitor C3 is formed of the trench capacitor 43, the trench capacitor 43 may be disposed along one side of the pixel isolation region 35 as in Figs. 34A and 34B, the trench capacitor 43 may be disposed along two sides of the pixel isolation region 35 as in Fig. 34C, the trench capacitor 43 may be disposed along three sides of the pixel isolation region 35 as in Fig. 34D, or the trench capacitor 43 may be disposed along four sides of the pixel isolation region 35 as in Fig. 34E.

[0205] In a case where the third capacitor C3 includes the MOS capacitor 30, the number of polysilicon gates 61 can be reduced by sharing the polysilicon gates 61 of the MOS capacitor 30 among the plurality of pixels PX.

[0206] In a case where the light detection device 1 according to the fifth embodiment is configured by a semiconductor chip having a laminated structure, various modifications can be taken as to the arrangement place and the number of polysilicon gates 64 for sharing the power supply voltage.

[0207] Fig. 37 is a layout diagram of a semiconductor chip according to a first modification of the fifth embodiment. In the first modification illustrated in Fig. 37, polysilicon gates 64 extending in the first direction X are disposed at both ends of the semiconductor chip in the second direction Y, and a plurality of contacts 63 is connected to those polysilicon gates 64. Since each pixel PX in the semiconductor chip shares these polysilicon gates 64, it is not necessary to provide a polysilicon gate 64 for power supply voltage sharing for each pixel PX. In the first modification, the plurality of pixels PX disposed in the second direction Y can share the two polysilicon gates 64 provided at both ends in the second direction Y.

[0208] Fig. 38 is a layout diagram of a semiconductor chip according to a second modification of the fifth embodiment. In the second modification illustrated in Fig. 38, the number of polysilicon gates 64 is increased as compared with the first modification. The semiconductor chip according to the second modification includes a plurality of polysilicon gates 64 each extending in the first direction X and arranged in the second direction Y. The plurality of pixels PX arranged in the second direction Y can share the plurality of polysilicon gates 64. In the second modification, since the number of polysilicon gates 64 is larger than that in the first modification, the parasitic capacitance of the polysilicon gate 64 can be reduced.

[0209] Fig. 39 is a layout diagram of a semiconductor chip according to a comparative example. In Fig. 39, a plurality of polysilicon gates 64 is disposed in each of the first direction X and the second direction Y. In one comparative example, since a large number of polysilicon gates 64 are disposed in the semiconductor chip, a place where other circuit elements are disposed is limited, and the degree of freedom of layout is reduced.

[0210] Fig. 40 is a layout diagram of a semiconductor chip according to a third modification of the fifth embodiment. In the third modification illustrated in Fig. 40, polysilicon gates 64 extending in the second direction Y are disposed at both ends of the semiconductor chip in the first direction X, and a plurality of contacts 63 is connected to those polysilicon gates 64. Since each pixel PX in the semiconductor chip shares the polysilicon gate 64, it is not necessary to provide the polysilicon gate 64 for each pixel PX. In the third modification, the plurality of pixels PX disposed in the first direction X can share two polysilicon gates 64 provided on both sides in the first direction X.

[0211] Fig. 41 is a layout diagram of a semiconductor chip according to a fourth modification of the fifth embodiment. In the fourth modification illustrated in Fig. 41, the number of polysilicon gates 64 is increased as compared with the third modification. The semiconductor chip according to the fourth modification includes a plurality of polysilicon gates 64 each extending in the second direction Y and arranged in the first direction X. The plurality of pixels PX arranged in the first direction X can share the plurality of polysilicon gates 64. In the fourth modification, since the number of polysilicon gates 64 is larger than that in the third modification, a parasitic capacitance of the polysilicon gate 64 can be reduced.

[0212] Fig. 42 is a layout diagram of a semiconductor chip according to a fifth modification of the fifth embodiment. In the fifth modification illustrated in Fig. 42, polysilicon gates 64 extending in the second direction Y are disposed at both ends in the first direction X of the semiconductor chip, and polysilicon gates 64 extending in the first direction X are disposed at both ends in the second direction Y of the semiconductor chip, and a plurality of contacts 63 is connected to the respective polysilicon gates 64. Since each pixel PX in the semiconductor chip shares these polysilicon gates 64, it is not necessary to provide the polysilicon gate 64 of the MOS capacitor 30 for each pixel PX.

[0213] Although Fig. 32 illustrates an example in which the polysilicon gate 61 of the MOS capacitor 30 is shared by the plurality of pixels PX, the polysilicon gate 61 may be symmetrically disposed and shared among the plurality of pixels PX.

[0214] Fig. 43 is a layout diagram of 2×2 pixels PX according to a sixth modification of the fifth embodiment. In the sixth modification illustrated in Fig. 43, the polysilicon gate 61 is mirror-disposed (X-mirror arrangement) in the first direction X with a pixel boundary line extending in the second direction Y (for example, the column direction) as an axis of symmetry. In the sixth modification, the polysilicon gate 61 of the MOS capacitor 30 can be shared by two pixels PX adjacent in the first direction X, and it is not necessary to dispose the polysilicon gate 61 for each pixel PX.

[0215] Fig. 44 is a layout diagram of 2×2 pixels PX according to a seventh modification of the fifth embodiment. In the seventh modification illustrated in Fig. 44, the polysilicon gate 61 is mirror-disposed (Y-mirror arrangement) in the second direction Y with a pixel boundary line extending in the first direction X (for example, the row direction) as an axis of symmetry. In the seventh modification, the polysilicon gate 61 of the MOS capacitor 30 can be shared by two pixels PX adjacent in the second direction Y, and it is not necessary to dispose the polysilicon gate 61 for each pixel PX.

[0216] Fig. 45 is a layout diagram of 2×2 pixels PX according to an eighth modification of the fifth embodiment. In the eighth modification illustrated in Fig. 45, the polysilicon gate 61 is mirror-disposed (XY-mirror arrangement) in the first direction X and the second direction Y with a first pixel boundary line extending in the first direction X (for example, the row direction) and a second pixel boundary line extending in the second direction Y (for example, the column direction) as symmetry axes. In the eighth modification, the 2×2 pixels PX can share the cross-shaped polysilicon gate 61.

[0217] Even in a case where the third capacitor C3 in the pre-stage circuit 11 is configured by the trench capacitor 43, the trench capacitor 43 can be shared by 2×2 pixels PX.

[0218] Fig. 46 is a layout diagram of 2×2 pixels PX according to a ninth modification of the fifth embodiment. In the ninth modification illustrated in Fig. 46, the trench capacitor 43 is mirror-disposed (X-mirror arrangement) in the first direction X with a pixel boundary line extending in the second direction Y (for example, the column direction) as an axis of symmetry.

[0219] Fig. 47 is a layout diagram of 2×2 pixels PX according to a tenth modification of the fifth embodiment. In the tenth modification illustrated in Fig. 47, the trench capacitor 43 is mirror-disposed (Y-mirror arrangement) in the second direction Y with a pixel boundary line extending in the first direction X (for example, the row direction) as an axis of symmetry.

[0220] Fig. 48 is a layout diagram of 2×2 pixels PX according to an eleventh modification of the fifth embodiment. In the eleventh modification illustrated in Fig. 48, the trench capacitor 43 is mirror-disposed (XY-mirror arrangement) in the first direction X and the second direction Y with a first pixel boundary line extending in the first direction X (for example, the row direction) and a second pixel boundary line extending in the second direction Y (for example, the column direction) as symmetry axes.

[0221] Fig. 49A is a cross-sectional view taken along line A-A' of Fig. 48, and Fig. 49B is a cross-sectional view taken along line B-B' of Fig. 48. Furthermore, Fig. 49C is a cross-sectional view of a modification of Fig. 49B.

[0222] A trench capacitor 43 according to the eleventh modification has a structure in which an oxide layer 46 and a polysilicon layer 62 are disposed inside and on an upper surface of a plurality of trenches 45 disposed in a P-type well region 44.

[0223] The trench capacitor 43 disposed between the two pixels PX adjacent to each other in the second direction Y may have a plurality of trenches 45 as illustrated in Fig. 49B, or may have one wide trench 45 as illustrated in Fig. 49C.

[0224] In a case where the third capacitor C3 includes the MOS capacitor 30, one or more contacts 63 are disposed in the polysilicon gate 61. By sharing not only the polysilicon gate 61 but also the contacts 63 in the 2×2 pixels PX, the number of polysilicon gates 61 and the number of contacts 63 can be reduced. Various modifications can be taken for the number and arrangement location of the contacts 63.

[0225] Fig. 50A is a layout diagram of 2×2 pixels PX according to a twelfth modification of the fifth embodiment. The twelfth modification illustrated in Fig. 50A includes a polysilicon gate 61 disposed in an XY mirror, and three contacts 63 disposed in a central portion of the polysilicon gate 61 along the second direction Y.

[0226] Fig. 50B is a layout diagram of 2×2 pixels PX according to a thirteenth modification of the fifth embodiment. The thirteenth modification illustrated in Fig. 50B includes a polysilicon gate 61 disposed in an XY mirror, and three contacts 63 disposed along the first direction X in a central portion of the polysilicon gate 61.

[0227] Fig. 50C is a layout diagram of 2×2 pixels PX according to a fourteenth modification of the fifth embodiment. The fourteenth modification illustrated in Fig. 50C includes a polysilicon gate 61 disposed in an XY mirror and one contact 63 disposed in a central portion of the polysilicon gate 61.

[0228] In a case where the third capacitor C3 in the pre-stage circuit 11 includes the MOS capacitor 30, the polysilicon gate 61 of the MOS capacitor 30 may be shared by 2×2 pixels PX.

[0229] Fig. 51A is a layout diagram of 2×2 pixels PX according to a fifteenth modification of the fifth embodiment. In the fifteenth modification illustrated in Fig. 51A, a polysilicon gate 64 that supplies a power supply voltage or a ground voltage is disposed along a pixel boundary line extending in the second direction Y through the center of the 2×2 pixel PX in the first direction X. The polysilicon gate 64 is shared by 2×2 pixels PX.

[0230] Fig. 51B is a layout diagram of 2×2 pixels PX according to a comparative example of the fifteenth modification. In the comparative example illustrated in Fig. 51B, two polysilicon gates 64 extending in the second direction Y through the centers of two pixels PX adjacent in the second direction Y are disposed. Each polysilicon gate 64 is shared by two pixels PX adjacent to each other in the second direction Y. In the fifteenth modification of Fig. 51A, one polysilicon gate 64 is shared by four pixels PX, whereas in the comparative example of Fig. 51B, one polysilicon gate 64 is shared by two pixels PX. Therefore, the number of polysilicon gates 64 can be further reduced in the fifteenth modification.

[0231] Fig. 52A is a layout diagram of 2×2 pixels PX according to a sixteenth modification of the fifth embodiment. In the sixteenth modification illustrated in Fig. 52A, a polysilicon gate 64 is disposed along a pixel boundary line extending in the first direction X through the center of the 2×2 pixel PX in the second direction Y. The polysilicon gate 64 is shared by 2×2 pixels PX.

[0232] Fig. 52B is a layout diagram of 2×2 pixels PX according to a comparative example of the sixteenth modification. In the comparative example illustrated in Fig. 52B, two polysilicon gates 64 extending in the first direction X through the centers of two pixels PX adjacent in the first direction X are disposed. Each polysilicon gate 64 is shared by two pixels PX adjacent to each other in the first direction X. In the sixteenth modification of Fig. 52A, one polysilicon gate 64 is shared by four pixels PX, whereas in the comparative example of Fig. 52B, one polysilicon gate 64 is shared by two pixels PX. Therefore, the number of polysilicon gates 64 can be further reduced in the sixteenth modification.

[0233] Fig. 53A is a layout diagram of 2×2 pixels PX according to a seventeenth modification of the fifth embodiment. In the seventeenth modification illustrated in Fig. 53A, two polysilicon gates 64 are disposed along a pixel boundary line extending in the first direction X and the second direction Y through the center of the 2×2 pixel PX in the second direction Y. These polysilicon gates 64 are shared by 2×2 pixels PX.

[0234] Fig. 53B is a layout diagram of 2×2 pixels PX according to a comparative example of the seventeenth modification. In the comparative example illustrated in Fig. 53B, a total of four polysilicon gates 64 extending in the first direction X and the second direction Y through the centers of two pixels PX adjacent in the first direction X are disposed. Two of the four polysilicon gates 64 are shared by two pixels PX adjacent in the first direction X, and the remaining two are shared by two pixels PX adjacent in the second direction Y. In the seventeenth modification of Fig. 53A, two polysilicon gates 64 are shared by four pixels PX, whereas in the comparative example of Fig. 53B, four polysilicon gates 64 are shared by four pixels PX. Therefore, the number of polysilicon gates 64 can be further reduced in the seventeenth modification.

[0235] As described above, in the fifth embodiment, since the MOS capacitor 30 or the trench capacitor 43 used as the third capacitor C3 in the pre-stage circuit 11 is shared by the plurality of pixels PX, it is not necessary to dispose the MOS capacitor 30 or the trench capacitor 43 for each pixel PX, and layout design becomes easy.

[0236] (Sixth embodiment) In the first to fifth embodiments, the example has been described in which the pre-stage circuit 11 of each pixel PX is disposed on the first substrate 21, and the plurality of first capacitors C1 and the plurality of second capacitors C2 for sample hold and the post-stage circuit 12 are disposed on the second substrate 22. However, the pre-stage circuit 11, the plurality of first capacitors C1 and the plurality of second capacitors C2 for sample hold, and the post-stage circuit 12 may be disposed on the same substrate.

[0237] Fig. 54 is a cross-sectional view of a light detection device 1 according to a sixth embodiment. The light detection device 1, according to the sixth embodiment includes, for example, a pixel PX having a circuit configuration similar to that of Fig. 2. A light detection device 1, according to the sixth embodiment illustrated in Fig. 54 has a laminated structure in which a first substrate 21 and a second substrate 22 are laminated. On the first substrate 21, a pre-stage circuit 11, a plurality of first capacitors C1 and a plurality of second capacitors C2, and a post-stage circuit 12 are disposed. A logic circuit 27 is disposed on the second substrate 22. The first substrate 21 and the second substrate 22 are bonded by CCC, via, bump, or the like to perform signal transmission.

[0238] A third capacitor C3 in the pre-stage circuit 11 is a MOS capacitor 30 and is disposed in the same layer as that of each transistor in the pre-stage circuit 11 and the post-stage circuit 12. The plurality of first capacitors C1 and the plurality of second capacitors C2 for sample hold are MIM capacitors having an MIM structure disposed in the wiring region 25 of the first substrate 21.

[0239] In a case where the pre-stage circuit 11 and the post-stage circuit 12 in the pixel PX are disposed on the same layer of the first substrate 21, in a case where a pixel transistor 24 (TRG transistor Q1, OFG transistor Q8, RST transistor Q2, FDG transistor Q20, FLG transistor Q10, and FCG transistor Q9) in the pre-stage circuit 11 transitions to on or off, potentials between a gate V2 of an SF2 transistor Q12 in the post-stage circuit 12 and connection nodes VCR and VCD of each transistor in the selection circuit 14 and the plurality of first capacitors C1 and the plurality of second capacitors C2 may fluctuate due to capacitive coupling. This potential fluctuation is called a shutter step.

[0240] Therefore, in the present embodiment, the polysilicon gate 61 of the third capacitor C3 in the pre-stage circuit 11 is disposed between the pixel transistor 24 in the pre-stage circuit 11 and the above-described nodes V2, VCR, and VCD in the post-stage circuit 12 so that capacitive coupling does not occur between the pixel transistor 24 in the pre-stage circuit 11 and the above-described nodes V2, VCR, and VCD in the post-stage circuit 12. The polysilicon gate 61 is connected to the VDD node.

[0241] Fig. 55 is a layout diagram of one pixel of the light detection device 1 according to the sixth embodiment. As illustrated in Fig. 55, the polysilicon gate 61 of the MOS capacitor 30 configuring the third capacitor C3 in the pre-stage circuit 11 is disposed between the arrangement region of the pixel transistor 24 in the pre-stage circuit 11 and the arrangement region of each transistor in the post-stage circuit 12. In Fig. 55, the polysilicon gate 61 is bent along two sides of the pixel isolation region 35, but the polysilicon gate 61 may be disposed at least between the arrangement region of the pixel transistor 24 in the pre-stage circuit 11 and the arrangement region of each transistor in the post-stage circuit 12.

[0242] Therefore, even if the pixel transistor 24 in the pre-stage circuit 11 transitions to on or off, there is no possibility that the potentials of the nodes V2, VCR, and VCD in the post-stage circuit 12 fluctuate due to the influence of the crosstalk, and the shutter step can be suppressed.

[0243] Fig. 56 is a layout diagram of one pixel of a light detection device 1 according to a first modification of the sixth embodiment. The first modification illustrated in Fig. 56 is configured to suppress potential fluctuation due to crosstalk between adjacent pixels PX. In the first modification, not only the polysilicon gate 61 of the MOS capacitor 30 configuring the third capacitor C3 is disposed between the arrangement region of the pixel transistor 24 in the pre-stage circuit 11 and the arrangement region of each transistor in the post-stage circuit 12, but also the polysilicon gate 61 is disposed near the boundary with the adjacent pixel PX. In the first modification, the polysilicon gate 61 is disposed along the boundary with the pixel PX adjacent in the second direction Y. Therefore, crosstalk between two pixels PX adjacent to each other in the second direction Y can be suppressed.

[0244] Fig. 57 is a layout diagram of 2×1 pixels PX of a light detection device 1 according to a second modification of the sixth embodiment. The second modification illustrated in Fig. 57 includes a layout in which a pixel boundary line extending in the second direction Y is mirrored in the first direction X as a symmetry axis. Each pixel PX has a layout similar to that in Fig. 55. The polysilicon gate 61 near the boundary between two pixels PX adjacent in the first direction X is shared by the two pixels PX. Therefore, the width of the polysilicon gate 61 in which the two pixels PX are disposed along the adjacent side can be further widened, and the crosstalk between the two pixels PX can be further suppressed.

[0245] Fig. 58 is a layout diagram of 2×2 pixels PX of a light detection device 1 according to a third modification of the sixth embodiment. The third modification illustrated in Fig. 58 includes a layout in which a first pixel boundary line extending in a first direction X and a second pixel boundary line extending in a second direction Y are mirror-disposed in the first direction X and the second direction Y as symmetrical axes. The polysilicon gate 61 near the boundary between two pixels PX adjacent in the first direction X and the second direction Y is shared by the two pixels PX.

[0246] Although Figs. 57 and 58 illustrate an example in which each pixel PX has a layout similar to that in Fig. 55, each pixel PX may have a layout similar to that in Fig. 56.

[0247] Fig. 59 is a cross-sectional view of a light detection device 1 according to a fourth modification of the sixth embodiment. In the fourth modification illustrated in Fig. 59, the third capacitor C3 in the pre-stage circuit 11 is an MIM capacitor having an MIM structure. As illustrated in Fig. 59, the third capacitor C3 in the pre-stage circuit 11, the plurality of first capacitors C1 and the plurality of second capacitors C2 for sample hold are disposed in the wiring region 25 of the first substrate 21.

[0248] Fig. 60 is a layout diagram of the wiring region 25 of the first substrate 21 in Fig. 59. As illustrated, in the wiring region 25, regions of six first capacitors C1 and second capacitors C2 for sample hold and a region of a third capacitor C3 in the pre-stage circuit 11 are disposed.

[0249] The third capacitor C3 is a MIM capacitor, and then the third capacitor C3 is disposed in the wiring region 25 of the first substrate 21, and the electrode wiring layer of the third capacitor C3 cannot be disposed between the arrangement region of the pixel transistor 24 in the pre-stage circuit 11 and the arrangement region of each transistor in the post-stage circuit 12. Therefore, the VDD wiring layer or the VSS wiring layer may be disposed between the arrangement region of the pixel transistor 24 in the pre-stage circuit 11 and the arrangement region of each transistor in the post-stage circuit 12 to suppress the crosstalk.

[0250] Fig. 61 is a layout diagram of one pixel of a light detection device 1 according to a fifth modification of the sixth embodiment. In the fifth modification illustrated in Fig. 61, the VDD wiring layer 65 is disposed between the arrangement region of the pixel transistor 24 in the pre-stage circuit 11 and the arrangement region of each transistor in the post-stage circuit 12. Therefore, crosstalk between the pixel transistor 24 in the pre-stage circuit 11 and each transistor in the post-stage circuit 12 can be suppressed.

[0251] Fig. 62 is a layout diagram of one pixel of a light detection device 1 according to a sixth modification of the sixth embodiment. In the sixth modification illustrated in Fig. 62, the VSS wiring layer 66 is disposed between the arrangement region of the pixel transistor 24 in the pre-stage circuit 11 and the arrangement region of each transistor in the post-stage circuit 12. Therefore, crosstalk between the pixel transistor 24 in the pre-stage circuit 11 and each transistor in the post-stage circuit 12 can be suppressed.

[0252] As described above, in the sixth embodiment, in a case where the pre-stage circuit 11 and the post-stage circuit 12 are disposed on the same layer of the first substrate 21, the polysilicon gate 61, the VDD wiring layer 65, or the VSS wiring layer 66 of the third capacitor C3 in the pre-stage circuit 11 is disposed between the arrangement region of the pixel transistor 24 in the pre-stage circuit 11 and the arrangement region of each transistor in the post-stage circuit 12. Therefore, crosstalk between the pre-stage circuit 11 and the post-stage circuit 12 can be suppressed, and the image quality can be improved. (Information processing system)

[0253] Fig. 63 is a diagram illustrating an example configuration of the information processing system 1001 of the present disclosure. As illustrated in Fig. 63, an information processing system 1001 according to the present embodiment is configured as a head mounted display (HMD). The example configuration of the HMD of the present embodiment will be described with reference to Fig. 63.

[0254] In this example, the HMD 1001 includes an output mechanism unit 1011 and a mounting mechanism unit 1012. The mounting mechanism unit 1012 includes a mounting band 1013 that is worn by the user to secure the device to the head; however, the mounting band 1013 need not extend completely around the head as long as the device is fixed to the head.

[0255] The output mechanism unit 1011 includes a housing 1014 having a shape that covers a user’s left and right eyes when the user wears the HMD 1001 and includes a display panel disposed inside the housing 1014 so as to face the user’s eyes during use. The housing 1014 may further include a lens disposed between the display panel (the display unit 2005 of Fig. 65) and the user's eyes in worn state of the HMD 1001, the lens being configured to increase the user’s viewing angle. A stereo image corresponding to parallax between the two eyes may be displayed in respective right and left regions obtained by dividing the display panel, thereby enabling stereoscopic vision.

[0256] The HMD 1001 may further include a speaker or an earphone provided at a position corresponding to the user's ears when worn. In this example, the HMD 1001 features of a camera 1015 mounted on the front surface of the housing 1014, which captures the surrounding real space as a moving image corresponding to the user's line of sight.

[0257] The camera 1015 includes, for example, an image sensor such as a charge coupled device (CCD) sensor or a complementary metal oxide semiconductor (CMOS) sensor, a light detection device such as a distance measuring sensor, and an optical system such as an imaging lens. For example, as shown in Fig. 63, the stereo camera is configured to capture the space in front of the user from left and right viewpoints corresponding to the user’s left and right eyes. However, the camera 1015 is not limited to this configuration and the camera 1015 may be a monocular camera or consist of three or more multi-view cameras. Furthermore, a combination of various types of sensors may be used. In applications such as of hand tracking, the camera 1015 may be positioned to capture images of the space below the information processing system. For eye tracking or face tracking, the camera 1015 may be arranged to image the user's eyes or face.

[0258] The HMD 1001 further includes a sensor 2008 (Fig. 65). The sensor 2008 may include one or more types of sensors capable of deriving the motion, posture, position, or the like of the HMD 1001, such as an acceleration sensor, a gyroscope sensor, an angular velocity sensor, or a geomagnetic sensor.

[0259] The HMD 1001 may be connected to another processing device by wireless communication or the HMD 1001 may be wired by a universal serial bus (USB) or the like.

[0260] In this case, the HMD 1001 may execute an online application, such as a game, in which a plurality of users can participate via a network. In such a case, the HMD 1001 performs predetermined processing on the images captured by the camera 1015 and generates a display image corresponding to the camera’s 1015 field of view for presentation to the user.

[0261] Here, the content of the display image is not particularly limited and may vary depending on factors such as functions required by the user, the content of the activated application, and the like.

[0262] For example, the HMD 1001 may perform various processing operations on an image captured by the camera 1015 or may superimpose and render a virtual object that interacts with an image of a real object. Alternatively, the HMD 1001 may render a virtual world within a visual field corresponding to the user’s line of sight, based on the captured image, measurement values from a motion sensor included in the sensor group of the HMD 1001, or the like.

[0263] Representative examples of such aspects include virtual reality (VR), augmented reality (AR), and mixed reality (MR). Furthermore, a video see-through (VST)configuration, in which the real world is viewed through the screen of the HMD 1001, may be realized by directly using the image captured by the camera 1015 as the display image.

[0264] Fig. 64 is a diagram illustrating an example configuration of the information processing system 1101 according to the present disclosure. As shown in Fig. 64, the information processing system 1101 according to the present embodiment is configured as a glass-type HMD.

[0265] An HMD main body 1111 is worn on the head of the user. The HMD main body 1111 includes a front portion 1112, a right temple portion 1113 provided on the right side of the front portion 1112, a left temple portion 1114 provided on a left side of the front portion 1112, and a glass portion 1115 attached to a lower side of the front portion 1112. It should be noted that, although a single integrated glass portion is illustrated in Fig. 64, the configuration is not limited to this and may include two separate glass portions for the respective eyes or may cover only one eye.

[0266] The display unit 1103 is a see-through type display unit provided on a surface of the glass portion 1115. The display unit 1103 performs AR display of a virtual object under control of the processing circuit 2001. It should be noted that the display unit 1103 may alternatively be a non-see-through type display unit. In such a case, an image in which a virtual object is superimposed on the image currently captured by the camera 1104 is displayed on the display unit 1103, thereby realizing AR display.

[0267] The camera 1104 includes, for example, an image sensor such as a charge coupled device (CCD) sensor or a complementary metal oxide semiconductor (CMOS) sensor, a light detection device such as a distance measuring sensor, and an optical system such as an imaging lens. The camera 1104 is provided outward on an outer surface of the front unit 1112, captures an object in the real space, and outputs image information obtained by the imaging to the processing circuit 2001. In the example configuration of Fig. 64, two cameras 1104 are provided at predetermined intervals in the lateral direction in the front part 1112. It should be noted that the camera 1104 is not limited to this configuration and may instead be a monocular camera or a set of three or more multi-view cameras. Furthermore, various types of sensors may be used in combination. For hand tracking applications, the camera 1104 may be arranged to capture a space below the information processing system. For eye tracking or face tracking applications, the camera 1104 may be arranged to image the user's eyes or face.

[0268] The glass-type HMD 1101 furthermore includes a sensor 2008 (Fig. 65). The sensor 2008 may include at least one of various types of sensors capable of deriving the motion, posture, position, and the like of the HMD 1001, such as an acceleration sensor, a gyroscope sensor, an angular velocity sensor, or a geomagnetic sensor.

[0269] Next, a hardware configuration example of the information processing system (i.e., the HMD 1001 or the glass-type HMD 1101) will be described with reference to Fig. 65. As illustrated in Fig. 65, the hardware of the information processing system includes a processing circuit 2001, a memory 2002, a camera 2003, a display unit 2005, an input unit 2006, an output unit 2007, a sensor 2008, a communication interface (IF) 2009, an external network 2010, and a secondary storage device 2011. These components are connected to one another via a bus 2012 and are capable of transmitting and receiving data and programs.

[0270] The processing circuit 2001 operates based on a program stored in the memory 2002 or the secondary storage device 2011 and controls the overall operation of the information processing systems 1001 and 1101. The processing circuit 2001 may be implemented, for example, as a processor that reads and executes programs stored in the memory 2002 to implement functions corresponding to executed program. The processor may include, for example, any one or more of a multi-core processor, a controller, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), an equivalent discrete logic circuit, or an integrated logic circuit. The processing circuit 2001 may also be implemented as a plurality of separate chips.

[0271] The memory 2002 may be implemented using, for example, a semiconductor memory element such as a random access memory (RAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electronically erasable programmable read-only memory (EEPROM), or a flash memory, a hard disk, an optical disc, or the like. The memory 2002 and may include any form of memory capable of storing data and executable software instructions.

[0272] The camera 2003 corresponds to the camera 1015 in Fig. 63 and the camera 1104 in Fig. 64 and includes a light detection device such as an image sensor or a distance measuring sensor, for example, a charge coupled device (CCD) sensor or a complemented metal oxide semiconductor (CMOS) sensor, and an optical system such as an imaging lens.

[0273] The display unit 2005 is a display panel provided inside the housing 1014 and includes a display device including a liquid crystal display (LCD), an organic electroluminescence (EL), or the like.

[0274] Although not illustrated in Figs. 63 and 64, the input unit 2006 includes an input device such as a keyboard, a mouse, a touch panel, a microphone, or a controller through which the user inputs operation commands. The input unit 2006 supplies various input signals to the processing circuit 2001.

[0275] The output unit 2007 includes an audio output device such as a speaker, a haptic presentation device, an odor presentation device, or the like. The output unit 2007 is controlled by the processing circuit 2001, and outputs processing results such as voice, haptic feedback, odor, or the like.

[0276] The sensor 2008 may include one of more types of sensors for deriving the movement, posture, position, or the like of the HMDs 1001 and 1101, such as an acceleration sensor, a gyroscope sensor, an angular velocity sensor, or a geomagnetic sensor. Furthermore, the sensor 2008 may include a biological sensor configured to sense biological information of a user or a pressure sensor configures to sense input.

[0277] The communication interface 2009 servers as an interface for connecting the information processing systems 1001 and 1101 to the external network 2010. Communication may be performed in a wired or wireless manner with a smartphone or other external devices, such as a personal computer (PC), a server device on a network, or the like. For example, the processing circuit 2001 receives data from, or transmits data to, another device via the communication interface 2009.

[0278] An example of the information processing system to which the technology according to the present disclosure may be applied has been described above. The technology according to the present disclosure can be applied, for example, to a light detection device 2004 included in the aforementioned configurations. For example, in the display unit 2005 illustrated in Fig. 65, a region of interest is displayed based on the Z1 image output from the light detection device 2004, while regions other than the region of interest are displayed based on at least one of the Z2 and Z3 images output from the light detection device 2004. Consequently, the display processing in the information processing systems 1001 and 1101 can be reduced, thereby reducing the power consumption. Furthermore, it is possible to perform display on the display unit 2005 based on image data output from the light detection device 2004 at different frame rates. Additionally, in the signal processing device 111 included in the processing circuit 2001 of the information processing systems 1001 and 1101, the Z1 image is processed at a first frequency, while the Z2 image is processed at a second frequency. As described above, by performing processing i at the first frequency for the Z1 image corresponding to the region of interest, and at the second frequency lower than the first frequency for the Z2 and Z3 images corresponding to the regions other than the region of interest, the load of the image processing can be reduced, thereby reducing the power consumption of the information processing system.

[0279] <Example of application to moving body> The technology according to the present disclosure (present technology) can be applied to various products. For example, the technology according to the present disclosure may be implemented in the form of a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility devices, an airplane, a drone, a vessel, or a robot.

[0280] Fig. 66 is a block diagram illustrating an example of a schematic configuration of a vehicle control system as an example of a moving body control system to which the technology according to the present disclosure can be applied.

[0281] A vehicle control system 12000 includes a plurality of electronic control units connected to one another via a communication network 12001. In the example illustrated in Fig. 66, the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an in-vehicle information detection unit 12040, and an integrated control unit 12050. Furthermore, the integrated control unit 12050 is functionally configured to include a microcomputer 12051, a sound / image output unit 12052, and a vehicle-mounted network interface (I / F) 12053.

[0282] The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various programs. For example, the driving system control unit 12010 functions as a control device for a driving force generating device, such as an internal combustion engine or a driving motor, a driving force transmitting mechanism configured to transmit driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

[0283] The body system control unit 12020 controls the operation of various devices provided to a vehicle body in accordance with various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, and various lamps such as a headlamp, backup lamp, brake lamp, turn signal, fog lamp, or the like. In this case, radio waves transmitted from a mobile device acting as an alternative to a key, or signals from various switches, may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the door lock device, power window device, lamps, or other components of the vehicle accordingly.

[0284] The outside-vehicle information detecting unit 12030 detects information related to the exterior of the vehicle equipped with the vehicle control system 12000. For example, the outside-vehicle information detecting unit 12030 is connected to an imaging unit 12031. The outside-vehicle information detecting unit 12030 causes the imaging unit 12031 to capture images of the exterior of the vehicle and receives the captured images. Based on the received images, the outside-vehicle information detecting unit 12030 may perform processing of detected objects such as humans, vehicles, obstacles, signs, characters on the road surface, and the like, and may also detect distances to such objects.

[0285] The imaging unit 12031 is an optical sensor that receives light and outputs an electric signal corresponding to a received amount of light. The imaging unit 12031 can output the electric signal as an image or as information relating to a measured distance. Furthermore, the light received by the imaging unit 12031 may be visible light or invisible light such as infrared rays.

[0286] The in-vehicle information detecting unit 12040 detects information relating to the interior of the vehicle. The in-vehicle information detecting unit 12040 is, for example, connected with a driver state detection unit 12041 that detects the state of a driver. The driver state detection unit 12041 may include a camera configured to image the driver. Based on detection information input from the driver state detection unit 12041, the in-vehicle information detecting unit 12040 may calculate the driver’s degree of fatigue, degree of concentration of the driver, or determine whether the driver is dozing off.

[0287] The microcomputer 12051 can calculate control target values for the driving force generating device, the steering mechanism, or the braking device based on information obtained by the outside-vehicle information detecting unit 12030 and the in-vehicle information detecting unit 12040, and output corresponding control commends to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS), including collision avoidance or shock mitigation, following driving based on a following distance, vehicle speed maintenance, warnings of potential collision, lane departure warnings, and the like.

[0288] Furthermore, the microcomputer 12051 can perform cooperative control for automated driving, enabling the vehicle to travel automatically without reliance on driver operation. This is achieved by controlling the driving force generating device, steering mechanism, braking device, or other systems based on information obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040.

[0289] Furthermore, the microcomputer 12051 can also output control commands to the body system control unit 12020 based on information about the vehicle’s exterior obtained by the outside-vehicle information detecting unit 12030. For example, the microcomputer 12051 can prevent glare by controlling the headlamp to switch from a high beam to a low beam in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030.

[0290] The sound / image output unit 12052 transmits output signals corresponding to sound and / or an image to an output device capable of visually or auditorily notifying information to occupants or persons outside the vehicle. In the example of Fig. 66, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as the output device. The display unit 12062 may include, for example at least one of an on-board display and a head-up display.

[0291] Fig. 67 is a diagram illustrating an example of the installation position of the imaging unit 12031.

[0292] In Fig. 67, imaging units 12101, 12102, 12103, 12104, and 12105 are included as the imaging unit 12031.

[0293] The imaging units 12101, 12102, 12103, 12104, and 12105 are, for example, disposed at positions on a front nose, sideview mirrors, a rear bumper, and back door of the vehicle 12100, as well as an upper portion of a windshield within the interior of the vehicle. The imaging unit 12101, provided on the front nose, and the imaging unit 12105, provided at the upper portion of the windshield, primarily captures images of the front of the vehicle 12100. The imaging units 12102 and 12103, provided on the sideview mirrors, primarily capture images of the sides of the vehicle 12100. The imaging unit 12104, provided on the rear bumper or back door, primarily captures images of the rear of vehicle 12100. The imaging unit 12105, inside the vehicle, is mainly used to detect preceding vehicles, pedestrians, obstacles, signals, traffic signs, lanes, and the like.

[0294] It should be noted that Fig. 67 illustrates example imaging ranges of the imaging units 12101 to 12104. An imaging range 12111 represents the imaging range of the imaging unit 12101 on the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging units 12102 and 12103 one the side view mirrors the. An imaging range 12114 represents the imaging range of the imaging unit 12104 on the rear bumper or the back door. A bird's-eye image of the vehicle 12100 as viewed from above can be obtained by superimposing image data captured by the imaging units 12101 to 12104.

[0295] At least one of the imaging units 12101 to 12104 may have the capability to obtain distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements or maybe an imaging element having pixels for phase difference detection.

[0296] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and temporal changes in distance (relative speed with respect to the vehicle 12100) based on distance information obtained from imaging units 12101 to 12104. Thereby, the microcomputer 12051 can extract, as a preceding vehicle, the nearest three-dimensional object on a traveling path of the vehicle 12100 and that travels in substantially the same direction at a predetermined speed (for example, equal to or more than 0 km / hour). Moreover, the microcomputer 12051 can set in advance a following distance to be maintained in front of the preceding vehicle and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or similar operations. This, cooperative control for automated driving can be performed to enable the vehicle to travel automatically without depending on the driver’s operation.

[0297] For example, the microcomputer 12051 can classify three-dimensional object data into categories such as two-wheeled vehicles, standard-sized vehicles, large-sized vehicles, pedestrians, utility poles, and other objects based on distance information from the imaging units 12101 to 12104. The extracted classified three-dimensional object data may be used for automatic obstacle avoidance. For instance, the microcomputer 12051 identifies obstacles around the vehicle 12100 as those recognizable visually by the driver and those difficult for the driver to visually recognize. The microcomputer 12051 then determines a collision risk for each obstacle. When the collision risk equals or exceeds a set threshold, indicating a potential collision, the microcomputer 12051 outputs warnings via the audio speaker 12061 or the display unit 12062, and executes forced deceleration or avoidance steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist the driver in collision avoidance.

[0298] At least one of the imaging units 12101 to 12104 may be an infrared camera configured to detect infrared rays. For example, the microcomputer 12051 can recognize pedestrians by analyzing images captured in infrared cameras among the imaging units 12101 to 12104. Pedestrian recognition may be performed by extracting characteristic points representing object contours from infrared images and applying pattern matching to determine whether the object is a pedestrian. Upon recognizing a pedestrian, microcomputer 12051 controls the sound / image output unit 12052 to display a square contour line superimposed on the recognized pedestrian on the display unit 12062. Additionally, the sound / image output unit 12052 may display an icon or similar indicator representing the pedestrian at a desired position.

[0299] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 12031 and related configurations described above.

[0300] It should be noted the present technology may have the following configurations. (1) A light detection device including: a photoelectric conversion element that accumulates charges corresponding to a light amount of incident light; a pre-stage circuit capable of switching a plurality of photoelectric conversion efficiencies, the pre-stage circuit performing control of transferring the accumulated charges of the photoelectric conversion element to a floating diffusion region, control of initializing the accumulated charges of the photoelectric conversion element and retained charges of the floating diffusion region, and control of generating a voltage signal according to the retained charges of the floating diffusion region; a plurality of first capacitors that holds a reset level of the voltage signal for each of the plurality of photoelectric conversion efficiencies; a plurality of second capacitors holds a signal level of the voltage signal for each of the plurality of photoelectric conversion efficiencies; a post-stage circuit that selects one of the plurality of first capacitors and the plurality of second capacitors and outputs a generated pixel signal to a signal line; a first substrate on which the photoelectric conversion element and at least a part of the pre-stage circuit are mounted; and a second substrate laminated on the first substrate and on which the plurality of first capacitors, the plurality of second capacitors, and the post-stage circuit are mounted, in which the pre-stage circuit includes: a third capacitor that stores a part of the accumulated charges of the photoelectric conversion element at a time of selecting the first photoelectric conversion efficiency; a first transistor that transfers the accumulated charges of the photoelectric conversion element to the floating diffusion region; a second transistor that discharges the accumulated charges in the photoelectric conversion element; a third transistor that discharges the accumulated charges of the photoelectric conversion element to a predetermined reference voltage node via the second transistor; a fourth transistor that switches whether or not to block a charge transfer path between the third capacitor and the floating diffusion region; and a fifth transistor that switches whether or not to block a connection node between the second transistor and the third transistor and a connection node between the third capacitor and the fourth transistor. (2) The light detection device according to item (1), in which the second transistor, the third transistor, and the fifth transistor are connected to a same first diffusion region. (3) The light detection device according to item (1) or (2), in which the third capacitor, the fourth transistor, and the fifth transistor are connected to a same second diffusion region. (4) The light detection device according to any one of items (1) to (3), in which the pre-stage circuit includes a sixth transistor that switches whether or not to block a charge transfer path between the fourth transistor and the floating diffusion region, and a third diffusion region is provided which is disposed in a region surrounded by gates of the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor and is set to a predetermined reference voltage level. (5) The light detection device according to any one of items (1) to (4), in which the second transistor and the first transistor are disposed adjacent to and substantially parallel to vicinity of a substantially center of a pixel region. (6) The light detection device according to any one of items (1) to (5), in which one electrode of the third capacitor is disposed in a same layer as that of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor on the first substrate. (7) The light detection device according to any one of items (1) to (6), in which a pixel isolation region is disposed in a boundary region of a pixel region, and the third capacitor is disposed along the pixel isolation region. (8) The light detection device according to item (7), further including a fourth diffusion region disposed inside the pixel region along the pixel isolation region, in which the photoelectric conversion element is disposed inside the fourth diffusion region and includes a photoelectric conversion region of a conductivity type different from that of the fourth diffusion region. (9) The light detection device according to any one of items (1) to (7), in which the photoelectric conversion element includes a photoelectric conversion region disposed in a depth direction from a same layer as that of the floating diffusion region. (10) The light detection device according to any one of items (1) to (9), in which the third capacitor is a metal-oxide-semiconductor (MOS) capacitor having a polysilicon gate set to a predetermined reference voltage level. (11) The light detection device according to any one of items (1) to (9), in which the third capacitor includes: a fifth diffusion region of a predetermined conductivity type; an insulating layer disposed along an inner wall of a trench extending in a depth direction from the fifth diffusion region; and a conductive layer disposed inside the trench to cover the insulating layer. (12) The light detection device according to item (11), in which the conductive layer is disposed along a pixel isolation region. (13) The light detection device according to item (12), in which the conductive layer is set to a predetermined reference voltage. (14) The light detection device according to any one of items (11) to (13), in which the insulating layer is a ZAZ structure in which ZrO2, Al2O3, and ZrO2are laminated, or a dielectric layer containing HfO2. (15) The light detection device according to any one of items (11) to (14), in which the conductive layer contains TiN. (16) The light detection device according to any one of items (1) to (9), in which the third capacitor has a metal-insulator-metal (MIM) structure. (17) The light detection device according to item (16), in which the third capacitor is disposed on a wiring region of the first substrate. (18) The light detection device according to item (16), in which the third capacitor is disposed on a wiring region of the second substrate. (19) The light detection device according to item (18), in which the first capacitor, the second capacitor, and the third capacitor are disposed on a wiring region of the second substrate. (20) The light detection device according to item (19), in which the first capacitor, and the second capacitor and the third capacitor are disposed on different layers of a wiring region of the second substrate. (21) The light detection device according to item (19), in which the first capacitor, the second capacitor, and the third capacitor are disposed in a same layer of a wiring region of the second substrate. (22) The light detection device according to any one of items (1) to (21), in which a fifth diffusion region connected to the second transistor, the third transistor, and the fifth transistor and a gate region of the second transistor are disposed at a distance causing capacitive coupling. (23) The light detection device according to any one of items (1) to (22), in which a first wiring layer set to a first reference voltage and a second wiring layer set to a second reference voltage are disposed between the floating diffusion region and a gate region of the third transistor. (24) The light detection device according to any one of items (1) to (23), in which the third capacitor and the third transistor are connected to a reference voltage wiring at a same voltage level. (25) The light detection device according to any one of items (1) to (24), in which the pre-stage circuit includes: a seventh transistor that converts the charges held in the floating diffusion region into the voltage signal, the post-stage circuit includes: a current source that causes a bias current to flow through the seventh transistor; a tenth transistor that generates the pixel signal according to an output voltage of the pre-stage circuit; an eleventh transistor that outputs the pixel signal to the signal line in synchronization with a selection signal; a plurality of twelfth transistors that switches whether or not to supply a voltage signal corresponding to the reset level held in any one of the plurality of first capacitors to a gate of the tenth transistor; and a plurality of thirteenth transistors that switches whether or not to supply a voltage signal corresponding to the signal level held in any one of the plurality of second capacitors to a gate of the tenth transistor, the current source includes an eighth transistor and a ninth transistor cascode-connected between an output node of the pre-stage circuit and a predetermined reference voltage node, the tenth transistor and the eleventh transistor are disposed in a first direction with a common drain region, the twelfth transistor and the thirteenth transistor having a same conversion efficiency are disposed in the first direction with a common drain region, and the eighth transistor and the ninth transistor are disposed in a second direction intersecting the first direction. (26) The light detection device according to item (25), in which the post-stage circuit includes a fourteenth transistor that switches between conduction and interruption between an output node of the pre-stage circuit and a gate of the tenth transistor. (27) The light detection device according to item (26), in which the fourteenth transistor is disposed in the second direction together with the eighth transistor and the ninth transistor. (28) The light detection device according to any one of items (1) to (27), further including a plurality of pixels arranged in a first direction and a second direction intersecting each other, in which each of the plurality of pixels includes the photoelectric conversion element, the pre-stage circuit, the plurality of first capacitors, the plurality of second capacitors, and the post-stage circuit, and the two pixels adjacent to each other in at least one of the first direction and the second direction share at least a part of the third capacitor. (29) The light detection device according to item (28), in which the third capacitor is a MOS capacitor having a gate formed of a polysilicon layer, and the polysilicon layer is disposed along a boundary region between the two pixels adjacent to each other in at least one of the first direction and the second direction. (30) The light detection device according to item (28), in which the third capacitor includes: a fifth diffusion region of a predetermined conductivity type; an insulating layer disposed along an inner wall of a trench extending in a depth direction from the fifth diffusion region; and a polysilicon layer disposed inside the trench to cover the insulating layer, and the polysilicon layer is disposed along a pixel isolation region. (31) The light detection device according to item (29) or (30), in which at least one contact extending from the polysilicon layer in a laminating direction is disposed in each of the two pixels. (32) The light detection device according to any one of items (29) to (31), further including at least one contact extending from the polysilicon layer in a laminating direction and shared by the two pixels. (33) The light detection device according to item (32), in which the contact is disposed in a boundary region between two adjacent pixels. (34) The light detection device according to any one of items (29) to (33), in which the two pixels adjacent to each other in at least one of the first direction and the second direction have a symmetrical structure with respect to a boundary line between the two pixels, and the polysilicon layer is disposed along the boundary line. (35) The light detection device according to any one of items (29) to (33), in which the four pixels adjacent to each other in the first direction and the second direction have a symmetrical structure with respect to the first direction and the second direction, and the polysilicon layer is disposed along a boundary line between the four pixels adjacent in the first direction and the second direction. (36) The light detection device according to any one of (1) to (35), further including a third substrate laminated on the second substrate and on which a logic circuit is mounted. (37) A light detection device including: a photoelectric conversion element that accumulates charges corresponding to a light amount of incident light; a pre-stage circuit capable of switching a plurality of photoelectric conversion efficiencies, the pre-stage circuit performing control of transferring the accumulated charges of the photoelectric conversion element to a floating diffusion region, control of initializing the accumulated charges of the photoelectric conversion element and retained charges of the floating diffusion region, and control of generating a voltage signal according to the retained charges of the floating diffusion region; a plurality of first capacitors that holds a reset level of the voltage signal for each of the plurality of photoelectric conversion efficiencies; a plurality of second capacitors holds a signal level of the voltage signal for each of the plurality of photoelectric conversion efficiencies; a post-stage circuit that selects one of the plurality of first capacitors and the plurality of second capacitors and outputs a generated pixel signal to a signal line; a first substrate on which the photoelectric conversion element, the pre-stage circuit, the plurality of first capacitors, the plurality of second capacitors, and the post-stage circuit are mounted; and a second substrate laminated on the first substrate and on which a logic circuit is mounted, in which the pre-stage circuit includes: a third capacitor that stores a part of the accumulated charges of the photoelectric conversion element at a time of selecting the first photoelectric conversion efficiency; a first transistor that transfers the accumulated charges of the photoelectric conversion element to the floating diffusion region; a second transistor that discharges the accumulated charges in the photoelectric conversion element; a third transistor that discharges the photoelectric conversion element to a predetermined reference voltage node through the second transistor; a fourth transistor that switches whether or not to block a charge transfer path between the third capacitor and the floating diffusion region; a fifth transistor that switches whether or not to block a charge transfer path between a connection node of the third capacitor and the first transistor, and the second transistor; a sixth transistor that switches whether or not to block a charge transfer path between the fourth transistor and the floating diffusion region; and a seventh transistor that converts the charges held in the floating diffusion region into the voltage signal, and the post-stage circuit includes: a current source that is cascode-connected between an output node of the pre-stage circuit and a predetermined reference voltage node and includes an eighth transistor and a ninth transistor that cause a bias current to flow in the seventh transistor; a tenth transistor that generates the pixel signal according to an output voltage of the pre-stage circuit; an eleventh transistor that outputs the pixel signal to the signal line in synchronization with a selection signal; a plurality of twelfth transistors that switches whether or not to supply a voltage signal corresponding to the reset level held in any one of the plurality of first capacitors to a gate of the tenth transistor; and a plurality of thirteenth transistors that switches whether or not to supply a voltage signal corresponding to the signal level held in any one of the plurality of second capacitors to a gate of the tenth transistor. (38) The light detection device according to item (37), in which the third capacitor is a metal-oxide-semiconductor (MOS) capacitor disposed on a same layer as that of an arrangement place of each transistor in the pre-stage circuit and the post-stage circuit on the first substrate. (39) The light detection device according to item (38), in which the MOS capacitor includes a polysilicon gate set to a predetermined reference voltage, and the polysilicon gate is disposed between an arrangement region of the pre-stage circuit and an arrangement region of the post-stage circuit. (40) The light detection device according to item (39), in which the polysilicon gate is disposed between a first arrangement region including the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor and a second arrangement region including the tenth transistor, the eleventh transistor, the plurality of twelfth transistors, and the plurality of thirteenth transistors. (41) The light detection device according to item (39), further including two pixels disposed adjacent to each other in a predetermined direction, in which each of the two pixels includes the photoelectric conversion element, the pre-stage circuit, the plurality of first capacitors, the plurality of second capacitors, and the post-stage circuit, and the polysilicon gate is disposed along a boundary region between the two pixels. (42) The light detection device according to item (37), in which the third capacitor is a metal-insulator-metal (MIM) capacitor. (43) The light detection device according to item (42), in which the third capacitor is disposed on a layer different from an arrangement region of the pre-stage circuit and the post-stage circuit on the first substrate. (44) The light detection device according to item (43), in which each of the plurality of first capacitors and the plurality of second capacitors is an MIM capacitor, and the third capacitor, the plurality of first capacitors, and the plurality of second capacitors are disposed on a same layer in the first substrate. (45) The light detection device according to any one of items (42) to (44), further including a wiring layer set to a predetermined reference voltage level and disposed between a first arrangement region including the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor and a second arrangement region including the tenth transistor, the eleventh transistor, the plurality of twelfth transistors, and the plurality of thirteenth transistors. (46) The light detection device according to item (45), in which the wiring layer is set to a power supply voltage level or a ground voltage level.

[0301] Modes of the present disclosure are not limited to the individual embodiments described above but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the contents described above. That is, various additions, modifications, and partial deletions can be made without departing from the conceptual idea and spirit of the present disclosure derived from the contents defined in the claims and equivalents thereof.

[0302] 1 Light detection device 2 Vertical scanning circuit 3 Pixel array unit 4 Timing control circuit 5 DAC 6 Load MOS circuit 7 Column signal processing circuit 8 Row selection line 11 Pre-stage circuit 12 Post-stage circuit 13 Current source 14 Selection circuit 15 ADC 16 Digital signal processing circuit 21 First substrate 22 Second substrate 23 Third substrate 24 Pixel transistor 25, 26 Wiring region 27 Logic circuit 28 Color filter layer 29 On-chip lens 30 MOS capacitor 31, 32 Diffusion region 33 VSS wiring layer 34 Pixel region 35 Pixel isolation region 36 Photoelectric conversion region 36a plug region 37 Solid-phase diffusion region 38 P-type diffusion layer 39 N-type diffusion layer 40 Element isolation region 41 VDD wiring region 42 VSS wiring region 43 Trench capacitor 44 P-type well region 45 Trench 46 Oxide layer 47 Conductive layer 51, 52, 53, 54 Diffusion region 55, 56, 57, 58 Arrangement row 60 Gate wiring 61 polysilicon gate 62 Polysilicon layer 63, 64 Contact 65 VDD wiring layer 66 VSS wiring layer

Claims

1. A light detection device, comprising: a photoelectric conversion element configured to accumulate charges corresponding to an amount of incident light; a first circuit configured to switch between a plurality of photoelectric conversion efficiencies; a plurality of first capacitors configured to hold a reset level of a voltage signal for each of the plurality of photoelectric conversion efficiencies; a plurality of second capacitors configured to hold a signal level of the voltage signal for each of the plurality of photoelectric conversion efficiencies; a second circuit configured to select one of the plurality of first capacitors and the plurality of second capacitors and to output a generated pixel signal to a signal line; a first substrate on which the photoelectric conversion element and at least a part of the first circuit are mounted; and a second substrate laminated on the first substrate and on which the plurality of first capacitors, the plurality of second capacitors, and the second circuit are mounted, wherein the second circuit comprises: a third capacitor configured to store a part of the accumulated charges of the photoelectric conversion element at a time of selecting a first photoelectric conversion efficiency of the plurality of photoelectric efficiencies; a first transistor configured to transfer the accumulated charges of the photoelectric conversion element to a floating diffusion region; a second transistor configured to discharge the accumulated charges in the photoelectric conversion element; a third transistor configured to discharge the accumulated charges of the photoelectric conversion element to a predetermined reference voltage node via the second transistor; a fourth transistor configured to switch between blocking and permitting a charge transfer path between the third capacitor and the floating diffusion region; and a fifth transistor configured to switch between blocking and permitting a connection node between the second transistor and the third transistor and a connection node between the third capacitor and the fourth transistor.

2. The light detection device according to claim 1, wherein the second transistor, the third transistor, and the fifth transistor are connected to a same first diffusion region.

3. The light detection device according to claim 1, wherein the third capacitor, the fourth transistor, and the fifth transistor are connected to a same second diffusion region.

4. The light detection device according to claim 1, wherein the first circuit includes a sixth transistor configured to switch between blocking and permitting a charge transfer path between the fourth transistor and the floating diffusion region, and a third diffusion region is disposed in a region surrounded by gates of the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor and is set to a predetermined reference voltage level.

5. The light detection device according to claim 1, wherein the second transistor and the first transistor are disposed adjacent to and substantially parallel to a central region of a pixel region.

6. The light detection device according to claim 1, wherein one electrode of the third capacitor is disposed in a same layer as that of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor on the first substrate.

7. The light detection device according to claim 1, wherein a pixel isolation region is disposed in a boundary region of a pixel region, and the third capacitor is disposed along the pixel isolation region.

8. The light detection device according to claim 1, wherein the third capacitor is a metal-oxide-semiconductor (MOS) capacitor having a polysilicon gate set to a predetermined reference voltage level.

9. The light detection device according to claim 1, wherein the third capacitor includes: a fifth diffusion region of a predetermined conductivity type; an insulating layer disposed along an inner wall of a trench extending in a depth direction from the fifth diffusion region; and a conductive layer disposed between the inner wall of the trench and insulating layer.

10. The light detection device according to claim 1, wherein the third capacitor has a metal-insulator-metal (MIM) structure.

11. The light detection device according to claim 1, wherein a fifth diffusion region, which is connected to the second transistor, the third transistor, and the fifth transistor and a gate region of the second transistor are spaced apart by distance that causes capacitive coupling therebetween.

12. The light detection device according to claim 1, wherein a first wiring layer set to a first reference voltage and a second wiring layer set to a second reference voltage are disposed between the floating diffusion region and a gate region of the third transistor.

13. The light detection device according to claim 1, wherein the first circuit comprises: a seventh transistor configured to convert the charges held in the floating diffusion region into the voltage signal, the second circuit comprises: a current source configured to cause a bias current to flow through the seventh transistor; a tenth transistor configured to generate the pixel signal according to an output voltage of the first circuit; an eleventh transistor configured to output the pixel signal to the signal line in synchronization with a selection signal; a plurality of twelfth transistors configured to switch between supplying and not supplying a voltage signal corresponding to the reset level held in any one of the plurality of first capacitors to a gate of the tenth transistor; and a plurality of thirteenth transistors configured to switch between supplying and not supplying a voltage signal corresponding to the signal level held in any one of the plurality of second capacitors to a gate of the tenth transistor, the current source includes an eighth transistor and a ninth transistor cascode-connected between an output node of the first circuit and a predetermined reference voltage node, the tenth transistor and the eleventh transistor are disposed in a first direction with a common drain region, the twelfth transistor and the thirteenth transistor having a same conversion efficiency are disposed in the first direction with a common drain region, and the eighth transistor and the ninth transistor are disposed in a second direction perpendicular to the first direction.

14. The light detection device according to claim 1, further comprising: a plurality of pixels arranged in a first direction and a second direction intersecting each other, wherein each of the plurality of pixels includes the photoelectric conversion element, the first circuit, the plurality of first capacitors, the plurality of second capacitors, and the second circuit, and two adjacent pixels in at least one of the first direction and the second direction of the plurality of pixels, share at least a part of the third capacitor.

15. The light detection device according to claim 14, wherein the third capacitor is a metal-oxide-semiconductor (MOS) capacitor having a gate formed of a polysilicon layer, and the polysilicon layer is disposed along a boundary region between the two adjacent pixels in at least one of the first direction and the second direction.

16. The light detection device according to claim 1, further comprising: a third substrate laminated on the second substrate and on which a logic circuit is mounted.

17. A light detection device, comprising: a photoelectric conversion element configured to accumulate charges corresponding to an amount of incident light; a first circuit configured to switch between a plurality of photoelectric conversion efficiencies; a plurality of first capacitors configured to hold a reset level of the voltage signal for each of the plurality of photoelectric conversion efficiencies; a plurality of second capacitors configured to hold a signal level of a voltage signal for each of the plurality of photoelectric conversion efficiencies; a second circuit configured to select one of the plurality of first capacitors and the plurality of second capacitors and outputs a generated pixel signal to a signal line; a first substrate on which the photoelectric conversion element, the first circuit, the plurality of first capacitors, the plurality of second capacitors, and the second circuit are mounted; and a second substrate laminated on the first substrate and on which a logic circuit is mounted, wherein the first circuit comprises: a third capacitor configured to store a part of the accumulated charges of the photoelectric conversion element at a time of selecting a first photoelectric conversion efficiency; a first transistor configured to transfer the accumulated charges of the photoelectric conversion element to a floating diffusion region; a second transistor configured to discharge the accumulated charges in the photoelectric conversion element; a third transistor configured to discharge the photoelectric conversion element to a predetermined reference voltage node through the second transistor; a fourth transistor configured to switch between blocking and permitting a charge transfer path between the third capacitor and the floating diffusion region; a fifth transistor configured to switch between blocking and permitting a charge transfer path between a connection node of the third capacitor and the first transistor, and the second transistor; a sixth transistor that configured to switch between blocking and permitting a charge transfer path between the fourth transistor and the floating diffusion region; and a seventh transistor configured to convert the charges held in the floating diffusion region into the voltage signal, and the second circuit comprises: a current source that is cascode-connected between an output node of the first circuit and a predetermined reference voltage node and includes an eighth transistor and a ninth transistor that cause a bias current to flow in the seventh transistor; a tenth transistor configured to generate the pixel signal according to an output voltage of the first circuit; an eleventh transistor configured to output the pixel signal to the signal line in synchronization with a selection signal; a plurality of twelfth transistors configured to switch supplying and not supplying a voltage signal corresponding to the reset level held in any one of the plurality of first capacitors to a gate of the tenth transistor; and a plurality of thirteenth transistors configured to switch between supplying and not supplying a voltage signal corresponding to the signal level held in any one of the plurality of second capacitors to a gate of the tenth transistor.

18. The light detection device according to claim 17, wherein the third capacitor is a metal-oxide-semiconductor (MOS) capacitor disposed on a same layer as that of each transistor in the first circuit and the second circuit on the first substrate.

19. The light detection device according to claim 18, wherein the MOS capacitor includes a polysilicon gate set to a predetermined reference voltage, and the polysilicon gate is disposed between the first circuit and the second circuit.

20. The light detection device according to claim 19, further comprising: two pixels of a plurality of pixels disposed adjacent to each other in a predetermined direction, wherein each of the two pixels includes the photoelectric conversion element, the first circuit, the plurality of first capacitors, the plurality of second capacitors, and the second circuit, and the polysilicon gate is disposed along a boundary region between the two pixels.

Images