Relay substrate, composite wiring board, and semiconductor device

Abstract

A relay substrate according to the present disclosure connects a plurality of semiconductor elements to a wiring board. The relay substrate comprises an organic resin substrate, a plurality of first wires, and a plurality of second wires. The plurality of first wires are located inside the substrate and electrically connect the plurality of semiconductor elements to the wiring board. The plurality of second wires are located inside the substrate and electrically connect semiconductor elements to each other. When viewed in plan view, the plurality of second wires are arranged at intervals in a first direction orthogonal to the direction in which the plurality of semiconductor elements are arranged. Each second wire comprises a diffusion barrier layer on side surfaces.

Description

Interposer substrate, composite wiring substrate and semiconductor device

[0001] The present disclosure relates to an interposer substrate, a composite wiring substrate and a semiconductor device.

[0002] Conventionally, there has been known a technique of mounting a plurality of semiconductor elements on a single base substrate via an interposer substrate made of organic resin called an interposer.

[0003] Patent Document 1 discloses a technique of embedding a high-density wiring structure formed with a plurality of wirings connecting adjacent semiconductor elements into an interposer substrate. According to this technique, a plurality of wirings connecting adjacent semiconductor elements can be arranged at high density.

[0004] Japanese Unexamined Patent Publication No. 2016-096196

[0005] The interposer substrate according to the present disclosure connects a plurality of semiconductor elements and a wiring substrate. The interposer substrate includes an organic resin substrate, a plurality of first wirings, and a plurality of second wirings. The plurality of first wirings are located inside the substrate and electrically connect the plurality of semiconductor elements and the wiring substrate. The plurality of second wirings are located inside the substrate and electrically connect the semiconductor elements to each other. The plurality of second wirings are arranged at intervals in a first direction orthogonal to the arrangement direction of the plurality of semiconductor elements in a plan view. Each second wiring has a diffusion suppression layer on a side surface. An interposer substrate.

[0006] Figure 1 is a schematic cross-sectional view showing a state where the semiconductor device according to the embodiment is mounted on a motherboard. Figure 2 is a schematic cross-sectional view showing the configuration of the interposer substrate and the semiconductor element according to the embodiment. Figure 3 is a schematic enlarged view of a region V1 shown in Figure 2. Figure 4 is a schematic perspective plan view showing a plurality of second wirings in the interposer substrate according to the embodiment. Figure 5 is a schematic enlarged view of a region V2 shown in Figure 2. Figure 6A is a schematic cross-sectional view showing another example of the interposer substrate and the wiring substrate according to the embodiment. Figure 6B is a schematic plan view showing another example of the interposer substrate according to the embodiment.

[0007] The embodiments for implementing the relay substrate, composite wiring substrate, and semiconductor device according to this disclosure (hereinafter referred to as "embodiments") will be described in detail below with reference to the drawings. However, this disclosure is not limited by these embodiments. Furthermore, each embodiment can be combined as appropriate, provided that the processing content is not inconsistent. Also, the same parts are denoted by the same reference numerals in each of the following embodiments, and redundant descriptions are omitted.

[0008] Furthermore, in the embodiments described below, expressions such as "constant," "orthogonal," "perpendicular," or "parallel" may be used, but these expressions do not require strict adherence to "constant," "orthogonal," "perpendicular," or "parallel" conditions. In other words, each of the above expressions allows for deviations such as manufacturing accuracy or installation accuracy.

[0009] Furthermore, in the drawings referenced below, for the sake of clarity, mutually orthogonal X-axis, Y-axis, and Z-axis directions are sometimes defined, and a Cartesian coordinate system is shown with the positive Z-axis direction as the vertically upward direction.

[0010] The technology of embedding wiring structures into organic resin relay substrates had room for further improvement from the perspective of cost reduction and labor reduction.

[0011] This disclosure provides a technology that enables easy and high-density connection of multiple wirings between adjacent semiconductor elements.

[0012] (Embodiment) First, the configuration of the semiconductor device 100 according to the embodiment will be described with reference to Figure 1. Figure 1 is a schematic cross-sectional view showing the semiconductor device 100 according to the embodiment mounted on a motherboard 6.

[0013] As shown in Figure 1, the semiconductor device 100 has a composite wiring substrate 1 and a plurality of semiconductor elements 2.

[0014] The composite wiring board 1 includes a wiring board 3 and a relay board 4.

[0015] The wiring board 3 is mounted on the motherboard 6. The wiring board 3 is electrically connected to the relay board 4 via a bonding material 9. Details of the wiring board 3 will be described later.

[0016] The relay board 4 is a so-called interposer, connecting the wiring board 3 and the multiple semiconductor elements 2. The relay board 4 is electrically connected to the semiconductor elements 2 via a bonding material 5, and is also electrically connected to the wiring board 3 via a bonding material 9. The bonding materials 5 and 9 are, for example, solder. The Young's modulus of the relay board 4 may be smaller than that of the wiring board 3. In this case, the relay board 4 may have the flexibility to deform according to the shape of the surface of the wiring board 3. Details of the relay board 4 will be described later.

[0017] Multiple semiconductor elements 2 are mounted on a relay substrate 4. The semiconductor elements 2 are, for example, chips or chiplets in which circuits and elements are formed on a substrate made of a material other than semiconductors, such as a semiconductor chip or a glass substrate. A chiplet is a functional block that constitutes part of the integrated circuit of the semiconductor device 100.

[0018] Although Figure 1 shows two semiconductor elements 2, the semiconductor device 100 may include three or more semiconductor elements 2. Alternatively, the semiconductor device 100 may include only one semiconductor element 2. For example, if the semiconductor element 2 is a chiplet, an integrated circuit with a single function may be formed by multiple semiconductor elements 2.

[0019] Next, the configuration of the wiring board 3 according to this embodiment will be described with reference to Figure 1.

[0020] The wiring board 3 has an inorganic substrate 10 and an organic substrate 20. The wiring board 3 is a laminate of the inorganic substrate 10 and the organic substrate 20.

[0021] <Inorganic Substrate> The inorganic substrate 10 is a ceramic substrate. The inorganic substrate 10 may be formed using a ceramic composite material containing a glass component, so-called glass ceramic. Glass ceramic can be any of the following: a composite of a glass phase and ceramic particles, a composite of a glass phase and a crystalline phase formed by the crystallization of a part of the glass phase, a form in which ceramic particles exist within the glass phase, or a form in which the glass phase exists at the grain boundaries between ceramic particles. An inorganic substrate 10 formed using ceramic in this way has higher rigidity compared to a glass core material.

[0022] For example, the inorganic substrate 10 may be LTCC (Low Temperature Co-fired Ceramics). When LTCC is used as the inorganic substrate 10, it is possible to use low-melting-point metals such as copper or silver, which have relatively low electrical resistance, as wiring. In this embodiment, a low-melting-point metal is a metal with a lower melting point than common metals used for wiring on ceramic substrates, such as tungsten or molybdenum.

[0023] The inorganic substrate 10 may contain ceramic fillers as ceramic particles. Examples of ceramic fillers include alumina (aluminum oxide), calcium titanate, or magnesium titanate. In particular, the inorganic substrate 10 containing alumina has high rigidity.

[0024] The inorganic substrate 10 has a first main surface 101 and a second main surface 102 located on the opposite side of the first main surface 101. The inorganic substrate 10 may also be a plate-like body with the first main surface 101 and the second main surface 102 as its main surfaces.

[0025] In this embodiment, the inorganic substrate 10 has a plurality of ceramic layers 11. The plurality of ceramic layers 11 are laminated along the thickness direction of the inorganic substrate 10. A wiring board 3 having such an inorganic substrate 10 offers a high degree of design freedom. Furthermore, by constructing the inorganic substrate 10 using a plurality of ceramic layers 11, the inorganic substrate 10 can be manufactured while checking whether the wiring inside the ceramic layer 11 is properly formed for each layer, thereby improving the yield of the inorganic substrate 10.

[0026] In the example shown in Figure 1, the inorganic substrate 10 has four ceramic layers 11, but the number of ceramic layers 11 is not limited to four. The number of ceramic layers 11 may be two, three, or five or more.

[0027] <Organic Substrate> The organic substrate 20 is a substrate made of organic resin. The organic resin may be, for example, epoxy resin, acrylic resin, polycarbonate resin, polyimide resin, olefin resin, or polyphenylene resin.

[0028] Furthermore, the organic resin may be, for example, polytetrafluoroethylene (PTFE) or other fluororesins or polyphenylene ether resins. The organic substrate 20 may also contain components other than the organic resin. In this disclosure, the organic resin may be, for example, a material that accounts for 30% by mass or more of the materials constituting the organic substrate 20.

[0029] The organic substrate 20 has a third main surface 103 and a fourth main surface 104 located on the opposite side of the third main surface 103. The organic substrate 20 may also be a plate-like body with the third main surface 103 and the fourth main surface 104 as its main surfaces.

[0030] The organic substrate 20 has two organic substrates 20. One of the two organic substrates 20 is bonded to the first main surface 101 of the inorganic substrate 10, and the other is bonded to the second main surface 102 of the inorganic substrate 10.

[0031] The organic substrate 20 located on the first main surface 101 of the inorganic substrate 10 has its third main surface 103 bonded to the first main surface 101 of the inorganic substrate 10, and a plurality of semiconductor elements 2 are placed on the fourth main surface 104 of the organic substrate 20 via a relay substrate 4 (see Figure 1).

[0032] The organic substrate 20 located on the second main surface 102 of the inorganic substrate 10 has its third main surface 103 joined to the second main surface 102 of the inorganic substrate 10, and the fourth main surface 104 of the organic substrate 20 is joined to the motherboard 6 via the joint 7.

[0033] The organic substrate 20 has a plurality of organic resin layers 21. The plurality of organic resin layers 21 are laminated along the thickness direction of the organic substrate 20. A wiring board 3 having such an organic substrate 20 offers a high degree of design freedom. In the example shown in Figure 1, the organic substrate 20 has five or seven organic resin layers 21, but the number of organic resin layers 21 is not limited to five or seven. The number of organic resin layers 21 may be two, three, four, or six, or eight or more.

[0034] The example shown in Figure 1 illustrates a case where the wiring board 3 has an organic substrate 20 on each of the first main surface 101 and the second main surface 102 of the inorganic substrate 10. However, the wiring board 3 is not limited to this example; it is sufficient that the organic substrate 20 is present on at least the first main surface 101 of the inorganic substrate 10.

[0035] The organic substrate 20, which contains organic components, is more likely to form fine wiring patterns compared to the inorganic substrate 10. On the other hand, the ceramic inorganic substrate 10 has higher rigidity and lower density than the organic substrate 20.

[0036] The wiring board 3 according to this embodiment can achieve miniaturization and narrow pitch of wiring while increasing rigidity by combining the inorganic substrate 10 and the organic substrate 20. As the size of the substrate increases, the warping of the substrate becomes more apparent, so the configuration of the wiring board 3 in which the low rigidity of the organic substrate 20 is compensated for by the inorganic substrate 10 is particularly useful when increasing the size of the substrate.

[0037] The inorganic substrate 10 and the organic substrate 20 are joined, for example, by hydrogen bonding. Specifically, the inorganic substrate 10 and the organic substrate 20 are joined by the bonding of hydroxyl groups of the inorganic substrate 10 and the organic substrate 20. In this case, the inorganic substrate 10 may be a ceramic material such as alumina having surface hydroxyl groups, and the organic substrate 20 may be an epoxy resin, which is a resin material containing hydroxyl groups. By directly joining the inorganic substrate 10 and the organic substrate 20 in this way without the need for solder or underfill, the thickness of the wiring board 3 can be reduced and the manufacturing process can be simplified.

[0038] Furthermore, the inorganic substrate 10 may contain a glass component, and the organic substrate 20 may contain a coupling agent that chemically bonds with the glass component. For example, a silane coupling agent can be used as the coupling agent. Alternatively, a titanium-based coupling agent or an aluminum-based coupling agent can be used. With this configuration, the inorganic substrate 10 and the organic substrate 20 are chemically bonded together, thereby creating a stronger bond between the two dissimilar materials.

[0039] Next, the configuration of the relay substrate 4 according to the embodiment will be described with reference to Figures 2 to 4. Figure 2 is a schematic cross-sectional view showing the configuration of the relay substrate 4 and semiconductor element 2 according to the embodiment. Figure 3 is a schematic enlarged view of the region V1 shown in Figure 2. Figure 4 is a schematic planar perspective view showing a plurality of second wirings 80 in the relay substrate 4 according to the embodiment. Note that the conductor 74 is omitted from Figures 2 and 3. Also, in Figure 4, the semiconductor element 2 mounted on the relay substrate 4 is shown by a dashed line.

[0040] The relay board 4 has a board 60, a plurality of first wirings 70, and a plurality of second wirings 80.

[0041] <Substrate> The substrate 60 is a substrate made of organic resin. The organic resin may be, for example, epoxy resin, acrylic resin, polycarbonate resin, polyimide resin, olefin resin, or polyphenylene resin.

[0042] Furthermore, the organic resin may be, for example, polytetrafluoroethylene (PTFE), another fluororesin, or a polyphenylene ether resin. The substrate 60 may contain components other than the organic resin. In the present disclosure, the organic resin may be a material that accounts for 30% by mass or more of the material constituting the substrate 60, for example.

[0043] The substrate 60 has a fifth main surface 601 and a sixth main surface 602 located on the opposite side to the fifth main surface 601. The substrate 60 may be a plate-shaped body having the fifth main surface 601 and the sixth main surface 602 as its main surfaces.

[0044] The fifth main surface 601 of the substrate 60 is bonded to the fourth main surface 104 (see FIG. 1) of the inorganic base material 10 via the bonding material 9, and the plurality of semiconductor elements 2 are mounted on the sixth main surface 602 of the substrate 60 via the bonding material 5. The sixth main surface 602 is a surface facing the semiconductor element 2.

[0045] The substrate 60 includes a plurality of organic resin layers 61. The plurality of organic resin layers 61 are laminated along the thickness direction of the substrate 60. The relay substrate 4 including such a substrate 60 has a high degree of design freedom. In the example shown in FIG. 2, the substrate 60 includes five organic resin layers 61, but the number of organic resin layers 61 is not limited to five. The number of organic resin layers 61 may be two, three, four, or six or more.

[0046] <First Wiring> The plurality of first wirings 70 are located inside the substrate 60, and electrically connect the plurality of semiconductor elements 2 and the wiring substrate 3 (see FIG. 1). The plurality of first wirings 70 include a plurality of via conductors 71, a plurality of lands 72, and a wiring layer 73.

[0047] The via conductor 71 penetrates one or more organic resin layers 61. The land 72 is located between adjacent organic resin layers 61, and electrically connects the plurality of via conductors 71 to each other. The land 72 is formed integrally with the via conductor 71 located in the same organic resin layer 61. The wiring layer 73 is located on the sixth main surface 602 of the substrate 60, and is electrically connected to the via conductor 71. Details of the first wiring 70 will be described later.

[0048] <Second Wiring> The plurality of second wirings 80 are located inside the substrate 60 and electrically connect the semiconductor elements 2 to each other. As shown in FIG. 3, the plurality of second wirings 80 may be located in the organic resin layer 61 having the sixth main surface 602 among the plurality of organic resin layers 61. As shown in FIG. 4, the plurality of second wirings 80 are arranged at intervals in a first direction (here, the Y-axis direction) orthogonal to the arrangement direction of the plurality of semiconductor elements 2 in a plan view of the interposer 4.

[0049] Each second wiring 80 includes a plurality of (here, two) wiring layers 81 and a bridge 82. Each wiring layer 81 is located on the sixth main surface 602 of the substrate 60, and is electrically connected to each semiconductor element 2 via the bonding material 5. The bridge 82 electrically connects the wiring layers 81 to each other.

[0050] The first wiring 70 and the second wiring 80 may be, for example, metal conductors containing copper or silver as a main component. For example, both the first wiring 70 and the second wiring 80 may be metal conductors containing copper as a main component. Alternatively, both the first wiring 70 and the second wiring 80 may be metal conductors containing silver as a main component. Further, one of the first wiring 70 and the second wiring 80 may be a metal conductor containing copper as a main component, and the other may be a metal conductor containing silver as a main component.

[0051] By forming all of the first wirings 70 and the second wirings 80 from metal conductors containing copper or silver as a main component, higher electrical characteristics can be obtained compared to, for example, a case where one of the first wirings 70 and the second wirings 80 is a metal conductor other than copper and silver. The first wiring 70 and the second wiring 80 may be formed by a copper plating process.

[0052] The first wiring 70 may be electrically and thermally connected to the semiconductor element 2 via the bonding material 5. Since the first wiring 70 containing copper or silver as a main component, which has relatively high thermal conductivity, is thermally connected to the semiconductor element 2 serving as a heat source, heat generated from the semiconductor element 2 can be efficiently dissipated via the first wiring 70.

[0053] Here, the relay substrate 4 according to the embodiment has a diffusion suppression layer 85 on the side surface of the second wiring 80. The side surface of the second wiring 80 is the surface that connects the surface of the second wiring 80 facing the semiconductor element 2 and the surface located on the opposite side of this facing surface. Specifically, as shown in Figure 3, the relay substrate 4 has a diffusion suppression layer 85 on the side surface of the bridge 82. The diffusion suppression layer 85 reduces the diffusion of metal components contained in the second wiring 80 into the organic resin layer 61. In other words, the relay substrate 4 according to the embodiment can reduce the diffusion of metal components contained in the second wiring 80 into the organic resin layer 61, which would cause adjacent second wirings 80 to become electrically connected to each other through the metal components diffused into the organic resin layer 61, thanks to the diffusion suppression layer 85. In other words, the relay substrate 4 according to the embodiment achieves high density (narrow pitch) of multiple second wirings 80 while maintaining high insulation reliability.

[0054] As a result, the relay substrate 4 according to the embodiment can reduce the number of man-hours compared to the technology of connecting adjacent semiconductor elements by embedding a wiring structure with multiple wirings formed on it into the relay substrate, and can also achieve a high density of multiple second wirings 80 connecting adjacent semiconductor elements 2 at low cost. Therefore, the density of multiple second wirings 80 connecting adjacent semiconductor elements 2 can be easily increased.

[0055] The diffusion-inhibiting layer 85 may contain any of Cr, Ti, Ni, or compounds combining two or more of these. With this configuration, the diffusion of metal components contained in the second wiring 80 into the organic resin layer 61 can be further reduced.

[0056] As shown in Figure 3, the diffusion suppression layer 85 may also be located on the surface of the second wiring 80 facing the semiconductor element 2. Specifically, the diffusion suppression layer 85 may also be located on the surface of the wiring layer 81 facing the semiconductor element 2 and on the surface of the bridge 82 facing the semiconductor element 2. This further reduces the possibility of adjacent second wirings 80 becoming electrically connected to each other via metal components diffused into the organic resin layer 61.

[0057] As shown in Figure 3, the via conductor 71 included in the first wiring 70 may have a diffusion suppression layer 75 (see Figure 5) on its side surface, and the side surface itself may have a shape that is inclined with respect to the thickness direction of the substrate 60. Specifically, the via conductor 71 can have a tapered shape such that its diameter increases from the upper surface on which the semiconductor element 2 is mounted towards the lower surface connected to the wiring substrate 3.

[0058] As shown in Figure 3, the land 72 may be covered with a diffusion-suppressing layer 75 (see Figure 5) on its upper and side surfaces that are in contact with the organic resin layer 61, thereby preventing metal diffusion and improving insulation from adjacent wiring. The upper surface referred to here is the surface facing the semiconductor element 2.

[0059] As shown in Figure 3, in the second wiring 80 connecting semiconductor elements 2, the bridge 82 connecting the wiring layers 81 may have a diffusion suppression layer 85 not only on the side but also on the upper surface facing the semiconductor elements 2. By providing a diffusion suppression layer 85 on both the side and the upper surface, the diffusion path of metal components can be suppressed, improving insulation reliability. This makes it possible to increase the density of the wiring.

[0060] As shown in Figure 4, the spacing between two adjacent second wirings 80 in the first direction (here, the Y-axis direction) may be narrower at the second position, which is further from the two semiconductor elements 2 than at the first position, than at the first position, which is closer to either of the two semiconductor elements 2, which is narrower at the second position, which is further from the two semiconductor elements 2 than at the first position, which is narrower first position, which is closer to the two semiconductor elements 2, which is narrower at the second position, which is further from the two semiconductor elements 2 than at the first position, which is closer to the first position, which is narrower at the first position, which is closer to either of the two semiconductor elements 2, which is narrower at the second position, which

[0061] The first position may be, for example, a position within one of three regions obtained by dividing the region between two adjacent second wirings 80 in a first direction (here, the Y-axis direction) into three equal parts in the direction in which the semiconductor elements 2 are aligned (here, the X-axis direction). In this case, the second position may be a position within the central region of these three regions.

[0062] The first position may be, for example, a position within the region between two adjacent wiring layers 73 in a first direction (here, the Y-axis direction). In this case, the second position may be, for example, a position within the region between two adjacent bridges 82 in a first direction (here, the Y-axis direction).

[0063] As described above, the relay substrate 4 according to the embodiment has a diffusion suppression layer 85 on the side surface of the second wiring 80. Therefore, even at the second position where the spacing S2 is narrow, the diffusion suppression layer 85 can reduce the possibility of adjacent second wirings 80 becoming electrically connected to each other via metal components diffused into the organic resin layer 61. In other words, the relay substrate 4 according to the embodiment achieves high density (narrow pitch) of multiple second wirings 80 at the second position while maintaining high insulation reliability.

[0064] Next, the configuration of the first wiring 70 according to the embodiment will be further explained with reference to Figure 5. Figure 5 is a schematic enlarged view of the region V2 shown in Figure 2.

[0065] The via conductors 71 of the first wiring 70 may have a diffusion suppression layer 75 on their side surfaces and on the surface facing the semiconductor element 2. Similarly, the lands 72 may have a diffusion suppression layer 75 on their side surfaces and on the surface facing the semiconductor element 2. The diffusion suppression layer 75 suppresses the diffusion of metal components contained in the first wiring 70 into the organic resin layer 61, thereby reducing the possibility of adjacent first wirings 70 becoming electrically connected to each other via metal components diffused into the organic resin layer 61. In other words, it provides high insulation reliability.

[0066] The diffusion-inhibiting layer 75 may contain any of Cr, Ti, Ni, or compounds combining two or more of these. With this configuration, the diffusion of metal components contained in the first wiring 70 into the organic resin layer 61 can be further reduced.

[0067] The wiring layer 73 of the first wiring 70 may have a diffusion suppression layer 75 only on the surface facing the semiconductor element 2. In other words, the wiring layer 73 does not need to have a diffusion suppression layer 75 on its side surface. This makes it possible to form the first wiring 70 at a lower cost compared to the case where the relatively large diameter wiring layer 81 has a diffusion suppression layer 75 on its side surface.

[0068] As shown in Figure 5, among the multiple organic resin layers 61, the organic resin layer 61A having the sixth main surface 602 may have both a via conductor 71 and a wiring layer 73. In this case, as described above, the via conductor 71 has a diffusion suppression layer 75 on its side surface, and the wiring layer 73 also has a diffusion suppression layer 75 on its side surface, so that the first wiring 70 can be formed at low cost while ensuring insulation reliability.

[0069] As shown in Figure 5, the first wiring 70 may further have a conductor 74 that protrudes from the wiring layer 73 in a direction toward the semiconductor element 2 (in this case, the positive Z-axis direction). The conductor 74 is electrically connected to the wiring layer 73.

[0070] This makes it easier to mount the semiconductor element 2 parallel to the substrate 60 compared to when the conductor 74 is not present. Therefore, the relay substrate 4 according to this embodiment has excellent structural stability when mounting the semiconductor element 2.

[0071] As shown in Figure 5, the wiring layer 73 has a first surface 73a facing the semiconductor element 2, a second surface 73b located opposite the first surface 73a, and a side surface 73c connecting the first surface 73a and the second surface 73b. In this case, the second surface 73b and the side surface 73c may be embedded in the organic resin layer 61. The first surface 73a may be flush with the sixth main surface 602 of the substrate 60.

[0072] This reduces variations in the height of the conductor 74 formed on the wiring layer 73. Therefore, the relay substrate 4 according to this embodiment has superior structural stability.

[0073] As shown in Figure 5, the diameter of the conductor 74 may be smaller than the diameter of the wiring layer 73. Here, diameter refers, for example, to the maximum length of the line segment connecting two points on the contour of the member in a plan view.

[0074] As shown in Figure 5, the relay substrate 4 may have a plating layer 90 covering the conductor 74. In this case, the plating layer 90 may cover at least a portion of the wiring layer 73 in addition to the conductor 74. Specifically, the plating layer 90 may cover a region of the first surface 73a of the wiring layer 73 that does not overlap with the conductor 74 in a plan view.

[0075] In this way, since the plating layer 90 covers the conductor 74 and at least a part of the wiring layer 73, direct contact between the wiring layer 73 and the conductor 74 is reduced, thereby reducing the occurrence of phenomena such as the metal constituting the wiring layer 73 dissolving into the bonding material 5.

[0076] The plating layer 90 may have an adhesion layer, a diffusion prevention layer, and a solder wetting layer (not shown). The adhesion layer, diffusion prevention layer, and solder wetting layer may be laminated in the order of adhesion layer, diffusion prevention layer, and solder wetting layer from the side closest to the conductor 74. The adhesion layer may contain, for example, nickel. The diffusion prevention layer may contain, for example, palladium or platinum. The solder wetting layer may contain, for example, copper plating.

[0077] Figure 6A is a schematic cross-sectional view showing another example of the relay board 4 and wiring board 3 according to the embodiment. Figure 6B is a schematic plan view showing another example of the relay board 4 according to the embodiment.

[0078] As shown in Figure 6A, the relay board 4 according to this embodiment may have a first wiring 70B without a conductor 74. Such first wiring 70B may be electrically connected to the outside via plated lead wires 110 located inside the wiring board 3.

[0079] As shown in Figure 6B, the first wiring 70A with the conductor 74 and the first wiring 70B without the conductor 74 may be arranged in a staggered pattern in a plan view.

[0080] Thus, because the relay board 4 has first wiring 70B without conductors 74, heat from the semiconductor element 2 can be dissipated to the wiring board 3 via the first wiring 70B. As a result, the relay board 4 has excellent heat dissipation properties. Furthermore, compared to the case where all first wirings 70 have conductors 74, the number of conductors 74 can be reduced, making it less likely for variations in the height of multiple conductors 74 to occur. As a result, the relay board 4 has excellent structural stability.

[0081] Furthermore, by arranging the first wiring 70B in an area where the spacing between adjacent first wirings 70A is relatively wide, the ratio of metal to substrate 60 can be made uniform throughout the substrate 60. As a result, the current density can be made uniform throughout the substrate 60.

[0082] Furthermore, this technology can also take the following configurations: (1) A relay substrate for connecting a plurality of semiconductor elements and a wiring substrate, comprising: a substrate made of organic resin; a plurality of first wirings located inside the substrate that electrically connect the plurality of semiconductor elements and the wiring substrate; and a plurality of second wirings located inside the substrate that electrically connect the semiconductor elements to each other, wherein the plurality of second wirings are arranged at intervals in a first direction perpendicular to the direction in which the plurality of semiconductor elements are arranged in a plan view, and each of the second wirings has a diffusion suppression layer on its side surface. (2) The relay substrate according to (1), wherein the spacing between two adjacent second wirings in the first direction is narrower at a second position further from the two semiconductor elements than at a first position closer to either of the two semiconductor elements. (3) The relay substrate according to (1) or (2), wherein the diffusion suppression layer contains any of Cr, Ti, Ni, and compounds combining two or more of these. (4) The substrate has a plurality of organic resin layers, the first wiring has a via conductor penetrating the organic resin layer and a wiring layer located on the surface of the substrate facing the semiconductor element and electrically connected to the via conductor, the via conductor and the wiring layer are located on the organic resin layer having the facing surface among the plurality of organic resin layers, the via conductor has a diffusion suppression layer on its side surface and the wiring layer does not have a diffusion suppression layer on its side surface, the relay substrate according to any one of (1) to (3). (5) The first wiring has a wiring layer located on the surface of the substrate facing the semiconductor element and a conductor electrically connected to the wiring layer and protruding from the wiring layer in a direction toward the semiconductor element, the relay substrate according to any one of (1) to (4). (6) The relay substrate according to (5), wherein the wiring layer has a first surface facing the semiconductor element, a second surface located opposite the first surface, and a side surface connecting the first surface and the second surface, the second surface and the side surface are embedded in the substrate, and the first surface is flush with the opposing surface. (7) The relay substrate according to (5) or (6), wherein the diameter of the conductor is smaller than the diameter of the wiring layer.(8) A relay substrate according to any one of (5) to (7), having a plating layer covering the conductor, wherein the plating layer covers at least a portion of the wiring layer. (9) A composite wiring substrate having a relay substrate according to any one of (1) to (8) and a wiring substrate electrically connected to the relay substrate via a bonding material. (10) A composite wiring substrate according to (9), wherein the wiring substrate has an inorganic substrate made of ceramic and an organic substrate made of organic resin bonded to the inorganic substrate. (11) A semiconductor device comprising a composite wiring substrate according to (9) or (10) and a plurality of semiconductor elements mounted on the relay substrate.

[0083] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. Indeed, the embodiments described above can be embodied in a variety of forms. Furthermore, the embodiments described above may be omitted, replaced, or modified in various ways without departing from the scope and spirit of the appended claims.

[0084] 1 Composite wiring board 2 Semiconductor element 3 Wiring board 4 Intermediate board 5,9 Bonding material 6 Motherboard 7 Bonding part 10 Inorganic substrate 11 Ceramic layer 20 Organic substrate 60 Substrate 70 First wiring 71 Via conductor 73 Wiring layer 73a First surface 73b Second surface 73c Side surface 74 Conductor 75,85 Diffusion suppression layer 80 Second wiring 90 Plating layer 100 Semiconductor device 602 Sixth main surface S1, S2 Spacing

Claims

1. A relay substrate for connecting a plurality of semiconductor elements and a wiring board, comprising: a substrate made of organic resin; a plurality of first wirings located inside the substrate that electrically connect the plurality of semiconductor elements and the wiring board; and a plurality of second wirings located inside the substrate that electrically connect the semiconductor elements to each other, wherein the plurality of second wirings are arranged at intervals in a first direction perpendicular to the direction in which the plurality of semiconductor elements are arranged in a plan view, and each of the second wirings has a diffusion suppression layer on its side surface.

2. The relay substrate according to claim 1, wherein the spacing between two adjacent second wirings in the first direction is narrower at a second position further from the two semiconductor elements than at a first position closer to either of the two semiconductor elements than at the first position.

3. The relay substrate according to claim 1 or 2, wherein the diffusion suppression layer contains any of Cr, Ti, Ni, or a compound obtained by combining two or more of these.

4. The relay substrate according to any one of claims 1 to 3, wherein the substrate has a plurality of organic resin layers, the first wiring has a via conductor penetrating the organic resin layer, and a wiring layer located on the surface of the substrate facing the semiconductor element and electrically connected to the via conductor, the via conductor and the wiring layer are located on the organic resin layer having the facing surface among the plurality of organic resin layers, the via conductor has a diffusion suppression layer on its side surface, and the wiring layer does not have a diffusion suppression layer on its side surface.

5. The relay substrate according to any one of claims 1 to 4, wherein the first wiring comprises a wiring layer located on the surface of the substrate facing the semiconductor element, and a conductor electrically connected to the wiring layer and protruding in a direction toward the semiconductor element from the wiring layer.

6. The relay substrate according to claim 5, wherein the wiring layer has a first surface facing the semiconductor element, a second surface located opposite the first surface, and a side surface connecting the first surface and the second surface, the second surface and the side surface are embedded in the substrate, and the first surface is flush with the opposing surface.

7. The relay substrate according to claim 5 or 6, wherein the diameter of the conductor is smaller than the diameter of the wiring layer.

8. A relay substrate according to any one of claims 5 to 7, having a plating layer covering the conductor, wherein the plating layer covers at least a portion of the wiring layer.

9. A composite wiring board having a relay board according to any one of claims 1 to 8, and a wiring board electrically connected to the relay board via a bonding material.

10. The composite wiring board according to claim 9, wherein the wiring board comprises a ceramic inorganic substrate and an organic resin organic substrate bonded to the inorganic substrate.

11. A semiconductor device comprising a composite wiring board according to claim 9 or 10, and a plurality of semiconductor elements mounted on the relay board.

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