Diamond and nitride-based semiconductor integrated device including metal buffer layer and manufacturing method therefor

Abstract

The present invention relates to a diamond and nitride-based semiconductor integrated device including a metal buffer layer and a manufacturing method therefor, and more specifically, provides a semiconductor integrated device which has improved heat dissipation performance and charge mobility by forming a nitride semiconductor device and a diamond semiconductor device on one substrate layer. The present invention relates to a diamond and nitride-based semiconductor integrated device including a metal buffer layer and a manufacturing method therefor, the method being a method for manufacturing a high-voltage and high-frequency semiconductor device using wide band gap characteristics of diamond and nitrides, by which device deterioration is prevented due to the excellent heat dissipation characteristics of diamond and a highly reliable semiconductor device can be manufactured.

Description

Diamond and nitride-based semiconductor integrated device including a metal buffer layer and manufacturing method

[0001] The present invention relates to a diamond and nitride-based semiconductor integrated device comprising a metal buffer layer and a method for manufacturing thereof, and more specifically, to a semiconductor integrated device having improved heat dissipation performance and charge mobility by forming a nitride semiconductor device and a diamond semiconductor device on a single substrate layer.

[0002]

[0003] CMOS (complementary metal-oxide semiconductor) is a semiconductor device manufactured such that P-channel FETs and N-channel FETs are placed adjacently on a single chip, with the gates of the P-channel FETs and N-channel FETs connected to the inputs and the drains connected to the outputs, allowing the two FETs to operate complementarily. CMOS has the advantage of low power consumption and is used as a switching device in most logic circuits.

[0004] Conventional CMOS devices were mostly based on silicon (Si), but as device miniaturization progressed, problems such as increased power consumption and heat generation occurred. In addition, due to the characteristics of silicon, conventional silicon-based CMOS devices have the problem of being difficult to utilize for high-speed switching, ultra-high voltage, and ultra-high frequency devices.

[0005] However, the electric vehicle, 5G, and aerospace sectors, where the market is currently expanding rapidly, require semiconductor devices capable of operating in high-voltage, high-temperature, and high-frequency environments with improved switching characteristics. Accordingly, there is a demand for new semiconductor devices to replace silicon-based devices.

[0006] In other words, there is a demand for semiconductor devices and manufacturing technologies that possess excellent withstand voltage characteristics, enable high-speed switching, prevent device degradation due to high temperatures, and operate in extreme environments such as space.

[0007]

[0008] The present invention aims to provide a diamond and nitride-based semiconductor integrated device including a metal buffer layer and a method for manufacturing such a device, wherein a diamond semiconductor device composed of single-crystal diamond is formed by depositing a metal buffer layer on a substrate layer on which a nitride semiconductor device is formed, thereby providing a semiconductor integrated device with improved heat dissipation performance and charge mobility.

[0009]

[0010] To solve the above problems, one embodiment of the present invention provides a semiconductor integrated device comprising: a substrate layer; a nitride semiconductor device formed on the substrate layer; and a diamond semiconductor device; wherein the nitride semiconductor device comprises: a buffer layer disposed on the substrate layer; a channel layer disposed on the buffer layer; a barrier layer disposed on the channel layer; a capping layer disposed on the barrier layer; and a first electrode disposed on the capping layer; and wherein the diamond semiconductor device comprises: a metal buffer layer disposed on the substrate layer; a diamond layer disposed on the metal buffer layer; and a second electrode disposed on the diamond layer; and wherein the semiconductor integrated device electrically connects the first electrode and the second electrode to form an integrated circuit.

[0011] In some embodiments of the present invention, the substrate layer may comprise any one of Si, Al2O3, SiC, GaN, AlN, and Ga2O3.

[0012] In some embodiments of the present invention, the nitride semiconductor device is gallium nitride (GaN), aluminum nitride (AlN), and aluminum gallium nitride (Al x Ga 1-x Includes 1 or more of N), and Al x Ga 1-x The x value of the above aluminum gallium nitride, represented by the chemical formula of N, can be from 0.1 to 99.9.

[0013] In some embodiments of the present invention, the nitride semiconductor device is the aluminum gallium (Al nitride) x Ga 1-x In the case of including N), aluminum gallium nitride (Al) included in each of the two layers disposed adjacent to each other among the channel layer, barrier layer, and capping layer. x Ga 1-x N) has different x values, and the aluminum gallium nitride (Al) included in the channel layer x Ga 1-x The x value of N) is the aluminum gallium nitride (Al) included in the barrier layer. x Ga 1-x It can be smaller than the x value of N).

[0014] In some embodiments of the present invention, the substrate layer is any one of Al2O3, Si, SiC, and Nitride-based substrates, and the nitride semiconductor device can be formed at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 400 to 1500°C.

[0015] In some embodiments of the present invention, the metal buffer layer may include one or more of iridium (Ir), ruthenium (Ru), Al2O3, YSZ, and SrTiO3.

[0016] In some embodiments of the present invention, the diamond semiconductor device is formed by chemical vapor deposition (CVD), the substrate layer comprises one or more of Al2O3, MgO, Si, SiC, and nitride-based substrates, and the diamond layer can be formed at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 100 to 1500°C.

[0017] In some embodiments of the present invention, the diamond semiconductor device further comprises an oxide film layer disposed on the diamond layer, and the second electrode may be disposed on the oxide film layer.

[0018] In some embodiments of the present invention, the first electrode comprises a first source, a first gate formed spaced apart from the first source, and a first drain formed spaced apart from the first source and the first gate, and the nitride semiconductor device may further comprise a p-aluminum gallium nitride layer formed between the first gate and the capping layer.

[0019] In some embodiments of the present invention, the second electrode comprises a second source, a second gate formed spaced apart from the second source, and a second drain formed spaced apart from the second source and the second gate, and the diamond semiconductor device may further comprise an n-diamond layer formed on the diamond layer; a p-diamond layer formed between the n-diamond layer and the second source, and between the n-diamond layer and the second drain, respectively; and an oxide layer formed between the n-diamond layer and the second gate.

[0020] To solve the above problems, one embodiment of the present invention comprises a method for manufacturing a semiconductor integrated device, the method comprising: a substrate layer preparation step of preparing a substrate layer; a nitride semiconductor device formation step of forming a nitride semiconductor device on the substrate layer; and a diamond semiconductor device formation step of forming a diamond semiconductor device on the substrate layer; wherein the nitride semiconductor device formation step comprises: a buffer layer placement step of placing a buffer layer on the substrate layer; a channel layer placement step of placing a channel layer on the buffer layer; a barrier layer placement step of placing a barrier layer on the channel layer; a capping layer placement step of placing a capping layer on the barrier layer; and a first electrode placement step of placing a first electrode on the capping layer; and wherein the diamond semiconductor device formation step comprises: a metal buffer layer placement step of placing a metal buffer layer on the substrate layer; and a diamond layer placement step of placing a diamond layer on the metal buffer layer. The present invention provides a method for manufacturing a semiconductor integrated device, comprising: a second electrode placement step of placing a second electrode on the diamond layer; wherein the semiconductor integrated device forms an integrated circuit by electrically connecting the first electrode and the second electrode.

[0021]

[0022] According to one embodiment of the present invention, a semiconductor integrated device can improve the withstand voltage characteristics and switching characteristics of the semiconductor integrated device by including an ultrawide bandgap material, thereby exhibiting the effect of expanding the usability of the device.

[0023] According to one embodiment of the present invention, the semiconductor integrated device includes a single-crystal diamond, thereby improving heat resistance performance. The diamond layer acts as a heat dissipation layer to prevent degradation caused by high temperatures during device operation, thereby extending the lifespan of the semiconductor integrated device and enabling operation in extreme environments such as high temperatures, which can then produce the effect of improving economic efficiency.

[0024] According to one embodiment of the present invention, a nitride semiconductor device has a multilayer structure including a buffer layer, a channel layer, a barrier layer, and a capping layer, and each of the buffer layer, channel layer, barrier layer, and capping layer includes aluminum gallium nitride having different detailed compositions, thereby forming a two-dimensional electric gas inside the channel layer to improve electron mobility of the semiconductor integrated device and reduce switching losses, thereby improving the electrical performance of the semiconductor integrated device.

[0025] According to one embodiment of the present invention, the metal buffer layer can perform the role of a base layer that reduces lattice mismatch between the diamond layer and the substrate layer, thereby preventing the occurrence of defects in the diamond semiconductor device and improving the electrical characteristics of the semiconductor integrated device.

[0026] According to one embodiment of the present invention, a diamond semiconductor device can improve hole mobility by including a channel composed of a two-dimensional hole gas, thereby exhibiting the effect of improving the performance of a semiconductor integrated device.

[0027] According to one embodiment of the present invention, the semiconductor integrated device can expand the application range of the semiconductor integrated device by controlling whether it is in e-mode and d-mode through a stacked structure of a nitride semiconductor device and a diamond semiconductor device.

[0028]

[0029] FIG. 1 illustrates a schematic diagram of a semiconductor integrated circuit according to one embodiment of the present invention.

[0030] FIG. 2 schematically illustrates a method for manufacturing a semiconductor integrated circuit according to one embodiment of the present invention.

[0031] FIG. 3 schematically illustrates a step for forming a nitride semiconductor device according to one embodiment of the present invention.

[0032] FIG. 4 schematically illustrates a diamond semiconductor device formation step according to one embodiment of the present invention.

[0033] FIG. 5 schematically illustrates the structure of a semiconductor integrated device including an oxide film layer according to one embodiment of the present invention.

[0034] FIG. 6 schematically illustrates the process of forming a two-dimensional hole gas according to one embodiment of the present invention.

[0035] FIG. 7 schematically illustrates the process of forming a two-dimensional electron gas according to one embodiment of the present invention.

[0036] FIG. 8 schematically illustrates the structure of a semiconductor integrated device further comprising an oxide film layer and a doped diamond multilayer structure according to one embodiment of the present invention.

[0037] FIG. 9 schematically illustrates the structure of a semiconductor integrated device further comprising a p-aluminum gallium nitride layer and a doped diamond multilayer structure according to one embodiment of the present invention.

[0038] FIG. 10 schematically illustrates the structure of a semiconductor integrated device further comprising a p-aluminum nitride gallium layer (2410) according to one embodiment of the present invention.

[0039]

[0040] Hereinafter, various embodiments and / or aspects are disclosed with reference to the drawings. For illustrative purposes, numerous specific details are disclosed in the following description to aid in a general understanding of one or more aspects. However, it will also be recognized by those skilled in the art that these aspects may be practiced without such specific details. The following description and the accompanying drawings describe specific exemplary aspects of one or more aspects in detail. However, these aspects are exemplary, and some of the various methods in the principles of the various aspects may be used, and the description is intended to include all such aspects and their equivalents.

[0041] In addition, various aspects and features will be presented by a system that may include multiple devices, components and / or modules, etc. It should also be understood and recognized that various systems may include additional devices, components and / or modules, etc., and / or may not include all of the devices, components, modules, etc. discussed in relation to the drawings.

[0042] As used herein, terms such as "examples," "examples," "aspects," "examples," etc., may not be interpreted as implying that any aspect or design described is better or more advantageous than other aspects or designs.

[0043] Additionally, the terms “comprising” and / or “comprising” should be understood to mean that the relevant feature and / or component is present, but not to exclude the presence or addition of one or more other features, components and / or groups thereof.

[0044] Additionally, terms including ordinal numbers, such as first, second, etc., may be used to describe various components, but said components are not limited by said terms. Such terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. The term "and / or" includes a combination of a plurality of related described items or any of a plurality of related described items.

[0045] Furthermore, in the embodiments of the present invention, all terms used herein, including technical or scientific terms, unless otherwise defined, have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in the embodiments of the present invention.

[0046]

[0047] CMOS is a switching device primarily used in logic circuits due to its low power consumption, and conventional CMOS was manufactured based on silicon. However, as device miniaturization progressed, conventional silicon-based CMOS faced issues such as increased power consumption and heat generation, and problems arose regarding its difficulty in being applied as high-speed switching, ultra-high voltage, and ultra-high frequency devices required by the market.

[0048] To solve this, the present invention proposes a diamond and nitride-based semiconductor integrated device (1) comprising a metal buffer layer (3100) in which conventional silicon is replaced with a diamond and nitride material, and a method for manufacturing the same.

[0049] More specifically, the present invention relates to single-crystal diamond and gallium aluminum nitride (Al), which are ultra-wide band-gap (UWBG) materials having a band gap wider than silicon. x Ga 1-xA semiconductor integrated device (1) corresponding to a CMOS structure can be manufactured by forming a diamond semiconductor device (3000) and a nitride semiconductor device (2000) based on N) on a single substrate layer (1000). At this time, a metal buffer layer (3100) can be placed on the substrate layer (1000) to form the diamond semiconductor device (3000) including a single crystal diamond on the substrate layer (1000). The diamond semiconductor device (3000) formed in this way may correspond to a p-channel FET, and the nitride semiconductor device (2000) may correspond to an N-channel FET.

[0050] With this configuration, the semiconductor integrated device (1) can operate even when a higher voltage than conventional silicon-based CMOS is applied, high-speed switching is possible, and heat can be effectively dissipated by the single-crystal diamond, making it easy to operate in a high-temperature environment. Therefore, the semiconductor integrated device (1) can be applied as an ultra-high voltage and ultra-high frequency device, such as a 5G device or a semiconductor device for space applications.

[0051]

[0052] That is, according to one embodiment of the present invention, the semiconductor integrated device (1) includes an ultrawide bandgap material, thereby improving the withstand voltage characteristics and switching characteristics of the semiconductor integrated device (1) and thereby having the effect of expanding the usability of the device.

[0053] In addition, according to one embodiment of the present invention, the semiconductor integrated device (1) includes a single-crystal diamond, thereby improving heat resistance performance and preventing deterioration caused by high temperatures during device operation, thereby extending the lifespan of the semiconductor integrated device (1) and enabling operation in extreme environments such as high temperatures, which can produce the effect of improving economic efficiency.

[0054]

[0055] Hereinafter, a diamond and nitride-based semiconductor integrated device (1) including a metal buffer layer (3100) according to one embodiment of the present invention and a method for manufacturing it will be described in detail.

[0056]

[0057] FIG. 1 illustrates a schematic diagram of a semiconductor integrated device (1) according to one embodiment of the present invention.

[0058]

[0059] A semiconductor integrated device (1) according to one embodiment of the present invention comprises a substrate layer (1000); a nitride semiconductor device (2000) formed on the substrate layer (1000); and a diamond semiconductor device (3000); wherein the nitride semiconductor device (2000) comprises a buffer layer (2100) disposed on the substrate layer (1000); a channel layer (2200) disposed on the buffer layer (2100); a barrier layer (2300) disposed on the channel layer (2200); a capping layer (2400) disposed on the barrier layer (2300); and a first electrode (2500) disposed on the capping layer (2400); and wherein the diamond semiconductor device (3000) comprises a metal buffer layer (3100) disposed on the substrate layer (1000); A diamond layer (3200) disposed on the metal buffer layer (3100); and a second electrode (3300) disposed on the diamond layer (3200); wherein the semiconductor integrated element (1) may be a semiconductor integrated element (1) that forms an integrated circuit by electrically connecting the first electrode (2500) and the second electrode (3300).

[0060] According to one embodiment of the present invention, the first electrode (2500) may include a first source (2510), a first gate (2520) formed spaced apart from the first source (2510), and a first drain (2530) formed spaced apart from the first source (2510) and the first gate (2520), and the second electrode (3300) may include a second source (3310), a second gate (3320) formed spaced apart from the second source (3310), and a second drain (3330) formed spaced apart from the second source (3310) and the second gate (3320).

[0061]

[0062] As illustrated in FIG. 1, a semiconductor integrated device (1) according to one embodiment of the present invention may include a nitride semiconductor device (2000) and a diamond semiconductor device (3000) that share a single substrate layer (1000), and the nitride semiconductor device (2000) and the diamond semiconductor device (3000) may be arranged adjacent to each other on the substrate layer (1000). However, the nitride semiconductor device (2000) and the diamond semiconductor device (3000) may be arranged adjacent to each other but do not come into contact with each other, and may be arranged spaced apart by a predetermined distance in a horizontal direction with respect to the substrate layer (1000).

[0063] The above nitride semiconductor device (2000) may include a buffer layer (2100), a channel layer (2200), a barrier layer (2300), a capping layer (2400), and a first electrode (2500). The buffer layer (2100) may be disposed in a portion of the substrate layer (1000), the channel layer (2200) may be disposed on the buffer layer (2100), the barrier layer (2300) may be disposed on the channel layer (2200), and the capping layer (2400) may be disposed on the barrier layer (2300). The first electrode (2500) may be disposed on the upper side of the capping layer (2400), but may not be disposed over the entire capping layer (2400), but may be formed only in a portion of the upper side of the capping layer (2400). Additionally, the first electrode (2500) includes a first source (2510), a first gate (2520), and a first drain (2530), and each of the first source (2510), the first gate (2520), and the first drain (2530) may be spaced apart from each other by a predetermined distance in a horizontal direction with respect to the upper surface of the capping layer (2400).

[0064] Meanwhile, the diamond semiconductor device (3000) may include a metal buffer layer (3100), a diamond layer (3200), and a second electrode (3300). The metal buffer layer (3100) may be placed on another part of the substrate layer (1000) where the buffer layer (2100) is not placed, and the diamond layer (3200) may be placed on the metal buffer layer (3100). The second electrode (3300) may include a second source (3310), a second gate (3320), and a second drain (3330), and may be placed on a part of the upper side of the diamond layer (3200). Additionally, the second source (3310), second gate (3320), and second drain (3330) of the second electrode (3300) may be spaced apart from each other by a predetermined distance in a horizontal direction with respect to the upper surface of the diamond layer (3200).

[0065] The second gate (3320) included in the second electrode (3300) can be electrically connected to the first gate (2520) included in the first electrode (2500), and the second drain (3330) can be electrically connected to the first drain (2530) to form the semiconductor integrated device (1) in which an integrated circuit is formed.

[0066]

[0067] According to one embodiment of the present invention, the nitride semiconductor device (2000) comprises gallium nitride (GaN), aluminum nitride (AlN), and aluminum gallium nitride (Al x Ga 1-x Includes 1 or more of N), and Al x Ga 1-x The x value of the above aluminum gallium nitride, represented by the chemical formula of N, can be from 0.1 to 99.9.

[0068] In addition, according to one embodiment of the present invention, the nitride semiconductor device (2000) is the aluminum gallium nitride (Al x Ga 1-x In the case of including N), aluminum gallium nitride (Al) included in each of the two layers arranged adjacent to each other among the channel layer (2200), barrier layer (2300), and capping layer (2400). x Ga 1-x N) has different x values, and the aluminum gallium nitride (Al) included in the channel layer (2200) x Ga 1-x The x value of N) is aluminum gallium nitride (Al) included in the barrier layer (2300). x Ga 1-x It can be smaller than the x value of N).

[0069]

[0070] Specifically, the nitride semiconductor device (2000) comprises gallium nitride (GaN), aluminum nitride (AlN), and aluminum gallium nitride (Al x Ga 1-xIt may include one or more of N). When the nitride semiconductor device (2000) includes aluminum gallium nitride, the aluminum gallium nitride is Al x Ga 1-x It can be expressed by the chemical formula of N, and x included in the chemical formula may be one of positive numbers between 0.1 and 99.9. Since the aluminum and gallium content included in the aluminum gallium nitride varies depending on the value of x, the detailed composition of the aluminum gallium nitride may differ from layer to layer.

[0071] More specifically, when the nitride semiconductor device (2000) includes aluminum gallium nitride, the detailed composition of the aluminum gallium nitride included in each of the buffer layer (2100), channel layer (2200), barrier layer (2300), and capping layer (2400) may differ from one another. That is, each of the buffer layer (2100), channel layer (2200), barrier layer (2300), and capping layer (2400) may include aluminum gallium nitride having different x values, and in the case of two layers among the channel layer (2200), barrier layer (2300), and capping layer (2400) that are arranged adjacent to each other, the aluminum gallium nitride included in each layer may have different x values. Additionally, the x value of the aluminum gallium nitride included in the channel layer (2200) may be smaller than the x value of the aluminum gallium nitride included in the buffer layer (2100) and the capping layer (2400).

[0072] For example, the x value of the aluminum gallium nitride contained in the buffer layer (2100) may be referred to as x1, the x value of the aluminum gallium nitride contained in the channel layer (2200) may be referred to as x2, the x value of the aluminum gallium nitride contained in the barrier layer (2300) may be referred to as x3, and the x value of the aluminum gallium nitride contained in the capping layer (2400) may be referred to as x4. In this case, x2 of the channel layer (2200) and x3 of the barrier layer (2300) placed above the channel layer (2200) may not have the same value and may have different values. Similarly, x3 and x4 may have different values, and for all the aforementioned cases, the value of x2 may be smaller than x3. Furthermore, according to one embodiment of the present invention, the value of x2 may be smaller than x3 and x4. That is, x2, x3, and x4 are x2 <x3, 및 x2<x4로 기재되는 부등식을 만족할 수 있다.

[0073] However, provided that the aforementioned conditions are satisfied, two layers that are not adjacent to each other may have the same x value. For example, if x1 and x2 have different values, x3 and x4 have different values, and x2 has a value smaller than x3 and x4, then x1 may have the same value as either x3 or x4.

[0074] Meanwhile, according to one embodiment of the present invention, the x value of the aluminum gallium nitride included in the buffer layer (2100) may be less than or equal to the x value of the aluminum gallium nitride included in the channel layer (2200). For example, when x2 and x3 have different values ​​and x3 and x4 have different values, x1 and x2 may have the same or different values. That is, x1 and x2 may satisfy the inequality described as x1 ≤ x2.

[0075]

[0076] The above nitride semiconductor device (2000) is composed of a buffer layer (2100), a channel layer (2200), a barrier layer (2300), and a capping layer (2400) each containing aluminum gallium nitride with different detailed compositions, thereby forming a layer composed of a two-dimensional electron gas (E) inside the channel layer (2200). The two-dimensional electron gas (E) is a structure in which electrons are arranged at a high density within a specific area range, and electrons can move at a high speed within the region of the two-dimensional electron gas (E). A more detailed description of the two-dimensional electron gas (E) will be provided in the drawings described later.

[0077]

[0078] That is, a nitride semiconductor device (2000) according to one embodiment of the present invention has a multilayer structure including a buffer layer (2100), a channel layer (2200), a barrier layer (2300), and a capping layer (2400), and each of the buffer layer (2100), the channel layer (2200), the barrier layer (2300), and the capping layer (2400) includes aluminum gallium nitride having different detailed compositions, thereby forming a two-dimensional electric gas inside the channel layer (2200) and thereby producing an effect that improves the performance of the semiconductor integrated device (1).

[0079]

[0080] Meanwhile, according to one embodiment of the present invention, the diamond layer (3200) may include a single-crystal diamond. Generally, diamond is a material that has higher heat dissipation characteristics than metallic materials such as copper or aluminum. That is, the semiconductor integrated device (1) according to one embodiment of the present invention can be used as a heat dissipation layer to dissipate heat generated when operating the semiconductor integrated device (1) by placing the diamond layer (3200) on the upper side of the diamond semiconductor device (3000). The diamond layer (3200) operating as the heat dissipation layer can prevent the deterioration of the device due to heat of the semiconductor integrated device (1) by diffusing heat to the outside so that the inside of the semiconductor integrated device (1) is not maintained at a high temperature.

[0081]

[0082] That is, the diamond layer (3200) according to one embodiment of the present invention can act as a heat dissipation layer, thereby having the effect of improving the lifespan of the semiconductor integrated device (1).

[0083]

[0084] FIG. 2 schematically illustrates a method for manufacturing a semiconductor integrated device (1) according to one embodiment of the present invention.

[0085]

[0086] A method for manufacturing a semiconductor integrated device (1) according to one embodiment of the present invention may include: a substrate layer preparation step (S10) for preparing a substrate layer (1000); a nitride semiconductor device formation step (S20) for forming a nitride semiconductor device (2000) on the substrate layer (1000); and a diamond semiconductor device formation step (S30) for forming a diamond semiconductor device (3000) on the substrate layer (1000).

[0087] In addition, according to one embodiment of the present invention, the substrate layer (1000) may include any one of Si, Al2O3, SiC, GaN, AlN, and Ga2O3.

[0088]

[0089] As illustrated in FIG. 2, the method for manufacturing the semiconductor integrated device (1) may include a substrate layer preparation step (S10) of selecting and preparing a substrate comprising any one of Si, Al2O3, SiC, GaN, AlN, and Ga2O3. By performing the substrate layer preparation step (S10), a substrate layer (1000) on which the nitride semiconductor device (2000) and the diamond semiconductor device (3000) are to be formed may be prepared. After the above substrate layer preparation step (S10) is performed, in one embodiment of the present invention, a nitride semiconductor device formation step (S20) for forming the nitride semiconductor device (2000) on a portion of the substrate layer (1000) may be performed, and a diamond semiconductor device formation step (S30) for forming the diamond semiconductor device (3000) on another portion of the substrate layer (1000) where the nitride semiconductor device (2000) is not formed may be performed.

[0090] According to one embodiment of the present invention, the execution order of the nitride semiconductor device formation step (S20) and the diamond semiconductor device formation step (S30) may not be fixed. In other words, the diamond semiconductor device formation step (S30) may be performed after the nitride semiconductor device formation step (S20), or the nitride semiconductor device formation step (S20) may be performed after the diamond semiconductor device formation step (S30), or the nitride semiconductor device formation step (S20) and the diamond semiconductor device formation step (S30) may each be performed individually and simultaneously.

[0091] A more detailed description of each of the above-mentioned nitride semiconductor device formation step (S20) and diamond semiconductor device formation step (S30) will be provided in the drawings described later.

[0092]

[0093] FIG. 3 schematically illustrates a nitride semiconductor device formation step (S20) according to one embodiment of the present invention.

[0094]

[0095] According to one embodiment of the present invention, the nitride semiconductor device forming step (S20) may include: a buffer layer placement step (S21) of placing a buffer layer (2100) on the substrate layer (1000); a channel layer placement step (S22) of placing a channel layer (2200) on the buffer layer (2100); a barrier layer placement step (S23) of placing a barrier layer (2300) on the channel layer (2200); a capping layer placement step (S24) of placing a capping layer (2400) on the barrier layer (2300); and a first electrode placement step (S25) of placing a first electrode (2500) on the capping layer (2400).

[0096] In addition, according to one embodiment of the present invention, the substrate layer (1000) is any one of Al2O3, Si, SiC, and Nitride-based substrates, and the nitride semiconductor device (2000) can be formed at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 400 to 1500°C.

[0097] According to one embodiment of the present invention, the buffer layer (2100) may be formed with a thickness of 1 to 2 μm, the channel layer (2200) may be formed with a thickness of 100 to 500 nm, the barrier layer (2300) may be formed with a thickness of 100 to 300 nm, and the capping layer (2400) may be formed with a thickness of 100 to 200 nm.

[0098]

[0099] As illustrated in FIG. 3, the nitride semiconductor device formation step (S20) may include a buffer layer placement step (S21), a channel layer placement step (S22), a barrier layer placement step (S23), a capping layer placement step (S24), and a first electrode placement step (S25).

[0100] Specifically, the nitride semiconductor formation step may place the buffer layer (2100) on the substrate layer (1000) by performing the buffer layer placement step (S21). As described above, the substrate layer (1000) may be a substrate comprising any one of Si, Al2O3, SiC, GaN, AlN, and Ga2O3. The buffer layer (2100) may have a thickness of 1 to 2 μm by being formed at a growth rate of 0.01 to 1000 μm / hr when a pressure of 0 to 1000 torr and a temperature of 400 to 1500°C are applied.

[0101] When the buffer layer (2100) is formed, the channel layer placement step (S22) of placing the channel layer (2200) on the buffer layer (2100) may be performed. Preferably, the channel layer (2200) may be formed at a growth rate of 0.01 to 1000 μm / hr when a pressure of 0 to 1000 torr and a temperature of 400 to 1500°C are applied, and the thickness of the channel layer (2200) is preferably 100 to 500 nm. The formation conditions of the channel layer (2200), including pressure, temperature, and growth rate, may correspond to the formation conditions of the buffer layer (2100).

[0102] When the placement of the channel layer (2200) is completed, the barrier layer placement step (S23) of placing the barrier layer (2300) on the channel layer (2200) may be performed. The formation conditions of the barrier layer placement step (S23) correspond to the formation conditions of the buffer layer (2100) and the channel layer (2200), and the barrier layer (2300) having a thickness of 100 to 300 nm may be formed by forming at a growth rate of 0.01 to 1000 μm / hr when a pressure of 0 to 1000 torr and a temperature of 400 to 1500°C are applied.

[0103] The capping layer (2400) can be placed on the barrier layer (2300) by performing the capping layer placement step (S24). The capping layer placement step (S24) can form the capping layer (2400) at a growth rate of 0.01 to 1000 μm / hr when a pressure of 0 to 1000 torr and a temperature of 400 to 1500°C are applied, and the thickness of the capping layer (2400) can be 100 to 200 nm. The formation conditions of the capping layer (2400), including pressure, temperature, and growth rate, may correspond to the formation conditions of the buffer layer (2100), channel layer (2200), and barrier layer (2300). That is, the pressure, temperature, and growth rate included in the formation conditions of each of the buffer layer (2100), channel layer (2200), barrier layer (2300), and capping layer (2400) may be the same as each other.

[0104] According to one embodiment of the present invention, the buffer layer placement step (S21), channel layer placement step (S22), barrier layer placement step (S23), and capping layer placement step (S24) may be performed by a thin film deposition process including chemical vapor deposition (CVD). As described above, each of the buffer layer (2100), channel layer (2200), barrier layer (2300), and capping layer (2400) may include gallium aluminum nitride with different detailed compositions, and the formation conditions of the buffer layer (2100), channel layer (2200), barrier layer (2300), and capping layer (2400) may correspond to each other with respect to pressure, temperature, and growth rate.

[0105]

[0106] When the capping layer placement step (S24) is completed, the first electrode placement step (S25) of placing the first electrode (2500) on the capping layer (2400) may be performed. The first electrode (2500) may be formed by depositing a metal on a portion of the capping layer (2400), and the other portion of the capping layer (2400) where the first electrode (2500) is not placed may be exposed to the outside. As described above, the first electrode (2500) may include a first source (2510), a first gate (2520), and a first drain (2530), and each of the first source (2510), the first gate (2520), and the first drain (2530) may be spaced apart from each other by a predetermined distance in a horizontal direction with respect to the upper surface of the capping layer (2400).

[0107]

[0108] FIG. 4 schematically illustrates a diamond semiconductor device formation step (S30) according to one embodiment of the present invention.

[0109]

[0110] According to one embodiment of the present invention, the diamond semiconductor device formation step (S30) comprises: a metal buffer layer placement step (S31) for placing a metal buffer layer (3100) on the substrate layer (1000); a diamond layer placement step (S32) for placing a diamond layer (3200) on the metal buffer layer (3100); and a second electrode placement step (S33) for placing a second electrode (3300) on the diamond layer (3200). The semiconductor integrated device (1) can form an integrated circuit by electrically connecting the first electrode (2500) and the second electrode (3300).

[0111] According to one embodiment of the present invention, the metal buffer layer (3100) may include one or more of iridium (Ir), ruthenium (Ru), Al2O3, YSZ, and SrTiO3.

[0112] In addition, according to one embodiment of the present invention, the diamond semiconductor device (3000) is formed by chemical vapor deposition (CVD), and the substrate layer (1000) may include one or more of Al2O3, MgO, Si, SiC, and nitride-based substrates.

[0113] Meanwhile, according to one embodiment of the present invention, the diamond layer (3200) can be formed at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 100 to 1500°C.

[0114]

[0115] As illustrated in FIG. 4, the diamond semiconductor device formation step (S30) may include a metal buffer layer placement step (S31), a diamond layer placement step (S32), and a second electrode placement step (S33).

[0116] Specifically, the diamond semiconductor device formation step (S30) can place the metal buffer layer (3100) on the substrate layer (1000) by performing the metal buffer layer placement step (S31). As described above, the metal buffer layer (3100) can be formed on a portion of the area included in the region where the nitride semiconductor device (2000) is not formed on the substrate layer (1000). The metal buffer layer (3100) may include one or more of iridium (Ir), ruthenium (Ru), Al2O3, YSZ, and SrTiO3.

[0117] The metal buffer layer (3100) may provide an environment where a single-crystal diamond thin film can be deposited on the upper side by including one or more of iridium (Ir), ruthenium (Ru), Al2O3, YSZ, and SrTiO3. In other words, the metal buffer layer (3100) can reduce the lattice mismatch between the diamond layer (3200) and the substrate layer (1000) and serve as a base layer for the growth of the diamond layer (3200).

[0118]

[0119] That is, the metal buffer layer (3100) according to one embodiment of the present invention can perform the role of a base layer that reduces lattice mismatch between the diamond layer (3200) and the substrate layer (1000), thereby preventing the occurrence of defects in the diamond semiconductor device (3000) and thereby improving the electrical characteristics of the semiconductor integrated device (1).

[0120]

[0121] Meanwhile, after the metal buffer layer (3100) is placed by the metal buffer layer placement step (S31), a diamond layer placement step (S32) may be performed in which the diamond layer (3200) is placed on the metal buffer layer (3100). Specifically, the diamond layer placement step (S32) may be performed by growing the single crystal diamond on the metal buffer layer (3100) by the chemical vapor deposition method.

[0122] The above diamond layer placement step (S32) can be performed under atmospheric conditions including methane (CH4), oxygen (O2), argon (Ar), nitrogen (N2), and hydrogen (H2) gases, and the diamond layer (3200) can be formed at a growth rate of 0.01 to 1000 μm / hr under pressure of 0 to 1000 torr and temperature of 100 to 1500°C.

[0123] In addition, according to one embodiment of the present invention, in the diamond layer placement step (S32), a hydrogen plasma treatment step of treating the diamond layer (3200) with hydrogen plasma may be further performed. A more detailed description of the hydrogen plasma treatment will be provided in the drawings described later.

[0124]

[0125] When the above diamond layer placement step (S32) is completed, a second electrode placement step (S33) for forming the electrode may be performed. The second electrode (3300) may be formed in a portion of the diamond layer (3200), and the other portion of the diamond layer (3200) where the second electrode (3300) is not placed may be exposed to the outside. By exposing the other portion of the diamond layer (3200) where the second electrode (3300) is not placed to the outside, heat generated when the semiconductor integrated circuit (1) is operated can be released to the outside.

[0126] As described above, the second electrode (3300) may include the second source (3310), the second gate (3320), and the second drain (3330). The second drain (3330) may be electrically connected to the first drain (2530) of the first electrode (2500), and the second gate (3320) may be electrically connected to the first gate (2520) to form the semiconductor integrated device (1) in which an integrated circuit is formed.

[0127]

[0128] FIG. 5 schematically illustrates the structure of a semiconductor integrated device (1) including an oxide film layer (O) according to one embodiment of the present invention.

[0129]

[0130] According to one embodiment of the present invention, the diamond semiconductor device (3000) further comprises an oxide film layer (O) disposed on the diamond layer (3200), and the second electrode (3300) may be disposed on the oxide film layer (O).

[0131] According to one embodiment of the present invention, the upper side of the diamond layer (3200) is treated with hydrogen plasma by applying a plasma power of 0.5 to 100 KW in an environment with a hydrogen content of 0.1 to 50%, and an oxide film layer (O) may be disposed on the upper side of the hydrogen plasma-treated diamond layer (3200).

[0132] According to one embodiment of the present invention, the diamond layer (3200) may include a two-dimensional hole gas (H) (2DHG, 2 Dimensional Hole Gas) composed of holes in the inner region of the diamond layer (3200) adjacent to the upper interface where the oxide film layer (O) is disposed.

[0133]

[0134] FIG. 5(a) schematically illustrates a top view of a semiconductor integrated device (1) including the oxide layer (O), and FIG. 5(b) schematically illustrates a front view of a semiconductor integrated device (1) including the oxide layer (O).

[0135]

[0136] As illustrated in FIGS. 5(a) and FIGS. 5(b), a semiconductor integrated device (1) according to one embodiment of the present invention may further include an oxide layer (O) between the diamond layer (3200) and the electrode. Additionally, the semiconductor integrated device (1) may partially etch the capping layer (2400) and the barrier layer (2300) of the nitride semiconductor device (2000), and may further include an oxide layer (O) between the partially etched barrier layer (2300) and the first gate (2520). Hereinafter, the semiconductor integrated device (1) including the oxide layer (O) is referred to as Example #1.

[0137]

[0138] As described above, the hydrogen plasma treatment may be further performed on the diamond layer (3200) included in Example #1 during the diamond layer placement step (S32). The hydrogen plasma treatment may be performed by placing Example #1 inside a plasma treatment apparatus including the chemical vapor deposition (CVD) method during the diamond layer placement step (S32), and applying a plasma power of 0.5 to 100 KW in an environment with a hydrogen content of 0.1 to 50%.

[0139] Additionally, as described above, the diamond layer (3200) comprises a single-crystal diamond, and the single-crystal diamond corresponds to a single-component material composed of carbon. That is, the diamond layer (3200) contains carbon atoms on its surface. Therefore, when the hydrogen plasma treatment is performed on the diamond layer (3200), the surface of the diamond layer (3200) can be modified by the carbon atoms contained on the surface of the diamond layer (3200) being combined with hydrogen atoms by the hydrogen plasma. The oxide film layer (O) can be deposited on the diamond layer (3200) with the modified surface. According to one embodiment of the present invention, the oxide film layer (O) may include any one of Al2O3, SiO2, HfO2, MoO3, V2O5, and WO3.

[0140] By the above hydrogen plasma treatment and the arrangement of the oxide film layer (O), a two-dimensional hole gas (H) (2DHG, 2 Dimensional Hole Gas) composed of holes can be formed inside the diamond layer (3200) of Example #1. As shown in FIG. 5(b), the two-dimensional hole gas (H) can be arranged inside the diamond layer (3200) adjacent to the interface between the diamond layer (3200) and the oxide film layer (O). A more detailed description of the two-dimensional hole gas (H) will be provided in the drawings described later.

[0141]

[0142] FIG. 6 schematically illustrates the process of forming a two-dimensional hole gas (H) according to one embodiment of the present invention.

[0143]

[0144] FIG. 6(a) schematically illustrates the band structure of the diamond layer (3200) in which the hydrogen plasma treatment is not performed, FIG. 6(b) schematically illustrates the band structure of the diamond layer (3200) in which the hydrogen plasma treatment is performed, and FIG. 6(c) schematically illustrates the band structure in which the oxide film layer (O) is placed on the diamond layer (3200) in which the hydrogen plasma treatment is performed.

[0145]

[0146] As described above, according to one embodiment of the present invention, the diamond layer (3200) is treated with hydrogen plasma, and an oxide film layer (O) is disposed on the upper side, so that a two-dimensional hole gas (H) (2DHG, 2 Dimensional Hole Gas) composed of holes is disposed adjacent to the interface between the diamond layer (3200) and the oxide film layer (O) and can be formed on the inner side of the diamond layer (3200).

[0147]

[0148] As shown in FIG. 6(a), when hydrogen plasma treatment is not performed on the diamond layer (3200), the diamond layer (3200) may have an unbent band structure. However, when hydrogen plasma treatment is performed on the diamond layer (3200), the surface of the diamond layer (3200) may be modified by the combination of a plurality of carbon atoms disposed on the upper surface of the diamond layer (3200) with a plurality of hydrogen atoms through the hydrogen plasma treatment, and a band bending phenomenon may occur as shown in FIG. 6(b).

[0149] The plurality of hydrogen atoms disposed on the modified surface of the diamond layer (3200) may have an electrical attraction, and the plurality of electrons disposed on the inner side of the diamond layer (3200) may move toward the modified surface of the diamond layer (3200) by the plurality of hydrogen atoms. At this time, the plurality of electrons moving due to the electrical attraction of the plurality of hydrogen atoms may be limited to electrons disposed on the inner side adjacent to the modified surface of the diamond layer (3200). As the plurality of electrons move toward the modified surface of the diamond layer (3200), a plurality of holes may be formed on the inner side of the diamond layer (3200) where the plurality of electrons were previously disposed. That is, a plurality of holes may be disposed on the inner side adjacent to the modified surface of the diamond layer (3200).

[0150] Meanwhile, the above Example #1 can be formed by further disposing of the oxide film layer (O) on the diamond layer (3200) on which the above hydrogen plasma treatment has been performed. As shown in FIG. 6(c), in the case of Example #1, the band of the diamond layer (3200) may have a more curved shape than in FIG. 6(b). Due to the electromagnetic attraction between a plurality of hydrogen atoms disposed on the surface of the diamond layer (3200) and the oxide film layer (O), a plurality of electrons disposed inside the diamond layer (3200) move toward the oxide film layer (O), thereby allowing a larger amount of multiple holes to be disposed inside the diamond layer (3200) than in FIG. 6(b). That is, a layer composed of holes may be formed within a certain distance range from the surface of the diamond layer (3200), and the layer composed of holes corresponds to the two-dimensional hole gas (H).

[0151] The above two-dimensional hole gas (H) can operate as a channel through which holes can move within the diamond semiconductor device (3000). Since the above two-dimensional hole gas (H) is formed inside the diamond semiconductor device (3000) of Example #1 even when no voltage is applied to the second electrode (3300), the diamond semiconductor device (3000) of Example #1 can function as a D-mode P-channel FET that maintains an always-on state by including a channel through which holes can move even when no voltage is applied.

[0152]

[0153] That is, the diamond semiconductor device (3000) according to one embodiment of the present invention can improve hole mobility by including a channel composed of a two-dimensional hole gas (H), thereby producing the effect of improving the performance of the semiconductor integrated device (1).

[0154]

[0155] FIG. 7 schematically illustrates the process of forming a two-dimensional electron gas (E) according to one embodiment of the present invention.

[0156]

[0157] FIG. 7(a) illustrates the band structure of each of the channel layer (2200) and the barrier layer (2300) according to one embodiment of the present invention, and FIG. 7(b) illustrates the band bending phenomenon occurring in the barrier layer (2300) when the barrier layer (2300) is placed on the channel layer (2200).

[0158]

[0159] According to one embodiment of the present invention, the channel layer (2200) may include a two-dimensional electron gas (E) (2DEG, 2 Dimensional Electron Gas) composed of electrons in an inner region of the channel layer (2200) adjacent to an upper interface where a barrier layer (2300) is disposed.

[0160]

[0161] As described above, the channel layer (2200) and the barrier layer (2300) may include aluminum gallium nitride having different detailed compositions. In addition, according to one embodiment of the present invention, aluminum gallium nitride (Al) included in the channel layer (2200) x Ga 1-x The x value corresponding to the aluminum composition of N) is aluminum gallium nitride (Al) included in the barrier layer (2300). x Ga 1-x It can have a value smaller than the x value of N).

[0162] As illustrated in FIG. 7(a), when the detailed composition of the aluminum gallium nitride included in each of the channel layer (2200) and the barrier layer (2300) is different, and the channel layer (2200) and the barrier layer (2300) are not placed adjacent to each other but exist as separate layers, the Fermi energy level (Ef) of the channel layer (2200) and the Fermi energy level of the barrier layer (2300) may be placed at different locations.

[0163] Meanwhile, as illustrated in FIG. 7(b), when the barrier layer (2300) is placed on top of the channel layer (2200), the Fermi energy level of the channel layer (2200) and the Fermi energy level of the barrier layer (2300) have a tendency to align at corresponding positions, so a band bending phenomenon may occur at the interface where the channel layer (2200) and the barrier layer (2300) are placed adjacent to each other. Due to the band bending phenomenon, a quantum well may be formed between the barrier layer (2300) and the channel layer (2200). Electrons that cross over to the interface between the barrier layer (2300) and the channel layer (2200) are trapped in the quantum well, and thus a two-dimensional electron gas (E) in which a plurality of electrons are placed may be formed in the region where the quantum well is formed. The above two-dimensional electron gas (E) may exist in the form of a layer that is positioned inside the interface of the channel layer (2200) bonded with the barrier layer (2300) and can only move in a horizontal direction relative to the surface of the channel layer (2200), thereby operating as a channel through which electrons move and allowing current to flow in the channel layer (2200).

[0164] The above two-dimensional electron gas (E) is formed inside the nitride semiconductor device (2000) included in Example #1 even when no voltage is applied to the first electrode (2500). That is, the nitride semiconductor device (2000) can function as a D-mode N-channel FET that maintains an always-on state by including a channel through which electrons can move even when no voltage is applied to the first electrode (2500).

[0165]

[0166] That is, the channel layer (2200) according to one embodiment of the present invention can have the effect of improving electrical conductivity by including the two-dimensional electron gas (E).

[0167] In addition, the nitride semiconductor device (2000) according to one embodiment of the present invention can improve the electrical performance of the semiconductor integrated device (1) by improving electron mobility and reducing switching loss through the two-dimensional electron gas (E).

[0168]

[0169] FIG. 8 schematically illustrates the structure of a semiconductor integrated device (1) further comprising an oxide film layer (O) and a doped diamond multilayer structure according to one embodiment of the present invention, FIG. 9 schematically illustrates the structure of a semiconductor integrated device (1) further comprising a p-aluminum gallium nitride layer (2410) and a doped diamond multilayer structure according to one embodiment of the present invention, and FIG. 10 schematically illustrates the structure of a semiconductor integrated device (1) further comprising a p-aluminum gallium nitride layer (2410) according to one embodiment of the present invention.

[0170]

[0171] According to one embodiment of the present invention, the nitride semiconductor device (2000) may further include a p-aluminum gallium nitride layer (2410) formed between the first gate (2520) and the capping layer (2400).

[0172] Additionally, according to one embodiment of the present invention, the diamond semiconductor device (3000) may further include: an n-diamond layer (3400) formed on the diamond layer (3200); a p-diamond layer (3410) formed between the n-diamond layer (3400) and the second source (3310), and between the n-diamond layer (3400) and the second drain (3330), respectively; and an oxide layer (O) formed between the n-diamond layer (3400) and the second gate (3320).

[0173]

[0174] As described above, the above embodiment #1 includes the two-dimensional electron gas (E) and the two-dimensional hole gas (H), and the nitride semiconductor device (2000) and the diamond semiconductor device (3000) can each operate as a d-mode N-channel FET and a d-mode P-channel FET, respectively, in an always-on state. Meanwhile, in the present invention, in addition to the semiconductor integrated device (1) in an always-on state, a plurality of embodiments of a semiconductor integrated device (1) utilizing an e-mode FET in an always-off state are manufactured and applied, and each is illustrated in FIGS. 8, FIGS. 9, and FIGS. 10.

[0175]

[0176] FIG. 8(a) schematically illustrates a top view of a semiconductor integrated device (1) further comprising a p-aluminum gallium nitride layer (2410) and a doped diamond multilayer structure according to one embodiment of the present invention, and FIG. 8(b) schematically illustrates a front view of a semiconductor integrated device (1) further comprising a p-aluminum gallium nitride layer (2410) and a doped diamond multilayer structure.

[0177]

[0178] As illustrated in FIG. 8 (a) and FIG. 8 (b), a semiconductor integrated device (1) according to one embodiment of the present invention may further include an oxide layer (O) in the nitride semiconductor device (2000), and may further include a doped diamond multilayer structure comprising the n-diamond layer (3400), the p-diamond layer (3410), and the oxide layer (O) in the diamond semiconductor device (3000). Hereinafter, the semiconductor integrated device (1) further including the oxide layer (O) and the doped diamond multilayer structure will be referred to as Example #2.

[0179]

[0180] The nitride semiconductor device (2000) of Example #2 above has a structure corresponding to the nitride semiconductor device (2000) of Example #1 above, and may further include an oxide layer (O) formed between the first gate (2520) and the barrier layer (2300) after the capping layer (2400) and the barrier layer (2300) are partially etched. The nitride semiconductor device (2000) may be in a state where a two-dimensional hole gas (E) is formed inside the channel layer (2200).

[0181] Accordingly, the nitride semiconductor device (2000) of the above embodiment #2 can function as a D-mode N-channel FET that maintains an always-on state by including a channel through which electrons can move even when no voltage is applied to the first electrode (2500).

[0182]

[0183] Meanwhile, the diamond semiconductor device (3000) of the above embodiment #2 further includes an n-diamond layer (3400) disposed on the diamond layer (3200), and may further include a p-diamond layer (3410) formed between the n-diamond layer (3400) and the second source (3310), and between the n-diamond layer (3400) and the second drain (3330), respectively, and an oxide layer (O) formed between the n-diamond layer (3400) and the second gate (3320).

[0184] The n-diamond layer (3400) may include a diamond doped with an n-type material, and the p-diamond layer (3410) may include a diamond doped with a p-type doping material. According to one embodiment of the present invention, the p-diamond layer (3410) may include a diamond that is heavily doped with a p-type doping material. The oxide layer (O) disposed between the n-diamond layer (3400) and the second gate (3320) may serve as an insulating layer that prevents the movement of charge. When the diamond semiconductor device (3000) of Example #2 further includes the n-diamond layer (3400), the p-diamond layer (3410), and the oxide layer (O), the hydrogen plasma treatment may not be performed on the diamond layer (3200) included in the diamond semiconductor device (3000) of Example #2. Accordingly, the two-dimensional hole gas (H) may not be formed in the diamond semiconductor device (3000) included in Example #2 above.

[0185] That is, in the diamond semiconductor device (3000) of the above embodiment #2, there is no channel through which holes can move when voltage is not applied to the second gate (3320), so the diamond semiconductor device (3000) included in the above embodiment #2 can operate as an e-mode P-channel FET that is always off.

[0186] That is, the above embodiment #2 includes the nitride semiconductor device (2000) which functions as a D-mode N-channel FET, thereby inducing electron movement even when no external voltage is applied, and when an external voltage is applied, a channel through which holes can move is formed inside the diamond semiconductor device (3000), thereby switching to an ON state and inducing a flow of holes.

[0187]

[0188] As illustrated in FIG. 9 (a) and FIG. 9 (b), a semiconductor integrated device (1) according to one embodiment of the present invention may further include a p-aluminum gallium nitride layer (2410) in the nitride semiconductor device (2000), and may further include a doped diamond multilayer structure comprising an n-diamond layer (3400), a p-diamond layer (3410), and an oxide layer (O) in the diamond semiconductor device (3000). Hereinafter, the semiconductor integrated device (1) further including the p-aluminum gallium nitride layer (2410) and the doped diamond multilayer structure will be referred to as Example #3.

[0189]

[0190] The nitride semiconductor device (2000) of Example #3 above may not include the capping layer (2400) and may further include a p-aluminum gallium nitride layer (2410) formed between the first gate (2520) and the barrier layer (2300). The p-aluminum gallium nitride layer (2410) may include doped aluminum gallium nitride. Additionally, the p-aluminum gallium nitride layer (2410) may perform the role of an internal negative battery for the nitride semiconductor device (2000), thereby forming a state in which a preset voltage is applied even when no external voltage is applied to the first gate (2520) of Example #3.

[0191] That is, the channel formed by the two-dimensional electron gas (E) included in the nitride semiconductor device (2000) of Example #3 can be switched to an off state by the p-aluminum gallium nitride layer (2410). Therefore, the nitride semiconductor device (2000) of Example #3 can operate as an e-mode N-channel FET in which the channel is always in an off state and becomes on when an external voltage is applied.

[0192] However, the two-dimensional electron gas (E) of the channel layer (2200) included in the nitride semiconductor device (2000) of the above embodiment #3 is switched to an off state when no external voltage is applied by the p-aluminum gallium nitride layer (2410), and when an external voltage is applied to the first gate (2520) and it becomes an on state, the two-dimensional electron gas (E) can operate as a channel through which electrons move, just as in embodiment #1 and embodiment #2.

[0193]

[0194] Meanwhile, the diamond semiconductor device (3000) of Example #3 may further include an n-diamond layer (3400) disposed on the diamond layer (3200), and may further include a p-diamond layer (3410) formed between the n-diamond layer (3400) and the second source (3310), and between the n-diamond layer (3400) and the second drain (3330), respectively, and an oxide layer (O) formed between the n-diamond layer (3400) and the second gate (3320). That is, the diamond semiconductor device (3000) of Example #3 may have a structure corresponding to the diamond semiconductor device (3000) of Example #2.

[0195] The n-diamond layer (3400) may include a diamond doped with an n-type material, and the p-diamond layer (3410) may include a diamond doped with a p-type doping material. According to one embodiment of the present invention, the p-diamond layer (3410) may include a diamond that is heavily doped with a p-type doping material. The oxide layer (O) disposed between the n-diamond layer (3400) and the second gate (3320) may serve as an insulating layer that prevents the movement of charge. When the diamond semiconductor device (3000) of Example #3 further includes the n-diamond layer (3400), the p-diamond layer (3410), and the oxide layer (O), the hydrogen plasma treatment may not be performed on the diamond layer (3200) included in the diamond semiconductor device (3000) of Example #3. In addition, since Example #3 does not include the oxide layer (O) that forms the two-dimensional hole gas (H) by being placed on the upper side of the diamond layer (3200) in Example #1, the two-dimensional hole gas (H) is not formed in the diamond semiconductor device (3000) included in Example #3.

[0196] That is, in the diamond semiconductor device (3000) of the above embodiment #3, there is no channel through which holes can move when voltage is not applied to the second gate (3320), so the diamond semiconductor device (3000) included in the above embodiment #2 can operate as an e-mode P-channel FET that is always off.

[0197] That is, when an external voltage is applied to the above embodiment #3, the nitride semiconductor device (2000) can be switched to an on state to induce a flow of electrons, and a channel through which holes can move is formed inside the diamond semiconductor device (3000) so that it can be switched to an on state to induce a flow of holes.

[0198]

[0199] As illustrated in FIG. 10(a) and FIG. 10(b), a semiconductor integrated device (1) according to one embodiment of the present invention may further include a p-aluminum gallium nitride layer (2410) in the nitride semiconductor device (2000) and may further include an oxide film layer (O) in the diamond semiconductor device (3000). Hereinafter, the semiconductor integrated device (1) in which the nitride semiconductor device (2000) further includes the p-aluminum gallium nitride layer (2410) and the diamond semiconductor device (3000) further includes the oxide film layer (O) will be referred to as Example #4.

[0200]

[0201] The nitride semiconductor device (2000) of Example #4 above may not include the capping layer (2400) and may further include a p-aluminum gallium nitride layer (2410) formed between the first gate (2520) and the barrier layer (2300). The p-aluminum gallium nitride layer (2410) may include doped aluminum gallium nitride. Additionally, the p-aluminum gallium nitride layer (2410) may perform the role of an internal negative battery for the nitride semiconductor device (2000), thereby forming a state in which a preset voltage is applied even when no external voltage is applied to the first gate (2520) of Example #4.

[0202] That is, the channel formed by the two-dimensional electron gas (E) included in the nitride semiconductor device (2000) of Example #4 can be switched to an off state by the p-aluminum gallium nitride layer (2410). Therefore, the nitride semiconductor device (2000) of Example #4 can operate as an e-mode N-channel FET in which the channel is always in an off state and becomes on when an external voltage is applied.

[0203] However, the two-dimensional electron gas (E) of the channel layer (2200) included in the nitride semiconductor device (2000) of the above embodiment #4 is switched to an off state when no external voltage is applied by the p-aluminum gallium nitride layer (2410), and when an external voltage is applied to the first gate (2520) and it becomes an on state, the two-dimensional electron gas (E) can operate as a channel through which electrons move, just as in embodiment #1 and embodiment #2.

[0204] Meanwhile, the diamond semiconductor device (3000) of Example #4 may have a structure corresponding to the diamond semiconductor device (3000) of Example #1. The diamond semiconductor device (3000) of Example #4 may perform hydrogen plasma treatment on the diamond layer (3200) as described above, and by including the oxide layer (O) between the second gate (3320) and the diamond layer (3200), the two-dimensional hole gas (H) may be formed inside the diamond layer (3200). Accordingly, the diamond semiconductor device (3000) of Example #4 may function as a d-mode P-channel FET that is always in an on state.

[0205] That is, when an external voltage is applied to the embodiment #4 according to one embodiment of the present invention, the nitride semiconductor device (2000) can be switched to an on state to induce a flow of electrons, and the diamond semiconductor device (3000) can continuously induce a flow of holes regardless of whether an external voltage is applied.

[0206]

[0207] A semiconductor integrated device (1) according to one embodiment of the present invention can have the effect of expanding the application range of the semiconductor integrated device (1) by controlling whether it is in e-mode and d-mode through the stacked structure of the nitride semiconductor device (2000) and the diamond semiconductor device (3000).

[0208]

[0209] According to one embodiment of the present invention, a semiconductor integrated device can improve the withstand voltage characteristics and switching characteristics of the semiconductor integrated device by including an ultrawide bandgap material, thereby exhibiting the effect of expanding the usability of the device.

[0210] According to one embodiment of the present invention, the semiconductor integrated device includes a single-crystal diamond, thereby improving heat resistance performance and preventing degradation caused by high temperatures during device operation, which extends the lifespan of the semiconductor integrated device and enables operation in extreme environments such as high temperatures, thereby improving economic efficiency.

[0211] According to one embodiment of the present invention, a nitride semiconductor device has a multilayer structure including a buffer layer, a channel layer, a barrier layer, and a capping layer, and each of the buffer layer, channel layer, barrier layer, and capping layer includes aluminum gallium nitride having different detailed compositions, thereby forming a two-dimensional electric gas inside the channel layer to improve the performance of the semiconductor integrated device.

[0212] According to one embodiment of the present invention, the diamond layer can act as a heat dissipation layer, thereby having the effect of improving the lifespan of a semiconductor integrated device.

[0213] According to one embodiment of the present invention, the metal buffer layer can perform the role of a base layer that reduces lattice mismatch between the diamond layer and the substrate layer, thereby preventing the occurrence of defects in the diamond semiconductor device and improving the electrical characteristics of the semiconductor integrated device.

[0214] According to one embodiment of the present invention, a diamond semiconductor device can improve hole mobility by including a channel composed of a two-dimensional hole gas, thereby exhibiting the effect of improving the performance of a semiconductor integrated device.

[0215] According to one embodiment of the present invention, the channel layer can have the effect of improving electrical conductivity by including a two-dimensional electron gas.

[0216] According to one embodiment of the present invention, a nitride semiconductor device can improve electron mobility and reduce switching losses by means of a two-dimensional electron gas, thereby improving the electrical performance of the semiconductor integrated device.

[0217] According to one embodiment of the present invention, the semiconductor integrated device can expand the application range of the semiconductor integrated device by controlling whether it is in e-mode and d-mode through a stacked structure of a nitride semiconductor device and a diamond semiconductor device.

[0218]

[0219] Although the embodiments have been described above with reference to limited examples and drawings, those skilled in the art can make various modifications and variations from the description above. For example, suitable results may be achieved even if the described techniques are performed in a different order than described, and / or if the components of the described system, structure, device, circuit, etc. are combined or assembled in a form different from described, or replaced or substituted by other components or equivalents. Therefore, other implementations, other embodiments, and equivalents to the claims below are also within the scope of the claims.

Claims

1. As a semiconductor integrated device, A substrate layer; a nitride semiconductor device formed on the substrate layer; and a diamond semiconductor device; are included. The above nitride semiconductor device is, A buffer layer disposed on the above substrate layer; A channel layer disposed on the above buffer layer; A barrier layer disposed on the above channel layer; A capping layer disposed on the above barrier layer; and A first electrode disposed on the capping layer; comprising The above diamond semiconductor device is, A metal buffer layer disposed on the above substrate layer; A diamond layer disposed on the metal buffer layer above; A second electrode disposed on the diamond layer; comprising The above semiconductor integrated device is a semiconductor integrated device that forms an integrated circuit by electrically connecting the first electrode and the second electrode.

2. In Claim 1, A semiconductor integrated device in which the substrate layer comprises any one of Si, Al2O3, SiC, GaN, AlN, and Ga2O3.

3. In Claim 1, The above nitride semiconductor device is gallium nitride (GaN), aluminum nitride (AlN), and aluminum gallium nitride (Al x Ga 1-x Includes 1 or more of N), Al x Ga 1-x A semiconductor integrated device in which the x value of the above-mentioned aluminum gallium nitride, represented by the chemical formula of N, is 0.1 to 99.

9.

4. In Claim 3, The above nitride semiconductor device is the above aluminum gallium nitride (Al x Ga 1-x In the case of including N), Gallium aluminum nitride (Al) included in each of the two layers arranged adjacent to each other among the channel layer, barrier layer, and capping layer. x Ga 1-x N) has different x values, Gallium aluminum nitride (Al) included in the above channel layer x Ga 1-x The x value of N) is the aluminum gallium nitride (Al) included in the barrier layer. x Ga 1-x A semiconductor integrated circuit smaller than the x value of N.

5. In Claim 1, The above substrate layer is any one of Al2O3, Si, SiC, and nitride-based substrates, and The above nitride semiconductor device is a semiconductor integrated device formed at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 400 to 1500℃.

6. In Claim 1, The above metal buffer layer comprises one or more of iridium (Ir), ruthenium (Ru), Al2O3, YSZ, and SrTiO3, forming a semiconductor integrated device.

7. In Claim 1, The above diamond semiconductor device is formed by chemical vapor deposition (CVD), and The above substrate layer comprises one or more of Al2O3, MgO, Si, SiC, and nitride-based substrates, and A semiconductor integrated device in which the diamond layer is formed at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 100 to 1500℃.

8. In Claim 1, The above diamond semiconductor device is, It further includes an oxide film layer disposed on the diamond layer above, and The above second electrode is a semiconductor integrated device disposed on the oxide film layer.

9. In Claim 1, The first electrode comprises a first source, a first gate formed spaced apart from the first source, and a first drain formed spaced apart from the first source and the first gate. The above nitride semiconductor device is, A semiconductor integrated device further comprising a p-gallium aluminum nitride layer formed between the first gate and the capping layer.

10. In Claim 1, The second electrode comprises a second source, a second gate formed spaced apart from the second source, and a second drain formed spaced apart from the second source and the second gate. The above diamond semiconductor device is, n-diamond layer formed on the above diamond layer; A p-diamond layer formed between the n-diamond layer and the second source, and between the n-diamond layer and the second drain, respectively; and A semiconductor integrated device further comprising an oxide film layer formed between the n-diamond layer and the second gate.

11. A method for manufacturing a semiconductor integrated circuit, Substrate layer preparation step for preparing a substrate layer; A step of forming a nitride semiconductor device on the substrate layer; and A diamond semiconductor device formation step for forming a diamond semiconductor device on the substrate layer; comprising The above nitride semiconductor device formation step is, A buffer layer placement step of placing a buffer layer on the substrate layer; A channel layer placement step of placing a channel layer on the above buffer layer; A barrier layer placement step of placing a barrier layer on the above channel layer; A capping layer placement step of placing a capping layer on the above barrier layer; and A first electrode placement step of placing a first electrode on the capping layer; comprising, The above diamond semiconductor device formation step is, A metal buffer layer placement step of placing a metal buffer layer on the above substrate layer; A diamond layer placement step of placing a diamond layer on the metal buffer layer above; and A second electrode placement step of placing a second electrode on the diamond layer; comprising A method for manufacturing a semiconductor integrated device, wherein the semiconductor integrated device electrically connects the first electrode and the second electrode to form an integrated circuit.

Images