Method and device for determining parameters of circuit on basis of pareto set

Abstract

The present invention relates to a method for determining parameter values of a circuit by using a computing device when a target performance or a target FoM of the circuit is given, the method comprising, by using a Pareto set based on performance metrics composed of designs for which performance metrics have been evaluated, determining designs which are to serve as references for a search, and deciding on a directionality of the search.

Description

Pareto set-based circuit parameter determination method and device

[0001] The present invention relates to a method for determining circuit parameters, and more particularly to a method for determining parameters that satisfy a target performance indicator based on a Pareto set when a target performance indicator is given in an analog circuit or a digital circuit, and to an apparatus for performing said method.

[0002]

[0003] In circuit design, determining the parameters of circuit components is a very important process. For example, when a component is a resistor, the parameter is the resistance value; when a component is a capacitor, the parameter is capacitance; when a component is an inductor, the parameter is inductance; and when a component is a transistor, the parameters can be the channel length and channel width.

[0004] The process of determining parameters requires a significant amount of time and labor, but currently, this process relies primarily on human hands.

[0005] Algorithms utilizing Bayesian optimization (BO) or reinforcement learning (RL) have been proposed to automate the process of determining parameters.

[0006] Although the BO algorithm has high search efficiency, it has the disadvantage that execution time increases rapidly as the number of searched designs increases because it directly utilizes all previous designs for each search. The RL algorithm uses the searched designs for training but does not directly use them for searching, so the time required for each search is constant. However, the RL algorithm has the disadvantage that its search efficiency is lower than that of BO when there is no pre-trained model.

[0007] Since the performance of both BO algorithms and RL algorithms drops sharply as the number of parameters increases, practical algorithms based on the aforementioned BO algorithms and RL algorithms utilize dimensionality reduction algorithms and search complexity reduction algorithms based on domain knowledge. However, these algorithms have poor scalability because they require separate hyperparameter tuning or separate data collection and processing steps.

[0008] In addition, using these separate algorithms requires an engineer with high proficiency in the aforementioned separate algorithms and circuits, but in reality, there are few engineers proficient in both circuits and algorithms, and there is a limitation in that dependence on highly skilled engineers cannot be avoided.

[0009]

[0010] The technical problem that the present invention aims to solve is to provide a method for determining parameters that satisfy a target performance indicator based on a Pareto set when a target performance indicator is given in an analog circuit or a digital circuit, and an apparatus for performing said method.

[0011]

[0012] A method for determining parameter values ​​of a circuit using a computing device according to an embodiment of the present invention comprises the steps of: comparing design performance indicator values ​​of each of the Pareto set candidate designs with one another and, based on the comparison result, extracting designs having non-dominant performance indicator values ​​from the Pareto set candidate designs to generate a Pareto set; and extracting first designs from the designs based on a first FoM (Figure of Merit) for each of the designs to generate a first design batch.

[0013] According to an embodiment, the method further comprises the steps of: proposing a change in parameter values ​​of each of the first designs to improve a first performance indicator value of each of the first designs; changing the parameter values ​​of each of the first designs using the change in parameter values ​​proposed for each of the first designs and generating second designs having changed parameter values; and proposing a second design arrangement including the second designs.

[0014] According to an embodiment, the method further comprises the steps of receiving a type of performance indicator and a circuit topology corresponding to the circuit, analyzing each of the second designs according to the circuit topology, and calculating a second performance indicator value corresponding to the type of performance indicator for each of the second designs according to the analysis result.

[0015] According to an embodiment, the method further comprises the step of comparing a performance indicator value of each of the designs with a third performance indicator value calculated for each of the second designs, and the step of calculating a Pareto score for each of the second designs based on the comparison result.

[0016] According to an embodiment, the method further comprises the steps of generating an approximate performance indicator value by approximating a second performance indicator value for each of the second designs using a critique network executed on the computing device, and generating an approximate Pareto score for each of the second designs using the critique network.

[0017] According to an embodiment, the method further comprises the steps of receiving a performance indicator target value and a performance indicator weight; calculating the difference between the approximate performance indicator value and the performance indicator target value; calculating a second FoM by multiplying the difference by the performance indicator weight; and calculating an acquisition function corresponding to the sum of the second FoM and the approximate Pareto score.

[0018] According to an embodiment, the method further comprises the steps of updating parameters of an actor network executed on a computing device that proposes the second design arrangement so as to maximize the acquisition function, updating parameters of a critique network that performs the approximation so as to minimize the approximation error for the third performance indicator value and the Pareto score, and updating the Pareto set using the second design arrangement and the Pareto score.

[0019]

[0020] The Pareto set-based circuit parameter determination method and apparatus according to an embodiment of the present invention has the effect of utilizing only the designs included in the Pareto set among the searched designs, instead of considering all searched designs.

[0021] In addition, since the Pareto set-based circuit parameter determination method and device do not require separate algorithms to reduce search complexity, they have the effect of reducing the need for high-cost, skilled engineers.

[0022] In addition, the Pareto set-based circuit parameter determination method and device utilize Pareto sets to more efficiently search for circuits that satisfy changing target performance indicators, thereby having the effect of significantly reducing time and labor in actual design.

[0023]

[0024] Detailed descriptions of each drawing are provided to help to more fully understand the drawings cited in the detailed description of the present invention.

[0025] FIG. 1 is a schematic block diagram of a computing device that performs a Pareto set-based circuit parameter determination method according to an embodiment of the present invention.

[0026] FIGS. 2 and FIGS. 3 are flowcharts for explaining a Pareto set-based circuit parameter determination method performed on a computing device shown in FIG. 1.

[0027]

[0028] FIG. 1 is a schematic block diagram of a computing device performing a Pareto set-based circuit parameter determination method according to an embodiment of the present invention, and FIG. 2 and FIG. 3 are flowcharts for explaining a Pareto set-based circuit parameter determination method performed in the computing device shown in FIG. 1.

[0029] Referring to FIGS. 1 and FIGS. 2, the computing device (100) includes an input device (110), a processor (120), and a memory device (150). According to embodiments, the computing device (100) may further include an output device (170) capable of outputting information (also referred to as 'data') processed by a program (130) executed on the processor (120).

[0030] The computing device (100) may be a PC or a cloud-based computing device. The input device (110) may be a keyboard or an external storage device, and the output device (170) may be a monitor or an external storage device.

[0031] The memory device (150) may be a data storage medium or a data storage device that stores a program (130) readable by a computer (or computing device, 100) for performing a method of optimizing circuit parameters (also referred to as ‘design’ or ‘determination’) using a computing device (100), and data generated during the operation of the program (130).

[0032] The processor (120) may be a CPU (Central Processing Unit), GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), FPGA (Field-Programmable Gate Array), ASIC (Application-Specific Integrated Circuit), or Neural Processing Unit (NPU), but is not limited thereto.

[0033] The program (130) may be a Pareto set-based circuit parameter optimization program (optimization may also be referred to as 'automation' or 'decision'), and may be loaded from a memory device (150) into a processor (120) and executed by the processor (120).

[0034] A Pareto set-based circuit parameter optimization program (130) can generate a Pareto set (PS) that includes some or all of the designs among all designs, rather than all designs, to overcome the limitations of Bayesian optimization or reinforcement learning, compare the performance indicator value for each design included in the Pareto set (PS) with the performance indicator value for the design to be evaluated, and change, determine, or optimize the parameter value of the design according to the comparison result.

[0035] In this specification, performance indicator values ​​collectively refer to one or more performance indicator values, and parameter values ​​collectively refer to one or more parameter values. Accordingly, comparing a first performance indicator value with a second performance indicator value may mean comparing each of a plurality of different first performance indicator values ​​(e.g., power consumption and operating speed) with each of a plurality of different second performance indicator values ​​(e.g., power consumption and operating speed).

[0036] The Pareto set-based circuit parameter optimization program (130) can maintain the execution time of a single search almost constant even if the search proceeds for a long time and the number of evaluated designs increases, and can effectively optimize the parameter values ​​of the designs without introducing dimensionality reduction or search complexity reduction algorithms, even for designs with many parameters. Additionally, performance can be further improved by introducing dimensionality reduction or search complexity reduction algorithms into the program (130).

[0037] The program (130) may include an artificial neural network (ANN) comprising an actor network (133) and a critique network (137). Each of the actor network (133) and the critique network (137) may be implemented as a recurrent neural network (RNN) or a transformer capable of accommodating variable-length inputs.

[0038] A program (130) includes configurations (131–140) executed therein, and each of the configurations (131–140) means a set of program codes functionally and / or structurally combined that can perform functions corresponding to each name described in this specification.

[0039] The processor (120) can receive designs (RC), circuit topology (CP, also called 'circuit design'), performance indicator type (PMT), performance indicator target value (PMV), performance indicator weight (WT), and termination condition (TC) that can be referenced through the input device (110) (S110).

[0040] The performance indicator type (PMT) may collectively refer to one or more performance indicators, the performance indicator target value (PMV) may collectively refer to one or more performance indicator target values, and the performance indicator weight (WT) may collectively refer to one or more performance indicator weights.

[0041] Circuit topology (CP) refers to structural characteristics indicating what components a circuit includes and how said components are connected to one another. The circuits described herein include analog circuits or digital circuits.

[0042] Reference designs (RC) may include designs that have been used in the past as reference designs before the program (130) is executed, and depending on the embodiment, reference designs (RC) may not be input.

[0043] The components include at least one of a passive component, an active component, or a source. The passive component includes a resistor, a capacitor, or an inductor, etc., the active component includes a MOSFET or a BJT, etc., and the source includes a voltage source or a current source, etc.

[0044] Performance metrics used to evaluate the performance of a circuit may differ depending on the type of circuit (e.g., analog circuits, digital circuits, or power circuits).

[0045] For example, the types of performance indicators of an analog circuit include at least one of power consumption, power efficiency, signal-to-noise ratio (SNR), bandwidth, gain, slew rate, propagation delay, or settling time.

[0046] The types of performance indicators of a digital circuit include at least one of propagation delay, clock frequency, setup time, hold time, settling time, static power consumption, dynamic power consumption, noise margin, or area efficiency.

[0047] The value of a performance metric is a numerical representation of the performance metric.

[0048] Each of the circuit parameters refers to each of the design variable values ​​that determine the operation of each of the components of the circuit. The parameters include resistance, capacitance, inductance, voltage, current, power, MOSFET parameters (e.g., gate oxide thickness, channel length, and / or channel width), and BJT parameters (e.g., base width, emitter area, and / or collector thickness).

[0049] A termination condition (TC) defining a termination criterion for a program (130) that executes a Pareto set-based circuit parameter optimization algorithm (also simply called an 'optimization algorithm') may include a condition for terminating when a design is found in which all performance indicator target values ​​are achieved, and may include at least one of the following: a maximum number of optimization iterations that terminates when the optimization algorithm exceeds a preset number of iterations, a condition for terminating when the Pareto set is no longer updated or changes are minimal, or a condition for terminating when the execution time of the optimization algorithm exceeds a preset reference time.

[0050] A Pareto set generator (131) generates a Pareto set (PS) when reference designs (RC) are received through an input device (110). Since the Pareto set (PS) is used as an input to an artificial neural network including an actor network (133) and a critic network (137), the Pareto set (PS) must include one or more designs.

[0051] Here, the design is a vector of circuit parameters, and optimizing the parameters means the process of finding a vector that satisfies the target performance indicator value in the parameter vector space. Additionally, the design refers to a circuit in which the values ​​of each of the simulateable parameters are specified by the program (130).

[0052] A design can refer to a circuit in which the values ​​of each parameter of the components of the circuit topology (CP) are determined. A Pareto set can be defined as a set of designs with no worse performance metrics.

[0053] The Pareto set generator (131) determines whether reference designs (RC, also referred to as 'initial Pareto set candidate designs') are input into the input device (110) (S115).

[0054] When referenceable designs (RC) are input (YES of S115), the Pareto set generator (131) compares the design performance indicator values ​​of each referenceable design (RC) with one another, and, based on the comparison result, configures (or selects) the designs among the referenceable designs (RC) that have non-dominated performance indicator values ​​as the first Pareto set (S120). In this specification, the performance indicator value includes one or more performance indicator values.

[0055] A non-dominated performance metric means a design that is not inferior to any other design in terms of all performance metrics, and has a better value in at least one performance metric. In this specification, a performance metric may mean a performance metric value.

[0056] Therefore, a Pareto set is a set of designs with non-dominant performance metrics, and each design is better than other designs in the Pareto set in one or more performance metrics but worse in other performance metrics.

[0057] However, when reference designs (RC) are not input (NO of S115), the Pareto set generator (131) randomly sets parameter values ​​for each component of the circuit topology (CP) to generate designs (also referred to as 'Pareto set candidate designs'), calculates design performance indicator values ​​for each of the designs, and compares the calculated design performance indicator values ​​with each other to form a second Pareto set of designs that have non-dominant performance indicator values ​​among the designs (S125).

[0058] The first Pareto set and / or the second Pareto set are collectively referred to as the Pareto set (PS), and the initial Pareto set candidate designs and Pareto set candidate designs are collectively referred to as Pareto set candidate designs.

[0059] Each design included in the Pareto set (PS) and the performance metric values ​​of each design are considered as one token in the inputs of the actor network (simply called an actor. 133) and the critic network (simply called a critic. 137).

[0060] A design batch extractor (132) receives a Pareto set (PS), calculates a Figure of Merit (FoM, also referred to as the 'first FoM') for each of the designs included in the Pareto set (PS), extracts some or all of the designs from the designs included in the Pareto set (PS) using the FoM for each of the designs, and constructs a first design batch (BAT) containing the extracted designs (also referred to as the 'first designs') (S130). The search is performed on a design batch basis.

[0061] FoM is a metric that comprehensively evaluates performance indicators (e.g., power consumption, performance, and area), and is a method of evaluating circuit performance as a single value by utilizing the weighted average, ratio, or log transformation of performance indicator values.

[0062] The design batch extractor (132) can construct a design batch (BAT) by a weighted sum-based FoM, that is, by assigning (or giving) weights to each of the performance indicator values ​​and then linearly combining them (S130).

[0063] For example, the FoM of a low-power high-speed system that simultaneously considers performance indicators (e.g., high bandwidth and low power) can be calculated as 'bandwidth ÷ power', and the FoM of a high-gain low-power amplifier that simultaneously considers performance indicators (e.g., high gain and low power) can be 'gain ÷ power'.

[0064] For example, the design batch extractor (132) calculates FoM using performance indicator values ​​for each of a designs included in a Pareto set (PS), and may include b designs with a high FoM among the a designs, and c designs randomly selected from the remaining (ab) designs regardless of FoM. In this case, the design batch (BAT) includes (b+c) designs. Here, a, b, and c are each natural numbers, and for example, when a is 100, b is 20, and c is 20, the design batch (BAT) may include 40 designs.

[0065] The program (130) has the effect of preventing local optimization by considering randomly selected designs (e.g., c designs) while rapidly optimizing superior designs (e.g., b designs).

[0066] The actor network (133) can update the parameters of the actor network (133) using gradient descent so that the gain function (AF) calculated from the gain function calculator (138) is maximized. For example, when the actor network (133) is a neural network, the parameters of the neural network include weights and biases, and by adjusting the parameters, the actor network (133) can learn a design that maximizes the value of the gain function.

[0067] The actor network (133) receives a first design batch (BAT) and a Pareto set (PS), analyzes the parameter values ​​of each design to improve each design included in the first design batch (BAT) (e.g., to improve the first performance indicator value for each design), proposes a variation of each parameter value of each design according to the analysis results, and proposes an improved design batch (BAT'), i.e., a second design batch (BAT'), by adding the variation of each parameter value proposed for each design to each parameter value of each design (S135).

[0068] That is, the actor network (133) can change the parameter values ​​of each of the first designs using the amount of change in the proposed parameter values ​​for each of the first designs included in the first design batch (BAT), generate second designs having the changed parameter values, and propose a second design batch (BAT') including the second designs.

[0069] For example, when the parameter value of design A included in the first design batch (BAT) is x1 and the amount of change of said parameter is Δx1, the parameter value of said design A to be included in the second design batch (BAT') may be (x1+Δx1).

[0070] For example, when the actor network (133) is a transformer, the first design batch (BAT) may be a query given as the decoder input of the transformer, and the Pareto set (PS) may be a context given as the encoder input of the transformer. The actor network (133) may aim to search for designs capable of updating the Pareto set (PS) in the vicinity of each design of the first design batch (BAT).

[0071] For example, the parameter value of each design includes at least one of resistance, capacitance, inductance, voltage, or current.

[0072] The circuit simulator (134) receives a second design batch (BAT'), a circuit topology (CP), and a performance indicator type (PMT), analyzes each of the designs included in the second design batch (BAT') (also referred to as 'second designs') according to the circuit topology (CP), evaluates a performance indicator value (also referred to as 'third performance indicator value') corresponding to the performance indicator type (PMT) for each of the designs according to the analysis result, generates the evaluated performance indicator value (PM), and generates a count value (CNT) indicating the number of times Pareto set-based circuit parameter optimization has been performed (S140). For example, the circuit simulator (134) may be a SPICE (Simulation Program with Integrated Circuit Emphasis) simulator.

[0073] For example, when the performance indicator is power consumption, the circuit simulator (134) can calculate the amount of power consumed according to the operation of each design included in the second design batch (BAT'), and when the performance indicator is operation speed, the circuit simulator (134) can calculate the response time of each design included in the second design batch (BAT').

[0074] Accordingly, the circuit simulator (134) can analyze each design included in the second design batch (BAT') according to the circuit topology (CP).

[0075] The comparator (135) receives the performance indicator value (PM) and Pareto set (PS) of each design included in the second design batch (BAT'), compares the performance indicator value (PM) of each design with the performance indicator value of each design included in the Pareto set (PS), and generates a Pareto score (PSCR) for each design included in the second design batch (BAT') (S145).

[0076] For example, when the performance indicator value (PM) includes power consumption and response speed values, the power consumption value of each design included in the second design batch (BAT') is compared with the power consumption value of each design included in the Pareto set (PS), and the response speed value of each design included in the second design batch (BAT') is compared with the response speed value of each design included in the Pareto set (PS).

[0077] The Pareto score (PSCR) for each design included in the second design batch (BAT') is an indicator that evaluates how well each design included in the second design batch (BAT') meets the Pareto optimization criteria.

[0078] In other words, the Pareto Score (PSCR) indicates how superior each design included in the second design batch (BAT') is compared to other designs belonging to the Pareto set (PS). The Pareto Score (PSCR) evaluates relative superiority, and designs with relatively good performance indicator values ​​are assigned a high Pareto score. Conversely, designs with relatively low performance indicator values ​​are assigned a low Pareto score.

[0079] For example, if Design C and Design D are included in Design Batch 2 (BAT'), and Design C has lower power consumption and a faster operating speed than all designs included in the Pareto Set (PS), then its performance metrics are superior to all designs in the Pareto Set (PS). Additionally, if Design D has lower power consumption but a slower operating speed compared to the designs in the Pareto Set (PS), then its performance metrics are non-dominant. In this case, Design C is assigned a higher Pareto score than Design D.

[0080] The critique network learner (136) can perform an operation corresponding to Equation 1 and output the operation result (LR) to the critique network (137). For example, the operation result (LR) can update the parameters of the critique network (137) according to gradient descent to minimize the L2 loss of the performance indicator value (PM) for each design, the Pareto score (PSCR) for each design, the approximate performance indicator value (PM') for each design, and the approximate Pareto score (PSCR') for each design. When the critique network (137) is a neural network, the parameters of the neural network include weights and biases, and the critique network (137) can learn the operation result (LR) by adjusting the parameters.

[0081]

[0082] The critique network (137) can approximate the Pareto score (PSCR) and performance metric (PM) for each design included in the second design batch (BAT') through the computation result (LR) of the critique network learner (136).

[0083] The critique network (137) compares each of the approximate performance metric values ​​(PM') approximated to the performance metric (PM) with each of the performance metric values ​​of each design included in the Pareto set (PS), and generates an approximate Pareto score (PSCR') for each design included in the second design batch (BAT') based on the comparison result (S150).

[0084] The critique network (137) can approximate the second performance indicator value for each of the second designs to generate an approximate performance indicator value, and can generate an approximate Pareto score for each of the second designs.

[0085] The acquisition function calculator (138) receives a performance indicator target value (PMV), a performance indicator weight (WT), approximate performance indicator values ​​(PM1) for each design, and an approximate Pareto score (PSCR') for each design, generates a FoM for each design (also referred to as 'second FoM') by multiplying the difference between the approximate performance indicator value (PM1) and the performance indicator target value (PMV) for each design by the performance indicator weight (WT), calculates the sum of the FoM for each design and the approximate Pareto score (PSCR') for each design, and calculates an acquisition function (AF) corresponding to the sum (S155).

[0086] For example, the acquisition function calculator (138) can generate FoM(FoM(x)) for the x-th design according to mathematical formula 2.

[0087]

[0088] Here, when the number of performance metrics is n, w i represents the i-th performance metric weight among n performance metric weights, and f i represents the i-th performance metric value among n performance metric values, and f * i represents the i-th performance indicator target value among n performance indicator target values.

[0089] The actor network (133) receives an acquisition function (AF) and can update the parameters of the actor network (133) using gradient descent so that the value of the acquisition function (AF) is maximized (S160).

[0090] The updater (139) can update the Pareto set (PS) using the second design batch (BAT') output from the actor network (133) and the Pareto score (PSCR) for each design output from the comparator (135) (S165).

[0091] For example, when design a is included in each of the Pareto set (PS) and design batch (BAT) and design a is improved by the actor network (133), the design a included in the Pareto set (PS) can be replaced with the improved design a included in the second design batch (BAT') based on the Pareto score for the improved design a', the improved design a' can be added to the Pareto set (PS), or the design that is inferior to the improved design a' among the designs in the Pareto set (PS) can be removed (165).

[0092] The decision unit (140) can determine whether each of the performance indicator values ​​of each design included in the second design batch (BAT') output from the actor network (133) satisfies each of the performance indicator target values ​​(PMV) or whether the count value (CNT) output from the circuit simulator (134) is equal to the maximum number of iterations included in the termination condition (TC), and determine whether to terminate based on the result of the determination (S170).

[0093] For example, when each of the performance indicator values ​​of each design included in the second design batch (BAT') generated by the actor network (133) satisfies each of the performance indicator target values ​​(PMV), or when the count value (CNT) is equal to the maximum number of iterations included in the termination condition (TC), the decision unit (140) can terminate the Pareto set-based circuit parameter optimization method (S170).

[0094] When the Pareto set-based circuit parameter optimization method is terminated, the Pareto set updated in step (S165) can be saved as a file in the memory device (150) or output from the output device (170) (S175). The termination result can be used as a design (RC) to be referenced to explore parameters that achieve other target performance in the future.

[0095] When the target performance or target FoM of a circuit is given, the design to be used as a search standard can be determined by using a Pareto set based on a performance indicator composed of designs in which the performance indicator is evaluated by using a computing device (100) to determine the parameter values ​​of the circuit, and the direction of the search can be determined.

[0096] The present invention has been described with reference to embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims.

Claims

1. In a method for determining the parameter values ​​of a circuit using a computing device, A step of generating a Pareto set by comparing the design performance indicator values ​​of each of the Pareto set candidate designs with one another and extracting designs having non-dominant performance indicator values ​​from the Pareto set candidate designs based on the comparison result; and A method for determining circuit parameters using a computing device comprising the step of extracting first designs from the designs based on a first FoM (Figure of Merit) for each of the above designs and generating a first design batch including the first designs.

2. In Paragraph 1, A step of proposing a change in the parameter value of each of the first designs to improve the first performance indicator value of each of the first designs; A step of changing the parameter values ​​of each of the first designs using the amount of change in the parameter values ​​proposed for each of the first designs and generating second designs having the changed parameter values; and A method for determining circuit parameters using a computing device, further comprising the step of proposing a second design arrangement including the above second designs.

3. In Paragraph 2, A step of receiving the type of performance indicator and the circuit topology corresponding to the above circuit; A step of interpreting each of the above second designs according to the circuit topology; and A method for determining circuit parameters using a computing device, further comprising the step of calculating a third performance indicator value corresponding to the type of performance indicator for each of the second designs according to the interpretation result.

4. In Paragraph 3, A step of comparing the performance indicator value of each of the above designs with the third performance indicator value calculated for each of the above second designs; and A method for determining circuit parameters using a computing device, further comprising the step of calculating a Pareto score for each of the second designs based on a comparison result.

5. In Paragraph 4, A step of generating an approximate performance indicator value by approximating a second performance indicator value for each of the second designs using a critique network executed on the computing device; and A method for determining circuit parameters using a computing device that further includes the step of generating approximate Pareto scores for each of the second designs using the aforementioned critique network.

6. In Paragraph 5, A step of receiving performance indicator target values ​​and performance indicator weights; A step of calculating the difference between the above approximate performance indicator value and the above performance indicator target value; A step of calculating the second FoM by multiplying the above difference by the above performance indicator weights; and A method for determining circuit parameters using a computing device, further comprising the step of calculating an acquisition function corresponding to the sum of the second FoM and the approximate Pareto score.

7. In Paragraph 6, A step of updating parameters of an actor network running on the computing device that proposes the second design arrangement so as to maximize the above acquisition function; A step of updating the parameters of the critique network that perform the approximation to minimize the approximation error for the third performance indicator value and the Pareto score; and A method for determining circuit parameters using a computing device, further comprising the step of updating the Pareto set using the second design layout and the Pareto score.

8. A computer-readable program for performing a method of determining circuit parameters using the computing device described in paragraph 1.

9. A memory device storing a Pareto set-based circuit parameter determination program; and It includes a processor that executes the above Pareto set-based circuit parameter determination program, and The above processor is, A step of generating a Pareto set by comparing the design performance indicator values ​​of each of the Pareto set candidate designs with one another and extracting designs having non-dominant performance indicator values ​​from the Pareto set candidate designs based on the comparison result; and A computing device that performs the step of extracting first designs from the designs based on a first FoM (Figure of Merit) for each of the above designs and generating a first design batch including the first designs.

10. In paragraph 9, the processor, A step of proposing a change in the parameter value of each of the first designs to improve the first performance indicator value of each of the first designs; A step of changing the parameter values ​​of each of the first designs using the amount of change in the parameter values ​​proposed for each of the first designs and generating second designs having the changed parameter values; and A computing device that further performs the step of proposing a second design arrangement including the above second designs.

11. In Clause 10, the above processor, A step of receiving the type of performance indicator and the circuit topology corresponding to the above circuit; A step of interpreting each of the above second designs according to the circuit topology; and A computing device that further performs the step of calculating a third performance indicator value corresponding to the type of performance indicator for each of the second designs according to the interpretation result.

12. In paragraph 11, the above processor, A step of comparing the performance indicator value of each of the above designs with the third performance indicator value calculated for each of the above second designs; A step of calculating a Pareto score for each of the second designs based on the comparison results; A step of generating an approximate performance indicator value by approximating a second performance indicator value for each of the second designs using a critique network executed in the processor; and A computing device that further performs the step of generating approximate Pareto scores for each of the second designs using the above critique network.

13. In Clause 12, the above processor, A step of receiving performance indicator target values ​​and performance indicator weights; A step of calculating the difference between the above approximate performance indicator value and the above performance indicator target value; A step of calculating the second FoM by multiplying the above difference by the above performance indicator weights; and A computing device that further performs the step of calculating an acquisition function corresponding to the sum of the second FoM and the approximate Pareto score.

14. In Paragraph 13, the above processor, A step of updating parameters of an actor network executed in the processor that proposes the second design arrangement so as to maximize the above acquisition function; A step of updating the parameters of the critique network that perform the approximation to minimize the approximation error for the third performance indicator value and the Pareto score; and A computing device that further performs the step of updating the Pareto set using the second design layout and the Pareto score.

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