Real-time debugging of constrained randomization code

Abstract

This patent application discloses a computing system to simulate a circuit design describing an electronic device and a test bench having constrained randomization code. At a breakpoint in the simulation, the computing system can evaluate constraints associated with the constrained randomization code to detect conflicting constraints. The computing system can modify the test bench to resolve the detected conflict by enabling or disabling one or more of the constraints or a random mode of one or more variables for the constrained randomization code. The computing system also can identify and inject a missing variable value for the constrained randomization code, and identify and block an invalid variable value for the constrained randomization code. The computing system can exit the breakpoint to continue the simulation of the circuit design with the modified constraints in the test bench without recompiling the test bench and restarting the simulation of the circuit design with the recompiled test bench.

Description

202419814 REAL-TIME DEBUGGING OF CONSTRAINED RANDOMIZATION CODETECHNICAL FIELD

[0001] This application is generally related to electronic design automation and, more specifically, to real-time debugging of constrained randomization code.BACKGROUND

[0002] Designing and fabricating electronic systems typically involves many steps, known as a “design flow.” The particular steps of a design flow often are dependent upon the type of electronic system to be manufactured, its complexity, the design team, and the fabricator or foundry that will manufacture the electronic system from a design. Initially, a specification for a new electronic system can be transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the electronic system. With this logical design, the electronic system can be described in terms of both the exchange of signals between hardware registers and the logical operations that can be performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as SystemVerilog or Very high speed integrated circuit Hardware Design Language (VHDL).

[0003] The logic of the electronic system can be analyzed to confirm that it will accurately perform the functions desired for the electronic system, sometimes referred to as “functional verification.” Design verification tools can perform functional verification operations, such as simulating, emulating, and / or prototyping the logical design. For202419814 example, when a design verification tool simulates the logical design, the design verification tool can provide transactions or sets of test vectors, for example, generated by a simulated test bench, to the simulated logical design. The design verification tools can determine how the simulated logical design responded to the transactions or test vectors, and verify, from that response, that the logical design describes circuitry to accurately perform functions.

[0004] Many test benches can generate a diverse set of transactions or test vectors during the simulation using randomization code, for example, which allows random selection of values utilized in the test stimulus provided to the logical designs during simulation. Since the range of the random values capable of being selected typically includes both valid and invalid values for the simulated logical design, designers often write constraints to restrict the randomization to a range of valid values for the simulated logical design. These constraints on the randomization, when properly defined, can allow for an efficient and thorough simulation of the logical design. When improperly defined, however, the bugs in the constraints can often be difficult identify, for example, often performed through manual inspection of the constraints, the generated random values, and the logical design. After a bug in a constraint has been identified, the designers rewrite the constraint in the test bench, recompile the test bench and logical design, and then restart the simulation, which can be an iterative, time-consuming process.SUMMARY

[0005] This application discloses a computing system to simulate a circuit design describing an electronic device and a test bench having constrained randomization code. At a breakpoint in the simulation, the computing system can evaluate constraints associated202419814 with the constrained randomization code to detect conflicting constraints. The computing system can modify the test bench to resolve the detected conflict by enabling or disabling one or more of the constraints or a random mode of one or more variables for the constrained randomization code. The computing system also can identify and inject a missing variable value for the constrained randomization code, and identify and block an invalid variable value for the constrained randomization code. The computing system can exit the breakpoint to continue the simulation of the circuit design with the modified constraints in the test bench without recompiling the test bench and restarting the simulation of the circuit design with the recompiled test bench. Embodiments will be described in greater detail below.DESCRIPTION OF THE DRAWINGS

[0006] Figures 1 and 2 illustrate an example of a computer system of the type that may be used to implement various embodiments.

[0007] Figure 3 illustrates an example design verification system that implements realtime debugging of constrained randomization code according to various embodiments.

[0008] Figure 4 illustrates an example flowchart implementing real-time debugging of constrained randomization code, which may be implemented according to various embodiments.DETAILED DESCRIPTIONIllustrative Operating Environment202419814

[0009] Various embodiments may be implemented through the execution of software instructions by a computing device 101, such as a programmable computer. Accordingly, Figure 1 shows an illustrative example of a computing device 101. As seen in this figure, the computing device 101 includes a computing unit 103 with a processing unit 105 and a system memory 107. The processing unit 105 may be any type of programmable electronic device for executing software instructions, but will conventionally be a microprocessor. The system memory 107 may include both a read-only memory (ROM) 109 and a random access memory (RAM) 111. As will be appreciated by those of ordinary skill in the art, both the read-only memory (ROM) 109 and the random access memory (RAM) 111 may store software instructions for execution by the processing unit 105.

[0010] The processing unit 105 and the system memory 107 are connected, either directly or indirectly, through a bus 113 or alternate communication structure, to one or more peripheral devices 117-123. For example, the processing unit 105 or the system memory 107 may be directly or indirectly connected to one or more additional memory storage devices, such as a hard disk drive 117, which can be magnetic and / or removable, a removable optical disk drive 119, and / or a flash memory card. The processing unit 105 and the system memory 107 also may be directly or indirectly connected to one or more input devices 121 and one or more output devices 123. The input devices 121 may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices 123 may include, for example, a monitor display, a printer and speakers. With various examples of the computing device 101, one or more of the peripheral devices 117-123 may be internally housed with the computing unit 103. Alternately, one or more of the peripheral devices 117-123 may be202419814 external to the housing for the computing unit 103 and connected to the bus 113 through, for example, a Universal Serial Bus (USB) connection.

[0011] With some implementations, the computing unit 103 may be directly or indirectly connected to a network interface 115 for communicating with other devices making up a network. The network interface 115 can translate data and control signals from the computing unit 103 into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) and the Internet protocol (IP). Also, the network interface 115 may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art, and thus will not be discussed here in more detail.

[0012] It should be appreciated that the computing device 101 is illustrated as an example only, and it not intended to be limiting. Various embodiments may be implemented using one or more computing devices that include the components of the computing device 101 illustrated in Figure 1, which include only a subset of the components illustrated in Figure 1, or which include an alternate combination of components, including components that are not shown in Figure 1. For example, various embodiments may be implemented using a multi-processor computer, a plurality of single and / or multiprocessor computers arranged into a network, or some combination of both.

[0013] With some implementations, the processor unit 105 can have more than one processor core. Accordingly, Figure 2 illustrates an example of a multi-core processor unit 105 that may be employed with various embodiments. As seen in this figure, the processor202419814 unit 105 includes a plurality of processor cores 201A and 201B. Each processor core 201A and 201B includes a computing engine 203A and 203B, respectively, and a memory cache 205A and 205B, respectively. As known to those of ordinary skill in the art, a computing engine 203A and 203B can include logic devices for performing various computing functions, such as fetching software instructions and then performing the actions specified in the fetched instructions. These actions may include, for example, adding, subtracting, multiplying, and comparing numbers, performing logical operations such as AND, OR, NOR and XOR, and retrieving data. Each computing engine 203A and 203B may then use its corresponding memory cache 205A and 205B, respectively, to quickly store and retrieve data and / or instructions for execution.

[0014] Each processor core 201A and 201B is connected to an interconnect 207. The particular construction of the interconnect 207 may vary depending upon the architecture of the processor unit 105. With some processor cores 201A and 201B, such as the Cell microprocessor created by Sony Corporation, Toshiba Corporation and IBM Corporation, the interconnect 207 may be implemented as an interconnect bus. With other processor units 201A and 201B, however, such as the Opteron™ and Athlon™ dual-core processors available from Advanced Micro Devices of Sunnyvale, California, the interconnect 207 may be implemented as a system request interface device. In any case, the processor cores 201A and 201B communicate through the interconnect 207 with an input / output interface 209 and a memory controller 210. The input / output interface 209 provides a communication interface to the bus 113. Similarly, the memory controller 210 controls the exchange of information to the system memory 107. With some implementations, the processor unit 105 may include additional components, such as a high-level cache memory accessible shared by202419814 the processor cores 201A and 201B. It also should be appreciated that the description of the computer network illustrated in Figure 1 and Figure 2 is provided as an example only, and it not intended to suggest any limitation as to the scope of use or functionality of alternate embodiments.Real-Time Debugging of Constrained Randomization Code

[0015] Figure 3 illustrates an example design verification system 300 that implements realtime debugging of constrained randomization code according to various embodiments. Figure 4 illustrates an example flowchart implementing real-time debugging of constrained randomization code, which may be implemented according to various embodiments. Referring to Figures 3 and 4, the design verification system 300 can include a simulator 310, for example, capable of being implemented with computing system, such as a computer network 101 described above with reference to Figure 1, which can simulate operations of an electronic device described by a circuit design 301. The circuit design 301 can describe the electronic device both in terms of an exchange of data signals between components in the electronic device, such as hardware registers, flip-flops, combinational logic, or the like, and in terms of logical operations that can be performed on the data signals in the electronic device. The circuit design 301 can model the electronic device at a register transfer level (RTL), for example, with code in a hardware description language (HDL), such as SystemVerilog, Very high speed integrated circuit Hardware Design Language (VHDL), System C, or the like.

[0016] The simulator 310, in a block 401 of Figure 4, can simulate the circuit design 301 describing the electronic device and a test bench 302 having constrained randomization202419814 code. The simulator 310 can utilize the test bench 302 to generate test stimulus during functional verification operations, such as clock signals, activation signals, power signals, control signals, data signals or the like. The test stimulus, when grouped, may form test bench transactions capable of prompting operation of the circuit design 301 being functionally verified by the simulator 310. In some embodiments, the test bench 302 can be written in an object-oriented programming language, for example, System Verilog or the like, which, when executed during elaboration, can dynamically generate test bench components for verification of the circuit design. A methodology library, for example, a Universal Verification Methodology (UVM) library, an Open Verification Methodology (OVM) library, an Advanced Verification Methodology (AVM) library, a Verification Methodology Manual (VMM) library, or the like, can be utilized as a base for creating the test bench 302.

[0017] The test bench 302 can include constrained randomization code corresponding to one or more variables being simulated, which can allow the simulator 310 to insert a random value for the variables corresponding to the constrained randomization code. The constrained randomization code can include one or more constraints that define which values can be selected as a random value 311 for the utilization during the simulation. During simulation of the circuit design 301 and the test bench 302, the simulator 310 can make one or more randomization calls 303 to a random solving engine 320 of the design verification system 300, which can prompt a random value generation system 322 in the random solving engine 320 to randomly select a value for the variable based on the constraints of the constrained randomization code. In some embodiments, the simulator 310 can provide the constrained randomization code in the test bench 302 to the random202419814 value generation system 322, and the random value generation system 322 can randomly select the value for the variable in a value space having been defined by the constraints in the constrained randomization code. The random solving engine 320 can provide the randomly selected value to the simulator 310 as random values 311, which can allow the simulator 310 to set the variable to the randomly selected value during simulation. By introducing random variation in the variable values during simulation, designers can avoid invalid variable values and prompt excitation of functionality of the electronic device described in the circuit design 301 that would otherwise be difficult to cover.

[0018] The simulator 310 can record output created during functional verification of the circuit design 301 with stimulus from the test bench 302, often called simulation results 305. In some embodiments, the simulation results 305 can include a simulation model corresponding to the signal and value states of the simulated version of the circuit design 301 and the test bench 302.

[0019] At a breakpoint in the simulation, the design verification system 300 can stop simulating the circuit design 301 and the test bench 302 to perform various analysis procedures on the circuit design 301, test bench 302, and / or the simulation results 305. One of the analysis performed by the design verification system 300 can be to evaluate a current scope of constraints associated with the constrained randomization code of the test bench 302 to determine whether the constraints include any errors or bugs and, if so, to modify the constrained randomization code in the test bench 302 to resolve the errors or bugs. Typically, there can be several different types of constraint errors or bugs, such as conflicting constraints, overly-limiting constraints, overly-broad constraints, or the like.202419814 The design verification system 300 can perform operations to identify constraint errors and bugs and modify the constraints in the test bench 302 to resolve the errors or bugs in realtime, without having to recompile the circuit design 301 and test bench 302 and restart simulation from the beginning. After the design verification system 300 has modified the constraints to resolve the identified errors or bugs, the simulator 310 can exit the breakpoint and continue with the current simulation of the circuit design 301 and modified test bench 302. Embodiments of this constraint debugging process will be described below in greater detail.

[0020] The random solving engine 320 can include a conflict detection system 324 that, in a block 402 of Figure 4, can evaluate, at a breakpoint in the simulation, constraints associated with the constrained randomization code in the test bench 302 to detect at least one conflict between a plurality of the constraints. In some embodiments, the conflict detection system 324 can utilize formal techniques, for example, implemented in a computing system, to compare the constraints in the test bench 302 against each other to identify when a definition in one constraint conflicts with a definition in another constraint. The formal techniques can attempt to prove or disprove the constraints in the constrain randomization code of the test bench 302 can operate together or not, for example, utilizing a Boolean Satisfiability (SAT) Solver, or the like.

[0021] The design verification system 300 can include a visualization system 330 that can work with the random solving engine 320 to perform the debug operations on the constraints in the test bench 302. In a block 403 of Figure 4, when the conflict detection system 324 determines a conflict between constraints exists, execution proceeds to block202419814 404 of Figure 4, where the visualization system 330 can modify at least a portion of the test bench 302 associated with at least one of the plurality of the constraints to resolve the detected conflict. The visualization system 330 can include a constraint conflict resolution system 332 that can receive the detected conflicts 317 from the conflict detection system 324 in the random solving engine 320, which can identify which of the constraints in the test bench 302 conflict with each other. The constraint conflict resolution system 332 can modify the constraint in the test bench 302 to remove the constraint conflict in multiple ways. For example, the constraint conflict resolution system 332 can remove the conflict between constraints by enabling or disabling at least one of the conflicting constraint in the test bench 302 to resolve the detected conflict. In another example, the constraint conflict resolution system 332 can remove the conflict between constraints by enabling or disabling a random mode of one or more variables for the constrained randomization code in the test bench 302.

[0022] In some embodiments, the visualization system 330 can generate a constraint debug presentation 333, which can include the constraints in the test bench 302 and annunciate which of the constraints were determined by the conflict detection system 324 to be in conflict. The constraint debug presentation 333 also can include one or more selectable items, which can receive input regarding the removal of the conflicting constraint. For example, the constraint debug presentation 333 can include an item adjacent to a constraint that, when selected, indicates the constraint should be enabled or disabled, allowing users to modify constrained randomization code through selection in a graphical user interface. The constraint conflict resolution system 332, in response, to a selection in202419814 the constraint debug presentation 333 can perform the modification of the constraint in the test bench 302 to remove the constraint conflict.

[0023] After the conflicting constraints have been resolved, execution can return to the block 402 of Figure 4, where the conflict detection system 324 can evaluate the constrained randomization code as modified in block 404 of Figure 4, to determine whether any additional conflicting constraints exist. When the conflict detection system 324, in a block 403, determines an additional conflict between constraints exists, execution can proceed to the block 404, so the additional conflict can be resolved. This process can iterate between the conflict detection system 324 and the constraint conflict resolution system 332 until the conflict detection system 324 determines no conflict between the constraints exists in the block 403 of Figure 4.

[0024] When, in the block 403 of Figure 4, the conflict detection system 324 determines no conflict between constraints exists, execution proceeds to block 405 of Figure 4, where a value distribution system 334 in the visualization system 330 can build a distribution presentation including a plurality of random values for variables based on the constraints associated with the constrained randomization code. In some embodiments, the value distribution system 334 can make several randomization calls for a constraint to the random value generation system 322 and the random value generation system 322 can provide multiple constrained random values 315 to the value distribution system 334 associated with the constrained randomization code in the test bench 302. The value distribution system 334 can build the distribution presentation from the constrained random values 315 received from the random value generation system 322. The202419814 distribution presentation can annunciate at least one missing variable value or at least one invalid variable value in the plurality of the random values. In some embodiments, the distribution presentation can be a histogram or similar binning presentation that can annunciate the values and frequency within the set of the constrained random values 315. The visualization system 330, in some embodiments, can incorporate the distribution presentation in the constraint debug presentation for display to designers.

[0025] In a block 406 of Figure 4, when it has been determined that the distribution of random values includes an invalid variable value or a missing variable value, execution can proceed to a block 407 in Figure 4, where an injection system 336 in the visualization system 330 can modify a constraint in the test bench 302 to inject the missing variable value or to block the invalid variable value. In some embodiments, the visualization system 330 can include a selectable item or an entry field in the constraint debug presentation 333, which allows designers to input information capable of prompting the injection system 336 to modify the constraint in real-time. The modification of the constraint can broaden the previously defined variable value range to include a missing value or to narrow the previously defined variable value range to exclude an invalid value. Execution would then proceed back to the block 402 in Figure 4, where the conflict detection system 324 would perform a comparison of the modified constraints to detect any newly created conflicts caused by the modification of the constraints by the injection system 336.

[0026] The modification of a constraint in the test bench 302 to inject the missing variable value or to block the invalid variable value, in some embodiments, can be performed to force a conflict between the constraints that can be detected by the conflict detection system 324.202419814 In some instances, the presence of an invalid value or the fact that there is a missing value in the distribution of random values can be indicative of another constraint in the test bench 302 being written to allow the invalid value or to exclude the missing value. By injecting the missing variable value or blocking the invalid variable value, the conflict detection system 324 can identify a conflict with the other constraint, which can act as an annunciation of which constraint should be reviewed to determine whether it includes a bug or error. Put differently, the injection values can help the design verification system 300 locate constraints that potentially include errors or bugs, which can speed up the constraint debug process.

[0027] When, in the block 406 of Figure 4, when it has been determined that the distribution of random values does not include an invalid variable value or a missing variable value, execution can proceed to a block 408 in Figure 4, where the simulator 310 can exit the breakpoint to continue the simulation of the circuit design 301 with the modified constraints in the test bench 302. The simulator 310 can advance the simulation after the breakpoint without recompiling the test bench 302 and restarting the simulation of the circuit design 302 with the recompiled test bench.

[0028] The system and apparatus described above may use dedicated processor systems, micro controllers, programmable logic devices, microprocessors, or any combination thereof, to perform some or all of the operations described herein. Some of the operations described above may be implemented in software and other operations may be implemented in hardware. Any of the operations, processes, and / or methods described herein may be202419814 performed by an apparatus, a device, and / or a system substantially similar to those as described herein and with reference to the illustrated figures.

[0029] The processing device may execute instructions or "code" stored in memory. The memory may store data as well. The processing device may include, but may not be limited to, an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, or the like. The processing device may be part of an integrated control system or system manager, or may be provided as a portable electronic device configured to interface with a networked system either locally or remotely via wireless transmission.

[0030] The processor memory may be integrated together with the processing device, for example RAM or FLASH memory disposed within an integrated circuit microprocessor or the like. In other examples, the memory may comprise an independent device, such as an external disk drive, a storage array, a portable FLASH key fob, or the like. The memory and processing device may be operatively coupled together, or in communication with each other, for example by an I / O port, a network connection, or the like, and the processing device may read a file stored on the memory. Associated memory may be "read only" by design (ROM) by virtue of permission settings, or not. Other examples of memory may include, but may not be limited to, WORM, EPROM, EEPROM, FLASH, or the like, which may be implemented in solid state semiconductor devices. Other memories may comprise moving parts, such as a known rotating disk drive. All such memories may be "machine-readable" and may be readable by a processing device.202419814

[0031] Operating instructions or commands may be implemented or embodied in tangible forms of stored computer software (also known as "computer program" or "code"). Programs, or code, may be stored in a digital memory and may be read by the processing device. “Computer-readable storage medium" (or alternatively, "machine-readable storage medium") may include all of the foregoing types of memory, as well as new technologies of the future, as long as the memory may be capable of storing digital information in the nature of a computer program or other data, at least temporarily, and as long at the stored information may be "read" by an appropriate processing device. The term "computer-readable" may not be limited to the historical usage of "computer" to imply a complete mainframe, mini- computer, desktop or even laptop computer. Rather, "computer-readable" may comprise storage medium that may be readable by a processor, a processing device, or any computing system. Such media may be any available media that may be locally and / or remotely accessible by a computer or a processor, and may include volatile and non-volatile media, and removable and non- removable media, or any combination thereof.

[0032] A program stored in a computer-readable storage medium may comprise a computer program product. For example, a storage medium may be used as a convenient means to store or transport a computer program. For the sake of convenience, the operations may be described as various interconnected or coupled functional blocks or diagrams. However, there may be cases where these functional blocks or diagrams may be equivalently aggregated into a single logic device, program or operation with unclear boundaries.Conclusion202419814

[0033] While the application describes specific examples of carrying out embodiments, those skilled in the art will appreciate that there are numerous variations and permutations of the above described systems and techniques that fall within the spirit and scope of the invention as set forth in the appended claims. For example, while some of the specific terminology has been employed above to refer to electronic design automation processes, it should be appreciated that various examples may be implemented using any electronic system.

[0034] One of skill in the art will also recognize that the concepts taught herein can be tailored to a particular application in many other ways. In particular, those skilled in the art will recognize that the illustrated examples are but one of many alternative implementations that will become apparent upon reading this disclosure.

[0035] Although the specification may refer to “an”, “one”, “another”, or “some” example(s) in several locations, this does not necessarily mean that each such reference is to the same example(s), or that the feature only applies to a single example.

Claims

202419814CLAIMS1. A method comprising:simulating, by a computing system, a circuit design describing an electronic device and a test bench having constrained randomization code;at a breakpoint in the simulation, evaluating, by the computing system, constraints associated with the constrained randomization code in the test bench to detect at least one conflict between a plurality of the constraints;modifying, by the computing system, at least a portion of the test bench associated with at least one of the plurality of the constraints to resolve the detected conflict; and exiting, by the computing, the breakpoint to continue the simulation of the circuit design with the modified constraints in the test bench.

2. The method of claim 1, wherein modifying at least the portion of the test bench associated with at least one of the plurality of the constraints comprises enabling or disabling one or more of the constraints in the test bench to resolve the detected conflict.

3. The method of claim 1, wherein modifying at least the portion of the test bench associated with at least one of the plurality of the constraints comprises enabling or disabling a random mode of one or more variables for the constrained randomization code in the test bench to resolve the detected conflict.

4. The method of claim 1, further comprising:202419814 generating, by the computing system, a plurality of random values for variables based on the constraints associated with the constrained randomization code; and building, by the computing system, a distribution presentation including the generated random values for the variables, wherein the distribution presentation is configured to annunciate at least one missing variable value or at least one invalid variable value in the plurality of the random values.

5. The method of claim 4, further comprising modifying, by the computing system, at least the portion of the test bench associated with at least one of the plurality of the constraints to inject the missing variable value or to block the invalid variable value.

6. The method of claim 1, further comprising displaying, by the computing system, a constraint debug presentation that includes the plurality of the constraints corresponding to the detected conflict, wherein the constraint debug presentation includes one or more options to resolve the detected conflict, and wherein modifying the at least a portion of the test bench associated with at least one of the plurality of the constraints to resolve the detected conflict is performed in response to a selection of at least one of the options presented in the constraint debug presentation.

7. The method of claim 1, wherein exiting the breakpoint to continue the simulation of the circuit design with the modified constraints in the test bench is performed without recompiling the test bench and restarting the simulation of the circuit design with the recompiled test bench.2024198148. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:simulating a circuit design describing an electronic device and a test bench having constrained randomization code;at a breakpoint in the simulation, evaluating constraints associated with the constrained randomization code in the test bench to detect at least one conflict between a plurality of the constraints;modifying at least a portion of the test bench associated with at least one of the plurality of the constraints to resolve the detected conflict; andexiting the breakpoint to continue the simulation of the circuit design with the modified constraints in the test bench.

9. The apparatus of claim 8, wherein modifying at least the portion of the test bench associated with at least one of the plurality of the constraints comprises enabling or disabling one or more of the constraints in the test bench to resolve the detected conflict.

10. The apparatus of claim 8, wherein modifying at least the portion of the test bench associated with at least one of the plurality of the constraints comprises enabling or disabling a random mode of one or more variables for the constrained randomization code in the test bench to resolve the detected conflict.202419814 11. The apparatus of claim 8, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising:generating a plurality of random values for variables based on the constraints associated with the constrained randomization code; andbuilding a distribution presentation including the generated random values for the variables, wherein the distribution presentation is configured to annunciate at least one missing variable value or at least one invalid variable value in the plurality of the random values.

12. The apparatus of claim 11, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising modifying at least the portion of the test bench associated with at least one of the plurality of the constraints to inject the missing variable value or to block the invalid variable value.

13. The apparatus of claim 8, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising:displaying a constraint debug presentation that includes the plurality of the constraints corresponding to the detected conflict, wherein the constraint debug presentation includes one or more options to resolve the detected conflict; and modifying the at least a portion of the test bench associated with at least one of the plurality of the constraints to resolve the detected conflict in response to a selection of at least one of the options presented in the constraint debug presentation.202419814 14. The apparatus of claim 8, wherein exiting the breakpoint to continue the simulation of the circuit design with the modified constraints in the test bench is performed without recompiling the test bench and restarting the simulation of the circuit design with the recompiled test bench.

15. A system comprising:a memory system configured to store computer-executable instructions; and a computing system, in response to execution of the computer-executable instructions, is configured to:simulate a circuit design describing an electronic device and a test bench having constrained randomization code;at a breakpoint in the simulation, evaluate constraints associated with the constrained randomization code in the test bench to detect at least one conflict between a plurality of the constraints;modify at least a portion of the test bench associated with at least one of the plurality of the constraints to resolve the detected conflict; andexit the breakpoint to continue the simulation of the circuit design with the modified constraints in the test bench.

16. The system of claim 15, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to modify at least the portion of the test bench associated with at least one of the plurality of the constraints by enabling or disabling one or more of the constraints in the test bench to resolve the detected conflict.20241981417. The system of claim 15, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to modify at least the portion of the test bench associated with at least one of the plurality of the constraints by enabling or disabling a random mode of one or more variables for the constrained randomization code in the test bench to resolve the detected conflict.

18. The system of claim 15, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to:generate a plurality of random values for variables based on the constraints associated with the constrained randomization code;build a distribution presentation including the generated random values for the variables, wherein the distribution presentation is configured to annunciate at least one missing variable value or at least one invalid variable value in the plurality of the random values; andmodify at least the portion of the test bench associated with at least one of the plurality of the constraints to inject the missing variable value or to block the invalid variable value.

19. The system of claim 15, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to:202419814 display a constraint debug presentation that includes the plurality of the constraints corresponding to the detected conflict, wherein the constraint debug presentation includes one or more options to resolve the detected conflict; andmodify the at least a portion of the test bench associated with at least one of the plurality of the constraints to resolve the detected conflict in response to a selection of at least one of the options presented in the constraint debug presentation.

20. The system of claim 15, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to exit the breakpoint to continue the simulation of the circuit design with the modified constraints in the test bench without recompiling the test bench and restarting the simulation of the circuit design with the recompiled test bench.

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