Infrared-emitting diode chip with microlenses

Abstract

An infrared-emitting diode (IRED) assembly is provided that includes a substrate, a first set of semiconductor layers disposed on a frontside surface of the substrate, an active IRED structure disposed on the first set of semiconductor layers, a second set of semiconductor layers disposed on the active IRED structure, and a first reflective layer and through-contacts disposed on the second set of semiconductor layers, the through-contacts disposed in through-holes defined by opened portions in the first reflective layer. The IRED assembly further includes a second reflective layer disposed on the first reflective layer and the through-contacts. The IRED assembly emits infrared radiation generated by the active IRED structure in a primary backside outcoupling direction that passes through a modified portion of a backside surface of the substrate.

Description

VIIV181-24-GPTO-003-W001INFRARED-EMITTING DIODE CHIP WITH MICROLENSESFIELD OF DISCLOSURE

[0001] This application relates to the field of electronic components, and more specifically, to infrared-emitting diodes.BACKGROUND

[0002] Infrared-emitting diodes are used in a variety of applications and typically include a Gallium Arsenide (GaAs) active region and an internal reflective layer. However, these diodes typically require wire bonding, leading to increased package size and increased manufacturing complexity and costs.SUMMARY

[0003] An infrared-emitting diode (IRED) assembly is disclosed herein. The IRED assembly has both electrical contacts on one side of the chip and outcouples infrared (IR) radiation (e.g., having a peak wavelength equal to or greater than about 900 nanometers (nm)) through the other side of the chip, where the surface condition of the chip backside has been altered to modulate light outcoupling from the chip. In some aspects, this arrangement provides for wireless and solder-free mounting of both electrical contacts of the IRED assembly to a leadframe by a glueing technique. In some aspects, this arrangement further provides for decreased material usage, shrinkage of device size (e.g., chip and package shrinkage), and reduction of manufacturing costs. In some aspects, this arrangement further provides for beam shapes and emission patterns of IRED chips that can be modulated to diffuse or collimate light.

[0004] According to an aspect of the disclosure, an IRED assembly is provided. The IRED assembly includes a substrate having a frontside surface and a backside surface opposite the frontside surface. The backside surface of the substrate includes a modified portion, such as one or more monolithic microlenses (e.g., convex monolithic microlenses, concave monolithic microlenses), print-on lenses (e.g., collimator print-on lenses, diffuser print-on lenses), roughened portions, or combinations thereof. The IRED assembly further includes a first set of semiconductor layers disposed on the frontside surface of the substrate. The IRED assembly further includes an active infrared-emitting diode structure disposed on a first portion of the first set of semiconductor layers and configured to generate IR radiation. The IRED assembly further includes a second set of semiconductor layers disposed on the active infrared-emitting diode structure. The IRED assembly furtherVIIV181-24-OPTO-003-WO01includes a first reflective layer disposed on a first portion of the second set of semiconductor layers. The first reflective layer has opened portions defining through-holes. The IRED assembly further includes through-contacts disposed on the second set of semiconductor layers and in the through-holes defined by the opened portions of the first reflective layer. Each of the opened portions surrounds a respective one of the through-contacts. The IRED assembly further includes a first electrical contact comprising a second reflective layer disposed on a first portion of the first reflective layer and the through-contacts exposed by the opened portions of the first reflective layer. The through-contacts electrically connect the first electrical contact and the second set of semiconductor layers. The IRED assembly further includes a second electrical contact disposed on a second portion of the first set of semiconductor layers. The IRED assembly further is configured to emit the IR radiation in a primary backside outcoupling direction that passes through the modified portion of the backside surface of the substrate.

[0005] In some aspects, the IRED assembly further includes a mesa trench etched through the second set of semiconductor layers and the active infrared-emitting diode structure and into at least the second portion of the first set of semiconductor layers. The second electrical contact is disposed in the mesa trench and electrically connects to the first set of semiconductor layers.

[0006] In some aspects, the IRED assembly further includes a passivation layer disposed on a third portion of the first set of semiconductor layers disposed laterally between the first portion and the second portion of the first set of semiconductor layers. In some aspects, the passivation layer is further disposed on the second reflective layer. In some aspects, the passivation layer has a first opened portion disposed on a portion of a surface of the first electrical contact and defining a first electrical contact window allowing electrical access to the first electrical contact. In some aspects, the passivation layer has a second opened portion disposed on a portion of a surface of the second electrical contact and defining a second electrical contact window allowing electrical access to the second electrical contact.

[0007] According to another aspect of the disclosure, an IRED assembly is provided. The IRED assembly includes an epitaxial substrate having a frontside surface and a backside surface opposite the frontside surface. The backside surface of the epitaxial substrate includes a modified portion, such as one or more monolithic microlenses (e.g., convex monolithic microlenses, concave monolithic microlenses), print-on lenses (e.g., collimator print-on lenses, diffuser print-on lenses), roughened portions, or combinations thereof. The IRED assembly further includes a first set of semiconductorVIIV181-24-OPTO-003-WO01layers disposed on the frontside surface of the epitaxial substrate. The IRED assembly further includes an active infrared-emitting diode structure disposed on the first set of semiconductor layers and configured to generate IR radiation. The IRED assembly further includes a second set of semiconductor layers disposed on the active infrared-emitting diode structure. The IRED assembly further includes an insulating reflective layer disposed on the second set of semiconductor layers. The insulating reflective layer has opened portions defining through-holes. The IRED assembly further includes metallic vias (or, in some aspects, substantially-transparent conductive oxide vias) disposed on the second set of semiconductor layers and in the through-holes defined by the opened portions of the insulating reflective layer. Each of the opened portions surrounds a respective one of the metallic vias. The IRED assembly further includes a metallic reflective layer disposed on the insulating reflective layer and the metallic vias exposed by the opened portions of the insulating reflective layer. The metallic vias electrically connect the metallic reflective layer and the second set of semiconductor layers. The IRED assembly further includes a metallic electrical contact disposed on the first set of semiconductor layers and laterally separated from the active infrared-emitting diode structure by a portion of the first set of semiconductor layers. The IRED assembly further includes a passivation layer disposed on the metallic reflective layer, the metallic electrical contact, and the portion of the first set of semiconductor layers that laterally separates the metallic electrical contact and the active infrared-emitting diode structure. The passivation layer has a first opened portion disposed on a portion of a surface of the metallic reflective layer and defining a first electrical contact window allowing electrical access to the metallic reflective layer. The passivation layer further has a second opened portion disposed on a portion of a surface of the metallic electrical contact and defining a second electrical contact window allowing electrical access to the metallic electrical contact. The IRED assembly is configured to emit the IR radiation in a primary backside outcoupling direction that passes through the modified portion of the backside surface of the epitaxial substrate.

[0008] According to another aspect of the disclosure, a method of manufacturing an IRED assembly is provided. The method includes providing an epitaxial substrate having a frontside surface and a backside surface opposite the frontside surface. The method further includes forming a modified portion on the backside surface of the epitaxial substrate, such as one or more monolithic microlenses (e.g., convex monolithic microlenses, concave monolithic microlenses), print-on lenses (e.g., collimator print-on lenses, diffuser print-on lenses), roughened portions, or combinations thereof. The method further includes forming a first set of semiconductor layers on the frontside surface of theVIIV181-24-OPTO-003-WO01epitaxial substrate. The method further includes forming an active infrared-emitting diode structure on the first set of semiconductor layers. The method further includes forming a second set of semiconductor layers on the active infrared-emitting diode structure. The method further includes forming an insulating reflective layer on the second set of semiconductor layers, the insulating reflective layer having opened portions defining through-holes. The method further includes forming metallic vias on the second set of semiconductor layers and in the through-holes defined by the opened portions of the insulating reflective layer. Each of the opened portions surrounds a respective one of the metallic vias. The method further includes forming a metallic reflective layer on the insulating reflective layer and the metallic vias exposed by the opened portions of the insulating reflective layer. The metallic vias electrically connect the metallic reflective layer and the second set of semiconductor layers. The method further includes forming a metallic electrical contact on the first set of semiconductor layers. The metallic electrical contact is laterally separated from the active infrared-emitting diode structure by a portion of the first set of semiconductor layers. The method further includes forming a passivation layer on the metallic reflective layer, the metallic electrical contact, and the portion of the first set of semiconductor layers that laterally separates the metallic electrical contact and the active infrared-emitting diode structure. The method further includes forming a first opened portion in the passivation layer. The first opened portion is disposed on a portion of a surface of the metallic reflective layer and defines a first electrical contact window allowing electrical access to the metallic reflective layer. The method further includes forming a second opened portion in the passivation layer. The second opened portion is disposed on a portion of a surface of the metallic electrical contact and defines a second electrical contact window allowing electrical access to the metallic electrical contact. The IRED assembly is configured to emit IR radiation generated by the active infrared-emitting diode structure in a primary backside outcoupling direction that passes through the modified portion of the backside surface of the epitaxial substrate.

[0009] These and other objects and advantages of the present disclosure will be recognized by one skilled in the art after having read the following detailed description, which are illustrated in the various drawing figures.BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A more detailed understanding may be had from the following description, given by way of example in conjunction with the accompanying drawings wherein:VIIV181-24-GPTO-003-W001

[0011] FIG. 1 shows a schematic cross-sectional view of an example infraredemitting diode (IRED) assembly according to aspects of the disclosure;

[0012] FIG. 2 shows a schematic cross-sectional view of an example IRED assembly having a modified backside surface according to aspects of the disclosure;

[0013] FIG. 3 shows a schematic cross-sectional view of another example IRED assembly having a modified backside surface according to aspects of the disclosure;

[0014] FIG. 4 shows a schematic cross-sectional view of another example IRED assembly having a modified backside surface according to aspects of the disclosure;

[0015] FIGS. 5A, 5B, and 5C show schematic cross-sectional views of an example IRED assembly having a chip-level package according to aspects of the disclosure;

[0016] FIG. 6 shows a top view of an example IRED assembly according to aspects of the disclosure;

[0017] FIG. 7 shows a top view of another example IRED assembly according to aspects of the disclosure;

[0018] FIG. 8 shows a top view of another example IRED assembly according to aspects of the disclosure;

[0019] FIG. 9 shows a flow chart with an example of a process of forming an example IRED assembly according to aspects of the disclosure;

[0020] FIG. 10 shows a flow chart with an example of a process of forming an example IRED assembly having a modified backside surface according to aspects of the disclosure;

[0021] FIG. 11 shows a flow chart with an example of a process of forming an example IRED assembly having a chip-level package according to aspects of the disclosure.DETAILED DESCRIPTION

[0022] Reference will now be made in detail to various aspects and / or embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. While the disclosure will be described in conjunction with these aspects and / or embodiments, it is understood that they are not intended to limit the disclosure to these aspects and / or embodiments. On the contrary, the disclosure is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the disclosure as defined by the appended claims. Furthermore, in the following detailed description of the disclosure, numerous specific details are set forth in order to provide a thorough understanding of the disclosure. However, it will be recognized by one of ordinaryVIIV181-24-GPTO-003-W001skill in the art that the disclosure may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the disclosure.

[0023] Certain terminology is used in the following description for convenience only and is not limiting. The words “top” and “bottom” designate directions in the drawings to which reference is made. The words “a” and “one,” as used in the claims and in the corresponding portions of the specification, are defined as including one or more of the referenced item unless specifically stated otherwise. This terminology includes the words above specifically mentioned, derivatives thereof, and words of similar import. The phrase “at least one” followed by a list of two or more items, such as “A, B, or C,” means any individual one of A, B, or C, as well as any combination thereof. The phrase “consists of” as used in the claims and in the corresponding portions of the specification, is defined as including only the elements or materials specified following that phrase. The phrase “consists essentially of” as used in the claims and in the corresponding portions of the specification, is defined as including only the elements or materials specified following that phrase and those that do not materially affect the characteristics of the claimed disclosure. The terms “generally”, “about”, and the like refer to + / - 10% of a specified value unless otherwise noted. The term “completely” means substantially all of, or about 100.0% of. As used herein, dimensional and percentage values are to be understood as approximate and to have a tolerance of plus or minus about 10.0% of the disclosed value.

[0024] In one example, the disclosure relates to an infrared-emitting diode (IRED) semiconductor chip on aluminum gallium arsenide (AIGaAs)-technology where both electrodes are on the same chip side and light (e.g., infrared (IR) radiation having a peak wavelength of at least 900 nanometers (nm)) is outcoupled through the other chip side. In some aspects, this arrangement provides a wireless and solder-free mounting of both contact electrodes of IRED chips to leadframes by gluing techniques. For example, the device may be mounted by gluing (e.g., using silver glues) onto a leadframe and no more wire bonding is necessary by having two opened electrode areas laterally separated by at least 100 micrometers (pm). In some aspects, the disclosure relates to an IRED assembly that includes an epitaxial substrate made of GaAs, which acts as a transparent medium for light outcoupled at substrate backside. The IRED assembly further includes first and second sets of semiconductor layers (e.g., several layers at the n side, several layers at the p side, with an active layer in between) made of an arsenic (As)-based or phosphorus (P)-based lll-V semiconductor material such as GaAs, AIGaAs, or gallium phosphide (GaP) with an active layer region (ALR) in between. The first and second sets of As-basedVIIV181-24-OPTO-003-WO01or P-based semiconductor layers are fabricated (e.g., epitaxilally grown by an epitaxial technique such as liquid-phase epitaxy (LPE), molecular-beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), etc.) on the frontside of the substrate. The IRED assembly further includes a first insulating reflective layer on the second set of semiconductor layers made of silicon dioxide (S iC>2), magnesium flouride (MgF2, to include “MgFx” having any suitable magnesium-to-flourine ratio), silicon nitride (Si3N4, to include “SiN” having any suitable silicon-to-nitrogen ratio), or another suitable material. The first insulating reflective layer has a refractive index that is smaller than the refractive index of the second set of semiconductor layers. The IRED assembly further includes multiple layer openings distributed over the first insulating reflective layer filled with metallic vias (or, in some aspects, substantially-transparent conductive oxide vias) which make electric contact to the second set of semiconductor layers. The IRED assembly further includes a second reflective layer made of metal on the first insulating reflective layer, which connects the metallic vias and forms the first electrode of the IRED assembly. The IRED assembly further includes a mesa trench etched into the second set of semiconductor layers, the ALR, and the first set of semiconductor layers to open the first set of semiconductor layers. The IRED assembly further includes a second metallic electrode in the mesa trench making electric contact to the first set of semiconductor layers. The IRED assembly further includes a passivation / insulating layer comprising SiC>2, SisN4 (to include “SiN” having any suitable silicon-to-nitrogen ratio), any other suitable material, or a combination thereof to cover the first and second electrodes, the first and second sets of semiconductor layers, and the first and second reflective layers. The passivation layer has at least two openings allowing electric contact to the first and second electrodes by, for example, contact glue. In some aspects, the distance between the at least two openings is not smaller than 100 pm. In some aspects, the first and second electrodes, mesa trench, metallic vias, and first insulating reflective layer can have different layouts, while the first insulating reflective layer consumes at least 50% of the total chip area and the metallic vias consume 1-10% of the area of the first insulating reflective layer. In some aspects, the systems, devices, assemblies, methods, and techniques disclosed herein avoid wire bonding during mounting of the chip during assembly and thereby provide for shrinkage of device size and less material usage, leading to denser packaging and substantial cost saving and new applications.

[0025] In another example, the disclosure relates to an IRED semiconductor chip on AIGaAs-technology where both electrodes are on the same chip side and a surface condition of chip backside is altered to modulate light outcoupling from the chip. In someVIIV181-24-GPTO-003-W001aspects, this arrangement provides an altered chip backside through which light is outcoupled. For example, the surface condition of the backside of the substrate may be shaped to form one or multiple convex or concave monolithically-integrated microlenses or Fresnel lenses. Additionally or alternatively, a print-on lens may be transferred to the chip backside to act as a collimator or diffuser. Additionally or alternatively, the surface of the chip backside may be roughened. In some aspects, as a result, the beam shapes and emission patterns of these IRED chips can be modulated to diffuse or collimate light, and chip and package shrinkage can be realized. In some aspects, the systems, devices, assemblies, methods, and techniques disclosed herein provide for optimization and / or specific adjustment of emission patterns of IREDs to match application and package requirements.

[0026] In yet another example, the disclosure relates to a fully chip surface passivated IRED semiconductor chip on AIGaAs-technology, where both electrodes are on the same chip side and light is outcoupled through the other chip side. In some aspects, by full passivation with materials as nitrides or oxides, the disclosure provides for a chip level package protecting the chip from external influences and enabling new applications beyond typical package designs. For example, the IRED assembly may further include a second passivation / insulating layer (P2) comprising Aluminum oxide, SiN or other oxides, nitrides or fluorides and covering the chip backside, chip sidewalls and part of chip frontside. In some aspects, the systems, devices, assemblies, methods, and techniques disclosed herein provide for an emitter having reduced package size, leading to substantial cost savings and new applications.

[0027] FIG. 1 shows a schematic cross-sectional view of an example IRED assembly 100 according to aspects of the disclosure. As shown, the IRED assembly 100 includes a substrate 102 having a frontside surface 103a and a backside surface 103b opposite the frontside surface 103a. In some aspects, the substrate 102 may be an epitaxial substrate. In some aspects, the epitaxial substrate is a GaAs substrate.

[0028] As shown, the IRED assembly 100 further includes a first set of semiconductor layers 110 disposed on the frontside surface 103a of the substrate 102. In some aspects, the first set of semiconductor layers 110 includes a first As-based or P-based lll-V semiconductor material selected from the group consisting of GaAs, AIGaAs, GaP, aluminum gallium indium phosphide (AIGalnP), any other suitable material, or a combination thereof. As shown, the IRED assembly 100 further includes an active IRED structure 130 disposed on a first portion 112 of the first set of semiconductor layers 110 and configured to generate IR radiation (e.g., having a peak wavelength equal to or greaterVIIV181-24-GPTO-003-W001than about 900 nm). As shown, the IRED assembly 100 further includes a second set of semiconductor layers 120 disposed on the active IRED structure 130. In some aspects, the second set of semiconductor layers 120 includes a second As-based or P-based lll-V semiconductor material selected from the group consisting of GaAs, AIGaAs, GaP, AIGalnP, any other suitable material, or a combination thereof. In some aspects, the first As-based or P-based lll-V semiconductor material is the same as the second As-based or P-based lll-V semiconductor material. In other aspects, the first As-based or P-based III-V semiconductor material may be different from the second As-based or P-based lll-V semiconductor material.

[0029] As shown, the IRED assembly 100 further includes a first reflective layer 150 disposed on a first portion 122 of the second set of semiconductor layers 120. In some aspects, the first reflective layer 150 is an insulating reflective layer. In some aspects, the insulating reflective layer includes SiO2, MgF2, SisN4, a metal oxide, any other suitable material, or a combination thereof. As shown, the first reflective layer 150 has opened portions 152 defining through-holes. In some aspects, the IRED assembly 100 further includes through-contacts 140 disposed on the second set of semiconductor layers 120 and in the through-holes defined by the opened portions 152 of the first reflective layer 150. As shown, each of the opened portions 152 surrounds a respective one of the through-contacts 140. In some aspects, the through-contacts 140 are metallic vias. For example, the metallic vias may include gold (Au), any other suitable metallic material, or a combination thereof (e.g., alloys). In other aspects, the through-contacts 140 are substantially-transparent conductive oxide (TCO) vias. For example, the TCO vias may include zinc oxide (ZnO), indium tin oxide (ITO), any other suitable metallic material, or a combination thereof. In some aspects, as shown, a footprint of the first reflective layer 150 is at least fifty percent (50%) of a total footprint of the IRED assembly 100, and a total combined footprint of the through-contacts 140 is between one percent (1%) and ten percent (10%) of the footprint of the first reflective layer 150.

[0030] As shown, the IRED assembly 100 further includes a first electrical contact comprising a second reflective layer 160 disposed on a first portion 154 of the first reflective layer 150 and the through-contacts 140 exposed by the opened portions 152 of the first reflective layer 150. The through-contacts 140 electrically connect the second reflective layer 160 (e.g., which provides the first electrical contact) and the second set of semiconductor layers 120.

[0031] As shown, the IRED assembly 100 further includes a second electrical contact 170 disposed on a second portion 114 of the first set of semiconductor layers 110.VIIV181-24-OPTO-003-WO01In some aspects, the second reflective layer 160 is a metallic reflective layer. In some aspects, the metallic reflective layer comprises silver (Ag) or gold (Au). In some aspects, the second set of semiconductor layers 120 has a first refractive index value, and the first reflective layer 150 has a second refractive index value that is less than the first refractive index value. In some aspects, the IRED assembly 100 further includes a mesa trench etched through the second set of semiconductor layers 120 and the active IRED structure 130 and into the second portion 114 of the first set of semiconductor layers 110 (and, in some aspects, even into the substrate 102). In some aspects, the second electrical contact 170 is disposed in the mesa trench and electrically connects to the first set of semiconductor layers 110. In some aspects, the through-contacts 140 and the second electrical contact 170 consist of, or consist essentially of, gold (Au). Optionally, in some aspects, a metallic adhesion layer (e.g., a Titanium (Ti) thin film) may be disposed on the top surfaces of the second reflective layer 160, the second electrical contact 170, or both to provide for improved adhesion to the passivation layer 180. Optionally, in some aspects, one or more metallic adhesion layers (e.g., Ti thin films) may be disposed on the surfaces of the through-contacts 140 to provide for improved adhesion to the second reflective layer 160, the first reflective layer 150, the second set of semiconductor layers 120, or a combination thereof.

[0032] In some aspects, as shown, the IRED assembly 100 further includes a passivation layer 180 disposed on a third portion 116 of the first set of semiconductor layers 110, where the third portion 116 of the of the first set of semiconductor layers 110 is disposed laterally between the first portion 112 and the second portion 114 of the first set of semiconductor layers 110. Optionally, as shown, the passivation layer 180 is further disposed on a second portion 124 of the second set of semiconductor layers 120 disposed laterally adjacent to the first portion 122 of the second set of semiconductor layers 120. Optionally, as shown, the passivation layer 180 is further disposed on a second portion 156 of the first reflective layer 150 disposed laterally adjacent to the first portion 154 of the first reflective layer 150. As shown, the passivation layer 180 is further disposed on the second reflective layer 160. As shown, the passivation layer 180 has a first opened portion 185 (e.g., formed by the sidewalls of the second portion 184 and the third portion 186 of the passivation layer 180) disposed on a portion of the surface of the first electrical contact (e.g., the second reflective layer 160) and defining a first electrical contact window allowing electrical access to the first electrical contact. As shown, the passivation layer 180 has a second opened portion 183 (e.g., formed by the sidewalls of the first portion 182 and the second portion 184 of the passivation layer 180) disposed on a portion of the surface ofVIIV181-24-GPTO-003-W001the second electrical contact 170 and defining a second electrical contact window allowing electrical access to the second electrical contact 170. In some aspects, the passivation layer 180 includes SiC>2, Si3N4, any other suitable material, or a combination thereof. In some aspects, a lateral distance between the first opened portion 185 of the passivation layer 180 and the second opened portion 183 of the passivation layer 180 (e.g., the lateral width of the second portion 184 of the passivation layer 180) is greater than 100 pm.

[0033] In some aspects, the IRED assembly 100 further is configured to emit the IR radiation generated by the active IRED structure 130 in a primary backside outcoupling direction D that passes through the backside surface 103b of the substrate 102 (and, in some aspects, in one or more secondary outcoupling directions that pass through, for example, the sidewalls of the IRED assembly 100). As shown, the primary backside outcoupling direction D is non-parallel to the backside surface 103b of the substrate 102. For example, as shown, the primary backside outcoupling direction D may be orthogonal to the backside surface 103b of the substrate 102 (e.g., substantially parallel to a longitudinal axis of the IRED assembly 100 that passes through the frontside surface 103a and the backside surface 103b of the substrate 102).

[0034] FIG. 2 shows a schematic cross-sectional view of an example IRED assembly 200 having a modified backside surface according to aspects of the disclosure. As shown, the IRED assembly 200 includes a substrate 202 having a frontside surface 203a and a backside surface 203b opposite the frontside surface 203a. In some aspects, the substrate 202 may be an epitaxial substrate. In some aspects, the epitaxial substrate is a GaAs substrate. In some aspects, the backside surface 203b of the substrate 202 may include a modified portion through which IR radiation generated by the active IRED structure 230 is configured to pass. For example, the modified portion of the backside surface 203b of the substrate 202 may include at least one monolithic microlens, such as the first convex monolithic microlens 204 and the second convex monolithic microlens 206, formed on the backside surface 203b of the substrate 202, where the IR radiation emitted in the primary backside outcoupling direction D passes through the at least one monolithic microlens. Additionally or alternatively, the modified portion of the backside surface 203b of the substrate 202 may include at least one print-on lens, such as one or more collimator print-on lenses, affixed to the backside surface 203b of the substrate 202, where the IR radiation emitted in the primary backside outcoupling direction D passes through the at least one print-on lens.

[0035] As shown, the IRED assembly 200 further includes a first set of semiconductor layers 210 disposed on the frontside surface 203a of the substrate 202. InVIIV181-24-GPTO-003-W001some aspects, the first set of semiconductor layers 210 includes a first As-based or P-based lll-V semiconductor material selected from the group consisting of GaAs, AIGaAs, GaP, AIGalnP, any other suitable material, or a combination thereof. As shown, the IRED assembly 200 further includes an active IRED structure 230 disposed on a first portion 212 of the first set of semiconductor layers 210 and configured to generate IR radiation (e.g., having a peak wavelength equal to or greater than about 900 nm). As shown, the IRED assembly 200 further includes a second set of semiconductor layers 220 disposed on the active IRED structure 230. In some aspects, the second set of semiconductor layers 220 includes a second As-based or P-based lll-V semiconductor material selected from the group consisting of GaAs, AIGaAs, GaP, AIGalnP, any other suitable material, or a combination thereof. In some aspects, the first As-based or P-based lll-V semiconductor material is the same as the second As-based or P-based lll-V semiconductor material. In other aspects, the first As-based or P-based lll-V semiconductor material may be different from the second As-based or P-based lll-V semiconductor material.

[0036] As shown, the IRED assembly 200 further includes a first reflective layer 250 disposed on a first portion 222 of the second set of semiconductor layers 220. In some aspects, the first reflective layer 250 is an insulating reflective layer. In some aspects, the insulating reflective layer includes SiO2, MgF2, SisN4, a metal oxide, any other suitable material, or a combination thereof. As shown, the first reflective layer 250 has opened portions 252 defining through-holes. In some aspects, the IRED assembly 200 further includes through-contacts 240 disposed on the second set of semiconductor layers 220 and in the through-holes defined by the opened portions 252 of the first reflective layer 250. As shown, each of the opened portions 252 surrounds a respective one of the through-contacts 240. In some aspects, the through-contacts 240 are metallic vias. For example, the metallic vias may include Au, any other suitable metallic material, or a combination thereof (e.g., alloys). In other aspects, the through-contacts 240 are TCO vias. For example, the TCO vias may include ZnO, ITO, any other suitable metallic material, or a combination thereof. In some aspects, as shown, a footprint of the first reflective layer 250 is at least fifty percent (50%) of a total footprint of the IRED assembly 200, and a total combined footprint of the through-contacts 240 is between one percent (1 %) and ten percent (10%) of the footprint of the first reflective layer 250.

[0037] As shown, the IRED assembly 200 further includes a first electrical contact comprising a second reflective layer 260 disposed on a first portion 254 of the first reflective layer 250 and the through-contacts 240 exposed by the opened portions 252 of the first reflective layer 250. The through-contacts 240 electrically connect the secondVIIV181-24-OPTO-003-WO01reflective layer 260 (e.g., which provides the first electrical contact) and the second set of semiconductor layers 220.

[0038] As shown, the IRED assembly 200 further includes a second electrical contact 270 disposed on a second portion 214 of the first set of semiconductor layers 210. In some aspects, the second reflective layer 260 is a metallic reflective layer. In some aspects, the metallic reflective layer comprising Ag or Au. In some aspects, the second set of semiconductor layers 220 has a first refractive index value, and the first reflective layer 250 has a second refractive index value that is less than the first refractive index value. In some aspects, the IRED assembly 200 further includes a mesa trench etched through the second set of semiconductor layers 220 and the active IRED structure 230 and into the second portion 214 of the first set of semiconductor layers 210 (and, in some aspects, even into the substrate 202). In some aspects, the second electrical contact 270 is disposed in the mesa trench and electrically connects to the first set of semiconductor layers 210. In some aspects, the through-contacts 240 and the second electrical contact 270 consist of, or consist essentially of, Au. Optionally, in some aspects, a metallic adhesion layer (e.g., a Ti thin film) may be disposed on the top surfaces of the second reflective layer 260, the second electrical contact 270, or both to provide for improved adhesion to the passivation layer 280. Optionally, in some aspects, one or more metallic adhesion layers (e.g., Ti thin films) may be disposed on the surfaces of the through-contacts 240 to provide for improved adhesion to the second reflective layer 260, the first reflective layer 250, the second set of semiconductor layers 220, or a combination thereof.

[0039] In some aspects, as shown, the IRED assembly 200 further includes a passivation layer 280 disposed on a third portion 216 of the first set of semiconductor layers 210, where the third portion 216 of the of the first set of semiconductor layers 210 is disposed laterally between the first portion 212 and the second portion 214 of the first set of semiconductor layers 210. Optionally, as shown, the passivation layer 280 is further disposed on a second portion 224 of the second set of semiconductor layers 220 disposed laterally adjacent to the first portion 222 of the second set of semiconductor layers 220. Optionally, as shown, the passivation layer 280 is further disposed on a second portion 256 of the first reflective layer 250 disposed laterally adjacent to the first portion 254 of the first reflective layer 250. As shown, the passivation layer 280 is further disposed on the second reflective layer 260. As shown, the passivation layer 280 has a first opened portion 285 (e.g., formed by the sidewalls of the second portion 284 and the third portion 286 of the passivation layer 280) disposed on a portion of the surface of the first electrical contact (e.g., the second reflective layer 260) and defining a first electrical contact window allowingVIIV181-24-GPTO-003-W001electrical access to the first electrical contact. As shown, the passivation layer 280 has a second opened portion 283 (e.g., formed by the sidewalls of the first portion 282 and the second portion 284 of the passivation layer 280) disposed on a portion of the surface of the second electrical contact 270 and defining a second electrical contact window allowing electrical access to the second electrical contact 270. In some aspects, the passivation layer 280 includes SiC>2, Si3N4, any other suitable material, or a combination thereof. In some aspects, a lateral distance between the first opened portion 285 of the passivation layer 280 and the second opened portion 283 of the passivation layer 280 (e.g., the lateral width of the second portion 284 of the passivation layer 280) is greater than 100 pm.

[0040] In some aspects, the IRED assembly 200 further is configured to emit the IR radiation generated by the active IRED structure 230 in a primary backside outcoupling direction D that passes through the modified portion (e.g., the first convex monolithic microlens 204 and the second convex monolithic microlens 206) of the backside surface 203b of the substrate 202 (and, in some aspects, in one or more secondary outcoupling directions that pass through, for example, the sidewalls of the IRED assembly 200). As shown, the primary backside outcoupling direction D is non-parallel to the backside surface 203b of the substrate 202. For example, as shown, the primary backside outcoupling direction D may be orthogonal to the backside surface 203b of the substrate 202 (e.g., substantially parallel to a longitudinal axis of the IRED assembly 200 that passes through the frontside surface 203a and the backside surface 203b of the substrate 202). In some aspects, the modified portion of the backside surface 203b of the substrate 202 is formed to have one or more convex microlenses (e.g., the first convex monolithic microlens 204 and the second convex monolithic microlens 206) by (i) forming one or more convex lens shapes in a resist layer (e.g., including thicker and thinner parts) disposed on the backside surface 203b of the substrate 202, and (ii) dry etching (e.g., by Argon-based ion etching, reactive ion etching (RIE), etc.) through the resist layer to copy substantially the one or more convex lens shapes formed in the resist layer into the substrate 202 (e.g., a GaAs substrate).

[0041] FIG. 3 shows a schematic cross-sectional view of an example IRED assembly 300 having a modified backside surface according to aspects of the disclosure. As shown, the IRED assembly 300 includes a substrate 302 having a frontside surface 303a and a backside surface 303b opposite the frontside surface 303a. In some aspects, the substrate 302 may be an epitaxial substrate. In some aspects, the epitaxial substrate is a GaAs substrate. In some aspects, the backside surface 303b of the substrate 302 may include a modified portion through which IR radiation generated by the active IREDVIIV181-24-GPTO-003-W001structure 330 is configured to pass. For example, the modified portion of the backside surface 303b of the substrate 302 may include at least one monolithic microlens, such as the first concave monolithic microlens 304 and the second concave monolithic microlens 306, formed on the backside surface 303b of the substrate 302, where the IR radiation emitted in the primary backside outcoupling direction D passes through the at least one monolithic microlens. Additionally or alternatively, the modified portion of the backside surface 303b of the substrate 302 may include at least one print-on lens, such as one or more diffuser print-on lenses, affixed to the backside surface 303b of the substrate 302, where the IR radiation emitted in the primary backside outcoupling direction D passes through the at least one print-on lens.

[0042] As shown, the IRED assembly 300 further includes a first set of semiconductor layers 310 disposed on the frontside surface 303a of the substrate 302. In some aspects, the first set of semiconductor layers 310 includes a first As-based or P-based lll-V semiconductor material selected from the group consisting of GaAs, AIGaAs, GaP, AIGalnP, any other suitable material, or a combination thereof. As shown, the IRED assembly 300 further includes an active IRED structure 330 disposed on a first portion 312 of the first set of semiconductor layers 310 and configured to generate IR radiation (e.g., having a peak wavelength equal to or greater than about 900 nm). As shown, the IRED assembly 300 further includes a second set of semiconductor layers 320 disposed on the active IRED structure 330. In some aspects, the second set of semiconductor layers 320 includes a second As-based or P-based lll-V semiconductor material selected from the group consisting of GaAs, AIGaAs, GaP, AIGalnP, any other suitable material, or a combination thereof. In some aspects, the first As-based or P-based lll-V semiconductor material is the same as the second As-based or P-based lll-V semiconductor material. In other aspects, the first As-based or P-based lll-V semiconductor material may be different from the second As-based or P-based lll-V semiconductor material.

[0043] As shown, the IRED assembly 300 further includes a first reflective layer 350 disposed on a first portion 322 of the second set of semiconductor layers 320. In some aspects, the first reflective layer 350 is an insulating reflective layer. In some aspects, the insulating reflective layer includes SiO2, MgF2, SisN4, a metal oxide, any other suitable material, or a combination thereof. As shown, the first reflective layer 350 has opened portions 352 defining through-holes. In some aspects, the IRED assembly 300 further includes through-contacts 340 disposed on the second set of semiconductor layers 320 and in the through-holes defined by the opened portions 352 of the first reflective layer 350. As shown, each of the opened portions 352 surrounds a respective one of theVIIV181-24-OPTO-003-WO01through-contacts 340. In some aspects, the through-contacts 340 are metallic vias. For example, the metallic vias may include Au, any other suitable metallic material, or a combination thereof (e.g., alloys). In other aspects, the through-contacts 340 are TCO vias. For example, the TCO vias may include ZnO, ITO, any other suitable metallic material, or a combination thereof. In some aspects, as shown, a footprint of the first reflective layer 350 is at least fifty percent (50%) of a total footprint of the IRED assembly 300, and a total combined footprint of the through-contacts 340 is between one percent (1 %) and ten percent (10%) of the footprint of the first reflective layer 350.

[0044] As shown, the IRED assembly 300 further includes a first electrical contact comprising a second reflective layer 360 disposed on a first portion 354 of the first reflective layer 350 and the through-contacts 340 exposed by the opened portions 352 of the first reflective layer 350. The through-contacts 340 electrically connect the second reflective layer 360 (e.g., which provides the first electrical contact) and the second set of semiconductor layers 320.

[0045] As shown, the IRED assembly 300 further includes a second electrical contact 370 disposed on a second portion 314 of the first set of semiconductor layers 310. In some aspects, the second reflective layer 360 is a metallic reflective layer. In some aspects, the metallic reflective layer comprising silver (Ag). In some aspects, the second set of semiconductor layers 320 has a first refractive index value, and the first reflective layer 350 has a second refractive index value that is less than the first refractive index value. In some aspects, the IRED assembly 300 further includes a mesa trench etched through the second set of semiconductor layers 320 and the active IRED structure 330 and into the second portion 314 of the first set of semiconductor layers 310 (and, in some aspects, even into the substrate 302). In some aspects, the second electrical contact 370 is disposed in the mesa trench and electrically connects to the first set of semiconductor layers 310. In some aspects, the through-contacts 340 and the second electrical contact 370 consist of, or consist essentially of, Au. Optionally, in some aspects, a metallic adhesion layer (e.g., a Ti thin film) may be disposed on the top surfaces of the second reflective layer 360, the second electrical contact 370, or both to provide for improved adhesion to the passivation layer 380. Optionally, in some aspects, one or more metallic adhesion layers (e.g., Ti thin films) may be disposed on the surfaces of the through-contacts 340 to provide for improved adhesion to the second reflective layer 360, the first reflective layer 350, the second set of semiconductor layers 320, or a combination thereof.

[0046] In some aspects, as shown, the IRED assembly 300 further includes a passivation layer 380 disposed on a third portion 316 of the first set of semiconductorVIIV181-24-OPTO-003-WO01layers 310, where the third portion 316 of the of the first set of semiconductor layers 310 is disposed laterally between the first portion 312 and the second portion 314 of the first set of semiconductor layers 310. Optionally, as shown, the passivation layer 380 is further disposed on a second portion 324 of the second set of semiconductor layers 320 disposed laterally adjacent to the first portion 322 of the second set of semiconductor layers 320. Optionally, as shown, the passivation layer 380 is further disposed on a second portion 356 of the first reflective layer 350 disposed laterally adjacent to the first portion 354 of the first reflective layer 350. As shown, the passivation layer 380 is further disposed on the second reflective layer 360. As shown, the passivation layer 380 has a first opened portion 385 (e.g., formed by the sidewalls of the second portion 384 and the third portion 386 of the passivation layer 380) disposed on a portion of the surface of the first electrical contact (e.g., the second reflective layer 360) and defining a first electrical contact window allowing electrical access to the first electrical contact. As shown, the passivation layer 380 has a second opened portion 383 (e.g., formed by the sidewalls of the first portion 382 and the second portion 384 of the passivation layer 380) disposed on a portion of the surface of the second electrical contact 370 and defining a second electrical contact window allowing electrical access to the second electrical contact 370. In some aspects, the passivation layer 380 includes SiC>2, Si3N4, any other suitable material, or a combination thereof. In some aspects, a lateral distance between the first opened portion 385 of the passivation layer 380 and the second opened portion 383 of the passivation layer 380 (e.g., the lateral width of the second portion 384 of the passivation layer 380) is greater than 100 pm.

[0047] In some aspects, the IRED assembly 300 further is configured to emit the IR radiation generated by the active IRED structure 330 in a primary backside outcoupling direction D that passes through the modified portion (e.g., the first concave monolithic microlens 304 and the second concave monolithic microlens 306) of the backside surface 303b of the substrate 302 (and, in some aspects, in one or more secondary outcoupling directions that pass through, for example, the sidewalls of the IRED assembly 300). As shown, the primary backside outcoupling direction D is non-parallel to the backside surface 303b of the substrate 302. For example, as shown, the primary backside outcoupling direction D may be orthogonal to the backside surface 303b of the substrate 302 (e.g., substantially parallel to a longitudinal axis of the IRED assembly 300 that passes through the frontside surface 303a and the backside surface 303b of the substrate 302). In some aspects, the modified portion of the backside surface 303b of the substrate 302 is formed to have one or more concave microlenses (e.g., the first concave monolithic microlens 304 and the second concave monolithic microlens 306) by (i) forming one or more concaveVIIV181-24-GPTO-003-W001lens shapes in a resist layer (e.g., including thicker and thinner parts) disposed on the backside surface 303b of the substrate 302, and (ii) dry etching (e.g., by Argon-based ion etching, reactive ion etching (RIE), etc.) through the resist layer to copy substantially the one or more concave lens shapes formed in the resist layer into the substrate 302 (e.g., a GaAs substrate).

[0048] FIG. 4 shows a schematic cross-sectional view of an example IRED assembly 400 having a modified backside surface according to aspects of the disclosure. As shown, the IRED assembly 400 includes a substrate 402 having a frontside surface 403a and a backside surface 403b opposite the frontside surface 403a. In some aspects, the substrate 402 may be an epitaxial substrate. In some aspects, the epitaxial substrate is a GaAs substrate. In some aspects, the backside surface 403b of the substrate 402 may include a modified portion through which IR radiation generated by the active IRED structure 430 is configured to pass. For example, the modified portion of the backside surface 403b of the substrate 402 may include at least one roughened portion, such as the roughened portion 404, formed on the backside surface 403b of the substrate 402, where the IR radiation emitted in the primary backside outcoupling direction D passes through the at least one roughened portion.

[0049] As shown, the IRED assembly 400 further includes a first set of semiconductor layers 410 disposed on the frontside surface 403a of the substrate 402. In some aspects, the first set of semiconductor layers 410 includes a first As-based or P-based lll-V semiconductor material selected from the group consisting of GaAs, AIGaAs, GaP, AIGalnP, any other suitable material, or a combination thereof. As shown, the IRED assembly 400 further includes an active IRED structure 430 disposed on a first portion 412 of the first set of semiconductor layers 410 and configured to generate IR radiation (e.g., having a peak wavelength equal to or greater than about 900 nm). As shown, the IRED assembly 400 further includes a second set of semiconductor layers 420 disposed on the active IRED structure 430. In some aspects, the second set of semiconductor layers 420 includes a second As-based or P-based lll-V semiconductor material selected from the group consisting of GaAs, AIGaAs, GaP, AIGalnP, any other suitable material, or a combination thereof. In some aspects, the first As-based or P-based lll-V semiconductor material is the same as the second As-based or P-based lll-V semiconductor material. In other aspects, the first As-based or P-based lll-V semiconductor material may be different from the second As-based or P-based lll-V semiconductor material.

[0050] As shown, the IRED assembly 400 further includes a first reflective layer 450 disposed on a first portion 422 of the second set of semiconductor layers 420. In someVIIV181-24-OPTO-003-WO01aspects, the first reflective layer 450 is an insulating reflective layer. In some aspects, the insulating reflective layer includes SiC>2, MgF2, SisN4, a metal oxide, any other suitable material, or a combination thereof. As shown, the first reflective layer 450 has opened portions 452 defining through-holes. In some aspects, the IRED assembly 400 further includes through-contacts 440 disposed on the second set of semiconductor layers 420 and in the through-holes defined by the opened portions 452 of the first reflective layer 450. As shown, each of the opened portions 452 surrounds a respective one of the through-contacts 440. In some aspects, the through-contacts 440 are metallic vias. For example, the metallic vias may include Au, any other suitable metallic material, or a combination thereof (e.g., alloys). In other aspects, the through-contacts 440 are TCO vias. For example, the TCO vias may include ZnO, ITO, any other suitable metallic material, or a combination thereof. In some aspects, as shown, a footprint of the first reflective layer 450 is at least fifty percent (50%) of a total footprint of the IRED assembly 400, and a total combined footprint of the through-contacts 440 is between one percent (1 %) and ten percent (10%) of the footprint of the first reflective layer 450.

[0051] As shown, the IRED assembly 400 further includes a first electrical contact comprising a second reflective layer 460 disposed on a first portion 454 of the first reflective layer 450 and the through-contacts 440 exposed by the opened portions 452 of the first reflective layer 450. The through-contacts 440 electrically connect the second reflective layer 460 (e.g., which provides the first electrical contact) and the second set of semiconductor layers 420.

[0052] As shown, the IRED assembly 400 further includes a second electrical contact 470 disposed on a second portion 414 of the first set of semiconductor layers 410. In some aspects, the second reflective layer 460 is a metallic reflective layer. In some aspects, the metallic reflective layer comprising silver (Ag). In some aspects, the second set of semiconductor layers 420 has a first refractive index value, and the first reflective layer 450 has a second refractive index value that is less than the first refractive index value. In some aspects, the IRED assembly 400 further includes a mesa trench etched through the second set of semiconductor layers 420 and the active IRED structure 430 and into the second portion 414 of the first set of semiconductor layers 410 (and, in some aspects, even into the substrate 402). In some aspects, the second electrical contact 470 is disposed in the mesa trench and electrically connects to the first set of semiconductor layers 410. In some aspects, the through-contacts 440 and the second electrical contact 470 consist of, or consist essentially of, Au. Optionally, in some aspects, a metallic adhesion layer (e.g., a Ti thin film) may be disposed on the top surfaces of the secondVIIV181-24-OPTO-003-WO01reflective layer 460, the second electrical contact 470, or both to provide for improved adhesion to the passivation layer 480. Optionally, in some aspects, one or more metallic adhesion layers (e.g., a Ti thin films) may be disposed on the surfaces of the through-contacts 440 to provide for improved adhesion to the second reflective layer 460, the first reflective layer 450, the second set of semiconductor layers 420, or a combination thereof.

[0053] In some aspects, as shown, the IRED assembly 400 further includes a passivation layer 480 disposed on a third portion 416 of the first set of semiconductor layers 410, where the third portion 416 of the of the first set of semiconductor layers 410 is disposed laterally between the first portion 412 and the second portion 414 of the first set of semiconductor layers 410. Optionally, as shown, the passivation layer 480 is further disposed on a second portion 424 of the second set of semiconductor layers 420 disposed laterally adjacent to the first portion 422 of the second set of semiconductor layers 420. Optionally, as shown, the passivation layer 480 is further disposed on a second portion 456 of the first reflective layer 450 disposed laterally adjacent to the first portion 454 of the first reflective layer 450. As shown, the passivation layer 480 is further disposed on the second reflective layer 460. As shown, the passivation layer 480 has a first opened portion 485 (e.g., formed by the sidewalls of the second portion 484 and the third portion 486 of the passivation layer 480) disposed on a portion of the surface of the first electrical contact (e.g., the second reflective layer 460) and defining a first electrical contact window allowing electrical access to the first electrical contact. As shown, the passivation layer 480 has a second opened portion 483 (e.g., formed by the sidewalls of the first portion 482 and the second portion 484 of the passivation layer 480) disposed on a portion of the surface of the second electrical contact 470 and defining a second electrical contact window allowing electrical access to the second electrical contact 470. In some aspects, the passivation layer 480 includes SiC>2, Si3N4, any other suitable material, or a combination thereof. In some aspects, a lateral distance between the first opened portion 485 of the passivation layer 480 and the second opened portion 483 of the passivation layer 480 (e.g., the lateral width of the second portion 484 of the passivation layer 480) is greater than 100 pm.

[0054] In some aspects, the IRED assembly 400 further is configured to emit the IR radiation generated by the active IRED structure 430 in a primary backside outcoupling direction D that passes through the modified portion (e.g., the roughened portion 404) of the backside surface 403b of the substrate 402 (and, in some aspects, in one or more secondary outcoupling directions that pass through, for example, the sidewalls of the IRED assembly 400). As shown, the primary backside outcoupling direction D is non-parallel to the backside surface 403b of the substrate 402. For example, as shown, the primaryVIIV181-24-GPTO-003-W001backside outcoupling direction D may be orthogonal to the backside surface 403b of the substrate 402 (e.g., substantially parallel to a longitudinal axis of the IRED assembly 400 that passes through the frontside surface 403a and the backside surface 403b of the substrate 402). In some aspects, the modified portion of the backside surface 403b of the substrate 402 (e.g., a GaAs substrate) is formed to have one or more roughened portions (e.g., the roughened portion 404) by wet etching (e.g., using nitric acid) the backside surface 403b of the substrate 402 (e.g., the entire backside surface, or a portion of the backside surface using a mask) and, in some aspects, the sidewalls of the IRED assembly 400 as well to form roughened sidewalls.

[0055] FIG. 5A shows a schematic cross-sectional view of an example IRED assembly 500 having a chip-level package according to aspects of the disclosure. As shown, the IRED assembly 500 includes a substrate 502 having a frontside surface 503a and a backside surface 503b opposite the frontside surface 503a. As shown, the substrate 502 further includes sidewall surfaces 503c formed after a dicing of the substrate 502. In some aspects, the substrate 502 may be an epitaxial substrate. In some aspects, the epitaxial substrate is a GaAs substrate.

[0056] As shown, the IRED assembly 500 further includes a first set of semiconductor layers 510 disposed on the frontside surface 503a of the substrate 502. In some aspects, the first set of semiconductor layers 510 includes a first As-based or P-based lll-V semiconductor material selected from the group consisting of GaAs, AIGaAs, GaP, AIGalnP, any other suitable material, or a combination thereof. As shown, the IRED assembly 500 further includes an active IRED structure 530 disposed on a first portion 512 of the first set of semiconductor layers 510 and configured to generate IR radiation (e.g., having a peak wavelength equal to or greater than about 900 nm). As shown, the IRED assembly 500 further includes a second set of semiconductor layers 520 disposed on the active IRED structure 530. In some aspects, the second set of semiconductor layers 520 includes a second As-based or P-based lll-V semiconductor material selected from the group consisting of GaAs, AIGaAs, GaP, AIGalnP, any other suitable material, or a combination thereof. In some aspects, the first As-based or P-based lll-V semiconductor material is the same as the second As-based or P-based lll-V semiconductor material. In other aspects, the first As-based or P-based lll-V semiconductor material may be different from the second As-based or P-based lll-V semiconductor material.

[0057] As shown, the IRED assembly 500 further includes a first reflective layer 550 disposed on a first portion 522 of the second set of semiconductor layers 520. In some aspects, the first reflective layer 550 is an insulating reflective layer. In some aspects, theVIIV181-24-OPTO-003-WO01insulating reflective layer includes SiC>2, MgF2, Si3N4, a metal oxide, any other suitable material, or a combination thereof. As shown, the first reflective layer 550 has opened portions 552 defining through-holes. In some aspects, the IRED assembly 500 further includes through-contacts 540 disposed on the second set of semiconductor layers 520 and in the through-holes defined by the opened portions 552 of the first reflective layer 550. As shown, each of the opened portions 552 surrounds a respective one of the through-contacts 540. In some aspects, the through-contacts 540 are metallic vias. For example, the metallic vias may include Au, any other suitable metallic material, or a combination thereof (e.g., alloys). In other aspects, the through-contacts 540 are TCO vias. For example, the TCO vias may include ZnO, ITO, any other suitable metallic material, or a combination thereof. In some aspects, as shown, a footprint of the first reflective layer 550 is at least fifty percent (50%) of a total footprint of the IRED assembly 500, and a total combined footprint of the through-contacts 540 is between one percent (1 %) and ten percent (10%) of the footprint of the first reflective layer 550.

[0058] As shown, the IRED assembly 500 further includes a first electrical contact comprising a second reflective layer 560 disposed on a first portion 554 of the first reflective layer 550 and the through-contacts 540 exposed by the opened portions 552 of the first reflective layer 550. The through-contacts 540 electrically connect the second reflective layer 560 (e.g., which provides the first electrical contact) and the second set of semiconductor layers 520.

[0059] As shown, the IRED assembly 500 further includes a second electrical contact 570 disposed on a second portion 514 of the first set of semiconductor layers 510. In some aspects, the second reflective layer 560 is a metallic reflective layer. In some aspects, the metallic reflective layer comprising silver (Ag). In some aspects, the second set of semiconductor layers 520 has a first refractive index value, and the first reflective layer 550 has a second refractive index value that is less than the first refractive index value. In some aspects, the IRED assembly 500 further includes a mesa trench etched through the second set of semiconductor layers 520 and the active IRED structure 530 and into the second portion 514 of the first set of semiconductor layers 510 (and, in some aspects, even into the substrate 502). In some aspects, the second electrical contact 570 is disposed in the mesa trench and electrically connects to the first set of semiconductor layers 510. In some aspects, the through-contacts 540 and the second electrical contact 570 consist of, or consist essentially of, Au. Optionally, in some aspects, a metallic adhesion layer (e.g., a Ti thin film) may be disposed on the top surfaces of the second reflective layer 560, the second electrical contact 570, or both to provide for improvedVIIV181-24-OPTO-003-WO01adhesion to the first passivation layer 580. Optionally, in some aspects, one or more metallic adhesion layers (e.g., Ti thin films) may be disposed on the surfaces of the through-contacts 540 to provide for improved adhesion to the second reflective layer 560, the first reflective layer 550, the second set of semiconductor layers 520, or a combination thereof.

[0060] In some aspects, as shown, the IRED assembly 500 further includes a first passivation layer 580 disposed on a third portion 516 of the first set of semiconductor layers 510, where the third portion 516 of the of the first set of semiconductor layers 510 is disposed laterally between the first portion 512 and the second portion 514 of the first set of semiconductor layers 510. Optionally, as shown, the first passivation layer 580 is further disposed on a second portion 524 of the second set of semiconductor layers 520 disposed laterally adjacent to the first portion 522 of the second set of semiconductor layers 520. Optionally, as shown, the first passivation layer 580 is further disposed on a second portion 556 of the first reflective layer 550 disposed laterally adjacent to the first portion 554 of the first reflective layer 550. As shown, the first passivation layer 580 is further disposed on the second reflective layer 560. As shown, the first passivation layer 580 has a first opened portion 585 (e.g., formed by the sidewalls of the second portion 584 and the third portion 586 of the first passivation layer 580) disposed on a portion of the surface of the first electrical contact (e.g., the second reflective layer 560) and defining a first electrical contact window allowing electrical access to the first electrical contact. As shown, the first passivation layer 580 has a second opened portion 583 (e.g., formed by the sidewalls of the first portion 582 and the second portion 584 of the first passivation layer 580) disposed on a portion of the surface of the second electrical contact 570 and defining a second electrical contact window allowing electrical access to the second electrical contact 570. In some aspects, the first passivation layer 580 includes SiC>2, Si3N4, any other suitable material, or a combination thereof. In some aspects, a lateral distance between the first opened portion 585 of the first passivation layer 580 and the second opened portion 583 of the first passivation layer 580 (e.g., the lateral width of the second portion 584 of the first passivation layer 580) is greater than 100 pm.

[0061] As shown, the IRED assembly 500 further includes a second passivation layer 590 disposed on the backside surface 503b of the substrate 502, the sidewall surfaces 503c of the substrate 502, and a portion of the first set of semiconductor layers 510 disposed on the frontside surface 503a of the substrate 502, wherein the second passivation layer 590 is in contact with the first passivation layer 580. In some aspects, the second passivation layer 590 may be formed to overlap at least a portion of the firstVIIV181-24-GPTO-003-W001passivation layer 580. For example, as shown in FIG. 5B, the second passivation layer 590 may be formed to have an overlap section 592 with at least a portion 588 of the first passivation layer 580. In another example, as shown in FIG. 5C, the second passivation layer 590 may be formed to have an overlap section 593 with at least a portion 589 of the first passivation layer 580. In some aspects, the second passivation layer 590 includes aluminum oxide (AI2O3), SisN4 (to include “SiN” having any suitable silicon-to-nitrogen ratio), any other suitable material, or a combination thereof. In some aspects, as shown, the IRED assembly 500 is fully chip-surface passivated by the combination of the first passivation layer 580 and the second passivation layer 590.

[0062] In some aspects, the IRED assembly 500 further is configured to emit the IR radiation generated by the active IRED structure 530 in a primary backside outcoupling direction D that passes through the backside surface 503b of the substrate 502 and the second passivation layer 590 disposed on the backside surface 503b of the substrate 502 (and, in some aspects, in one or more secondary outcoupling directions that pass through, for example, the sidewalls of the IRED assembly 400). As shown, the primary backside outcoupling direction D is non-parallel to the backside surface 503b of the substrate 502. For example, as shown, the primary backside outcoupling direction D may be orthogonal to the backside surface 503b of the substrate 502 (e.g., substantially parallel to a longitudinal axis of the IRED assembly 500 that passes through the frontside surface 503a and the backside surface 503b of the substrate 502).

[0063] FIG. 6 shows a top view of an example IRED assembly 600 according to aspects of the disclosure. The example IRED assembly 600 may include any combination of structures and features described herein. For example, the top view of the example IRED assembly 600 shown in FIG. 6 may correspond to the top view of any of the example IRED assemblies 100, 200, 300, 400, and 500 shown in FIGS. 1-5.

[0064] The IRED assembly 600 includes a substrate, a first set of semiconductor layers disposed on a frontside surface of the substrate, and an active IRED structure disposed on a first portion of the first set of semiconductor layers. As shown, the IRED assembly 600 further includes a second set of semiconductor layers 620 disposed on the active IRED structure, a first reflective layer 650 disposed on a first portion of the second set of semiconductor layers 620 and having opened portions 652 defining through-holes, and through-contacts 640 disposed on the second set of semiconductor layers 620 and in the through-holes defined by the opened portions 652 of the first reflective layer 650. As shown, each of the opened portions 652 surrounds a respective one of the through-contacts 640.VIIV181-24-GPTO-003-W001

[0065] As shown, the IRED assembly 600 further includes a second reflective layer 660 disposed on a first portion of the first reflective layer 650 and the through-contacts 640 exposed by the opened portions 652 of the first reflective layer 650. The through-contacts 640 electrically connect the second reflective layer 660 and the second set of semiconductor layers 620. As shown, the IRED assembly 600 further includes a mesa trench 692 etched through the second set of semiconductor layers 620 and the active IRED structure and into a second portion of the first set of semiconductor layers (and, in some aspects, even into the substrate). As a result of the mesa etching being deep enough to open at least the first set of semiconductor layers, either the opened portion of the first set of semiconductor layers or the opened portion of the substrate may be visible in the opened portion formed by the mesa trench 692 in the top view of the example IRED assembly 600 shown in FIG. 6. As shown, the IRED assembly 600 further includes a second electrical contact 670 disposed in the mesa trench 692 and on the second portion of the first set of semiconductor layers, where the second electrical contact 670 electrically connects to the first set of semiconductor layers.

[0066] As shown, the IRED assembly 600 further includes a passivation layer 680 disposed on a third portion of the first set of semiconductor layers disposed laterally between the first portion and the second portion of the first set of semiconductor layers. As shown, the passivation layer 680 is further disposed on the second reflective layer 660. As shown, the passivation layer 680 has a first opened portion 685 disposed on a portion of the surface of the second reflective layer 660 and defining a first electrical contact window allowing electrical access to the second reflective layer 660 to form a first electrical contact. As shown, the passivation layer 680 has a second opened portion 683 disposed on a portion of the surface of the second electrical contact 670 and defining a second electrical contact window allowing electrical access to the second electrical contact 670. In some aspects, a lateral distance between the first opened portion 685 of the passivation layer 680 and the second opened portion 683 of the passivation layer 680 is greater than 100 pm.

[0067] FIG. 7 shows a top view of an example IRED assembly 700 according to aspects of the disclosure. The example IRED assembly 700 may include any combination of structures and features described herein. For example, the top view of the example IRED assembly 700 shown in FIG. 7 may correspond to the top view of any of the example IRED assemblies 100, 200, 300, 400, and 500 shown in FIGS. 1-5.

[0068] The IRED assembly 700 includes a substrate, a first set of semiconductor layers disposed on a frontside surface of the substrate, and an active IRED structureVIIV181-24-OPTO-003-WO01disposed on a first portion of the first set of semiconductor layers. As shown, the IRED assembly 700 further includes a second set of semiconductor layers 720 disposed on the active IRED structure, a first reflective layer 750 disposed on a first portion of the second set of semiconductor layers 720 and having opened portions 752 defining through-holes, and through-contacts 740 disposed on the second set of semiconductor layers 720 and in the through-holes defined by the opened portions 752 of the first reflective layer 750. As shown, each of the opened portions 752 surrounds a respective one of the through-contacts 740.

[0069] As shown, the IRED assembly 700 further includes a second reflective layer 760 disposed on a first portion of the first reflective layer 750 and the through-contacts 740 exposed by the opened portions 752 of the first reflective layer 750. The through-contacts 740 electrically connect the second reflective layer 760 and the second set of semiconductor layers 720. As shown, the IRED assembly 700 further includes a mesa trench 792 etched through the second set of semiconductor layers 720 and the active IRED structure and into a second portion of the first set of semiconductor layers (and, in some aspects, even into the substrate). As a result of the mesa etching being deep enough to open at least the first set of semiconductor layers, either the opened portion of the first set of semiconductor layers or the opened portion of the substrate may be visible in the opened portion formed by the mesa trench 792 in the top view of the example IRED assembly 700 shown in FIG. 7. As shown, the IRED assembly 700 further includes a second electrical contact 770 disposed in the mesa trench 792 and on the second portion of the first set of semiconductor layers, where the second electrical contact 770 electrically connects to the first set of semiconductor layers.

[0070] As shown, the IRED assembly 700 further includes a passivation layer 780 disposed on a third portion of the first set of semiconductor layers disposed laterally between the first portion and the second portion of the first set of semiconductor layers. As shown, the passivation layer 780 is further disposed on the second reflective layer 760. As shown, the passivation layer 780 has a first opened portion 785 disposed on a portion of the surface of the second reflective layer 760 and defining a first electrical contact window allowing electrical access to the second reflective layer 760 to form a first electrical contact. As shown, the passivation layer 780 has a second opened portion 783 disposed on a portion of the surface of the second electrical contact 770 and defining a second electrical contact window allowing electrical access to the second electrical contact 770. In some aspects, a lateral distance between the first opened portion 785 of the passivationVIIV181-24-GPTO-003-W001layer 780 and the second opened portion 783 of the passivation layer 780 is greater than 100 pm.

[0071] FIG. 8 shows a top view of an example IRED assembly 800 according to aspects of the disclosure. The example IRED assembly 800 may include any combination of structures and features described herein. For example, the top view of the example IRED assembly 800 shown in FIG. 8 may correspond to the top view of any of the example IRED assemblies 100, 200, 300, 400, and 500 shown in FIGS. 1-5.

[0072] The IRED assembly 800 includes a substrate, a first set of semiconductor layers disposed on a frontside surface of the substrate, and an active IRED structure disposed on a first portion of the first set of semiconductor layers. As shown, the IRED assembly 800 further includes a second set of semiconductor layers 820 disposed on the active IRED structure, a first reflective layer 850 disposed on a first portion of the second set of semiconductor layers 820 and having opened portions 852 defining through-holes, and through-contacts 840 disposed on the second set of semiconductor layers 820 and in the through-holes defined by the opened portions 852 of the first reflective layer 850. As shown, each of the opened portions 852 surrounds a respective one of the through-contacts 840.

[0073] As shown, the IRED assembly 800 further includes a second reflective layer 860 disposed on a first portion of the first reflective layer 850 and the through-contacts 840 exposed by the opened portions 852 of the first reflective layer 850. The through-contacts 840 electrically connect the second reflective layer 860 and the second set of semiconductor layers 820. As shown, the IRED assembly 800 further includes a mesa trench 892 etched through the second set of semiconductor layers 820 and the active IRED structure and into a second portion of the first set of semiconductor layers (and, in some aspects, even into the substrate). As a result of the mesa etching being deep enough to open at least the first set of semiconductor layers, either the opened portion of the first set of semiconductor layers or the opened portion of the substrate may be visible in the opened portion formed by the mesa trench 892 in the top view of the example IRED assembly 800 shown in FIG. 8. As shown, the IRED assembly 800 further includes a second electrical contact 870 disposed in the mesa trench 892 and on the second portion of the first set of semiconductor layers, where the second electrical contact 870 electrically connects to the first set of semiconductor layers.

[0074] As shown, the IRED assembly 800 further includes a passivation layer 880 disposed on a third portion of the first set of semiconductor layers disposed laterally between the first portion and the second portion of the first set of semiconductor layers.VIIV181-24-GPTO-003-W001As shown, the passivation layer 880 is further disposed on the second reflective layer 860. As shown, the passivation layer 880 has a first opened portion 885 disposed on a portion of the surface of the second reflective layer 860 and defining a first electrical contact window allowing electrical access to the second reflective layer 860 to form a first electrical contact. As shown, the passivation layer 880 has a second opened portion 883 disposed on a portion of the surface of the second electrical contact 870 and defining a second electrical contact window allowing electrical access to the second electrical contact 870. In some aspects, a lateral distance between the first opened portion 885 of the passivation layer 880 and the second opened portion 883 of the passivation layer 880 is greater than 100 pm.

[0075] FIG. 9 is an example method 900 for forming or manufacturing an IRED assembly (e.g., IRED assembly 100) according to some aspects of the present disclosure or portion(s) thereof. The operations described with reference to example method 900 can be performed by, or according to, any of the systems, apparatuses, components, techniques, or combinations thereof described herein, such as those described with reference to FIG. 1 above. It is noted that one or more steps may be combined, that certain steps may be omitted, and that the steps may be performed in any preferred order as desired.

[0076] In some aspects, at optional step 902, the method 900 includes providing an epitaxial substrate (e.g., substrate 102) having a frontside surface (e.g., frontside surface 103a) and a backside surface (e.g., backside surface 103b) opposite the frontside surface.

[0077] At step 904, the method 900 includes forming a first set of semiconductor layers (e.g., first set of semiconductor layers 110) on the frontside surface of the epitaxial substrate.

[0078] At step 906, the method 900 further includes forming an active IRED structure (e.g., active IRED structure 130) on the first set of semiconductor layers.

[0079] At step 908, the method 900 further includes forming a second set of semiconductor layers (e.g., second set of semiconductor layers 120) on the active IRED structure.

[0080] At step 910, the method 900 further includes forming an insulating reflective layer (e.g., first reflective layer 150) on the second set of semiconductor layers, the insulating reflective layer having opened portions (e.g., opened portions 152) defining through-holes.

[0081] At step 912, the method 900 further includes forming metallic or TCO vias (e.g., through-contacts 140) on the second set of semiconductor layers and in the through-VIIV181-24-OPTG-003-W001holes defined by the opened portions of the insulating reflective layer. Each of the opened portions surrounds a respective one of the metallic or TCO vias.

[0082] At step 914, the method 900 further includes forming a metallic reflective layer (e.g., second reflective layer 160) on the insulating reflective layer and the metallic or TCO vias exposed by the opened portions of the insulating reflective layer. The metallic or TCO vias electrically connect the metallic reflective layer and the second set of semiconductor layers.

[0083] At step 916, the method 900 further includes forming a metallic electrical contact (e.g., second electrical contact 170) on the first set of semiconductor layers. The metallic electrical contact is laterally separated from the active IRED structure by a portion (e.g., third portion 116) of the first set of semiconductor layers. In some aspects, the forming of the metallic electrical contact includes etching a mesa trench through the second set of semiconductor layers and the active IRED structure and into the first set of semiconductor layers, and forming the metallic electrical contact in the mesa trench and in electrical contact with the first set of semiconductor layers.

[0084] At step 918, the method 900 further includes forming a passivation layer (e.g., passivation layer 180) on the metallic reflective layer, the metallic electrical contact, and the portion (e.g., third portion 116) of the first set of semiconductor layers that laterally separates the metallic electrical contact and the active IRED structure.

[0085] At step 920, the method 900 further includes forming a first opened portion (e.g., first opened portion 185) in the passivation layer. The first opened portion is disposed on a portion of the surface of the metallic reflective layer and defines a first electrical contact window allowing electrical access to the metallic reflective layer.

[0086] At step 922, the method 900 further includes forming a second opened portion (e.g., second opened portion 183) in the passivation layer. The second opened portion is disposed on a portion of the surface of the metallic electrical contact and defines a second electrical contact window allowing electrical access to the metallic electrical contact.

[0087] In some aspects, the IRED assembly manufactured according to method 900 is configured to emit IR radiation generated by the active IRED structure in a backside outcoupling direction (e.g., primary backside outcoupling direction D) that passes through the backside surface of the epitaxial substrate.

[0088] FIG. 10 is an example method 1000 for forming or manufacturing an IRED assembly (e.g., IRED assembly 200, 300, 400) according to some aspects of the present disclosure or portion(s) thereof. The operations described with reference to exampleVIIV181-24-GPTO-003-W001method 1000 can be performed by, or according to, any of the systems, apparatuses, components, techniques, or combinations thereof described herein, such as those described with reference to FIGS. 2-4 above. It is noted that one or more steps may be combined, that certain steps may be omitted, and that the steps may be performed in any preferred order as desired.

[0089] At step 1002, the method 1000 includes providing an epitaxial substrate (e.g., substrate 202) having a frontside surface (e.g., frontside surface 203a) and a backside surface (e.g., backside surface 203b) opposite the frontside surface.

[0090] At step 1004, the method 1000 includes forming a first set of semiconductor layers (e.g., first set of semiconductor layers 210) on the frontside surface of the epitaxial substrate.

[0091] At step 1006, the method 1000 further includes forming an active IRED structure (e.g., active IRED structure 230) on the first set of semiconductor layers.

[0092] At step 1008, the method 1000 further includes forming a second set of semiconductor layers (e.g., second set of semiconductor layers 220) on the active IRED structure.

[0093] At step 1010, the method 1000 further includes forming an insulating reflective layer (e.g., first reflective layer 250) on the second set of semiconductor layers, the insulating reflective layer having opened portions (e.g., opened portions 252) defining through-holes.

[0094] At step 1012, the method 1000 further includes forming metallic or TCO vias (e.g., through-contacts 240) on the second set of semiconductor layers and in the through-holes defined by the opened portions of the insulating reflective layer. Each of the opened portions surrounds a respective one of the metallic or TCO vias.

[0095] At step 1014, the method 1000 further includes forming a metallic reflective layer (e.g., second reflective layer 260) on the insulating reflective layer and the metallic or TCO vias exposed by the opened portions of the insulating reflective layer. The metallic or TCO vias electrically connect the metallic reflective layer and the second set of semiconductor layers.

[0096] At step 1016, the method 1000 further includes forming a metallic electrical contact (e.g., second electrical contact 270) on the first set of semiconductor layers. The metallic electrical contact is laterally separated from the active IRED structure by a portion (e.g., third portion 216) of the first set of semiconductor layers. In some aspects, the forming of the metallic electrical contact includes etching a mesa trench through the second set of semiconductor layers and the active IRED structure and into the first set ofVIIV181-24-OPTO-003-WO01semiconductor layers, and forming the metallic electrical contact in the mesa trench and in electrical contact with the first set of semiconductor layers.

[0097] At step 1018, the method 1000 further includes forming a passivation layer (e.g., passivation layer 280) on the metallic reflective layer, the metallic electrical contact, and the portion (e.g., third portion 216) of the first set of semiconductor layers that laterally separates the metallic electrical contact and the active IRED structure.

[0098] At step 1020, the method 1000 further includes forming a first opened portion (e.g., first opened portion 285) in the passivation layer. The first opened portion is disposed on a portion of the surface of the metallic reflective layer and defines a first electrical contact window allowing electrical access to the metallic reflective layer.

[0099] At step 1022, the method 1000 further includes forming a second opened portion (e.g., second opened portion 283) in the passivation layer. The second opened portion is disposed on a portion of the surface of the metallic electrical contact and defines a second electrical contact window allowing electrical access to the metallic electrical contact.

[0100] At step 1024, the method 1000 includes forming a modified portion on the backside surface of the epitaxial substrate. In some aspects, the forming of the modified portion on the backside surface of the epitaxial substrate includes forming at least one monolithic microlens (e.g., first convex monolithic microlens 204, second convex monolithic microlens 206, first concave monolithic microlens 304, second concave monolithic microlens 306) on the backside surface of the epitaxial substrate, where the infrared radiation emitted in the backside outcoupling direction passes through the at least one monolithic microlens. In some aspects, the forming of the modified portion on the backside surface of the epitaxial substrate includes forming at least one print-on lens (e.g., collimator print-on lenses, diffuser print on lenses) on the backside surface of the epitaxial substrate, where the infrared radiation emitted in the backside outcoupling direction passes through the at least one print-on lens. In some aspects, the forming of the modified portion on the backside surface of the epitaxial substrate includes forming at least one roughened portion (e.g., roughened portion 404) on the backside surface of the epitaxial substrate, where the infrared radiation emitted in the backside outcoupling direction passes through the at least one roughened portion.

[0101] In some aspects, the IRED assembly manufactured according to method 1000 is configured to emit IR radiation generated by the active IRED structure in a backside outcoupling direction (e.g., primary backside outcoupling direction D) that passes through the modified portion of the backside surface of the epitaxial substrate.VIIV181-24-OPTO-003-WO01

[0102] FIG. 11 is an example method 1100 for forming or manufacturing an IRED assembly (e.g., IRED assembly 500) according to some aspects of the present disclosure or portion(s) thereof. The operations described with reference to example method 1100 can be performed by, or according to, any of the systems, apparatuses, components, techniques, or combinations thereof described herein, such as those described with reference to FIGS. 5A, 5B, and 5C above. It is noted that one or more steps may be combined, that certain steps may be omitted, and that the steps may be performed in any preferred order as desired.

[0103] At step 1102, the method 1100 includes providing an epitaxial substrate (e.g., substrate 502) having a frontside surface (e.g., frontside surface 503a) and a backside surface (e.g., backside surface 503b) opposite the frontside surface.

[0104] At step 1104, the method 1100 includes forming a first set of semiconductor layers (e.g., first set of semiconductor layers 510) on the frontside surface of the epitaxial substrate.

[0105] At step 1106, the method 1100 further includes forming an active IRED structure (e.g., active IRED structure 530) on the first set of semiconductor layers.

[0106] At step 1108, the method 1100 further includes forming a second set of semiconductor layers (e.g., second set of semiconductor layers 520) on the active IRED structure.

[0107] At step 1110, the method 1100 further includes forming an insulating reflective layer (e.g., first reflective layer 550) on the second set of semiconductor layers, the insulating reflective layer having opened portions (e.g., opened portions 552) defining through-holes.

[0108] At step 1112, the method 1100 further includes forming metallic or TOO vias (e.g., through-contacts 540) on the second set of semiconductor layers and in the through-holes defined by the opened portions of the insulating reflective layer. Each of the opened portions surrounds a respective one of the metallic or TCO vias.

[0109] At step 1114, the method 1100 further includes forming a metallic reflective layer (e.g., second reflective layer 560) on the insulating reflective layer and the metallic or TCO vias exposed by the opened portions of the insulating reflective layer. The metallic or TCO vias electrically connect the metallic reflective layer and the second set of semiconductor layers.

[0110] At step 1116, the method 1100 further includes forming a metallic electrical contact (e.g., second electrical contact 570) on the first set of semiconductor layers. The metallic electrical contact is laterally separated from the active IRED structure by a portionVIIV181-24-OPTO-003-WO01(e.g., third portion 516) of the first set of semiconductor layers. In some aspects, the forming of the metallic electrical contact includes etching a mesa trench through the second set of semiconductor layers and the active I RED structure and into the first set of semiconductor layers, and forming the metallic electrical contact in the mesa trench and in electrical contact with the first set of semiconductor layers.

[0111] At step 1118, the method 1100 further includes forming a first passivation layer (e.g., first passivation layer 580) on the metallic reflective layer, the metallic electrical contact, and the portion (e.g., third portion 516) of the first set of semiconductor layers that laterally separates the metallic electrical contact and the active IRED structure.

[0112] At step 1120, the method 1100 further includes forming a first opened portion (e.g., first opened portion 585) in the first passivation layer. The first opened portion is disposed on a portion of the surface of the metallic reflective layer and defines a first electrical contact window allowing electrical access to the metallic reflective layer.

[0113] At step 1122, the method 1100 further includes forming a second opened portion (e.g., second opened portion 583) in the first passivation layer. The second opened portion is disposed on a portion of the surface of the metallic electrical contact and defines a second electrical contact window allowing electrical access to the metallic electrical contact.

[0114] At step 1124, the method 1100 further includes forming a second passivation layer (e.g., second passivation layer 590) on the backside surface of the epitaxial substrate, the sidewall surfaces of the epitaxial substrate, and a portion of the first set of semiconductor layers disposed on the frontside surface of the epitaxial substrate, wherein the second passivation layer is in contact with the first passivation layer. In some aspects, the forming of the second passivation layer includes forming the second passivation layer to overlap at least a portion of the first passivation layer. In some aspects, the forming of the second passivation layer includes forming the second passivation layer to overlap (e.g., to have an overlap section 592, 593 with) at least a portion (e.g., portion 588, 589) of the first passivation layer 580.

[0115] In some aspects, the IRED assembly manufactured according to method 1100 is configured to emit IR radiation generated by the active IRED structure in a backside outcoupling direction (e.g., primary backside outcoupling direction D) that passes through the backside surface of the epitaxial substrate and the second passivation layer disposed on the backside surface of the substrate.

[0116] Although the features and elements of the present disclosure are described in the example aspects and / or embodiments in particular combinations, each feature mayVIIV181-24-OPTO-003-WO01be used alone without the other features and elements of the example aspects and / or embodiments or in various combinations with or without other features and elements of the present disclosure. The foregoing descriptions of specific aspects and / or embodiments of the present technology have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the disclosure to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The aspects and / or embodiments were chosen and described in order to best explain the principles of the present technology and its practical application, to thereby enable others skilled in the art to best utilize the present technology and various aspects and / or embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the disclosure be defined by the claims appended hereto and their equivalents.

[0117] It will be appreciated by persons skilled in the art that the present disclosure is not limited by what has been particularly shown and described hereinabove. Rather the scope of the present disclosure includes both combinations and sub-combinations of various features described herein as well as modifications thereof which are not in the prior art.* * *

Claims

VIIV181-24-OPTO-003-WO01CLAIMSWhat is claimed is:

1. An infrared-emitting diode assembly, comprising:a substrate having a frontside surface and a backside surface opposite the frontside surface, the backside surface of the substrate comprising a modified portion;a first set of semiconductor layers disposed on the frontside surface of the substrate;an active infrared-emitting diode structure disposed on a first portion of the first set of semiconductor layers and configured to generate infrared radiation;a second set of semiconductor layers disposed on the active infrared-emitting diode structure;a first reflective layer disposed on a first portion of the second set of semiconductor layers, the first reflective layer having opened portions defining through-holes;through-contacts disposed on the second set of semiconductor layers and in the through-holes defined by the opened portions of the first reflective layer, each of the opened portions surrounding a respective one of the through-contacts;a first electrical contact comprising a second reflective layer disposed on a first portion of the first reflective layer and the through-contacts exposed by the opened portions of the first reflective layer, the through-contacts electrically connecting the first electrical contact and the second set of semiconductor layers; anda second electrical contact disposed on a second portion of the first set of semiconductor layers,wherein the infrared-emitting diode assembly is configured to emit the infrared radiation in a primary backside outcoupling direction that passes through the modified portion of the backside surface of the substrate.

2. The infrared-emitting diode assembly of claim 1, the modified portion of the backside surface of the substrate comprising at least one monolithic microlens formed on the backside surface of the substrate, wherein the infrared radiation emitted in the primary backside outcoupling direction passes through the at least one monolithic microlens.

3. The infrared-emitting diode assembly of claim 2, the at least one monolithic microlens comprising at least one convex monolithic microlens.VIIV181-24-GPTO-003-W0014. The infrared-emitting diode assembly of claim 2, the at least one monolithic microlens comprising at least one concave monolithic microlens.

5. The infrared-emitting diode assembly of claim 1, the modified portion of the backside surface of the substrate comprising at least one print-on lens, wherein the infrared radiation emitted in the primary backside outcoupling direction passes through the at least one print-on lens.

6. The infrared-emitting diode assembly of claim 5, the at least one print-on lens comprising at least one collimator print-on lens.

7. The infrared-emitting diode assembly of claim 5, the at least one print-on lens comprising at least one diffuser print-on lens.

8. The infrared-emitting diode assembly of claim 1, the modified portion of the backside surface of the substrate comprising at least one roughened portion, wherein the infrared radiation emitted in the primary backside outcoupling direction passes through the at least one roughened portion.

9. The infrared-emitting diode assembly of claim 1, wherein:the substrate is an epitaxial substrate, the epitaxial substrate comprising gallium arsenide (GaAs);the first set of semiconductor layers comprises a first arsenic (As)-based or phosphorus (P)-based lll-V semiconductor material, the first As-based or P-based lll-V semiconductor material comprising GaAs, aluminum gallium arsenide (AIGaAs), or gallium phosphide (GaP);the second set of semiconductor layers comprises a second As-based or P-based lll-V semiconductor material, the second As-based or P-based lll-V semiconductor material comprising GaAs, AIGaAs, or GaP;the first reflective layer is an insulating reflective layer, the insulating reflective layer comprising silicon dioxide (SiO2), magnesium flouride (MgF2), or silicon nitride (SisN4); the second reflective layer is a metallic reflective layer, the metallic reflective layer comprising silver (Ag) or gold (Au); andVIIV181-24-OPTO-003-WO01the through-contacts are metallic vias, the metallic vias consisting essentially of gold (Au).

10. The infrared-emitting diode assembly of claim 1, the second set of semiconductor layers having a first refractive index value, and the first reflective layer having a second refractive index value that is less than the first refractive index value.

11. The infrared-emitting diode assembly of claim 1, further comprising a mesa trench etched through the second set of semiconductor layers and the active infrared-emitting diode structure and into at least the second portion of the first set of semiconductor layers, the second electrical contact disposed in the mesa trench and electrically connecting to the first set of semiconductor layers.

12. The infrared-emitting diode assembly of claim 1 , further comprising:a passivation layer disposed on a third portion of the first set of semiconductor layers disposed laterally between the first portion and the second portion of the first set of semiconductor layers,the passivation layer further disposed on the second reflective layer,the passivation layer having a first opened portion disposed on a portion of a surface of the first electrical contact and defining a first electrical contact window allowing electrical access to the first electrical contact,the passivation layer having a second opened portion disposed on a portion of a surface of the second electrical contact and defining a second electrical contact window allowing electrical access to the second electrical contact, andthe passivation layer comprising silicon dioxide (SiC ) or silicon nitride (SisN4), wherein a lateral distance between the first opened portion of the passivation layer and the second opened portion of the passivation layer is greater than 100 micrometers (pm).

13. The infrared-emitting diode assembly of claim 1, wherein a footprint of the first reflective layer is at least fifty percent (50%) of a total footprint of the infrared-emitting diode assembly, and wherein a total combined footprint of the through-contacts is between one percent (1 %) and ten percent (10%) of the footprint of the first reflective layer.

14. An infrared-emitting diode assembly, comprising:VIIV181-24-OPTO-003-WO01an epitaxial substrate having a frontside surface and a backside surface opposite the frontside surface, the backside surface of the epitaxial substrate comprising a modified portion;a first set of semiconductor layers disposed on the frontside surface of the epitaxial substrate;an active infrared-emitting diode structure disposed on the first set of semiconductor layers and configured to generate infrared radiation;a second set of semiconductor layers disposed on the active infrared-emitting diode structure;an insulating reflective layer disposed on the second set of semiconductor layers, the insulating reflective layer having opened portions defining through-holes;metallic vias disposed on the second set of semiconductor layers and in the through-holes defined by the opened portions of the insulating reflective layer, each of the opened portions surrounding a respective one of the metallic vias;a metallic reflective layer disposed on the insulating reflective layer and the metallic vias exposed by the opened portions of the insulating reflective layer, the metallic vias electrically connecting the metallic reflective layer and the second set of semiconductor layers;a metallic electrical contact disposed on the first set of semiconductor layers and laterally separated from the active infrared-emitting diode structure by a portion of the first set of semiconductor layers; anda passivation layer disposed on the metallic reflective layer, the metallic electrical contact, and the portion of the first set of semiconductor layers that laterally separates the metallic electrical contact and the active infrared-emitting diode structure,the passivation layer having a first opened portion disposed on a portion of a surface of the metallic reflective layer and defining a first electrical contact window allowing electrical access to the metallic reflective layer, andthe passivation layer having a second opened portion disposed on a portion of a surface of the metallic electrical contact and defining a second electrical contact window allowing electrical access to the metallic electrical contact,wherein the infrared-emitting diode assembly is configured to emit the infrared radiation in a primary backside outcoupling direction that passes through the modified portion of the backside surface of the epitaxial substrate.VIIV181-24-OPTO-003-WO0115. A method of manufacturing a reflector system for an infrared-emitting diode assembly, the method comprising:providing an epitaxial substrate having a frontside surface and a backside surface opposite the frontside surface;forming a first set of semiconductor layers on a frontside surface of the epitaxial substrate;forming an active infrared-emitting diode structure on the first set of semiconductor layers;forming a second set of semiconductor layers on the active infrared-emitting diode structure;forming an insulating reflective layer on the second set of semiconductor layers, the insulating reflective layer having opened portions defining through-holes;forming metallic vias on the second set of semiconductor layers and in the through-holes defined by the opened portions of the insulating reflective layer, each of the opened portions surrounding a respective one of the metallic vias;forming a metallic reflective layer on the insulating reflective layer and the metallic vias exposed by the opened portions of the insulating reflective layer, the metallic vias electrically connecting the metallic reflective layer and the second set of semiconductor layers;forming a metallic electrical contact on the first set of semiconductor layers, the metallic electrical contact laterally separated from the active infrared-emitting diode structure by a portion of the first set of semiconductor layers; andforming a modified portion on the backside surface of the epitaxial substrate, wherein the infrared-emitting diode assembly is configured to emit infrared radiation generated by the active infrared-emitting diode structure in a primary backside outcoupling direction that passes through the modified portion of the backside surface of the epitaxial substrate.

16. The method of claim 15, the forming the modified portion on the backside surface of the epitaxial substrate comprising:forming at least one monolithic microlens on the backside surface of the epitaxial substrate, wherein the infrared radiation emitted in the primary backside outcoupling direction passes through the at least one monolithic microlens.VIIV181-24-OPTO-003-WO0117. The method of claim 15, the forming the modified portion on the backside surface of the epitaxial substrate comprising:forming at least one print-on lens on the backside surface of the epitaxial substrate, wherein the infrared radiation emitted in the primary backside outcoupling direction passes through the at least one print-on lens.

18. The method of claim 15, the forming the modified portion on the backside surface of the epitaxial substrate comprising:forming at least one roughened portion on the backside surface of the epitaxial substrate, wherein the infrared radiation emitted in the primary backside outcoupling direction passes through the at least one roughened portion.

19. The method of claim 15, the forming the metallic electrical contact comprising:etching a mesa trench through the second set of semiconductor layers and the active infrared-emitting diode structure and into at least a portion of the first set of semiconductor layers; andforming the metallic electrical contact in the mesa trench and in electrical contact with the first set of semiconductor layers.

20. The method of claim 15, further comprising:forming a passivation layer on the metallic reflective layer, the metallic electrical contact, and the portion of the first set of semiconductor layers that laterally separates the metallic electrical contact and the active infrared-emitting diode structure,forming a first opened portion in the passivation layer, the first opened portion disposed on a portion of a surface of the metallic reflective layer and defining a first electrical contact window allowing electrical access to the metallic reflective layer, and forming a second opened portion in the passivation layer, the second opened portion disposed on a portion of a surface of the metallic electrical contact and defining a second electrical contact window allowing electrical access to the metallic electrical contact.

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