Adaptive hybrid electronic circuit layout parasitic capacitance extraction

Abstract

A method for determining a parasitic capacitance of an electronic circuit layout is provided, wherein the electronic circuit layout includes a plurality of conductor patterns. The method may include retrieving the capacitance information of the respective conductor pattern from the capacitance data store when capacitance information of the respective conductor pattern is available in a capacitance data store. If no capacitance information of the respective conductor pattern is available in the capacitance data store, the method may include determining the respective capacitance information of the respective conductor pattern using a field solver; and storing the determined respective capacitance information of the respective conductor pattern in the capacitance data store. The method may further include determining the parasitic capacitance of the electronic circuit layout using the respective capacitance information of the plurality of conductor patterns; and communicating the determined parasitic capacitance of the electronic circuit layout to a user.

Description

ADAPTIVE HYBRID ELECTRONIC CIRCUIT LAYOUT PARASITIC CAPACITANCE EXTRACTION TECHNICAL FIELD

[0001] The present disclosure is directed to electronic design automation (EDA) and, more specifically, to the adaptive hybrid electronic circuit layout parasitic capacitance extraction, e.g., by determining a parasitic capacitance of an electronic circuit layout. Such electronic design automation systems and parasitic elements determination systems are collectively referred to herein as product systems.BACKGROUND

[0002] The development of electronic devices with electronic circuits may involve many steps known as a design flow. This design flow may start with a specification for a new electronic device to be implemented with an electronic circuit, such as a printed circuit board (PCB) or an integrated circuit (IC). The specification of the electronic device can be transformed into an electronic device design, such as a netlist, for example, by a schematic capture tool or by synthesizing a logical design, sometimes referred to as a register transfer level (RTL) description of the electronic device. The netlist may be specified in an Electronic Design Interchange Format (EDIF) or the like, which can describe nets or connectivity between various components or parts in the electronic device design.

[0003] The design flow may continue by verifying functionality of the electronic device design, for example, by simulating, emulating, or prototyping the electronic device design and verifying that the results of the simulation or emulation correspond with an expected output from the electronic device design. The functionality also can be verified by formally verifying with one or more solvers or statically checking the electronic device design for various attributes that may be problematic during operation of the electronic device built utilizing the electronic device design.

[0004] Once the electronic device design has been functionally verified, the design flow may utilize the logical design to generate a layout design for the electronic device. This procedure can be implemented in different ways, e.g., through the use of a layout tool, which can place and interconnect various components or parts into a representation of an electronic circuit. For example, the layout tool implemented in a computing system can present a graphical view of the electronic circuit and allow a designer to utilize the layout tool to place parts from a library onto the electronic circuit in the graphical view.

[0005] The layout of the electronic circuit may then physically be verified, e.g., to address functional yield challenges in IC designs. Such a physical verification helps to provide accurate circuit behavior with precise device parameters, while parasitic extraction tools help to provide accurate and high-performance extraction required for all design styles.In some respects, the present patent disclosure focuses on the physical verification of an electronic circuit layout.

[0006] Currently, there exist product systems and solutions that support determining a parasitic capacitance of an electronic circuit layout. Such product systems may benefit from improvements.SUMMARY

[0007] Variously disclosed embodiments include methods and computer systems that may be used to facilitate determining a parasitic capacitance of an electronic circuit layout.

[0008] According to a first aspect, a computer-implemented method for determining a parasitic capacitance of an electronic circuit layout, wherein the electronic circuit layout may include a plurality of conductor patterns. The method may include retrieving capacitance information of a respective conductor pattern from a capacitance data store when the capacitance information of the respective conductor pattern is available in the capacitance data store. The method may further include determining the respective capacitance information of the respective conductor pattern using a field solver and storing the determined respective capacitance information of the respective conductor pattern in the capacitance data store when no capacitance information of the respective conductor pattern is available in the capacitance data store. The method may further include determining the parasitic capacitance of the electronic circuit layout using the respective capacitance information of the plurality of conductor patterns. The method may further include communicating the determined parasitic capacitance of the electronic circuit layout to a user.

[0009] According to a second aspect, a computer system may be arranged and configured to execute the acts of this computer-implemented method according to the first aspect.

[0010] According to a third aspect, a computer program product may include computer program code that, when executed by the computer system according to the second aspect, causes the computer system to carry out the method according to the first aspect.

[0011] According to a fourth aspect, a computer-readable medium may include the computer program product according to the third aspect. By way of example, the described computer-readable medium may be non-transitory and may further be a software component on a storage device.

[0012] The foregoing has outlined the technical features of the present disclosure so that those skilled in the art may better understand the detailed description that follows. Additional features and advantages of the disclosure are described hereinafter that form the subject of the claims. Those skilled in the art will appreciate that they may readily use the conception and the specific embodiments disclosed as a basis for determining a parasitic capacitance of an electronic circuit layout or for carrying out the same purposes of the present disclosure.Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure in its broadest form.

[0013] Also, before undertaking the detailed description below, various definitions for certain words and phrases are provided throughout this patent document and those of ordinary skill in the art will understand that such definitions apply in many, if not most, instances to prior as well as future uses of such defined words and phrases. While some terms may include a wide variety of embodiments, the appended claims may expressly limit these terms to specific embodiments.

[0014] Embodiments are described below in greater detail.BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figs. 1-3 depict a functional block diagram of an example system that facilitates determining a parasitic capacitance of an electronic circuit layout in a product system, respectively.

[0016] Figs. 4-6 depict different aspects of example maps and example capacitance data stores that may facilitate determining a parasitic capacitance of an electronic circuit layout in a product system, respectively.

[0017] Figs. 7-10 depict a flow diagram of an example methodology that facilitates determining a parasitic capacitance of an electronic circuit layout in a product system, respectively.

[0018] Fig. 11 depicts a block diagram of a data processing system in which an embodiment can be implemented.DETAILED DESCRIPTION

[0019] Various technologies that pertain to systems and methods for determining a parasitic capacitance of an electronic circuit layout in a product system are now described with reference to the drawings, where like reference numerals represent like elements throughout. The drawings discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged apparatus. It is to be understood that functionality that is described as being carried out by certain system elements may be performed by multiple elements. Similarly, for instance, an element may be configured to perform functionality that is described as being carried out by multiple elements. The numerous innovative teachings of the present patent document are now described with reference to exemplary non-limiting embodiments.

[0020] With reference to Fig. 1 , a functional block diagram of a first example computer system or data processing system 100 is depicted that facilitates determining a parasiticcapacitance 130 of an electronic circuit layout 120 in a product system. The processing system 100 may include an electronic circuit verification (ECV) system 118 that may include at least one processor 102 configured to execute at least one application software component 106 from a memory 104 accessed by the processor 102. The application software component 106 may be configured (i.e., programmed) to cause the processor 102 to carry out various acts and functions described herein. For example, the described application software component 106 may include and / or correspond to one or more components of an application for determining a parasitic capacitance 130 of an electronic circuit layout 120, wherein the application software component 106 may be configured to generate and store product data in a data store 108 such as a database.

[0021] By way of example, the ECV system 118 may be cloud-based, internet- based, and / or be operated by a provider providing support determining a parasitic capacitance 130 of an electronic circuit layout 120. In some examples, the user may be located close to the ECV system 118 or remote to the ECV system 118, e.g., anywhere else, e.g., using a mobile device for connecting to the ECV system 118, e.g., via the internet, wherein the mobile device may include an input device 110 and a display device 112. In some examples, the ECV system 118 may be installed and run on a user’s device, such as a computer, laptop, pad, on-premises computing facility, or the like.

[0022] Determining a parasitic capacitance 130 of an electronic circuit layout 120 may be a challenging and time-consuming process that may require highly skilled engineers with many years of training. For example, advanced knowledge in electronics, physics, and other scientific domains may be required, or selections of many options need to be made consciously, each involving many manual acts, which is a long and not efficient process. Further, according to other approaches, each parasitic capacitance 130 of an electronic circuit layout 120 may be determined using a field solver 128 that results in long runtimes of the parasitic capacitance determination and is therefore not attractive.

[0023] To enable the enhanced determining a parasitic capacitance 130 of an electronic circuit layout 120, the described product system or processing system 100 may include at least one input device 110 and at least one display device 112 (such as a display screen). The described processor 102 may be configured to generate a graphical user interface (GUI) 114 through the display device 112. Such a GUI 114 may include GUI elements such as buttons, links, search boxes, lists, text boxes, images, or scroll bars usable by a user to provide inputs through the input device 110 that cause determining a parasitic capacitance 130 of an electronic circuit layout 120. Byway of example, the GUI 114 may include an ECV user interface (Ul) 116 provided to a user.

[0024] In an example embodiment, for determining a parasitic capacitance 130 of an electronic circuit layout 120, the electronic circuit layout 120 may include a plurality ofconductor patterns 122, wherein the application software component 106 and / or the processor 102 may be configured to retrieve capacitance information 124 of the respective conductor pattern 122 from a capacitance data store 126 if the if the capacitance information 124 of the respective conductor pattern 122 is available in the capacitance data store 126.

[0025] Herein, the electronic circuit layout 120 may be understood as the above-mentioned layout design for an electronic device obtained after the functional verification act and the completion of the layout act of the above-mentioned design flow. The electronic circuit 162 corresponding to the electronic circuit layout 120 may include an integrated circuit, also known as a microchip, chip, or IC, i.e., a small electronic device made up of multiple interconnected electronic components 152 such as transistors, resistors, and capacitors. These components 152 may be etched onto a small piece of semiconductor material, e.g., silicon. Integrated circuits are used in a wide range of electronic devices, including computers, smartphones, and televisions, to perform various functions such as processing and storing information. They have impacted the field of electronics by enabling device miniaturization and enhanced functionality. In some examples, electronic circuits 162 corresponding to the electronic circuit layout 120 may include a printed circuit board (PCB), also called printed wiring board (PWB), i.e., a medium used to connect or "wire" the above-mentioned components 152 to one another in an electric circuit. In some examples, the electronic circuit 162 and the corresponding electronic circuit layout 120 may include millions or even billions of the mentioned components 152, e.g., transistors.

[0026] By way of example, the respective conductor pattern 122 may be understood as a route or metallization layer(s) through which individual components 152, (e.g., transistors, capacitors, resistors, etc.), may electrically be interconnected with wiring on wafer. In some examples, the electronic circuit layout 120 with the plurality of conductor patterns 122 may include geometric, physical, or material properties of the respective conductor pattern 122. Sometimes, the respective conductor pattern 122 may be called interconnect. In further examples, the respective conductor pattern 122 may be a part or a segment of the mentioned route, metallization layer or interconnect so that several or a plurality of conductor patterns 122 form a mentioned route, metallization layer or interconnect. In yet further examples, the respective conductor pattern 122 may include the respective component 152 or a part of the respective component 152.

[0027] The parasitic capacitance 130 may sometimes also be known as stray capacitance and, e.g., be understood as the unavoidable and, e.g., unwanted capacitance that exists between the parts of an electronic component 152 or circuit simply because of their proximity to each other. For example, when two electrical conductors at different voltages are close together, the electric field between them causes electric charge to be stored on them; this effect is capacitance. In the present context, to determine the parasiticcapacitance 130 of the electronic circuit layout 120, individual capacitance information 124 of the respective conductor pattern 122 may be used.

[0028] Herein, capacitance information 124 of the respective conductor pattern 122 may characterize the unavoidable and, e.g., unwanted capacitance of the respective conductor pattern 122. The respective capacitance information 124 of some of the conductor patterns 122 may be available in the capacitance data store 126 and may include a specific capacitance value for the respective conductor pattern 122. In further examples, the respective capacitance information 124 may include a formula or a table that may be used to derive a specific capacitance value for the respective conductor pattern 122. Byway of example, the capacitance data store 126 may be a database that may be included by the ECV system 118, or that may be separate from the ECV system 118 but be communicatively coupled to the ECV system 118.

[0029] If the capacitance data store 126 includes the capacitance information 124 of one of the conductor patterns 122 of the electronic circuit layout 120, this capacitance information 124 may be retrieved from the capacitance data store 126 and be used to determine the parasitic capacitance 130 of the electronic circuit layout 120. By way of example, the capacitance information 124 of the respective conductor patterns 122 may have been determined earlier using a field solver 128 in constellations explained below, e.g., when the capacitance information 124 of the respective conductor patterns 122 was required to determine the parasitic capacitance 130 of the same or another electronic circuit layout 120 and the determined capacitance information 124 has been stored in the capacitance data store 126 for a potential later reuse.

[0030] By way of example, the application software component 106 and / or the processor 102 may further be configured to determine the respective capacitance information 124 of the respective conductor pattern 122 using a field solver 128 if no capacitance information 124 of the respective conductor pattern 122 is available in the capacitance data store 126.

[0031] In the context of EDA, electromagnetic field solvers or sometimes just field solvers 126 may be understood as specialized programs that solve (a subset of) Maxwell's equations directly. They form a part of the field of electronic design automation, or EDA, and are commonly used in the design of integrated circuits and printed circuit boards. In EDA, field solvers 126 may be used when a solution from first principles or the highest accuracy is required.

[0032] If the capacitance data store 126 does not include the capacitance information 124 of one of the conductor patterns 122 of the electronic circuit layout 120, the respective capacitance information 124 may be determined using the field solver 128. Byway of example, the field solver 128 may determine the specific capacitance value of the respective conductor pattern 122. In some examples, the field solver 128 may only be used if thecapacitance data store 126 does not include the capacitance information 124 of the respective conductor pattern 122. The described selective and restricted use of the field solver 128 may contribute to the efficiency of the suggested approach since the use of the field solver 128 for the determination of the respective capacitance information 124 may consume considerable compute or memory resources and may lead to an increased runtime and therefore to delays. Hence, e.g., only if no suitable capacitance information 124 is yet available in the capacitance data store 126, an accurate but complex determination of the desired capacitance information 124 is done using the field solver 128.

[0033] The respective capacitance information 124 that has been determined using the field solver 128 may then be used to determine the parasitic capacitance 130 of the electronic circuit layout 120.

[0034] In further examples, if no capacitance information 124 of the respective conductor pattern 122 is available in the capacitance data store 126 and if the respective capacitance information 124 of the respective conductor pattern 122 has been determined using the field solver 128, the application software component 106 and / or the processor 102 may further be configured to store the determined respective capacitance information 124 of the respective conductor pattern 124 in the capacitance data store 126.

[0035] Besides using the determined, respective capacitance information 124 for the determination of the parasitic capacitance 130 of the electronic circuit layout 120, the determined, respective capacitance information 124 may further be stored in the capacitance data store 126. Byway of example, the determined, respective capacitance information 124 may be stored in the capacitance data store 126 together with information on the respective conductor pattern 122 allowing to find and retrieve the respective conductor pattern 122 and the corresponding capacitance information 124 from the capacitance data store 126 conveniently and fast.

[0036] The described storage of the determined capacitance information 124 in the capacitance data store 126 for a potential later reuse may contribute to the efficiency of the suggested approach since the use of the field solver 128 to determine a specific capacitance information 124 may be leveraged multiple times, e.g., if the same electronic circuit layout 120 includes two or more of the same conductor pattern 122 or if another electronic circuit layout 120 of which the parasitic capacitance 130 is to be determined includes the same conductor pattern 122 at least once. In such examples, the determined and stored corresponding capacitance information 124 may be used twice or more during the determination of the parasitic capacitance 130 of the respective electronic circuit layout 120, wherein the repeated determination of the corresponding capacitance information 124 using the field solver 128 and corresponding efforts and delays may be saved.

[0037] In some examples, thanks to the described storage of the determined capacitance information 124 in the capacitance data store 126, the capacitance data store 126 may over time become a comprehensive collection of capacitance information 124 for a comprehensive collection of conductor patterns 122. Such a comprehensive capacitance data store 126 may speed up the determination of the parasitic capacitance 130 of an electronic circuit layout 120 since many if not most or all of the conductor patterns 122 included in the electronic circuit layout 120 may already be included in the capacitance data store 126 together with the corresponding capacitance information 124. For example, the field solver 128 may only be used if the capacitance information 124 of the respective conductor pattern 122 is required to determine the parasitic capacitance 130 of the same or another electronic circuit layout 120 and if the mentioned capacitance information 124 is not stored in the capacitance data store 126. In such examples, the field solver 128 may be used to determine the mentioned capacitance information 124, wherein the determined capacitance information 124 of the respective conductor pattern 122 may then be stored in the capacitance data store 126 for a potential later reuse. Accordingly, the field solver 128 may only rarely be required to determine the capacitance information 124 of a not yet covered conductor pattern 122 that may also offer the advantage of a computationally slim and fast approach of determining the parasitic capacitance 130 of an electronic circuit layout 120.

[0038] By way of example, the determined respective capacitance information 124 of the respective conductor pattern 124 may be stored in the capacitance data store 126 during the extraction process, i.e., during the determination of the parasitic capacitance 130 of an electronic circuit layout 120. In such an example, the capacitance data store 126 may be understood as an adaptive and ever learning library or capacitance data store 126. Hence, the capacitance data store 126 may continuously learn and update itself with new capacitance information 124 of new conductor patterns 124, thereby improving coverage and accuracy overtime. According to other approaches, other libraries may be static and do not accept new capacitance information 124 of new conductor patterns 124 during the extraction runtime.

[0039] In further examples, the application software component 106 and / or the processor 102 may further be configured to determine the parasitic capacitance 130 of the electronic circuit layout 120 using the respective capacitance information 124 of the plurality of conductor patterns 122.

[0040] By way of example, for a given electronic circuit layout, some of the respective capacitance information 124 of the plurality of conductor patterns 122 may be retrieved from the capacitance data store 126 and some of the respective capacitance information 124 of the plurality of conductor patterns 122 may be determined using the field solver 128. In otherexamples, all the required capacitance information 124 may be available in the capacitance data store 126 so that all the required capacitance information 124 may be retrieved from the capacitance data store 126. In yet further examples, none of the required capacitance information 124 may be available in the capacitance data store 126 so that all the required capacitance information 124 may be determined using the field solver 128. As described above, the respective capacitance information 124 that has been determined using the field solver 128 may then be stored in the capacitance data store 126, e.g., for later reuse to determine the parasitic capacitance 130 of the same or another electronic circuit layout 120.

[0041] In some examples, if for a given electronic circuit layout 120 the respective capacitance information 124 is determined using the field solver 128, the determined respective capacitance information 124 may directly be used for the determination of the parasitic capacitance 130 of the electronic circuit layout 120 and parallelly or later be stored in the capacitance data store 126. In other examples, if for a given electronic circuit layout 120 the respective capacitance information 124 is determined using the field solver 128, the determined respective capacitance information 124 may first be stored in the capacitance data store 126 and then be retrieved again from the capacitance data store 126 for the determination of the parasitic capacitance 130 of the electronic circuit layout 120.

[0042] The parasitic capacitance 130 of the electronic circuit layout 120 may then be determined using the respective capacitance information 124 of the plurality of conductor patterns 122 included in the electronic circuit layout 120. In some examples, the mentioned determination of the parasitic capacitance 130 relying on the previously determined capacitance information 124 may be done with available parasitic extraction tools, such as the Calibre product family of Siemens Industry Software, Inc. of Plano, Texas, USA, or other physical verification tools of other vendors.

[0043] In some examples, the application software component 106 and / or the processor 102 may further be configured to communicate the determined parasitic capacitance 130 of the electronic circuit layout 120 to a user.

[0044] The communication of the determined parasitic capacitance 130 to the user may involve displaying the determined parasitic capacitance 130 via the ICV Ul 116 to the user. In further examples, the determined parasitic capacitance 130 may be communicated to the user via a text message, an alarm or using an acoustic signal that may be provided to the user. Herein, the alarm or the acoustic signal may be used if the determined parasitic capacitance 130 of the electronic circuit layout 120 does not comply with pre-configurable expectations, e.g., if determined parasitic capacitance 130 does not comply with a pre-configurable threshold or range with respect to a parasitic capacitance.

[0045] By way of example, the capacitance information 124 of the respective conductor pattern 122 may be stored in the capacitance data store 126 using a map 132 mapping acorresponding key 134 identifying a respective conductor pattern 122 to the capacitance information 124 of the respective conductor pattern 122.

[0046] Herein, the map 132 may be understood as a collection of key-value-pairs, such that each key 134 appears at most once in the collection. Herein, the respective key 134 may identify the respective conductor pattern 122, and the respective value may correspond to the capacitance information 124 of the respective conductor pattern 122. The map 132 may also be understood as an associative array, symbol table, or dictionary. By way of example, there may be a unique key 134 for each individual conductor pattern 122 so that each different conductor pattern 122 may unambiguously be identified. Further, the mentioned value may include the above-mentioned specific capacitance value for the respective conductor pattern 122 or the above-mentioned formula or table allowing to derive the specific capacitance value for the respective conductor pattern 122.

[0047] Thanks to the map 132, the capacitance information 124 of the respective conductor pattern 122 may be stored and retrieved efficiently and fast from the capacitance data store 126 that may contribute to the efficiency of the suggested approach.

[0048] In further examples, the respective key 134 may include a capacitance indication 136 of the capacitance type 148 of the respective conductor pattern 122 and a pattern indication 138 of a unique characterization of the respective conductor pattern 122.

[0049] As mentioned above, the respective key 134 may identify the respective conductor pattern 122 more precisely using the pattern indication 138. Herein, the pattern indication 138 may include information on the relevant geometry or structure of the respective conductor pattern 122 so that a unique characterization of the respective conductor pattern 122 may be achieved. The respective key 134 may further identify the considered capacitance type 148 of the respective conductor pattern 122 more precisely using the capacitance indication 136. Herein, the capacitance indication 136 may include information on those parts of the respective conductor pattern 122 that are relevant to the considered capacitance type 148 of the respective conductor pattern 122. In some examples, the respective conductor pattern 122 may be decomposed into several pattern components so that the considered capacitance type 148 of the respective conductor pattern 122 may refer to a subset of these components, e.g., two components out of several components making up the respective conductor pattern 122. For example, a specific conductor pattern 122 may include several components arranged along two axes that are perpendicular to each other, wherein for a first capacitance type 148 of the specific conductor pattern 122, the components arranged along the first axis are considered, and wherein for a second capacitance type 148 of the specific conductor pattern 122, the components arranged along the second axis are considered.

[0050] Hence, the key 134 may provide more precise information on the respective conductor pattern 122 and the corresponding, considered capacitance type 148 that further may contribute to an efficient and fast storage and retrieval of the capacitance information 124 of the respective conductor pattern 122 from the capacitance data store 126.

[0051] In some examples, the map 132 may include a hash map, wherein the respective key 134 may correspond to a hash value 140, and wherein the respective hash value 140 may indicate the storage address 142 of the corresponding capacitance information 124 of the respective conductor pattern 122 in the capacitance data store 126.

[0052] In this context, a hash table may be understood as a data structure that implements the map 132, wherein a hash table may use a hash function to compute the hash value 140 into the storage address 142 from which the desired value can be found. During lookup of a specific capacitance information 124 of a specific conductor pattern 122, the corresponding key 134 may be hashed and the resulting hash value 140 may indicate where the corresponding value, here the capacitance information 124, is stored in the capacitance data store 126. A map 132 implemented by a hash table may be called a hash map. Further, the respective storage space 142 may be understood as a memory address, such as a reference to a specific memory location in memory, e.g., the capacitance data store 126, used by software and / or hardware. Further details are provided below in the context of Fig. 6 depicting third aspects of example maps 132 and example capacitance data stores 126.

[0053] The described use of a hash map for the storage and retrieval of the capacitance information 124 of the respective conductor pattern 122 from the capacitance data store 126 may further contribute to the efficiency of the suggested approach.

[0054] By way of example, the pattern indication 138 may include information on the dimensionality 144 of the respective conductor pattern 122, on a target metal layer 146t of the respective conductor pattern 122, and if applicable on a neighboring upper and / or lower metal layer 146u, 1461 of the respective conductor pattern 122, wherein the capacitance indication 136 may include information on a lateral capacitance type 148L, a top capacitance type 148t and / or a bottom capacitance type 148b of the respective conductor pattern 122.

[0055] Referring to the above example of a conductor pattern 122 including several components arranged along two axes that are perpendicular to each other, the dimensionality 144 may indicate whether a specific conductor pattern 122 or optionally its currently considered components are arranged along one or several of the axes. For example, if for a first capacitance type 148 of the specific conductor pattern 122, the components of the specific conductor pattern 122 are arranged along the first axis, then the dimensionality 144 may be one-dimensional (1D). If for a further capacitance type 148 of the specific conductor pattern 122, the components of the specific conductor pattern 122 arearranged in a plane spanned by the two perpendicular axes, then the dimensionality 144 may be two-dimensional (2D). Accordingly, the dimensionality 144 may also be three-dimensional (3D) if three perpendicular axes are involved. Byway of example, 1D may mean an interval of the conductor pattern 122, and 2D may be applicable for the conductor pattern 122 of a transistor.

[0056] By way of example, the electronic circuit layout 120 may include a stack of several metal layers 146, wherein the considered conductor pattern 122 may include three of these metal layers 146u, 146t, 1461. Hence, the respective pattern indication 138 may include information on these three metal layers 146u, 146t, 1461. Further, the considered conductor pattern 122 may include a wire in one of the three metal layers 146u, 146t, 1461, e.g., the center metal layer 1461 Further, the capacitance indication 136 may indicate a lateral capacitance type 148L if the respective conductor pattern 122 includes another wire in the same metal layer 146t and the corresponding lateral capacitance type 148L is considered. In addition, the capacitance indication 136 may further include a top capacitance type 148t (ora bottom capacitance type 148b) if the respective conductor pattern 122 includes another wire in a neighboring upper metal layer 146u (or in a neighboring lower metal layer 1461) and the corresponding top capacitance type 148t (or a bottom capacitance type 148b) is considered. By way of example, the lateral capacitance type 148L, the top capacitance type 148t, and the bottom capacitance type 148b and their corresponding (parts of) the respective conductor pattern 122 may be understood as corresponding coupling components of the respective conductor pattern 122. Further details are provided below in the context of Fig. 5 depicting second aspects of example maps 132 and example capacitance data stores 126.

[0057] Hence, the key 134 may provide more precise information on the respective conductor pattern 122 and the corresponding, considered capacitance type 148 that may further contribute to an efficient and fast storage and retrieval of the capacitance information 124 of the respective conductor pattern 122 from the capacitance data store 126.

[0058] In some examples, the capacitance data store 126 may include a virtual file system.

[0059] A virtual file system (VFS), also sometimes called a virtual filesystem switch, may be understood as an abstract layer on top of a more concrete file system. The purpose of a VFS is to allow client applications to access different types of concrete file systems in a uniform way. In the present context, the capacitance data store 126 may include or be implemented as a virtual file system thereby further enhancing the storage and retrieval of the capacitance information 124 of the respective conductor pattern 122. This may be achieved using the above-mentioned examples of the map 132, e.g., implemented as the hash map, and / or of the key 134, wherein the key 134 may correspond to a hash value 140,or the key 134 may include the capacitance indication 136 of the capacitance type 148 and the pattern indication 138.

[0060] In further examples, the electronic circuit layout 120 may include electric conductors 150 and electric components 152, wherein the electric conductors 150 may electrically connect the electric components 152, and wherein the application software component 106 and / or the processor 102 may further be configured to determine a position 154 of the respective electric component 152 and / or a shape 156 of the respective electric conductor 150 using the capacitance information 124 of the respective conductor pattern 122 stored in the capacitance data store 126 and / or to determine a position 154 of the respective electric component 152 and / or a shape 156 of the respective electric conductor 150 using the determined parasitic capacitance 130 of the electronic circuit layout 120.

[0061] By way of example, the electronic components 152 may include as transistors, resistors, capacitors, diodes, inductances, and the like. The respective electric conductor 150 may include structures that connect two or more electronic components 152 together electrically. By way of example, the respective electric conductor 150 may include interconnects and vias. In further examples, the respective electric conductor 150 may correspond to one conductor pattern 122 or to several interconnected conductor patterns 122, e.g., such that the respective electric conductor 150 may act as a route or metallization layer(s) through which individual components 152, such as transistors, capacitors, resistors, etc., may electrically be interconnected with wiring on wafer. In yet further examples, the respective conductor pattern 122 may include the respective component 152 or a part of the respective component 152.

[0062] Determining the parasitic capacitance 130 of the electronic circuit layout 120 may be an act in the above-mentioned design flow, wherein the determined parasitic capacitance 130 may be used to determine the position 154 of the respective electric component 152 and the shape 156 of the respective electric conductor 150. For example, the initial electronic circuit layout 120 may include a respective tentative position 154 and a respective tentative shape 156 that may be validated if the determined parasitic capacitance 130 of the corresponding electronic circuit layout 120 complies with predefined expectations, such as thresholds or ranges of the parasitic capacitance 130 that need to be observed by the corresponding electronic circuit layout 120. In further examples, the respective capacitance information 124 of the respective conductor pattern 122 may be used in this context, i.e., to validate a respective tentative position 154 and a respective tentative shape 156.

[0063] If the mentioned expectations, such as thresholds or ranges of the parasitic capacitance 130 or of the respective capacitance information 124, are not met by the electronic circuit layout 120 including the mentioned position 154 and the mentioned shape 156, adaptations may be made to the electronic circuit layout 120, e.g., by amending one ormore of the positions 154 and / or of the shapes 156. The respective capacitance information 124 of the amended conductor patterns 122 and / or the parasitic capacitance 130 of the amended electronic circuit layout 120’ may then be determined using the suggested approach, wherein the described validation may then be performed, etc., until an acceptable electronic circuit layout 120’ has been found that complies with the mentioned expectations, such as thresholds or ranges of the parasitic capacitance 130 or of the respective capacitance information 124.

[0064] In some examples, the mentioned amendments to the positions 154 and / or of the mentioned shapes 156 may be made by the user. In other examples, these amendments may be determined applying incremental changes to one or more of the positions 154 and / or of the shapes 156. Byway of example, the incremental changes may be done randomly or may be determined using design rules.

[0065] Herein, determining the position 154 of the respective electric component 152 and / or the shape 156 of the respective electric conductor 150 may be understood to be part of place and route (also called PnR or P&R) that is a stage in the design of electronic circuits, such as printed circuit boards, integrated circuits, and field-programmable gate arrays. As implied by the name, it is composed of two acts, placement and routing. The first act (i.e., placement) may involve deciding where to place all electronic components 152, circuitry, and logic elements in a limited amount of space. This may be followed by the second act (i.e., routing), which decides the exact design of all the wires needed to connect the placed components 152. This act may implement all the desired connections while following the rules and limitations of the manufacturing process. The final result when placing and routing is finished may be the (final) "layout," here the (final) electronic circuit layout 120’, including a geometric description of the location and rotation of each component 152, and the exact path of each wire or conductor 150 connecting them.

[0066] In some examples, the application software component 106 and / or the processor 102 may further be configured to communicate the determined position 154 of the respective electric component 152, the determined shape 156 of the respective electric conductor 150 and / or the corresponding amended electronic circuit layout 120’ to the user, e.g., by displaying the corresponding information 130 via the ICV Ul 116 to the user.

[0067] In some examples, the electronic circuit layout 120 may be decomposed into one or more nets, wherein the respective net may be decomposed into the plurality of conductor patterns 122.

[0068] Herein, a net may be understood as electrically interconnected parts within the electronic circuit layout 120, such as metal layers 146, components 152, conductors 150, and conductor patterns 122. Hence, a net may include transistors, capacitances, vias,interconnects electrically connecting such components 152, etc. of the electronic circuit layout 120.

[0069] To identify the conductor patterns 122 included in the electronic circuit layout 120, the electronic circuit layout 120 may first be decomposed into the included one or more nets. Then, for each net, the included conductors 150 and optionally the included components 152 may be analyzed to find identify conductor segments of the same or optionally of similar shape, wherein these conductor segments may then be used as the conductor patterns 122. In further examples, the interfaces of the electronic circuit layout 120 to adjacent devices or chips may also be considered to identify the conductor patterns 122. Hence, the conductor patterns 122 including the corresponding capacitance information 124 of the electronic circuit layout 120 including interfaces and interactions with adjacent devices or chips may be considered to determine the parasitic capacitance 130 of the electronic circuit layout 120. Byway of example, the segmentation of the electronic circuit layout 120 into the plurality of conductor patterns 122 may be done with available parasitic extraction tools, such as the Calibre product family of Siemens Industry Software, Inc. of Plano, Texas, USA, or other physical verification tools of other vendors.

[0070] By way of example, the application software component 106 and / or the processor 102 may further be configured to transmit the electronic circuit layout 120 to an electronic circuit manufacturing machine 160, and optionally to cause the electronic circuit manufacturing machine 160 to manufacture one or more electronic circuits 162 according to the transmitted, electronic circuit layout 120.

[0071] In some examples, the transmission of the electronic circuit layout 120 to an electronic circuit manufacturing machine 160 and optionally, the manufacture of the one or more electronic circuits 162 by the electronic circuit manufacturing machine 160 may only be done or triggered, if the determined parasitic capacitance 130 of the electronic circuit layout 120 complies with pre-configurable expectations, e.g., if determined parasitic capacitance 130 complies with a pre-configurable threshold or range with respect to a parasitic capacitance 130.

[0072] The described the application software component 106 and / or the processor 102 may carry out an analogous method of determining a parasitic capacitance 130 of an electronic circuit layout 120. Further, a computer-readable medium 170, which may include a computer program product 172, is depicted in Fig. 1. The computer program product 172 may be encoded with executable instructions that, when executed, cause the computer system 100 or and / or the ECV system 118 to carry out the described method.

[0073] The proposed approach of determining a parasitic capacitance of an electronic circuit layout may include these main advantages:

[0074] Continuous Learning: Unlike static libraries, the adaptive library, i.e., the capacitance data store, may continuously learn and update itself with new patterns and capacitance values, improving accuracy overtime.

[0075] High Efficiency: By caching previously solved conductor patterns, the adaptive library may reduce the need for repeated field-solver computations, significantly speeding up the extraction process.

[0076] Scalability: The adaptive library can handle increasing design complexities and larger datasets without a significant drop in performance, making it suitable for modern, high-density layouts.

[0077] Dynamic Updates: The ability to dynamically update and incorporate new data may provide that the library remains relevant and accurate, adapting to new design challenges as they arise.

[0078] Reduced Manual Intervention: The adaptive nature of the library may minimize the need for manual fixes and interventions, reducing the workload on the R&D team and improving overall efficiency.

[0079] Virtual File System: Implementing the library as a virtual file system enhances the speed of caching and retrieval operations, further optimizing the extraction process.

[0080] Comprehensive Coverage: By continuously expanding its database of patterns and capacitance values, the adaptive library may aim to cover a broader range of layout scenarios, reducing the likelihood of encountering unsupported patterns.

[0081] The proposal introduces a new adaptive hybrid layout parasitic capacitance extraction flow. In this flow, the capacitance data store may be implemented as an adaptive library that continuously improves and is enriched with each new layout parasitic capacitance extraction process. The proposed adaptive hybrid flow may aim to detect problematic layout patterns or intervals (those not covered by the library), extract their parasitic capacitance using a field solver, and store their values and features in the adaptive library for future use in the same or other extraction processes. Once a layout pattern is extracted using a field solver, it may be cached in the adaptive library. Therefore, the next time this pattern is encountered, its parasitic values may be retrieved from the adaptive library instead of being re-extracted using a field-solver. Additionally, the adaptive library may be implemented as a virtual file system to speed up caching and extraction operations.

[0082] Contrary to this beneficial proposal, other approaches suffer from substantial drawbacks. In certain examples, with the advent of advanced process technology nodes, the precision in extracting layout parasitic capacitance elements has become crucial. The increasing design complexity and layout density have introduced significant challenges in layout parasitic capacitance extraction methodologies.

[0083] Other approaches may rely on two main types of layout parasitic capacitance extractors: 3D Fieldsolver extractors that rely on electrostatic simulations or 2.5D capacitance extractors that use rule-based or pattern-matching methods. 3D Fieldsolver methods may provide high accuracy but have limited capacity. Conversely, 2.5D extractors may offer reasonable accuracy with very high capacity, making them suitable for handling full chips.

[0084] According to other approaches, 2.5D extractors may be used by designers, especially in digital flows, due to their speed and high capacity with reasonable accuracy.2.5D extraction methods may rely on a pre-characterized library of empirical capacitance equations and lookup tables. Each equation or table may address specific capacitance effects for certain layout patterns. 2.5D extraction tools may scan full layouts and divide them into patterns or intervals. They then may use the pre-characterized library to match each layout pattern or interval with the corresponding capacitance equations or lookup tables.

[0085] The major problem with the 2.5D extraction method is the pattern / equation coverage. The pre-characterized library may lack sufficient data to provide accurate results. Since each capacitance equation or lookup table corresponds to a specific layout pattern or interval, many layout patterns or intervals may not be covered by the equations. This is because the capacitance equations in the pre-characterized library are not comprehensive enough to capture all different layout structures.

[0086] A simple solution might be to pass the unsupported patterns or intervals to a field solver to extract their corresponding parasitic capacitances. However, this solution is not sustainable if the coverage of the pre-characterized library is low. In such cases, most of the design would be passed to a field-solver, resulting in long runtimes and limited capacity.

[0087] Fig. 2 depicts a functional block diagram of second example system 100 that facilitates determining a parasitic capacitance 130 of an electronic circuit layout 120 in a product system.

[0088] The electronic circuit layout 120 may be transmitted to an electronic circuit manufacturing machine 160. The electronic circuit manufacturing machine 160 may be caused or triggered to manufacture one or more corresponding electronic circuits 162.

[0089] In some examples, the transmission of the electronic circuit layout 120 to the electronic circuit manufacturing machine 160 may only done, if the determined parasitic capacitance 130 of the electronic circuit layout 120 complies with pre-configurable expectations, e.g., if determined parasitic capacitance 130 complies with a pre-configurable threshold or range with respect to a parasitic capacitance 130.

[0090] Fig. 3 depicts a functional block diagram of third example system 100 that facilitates determining a parasitic capacitance 130 of an electronic circuit layout 120 in a product system.

[0091] The electronic circuit layout 120 may include electric conductors 150 and electric components 152, wherein the electric conductors 150 may electrically connect the electric components 152. After determining the parasitic capacitance 130 of the electronic circuit layout 120, a position 154 of the respective electric component 152 and / or a shape 156 of the respective electric conductor 150 may be determined, wherein the capacitance information 124 of the respective conductor pattern 122 stored in the capacitance data store 126 may be used. In some examples, the determined parasitic capacitance 130 of the electronic circuit layout 120 may be used for the determination of the position 154 and / or the shape 156.

[0092] If certain expectations, such as thresholds or ranges of the parasitic capacitance 130 or of the respective capacitance information 124, are not met by the electronic circuit layout 120 including the mentioned position 154 and the mentioned shape 156, adaptations may be made to the electronic circuit layout 120, e.g., by amending one or more of the positions 154 and / or of the shapes 156 to obtain an amended electronic circuit layout 120’. The respective capacitance information 124 of the amended conductor patterns 122 and / or the parasitic capacitance 130 of the amended electronic circuit layout 120’ may then be determined using the suggested approach, wherein the described validation may then be performed, etc., until an acceptable electronic circuit layout 120’ has been found that complies with the mentioned expectations, such as thresholds or ranges of the parasitic capacitance 130 or of the respective capacitance information 124.

[0093] The amended electronic circuit layout 120’, including the determined position 154 and the determined shape 156, may be displayed to the user via the ICV Ul 116. Further, the amended electronic circuit layout 120’ may be transmitted to an electronic circuit manufacturing machine 160. The electronic circuit manufacturing machine 160 may be caused or triggered to manufacture one or more corresponding electronic circuits 162.

[0094] Fig. 4 depicts first aspects of example maps 132 and example capacitance data stores 126 that may facilitate determining a parasitic capacitance 130 of an electronic circuit layout 120 in a product system.

[0095] In the second line of Fig. 4, a one-dimensional conductor pattern 122 may have the key 134 “1D_<target layer>_<upper layer>_<lower layer>_<target capacitance>”, wherein the “1 D” part of the key 134 corresponds to the indication 138 of a unique characterization of the conductor pattern 122 in that the dimensionality of the conductor pattern 122 is one-dimensional. The “targetjayer” part of the key 134 corresponds to the indication 138 of a unique characterization of the conductor pattern 122 in that the metallayer 146t is indicated for which the capacitance information 124 is to be determined, stored or retrieved. The “upper layer” part of the key 134 corresponds to the indication 138 of a unique characterization of the conductor pattern 122 in that represent the upper and lower shielding metal layers 146u (“u” for upper) and 1461 (“I” for lower) are indicated. The “target capacitance” part of the key 134 corresponds to the indication 136 of the capacitance information 124 of the required capacitance element or parasitic capacitance type 148, such as lateral capacitance type 148L (“L” for lateral).

[0096] The entries corresponding to the described key 134 of the one-dimensional conductor pattern 122 in the capacitance data store 126 may include the indication 138 of a unique characterization of the conductor pattern 122 that may include geometric informational, such as the width and the spacings of the contactor pattern 122. Further, the capacitance information 124 corresponding to the described key 134 of the one-dimensional conductor pattern 122 is also stored in the capacitance data store 126.

[0097] In the third line of Fig. 4, a two-dimensional conductor pattern 122 may have the key 134 “2D_<gate layer>_<diffusion layer>_<M1 layer>_<target capacitance>”, wherein the “2D” part of the key 134 corresponds to the indication 138 of a unique characterization of the conductor pattern 122 in that the dimensionality of the conductor pattern 122 is two-dimensional that may correspond to a transistor. The “gate layer,” “diffusion layer,” and “M1 layer” parts of the key 134 correspond to the indication 138 of a unique characterization of the conductor pattern 122 in that the layers that conform the transistor (i.e., the conductor pattern 122) are indicated. The “target capacitance” part of the key 134 corresponds to the indication 136 of the capacitance information 124 of the required capacitance element or capacitance type 148 that may be either the gate to source / drain capacitance or the source to drain capacitance.

[0098] The entries corresponding to the described key 134 of the two-dimensional conductor pattern 122 in the capacitance data store 126 may include the indication 138 of a unique characterization of the conductor pattern 122 that may include geometric informational, such as the widths of the gate and of the M1 metal layer, and the spacing between the gate and the M1 metal layer. Further, the capacitance information 124 corresponding to the described key 134 of the two-dimensional conductor pattern 122 is also stored in the capacitance data store 126.

[0099] Fig. 5 depicts second aspects of example maps 132 and example capacitance data stores 126 that may facilitate determining a parasitic capacitance 130 of an electronic circuit layout 120 in a product system.

[0100] On the left of Fig. 5, three keys 134 of the conductor pattern 122 depicted on the right of Fig. 5 are depicted, wherein a cross section of the conductor pattern 122 is depicted on the right of Fig. 5. The three keys 134 relate to the lateral capacitance type 148L, the topcapacitance type 148t, and the bottom capacitance type 148b, respectively. Further, corresponding entries in the capacitance data store 126 are depicted on the left of Fig. 5. Herein, the nomenclature and logic of the keys 132 and the entries in the capacitance data store 126 are the same as depicted in Fig. 4 and described above.

[0101] As depicted on the right of Fig. 5, the conductor pattern 122 may include three stacked metal layers 146u, 146t, and 146b, wherein the considered conductor pattern 122 may include a center wire of a certain width in the center or target metal layer 146t. The center metal layer 146t may include further wires that have a certain width, and that are spaced from the center wire, respectively, wherein the center wire is arranged between the two other wires.

[0102] The capacitance indication 136 may indicate a lateral capacitance type 148L for which the center wire and another wire in the same center metal layer 146t are considered. Hence, in this aspect, the relevant parts of the conductor pattern 122 are one-dimensional since they are arranged in a direction that lies within the plane of the center metal layer 146t, wherein this line is perpendicular to the center wire. The capacitance indication 136 may further indicate a top (or bottom) capacitance type 148t (148b) for which the center wire and another wire in the neighboring upper (or lower) metal layer 146u (1481) are considered. Hence, in this aspect, the relevant parts of the conductor pattern 122 are also onedimensional since they are arranged in a direction that is perpendicular to the center wire and to the plane of the center metal layer 146t.

[0103] Fig. 6 depicts third aspects of example maps 132 and example capacitance data stores 126 that may facilitate determining a parasitic capacitance 130 of an electronic circuit layout 120 in a product system.

[0104] The map 132 may be implemented as a hash map and may include three keys 134-1, 134-2, 134-3. Using a hash function, the respective key 134-1, 134-2, 134-3 may be assigned to a corresponding hash value 140-01, 140-02, 140-14 that may indicate the corresponding storage address 142-01 , 142-02, 142-14 at which the corresponding capacitance information 124-1, 124-2, 124-3 of the corresponding conductor patterns 122-1, 122-2, 122-3 corresponding to the respective key 134-1, 134-2, 134-3 may be stored in the capacitance data store 126.

[0105] Fig. 7 depicts a flow diagram of a first example methodology M1 that facilitates determining a parasitic capacitance 130 of an electronic circuit layout 120 in a product system, wherein the electronic circuit layout 120 may include a plurality of conductor patterns 122.

[0106] If capacitance information 124 of the respective conductor pattern 122 is available in a capacitance data store 126, the capacitance information 124 of the respective conductor pattern 122 may be retrieved from the capacitance data store 126.

[0107] If no capacitance information 124 of the respective conductor pattern 122 is available in the capacitance data store 126, the respective capacitance information 124 of the respective conductor pattern 122 may be determined using a field solver 128, wherein the determined respective capacitance information 124 of the respective conductor pattern 124 may be stored in the capacitance data store 126.

[0108] The parasitic capacitance 130 of the electronic circuit layout 120 may then be determined using the respective capacitance information 124 of the plurality of conductor patterns 122. Herein, the respective capacitance information 124 may have been retrieved from the capacitance data store 126 or been determined using the field solver 128. The determined parasitic capacitance 130 of the electronic circuit layout 120 may then be communicated to a user.

[0109] As a result, the adaptive library, i.e., the capacitance data store 126, may continuously learn from each extraction process performed by the field solver 128. This ongoing improvement may enhance the quality and coverage of the adaptive library over time, leading to a faster and more accurate parasitic capacitance extraction process.

[0110] Fig. 8 depicts a flow diagram of a second example methodology M2 that facilitates determining a parasitic capacitance of an electronic circuit layout in a product system, wherein the electronic circuit layout may include a plurality of conductor patterns. The method may start at M02, and the methodology may include several acts carried out through operation of at least one processor.

[0111] These acts may include an act M04 of retrieving capacitance information of the respective conductor pattern from a capacitance data store if the capacitance information of the respective conductor pattern is available in the capacitance data store; if no capacitance information of the respective conductor pattern is available in the capacitance data store an act M06 of determining the respective capacitance information of the respective conductor pattern using a field solver, and an act M08 of storing the determined respective capacitance information of the respective conductor pattern in the capacitance data store; an act M10 of determining the parasitic capacitance of the electronic circuit layout using the respective capacitance information of the plurality of conductor patterns; and an act M 12 of communicating the determined parasitic capacitance of the electronic circuit layout to a user. At M14 the methodology may end.

[0112] In some examples, the methodology M2 may include other acts and features discussed previously or below with respect to the computer-implemented method of determining a parasitic capacitance of an electronic circuit layout.

[0113] Fig. 9 depicts a flow diagram of a third example methodology M3 that facilitates determining a parasitic capacitance 130 of an electronic circuit layout 120 in a product system, wherein the electronic circuit layout may include a plurality of conductor patterns,wherein the electronic circuit layout may further include electric conductors and electric components, and wherein the electric conductors may electrically connect the electric components. The method may start at M02, and the methodology may include several acts carried out through operation of at least one processor.

[0114] These acts may include an act M04 of retrieving capacitance information of the respective conductor pattern from a capacitance data store if the capacitance information of the respective conductor pattern is available in the capacitance data store; if no capacitance information of the respective conductor pattern is available in the capacitance data store an act M06 of determining the respective capacitance information of the respective conductor pattern using a field solver, and an act M08 of storing the determined respective capacitance information of the respective conductor pattern in the capacitance data store; an act M10 of determining the parasitic capacitance of the electronic circuit layout using the respective capacitance information of the plurality of conductor patterns; an act M12 of communicating the determined parasitic capacitance of the electronic circuit layout to a user; an act M 14 of determining a position of the respective electric component and / or a shape of the respective electric conductor using the capacitance information of the respective conductor pattern stored in the capacitance data store and / or an act M 16 of determining a position of the respective electric component and / or a shape of the respective electric conductor using the determined parasitic capacitance of the electronic circuit layout. At M18 the methodology may end.

[0115] By way of example, the methodology M3 may include other acts and features discussed previously or below with respect to the computer-implemented method of determining a parasitic capacitance of an electronic circuit layout.

[0116] Fig. 10 depicts a flow diagram of a fourth example methodology M4 that facilitates determining a parasitic capacitance 130 of an electronic circuit layout 120 in a product system, wherein the electronic circuit layout may include a plurality of conductor patterns. The method may start at M02, and the methodology may include several acts carried out through operation of at least one processor.

[0117] These acts may include an act M04 of retrieving capacitance information of the respective conductor pattern from a capacitance data store if the capacitance information of the respective conductor pattern is available in the capacitance data store; if no capacitance information of the respective conductor pattern is available in the capacitance data store an act M06 of determining the respective capacitance information of the respective conductor pattern using a field solver, and an act M08 of storing the determined respective capacitance information of the respective conductor pattern in the capacitance data store; an act M10 of determining the parasitic capacitance of the electronic circuit layout using the respective capacitance information of the plurality of conductor patterns; an act M12 of communicatingthe determined parasitic capacitance of the electronic circuit layout to a user; and an act M14 of transmitting the electronic circuit layout to an electronic circuit manufacturing machine and optionally of causing the electronic circuit manufacturing machine to manufacture one or more electronic circuits according to the transmitted, electronic circuit layout, e.g., if the determined parasitic capacitance of the electronic circuit layout complies with pre-configurable expectations, e.g., if determined parasitic capacitance complies with a pre-configurable threshold or range with respect to a parasitic capacitance. At M16 the methodology may end.

[0118] In further examples, the methodology M4 may include other acts and features discussed previously with respect to the computer-implemented method of determining a parasitic capacitance of an electronic circuit layout.

[0119] Fig. 11 depicts a block diagram of a data processing system 1000 (also referred to as a computer system) in which an embodiment can be implemented, for example, as a portion of a product system, and / or other system operatively configured by software or otherwise to perform the processes as described herein. The data processing system 1000 may comprise, for example, the computer or IT system or data processing system 100 mentioned above. The data processing system depicted comprises at least one processor 1002 (e.g., a CPU) that may be connected to one or more bridges / controllers / buses 1004 (e.g., a north bridge, a south bridge). One of the buses 1004, for example, may comprise one or more I / O buses such as a PCI Express bus. Also connected to various buses in the depicted example may comprise a main memory 1006 (RAM) and a graphics controller 1008. The graphics controller 1008 may be connected to one or more display devices 1010. It should also be noted that in some embodiments one or more controllers (e.g., graphics, south bridge) may be integrated with the CPU (on the same chip or die). Examples of CPU architectures comprise IA-32, x86-64, and ARM processor architectures.

[0120] Other peripherals connected to one or more buses may comprise communication controllers 1012 (Ethernet controllers, WiFi controllers, cellular controllers) operative to connect to a local area network (LAN), Wide Area Network (WAN), a cellular network, and / or other wired or wireless networks 1014 or communication equipment.

[0121] Further components connected to various busses may comprise one or more I / O controllers 1016 such as USB controllers, Bluetooth controllers, and / or dedicated audio controllers (connected to speakers and / or microphones). It should also be appreciated that various peripherals may be connected to the I / O controller(s) (via various ports and connections) comprising input devices 1018 (e.g., keyboard, mouse, pointer, touch screen, touch pad, drawing tablet, trackball, buttons, keypad, game controller, gamepad, camera, microphone, scanners, motion sensing devices that capture motion gestures), output devices 1020 (e.g., printers, speakers) or any other type of device that is operative toprovide inputs to or receive outputs from the data processing system. Also, any devices referred to as input devices or output devices may both provide inputs and receive outputs of communications with the data processing system. For example, the processor 1002 may be integrated into a housing (such as a tablet) that comprises a touch screen that serves as both an input and display device. Further, some input devices (such as a laptop) may comprise a plurality of different types of input devices (e.g., touch screen, touch pad, keyboard). Also, other peripheral hardware 1022 connected to the I / O controllers 1016 may comprise any type of device, machine, or component that is configured to communicate with a data processing system.

[0122] Additional components connected to various busses may comprise one or more storage controllers 1024 (e.g., SATA). A storage controller may be connected to a storage device 1026 such as one or more storage drives and / or any associated removable media, which can be any suitable non-transitory machine usable or machine-readable storage medium. Examples comprise nonvolatile devices, volatile devices, read only devices, writable devices, ROMs, EPROMs, magnetic tape storage, floppy disk drives, hard disk drives, solid-state drives (SSDs), flash memory, optical disk drives (CDs, DVDs, Blu-ray), and other known optical, electrical, or magnetic storage devices drives and / or computer media. Also, in some examples, a storage device such as an SSD may be connected directly to an I / O bus 1004 such as a PCI Express bus.

[0123] A data processing system in accordance with an embodiment of the present disclosure may comprise an operating system 1028, software / firmware 1030, and data stores 1032 (that may be stored on a storage device 1026 and / or the memory 1006). Such an operating system may employ a command line interface (CLI) shell and / or a graphical user interface (GUI) shell. The GUI shell permits multiple display windows to be presented in the graphical user interface simultaneously, with each display window providing an interface to a different application or to a different instance of the same application. A cursor or pointer in the graphical user interface may be manipulated by a user through a pointing device such as a mouse or touch screen. The position of the cursor / pointer may be changed and / or an event, such as clicking a mouse button or touching a touch screen, may be generated to actuate a desired response. Examples of operating systems that may be used in a data processing system may comprise Microsoft Windows™, Linux™, UNIX™, iOS™, and Android™ operating systems. Also, examples of data stores comprise data files, data tables, relational database (e.g., Oracle™, Microsoft SQL™ Server), database servers, or any other structure and / or device that is capable of storing data, which is retrievable by a processor.

[0124] The communication controllers 1012 may be connected to the network 1014 (not a part of data processing system 1000), which can be any public or private data processing system network or combination of networks, as known to those of skill in the art, comprisingthe Internet. Data processing system 1000 can communicate over the network 1014 with one or more other data processing systems such as a server 1034 (also not part of the data processing system 1000). However, an alternative data processing system may correspond to a plurality of data processing systems implemented as part of a distributed system in which processors associated with several data processing systems may be in communication by way of one or more network connections and may collectively perform tasks described as being performed by a single data processing system. Thus, it is to be understood that when referring to a data processing system, such a system may be implemented across several data processing systems organized in a distributed system in communication with each other via a network.

[0125] Further, the term “controller” means any device, system, or part thereof that controls at least one operation, whether such a device is implemented in hardware, firmware, software, or some combination of at least two of the same. The functionality associated with any particular controller may be centralized or distributed, whether locally or remotely.

[0126] In addition, data processing systems may be implemented as virtual machines in a virtual machine architecture or cloud environment. For example, the processor 1002 and associated components may correspond to a virtual machine executing in a virtual machine environment of one or more servers. Examples of virtual machine architectures comprise VMware ESCi, Microsoft Hyper-V, Xen, and KVM.

[0127] Those of ordinary skill in the art will appreciate that the hardware depicted for the data processing system may vary for particular implementations. For example, the data processing system 1000 in this example may correspond to a computer, workstation, server, PC, notebook computer, tablet, mobile phone, and / or any other type of apparatus / system that is operative to process data and carry out functionality and features described herein associated with the operation of a data processing system, computer, processor, and / or a controller discussed herein. The depicted example is provided for the purpose of explanation only and is not meant to imply architectural limitations with respect to the present disclosure.

[0128] Also, the processor described herein may be located in a server that is remote from the display and input devices described herein. In such an example, the described display device and input device may be comprised in a client device that communicates with the server (and / or a virtual machine executing on the server) through a wired or wireless network (which may comprise the Internet). In some embodiments, such a client device, for example, may execute a remote desktop application or may correspond to a portal device that carries out a remote desktop protocol with the server in order to send inputs from an input device to the server and receive visual information from the server to display through a display device. Examples of such remote desktop protocols comprise Teradici's PColP,Microsoft's RDP, and the RFB protocol. In such examples, the processor described herein may correspond to a virtual processor of a virtual machine executing in a physical processor of the server.

[0129] As used herein, the terms “component” and “system” are intended to encompass hardware, software, or a combination of hardware and software. Thus, for example, a system or component may be a process, a process executing on a processor, or a processor. Additionally, a component or system may be localized on a single device or distributed across several devices.

[0130] Also, as used herein a processor corresponds to any electronic device that is configured via hardware circuits, software, and / or firmware to process data. For example, processors described herein may correspond to one or more (or a combination) of a microprocessor, CPU, FPGA, ASIC, or any other integrated circuit (IC) or other type of circuit that is capable of processing data in a data processing system, which may have the form of a controller board, computer, server, mobile phone, and / or any other type of electronic device.

[0131] Those skilled in the art will recognize that, for simplicity and clarity, the full structure and operation of all data processing systems suitable for use with the present disclosure is not being depicted or described herein. Instead, only so much of a data processing system as is unique to the present disclosure or necessary for an understanding of the present disclosure is depicted and described. The remainder of the construction and operation of data processing system 1000 may conform to any of the various current implementations and practices known in the art.

[0132] Also, the words or phrases used herein should be construed broadly, unless expressly limited in some examples. For example, the terms “comprise” and “comprise,” as well as derivatives thereof, mean inclusion without limitation. The singular forms “a,” “an,” and “the” are intended to comprise the plural forms as well, unless the context clearly indicates otherwise. Further, the term “and / or” as used herein refers to and encompasses any and all combinations of one or more of the associated listed items. The term “or” is inclusive, meaning and / or, unless the context clearly indicates otherwise. The phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to comprise, be comprised within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.

[0133] Also, although the terms “first,” “second,” “third,” and so forth may be used herein to describe various elements, functions, or acts, these elements, functions, or acts should not be limited by these terms. These numeral adjectives are used to distinguish different elements, functions or acts from each other. For example, a first element, function, or actcould be termed a second element, function, or act, and, similarly, a second element, function, or act could be termed a first element, function, or act, without departing from the scope of the present disclosure.

[0134] In addition, phrases such as “processor is configured to” carry out one or more functions or processes, may mean the processor is operatively configured to or operably configured to carry out the functions or processes via software, firmware, and / or wired circuits. For example, a processor that is configured to carry out a function / process may correspond to a processor that is executing the software / firmware, which is programmed to cause the processor to carry out the function / process and / or may correspond to a processor that has the software / firmware in a memory or storage device that is available to be executed by the processor to carry out the function / process. It should also be noted that a processor that is “configured to” carry out one or more functions or processes, may also correspond to a processor circuit particularly fabricated or “wired” to carry out the functions or processes (e.g., an ASIC or FPGA design). Further the phrase “at least one” before an element (e.g., a processor) that is configured to carry out more than one function may correspond to one or more elements (e.g., processors) that each carry out the functions and may also correspond to two or more of the elements (e.g., processors) that respectively carry out different ones of the one or more different functions.

[0135] In addition, the term “adjacent to” may mean that an element is near to but not in contact with a further element, or that the element is in contact with the further portion, unless the context clearly indicates otherwise.

[0136] Although an exemplary embodiment of the present disclosure has been described in detail, those skilled in the art will understand that various changes, substitutions, variations, and improvements disclosed herein may be made without departing from the spirit and scope of the disclosure in its broadest form.

[0137] None of the description in the present patent document should be read as implying that any particular element, step, act, or function is an essential element, which must be included in the claim scope: the scope of patented subject matter is defined only by the allowed claims.

Claims

CLAIMS1. A computer-implemented method for determining a parasitic capacitance of an electronic circuit layout, wherein the electronic circuit layout comprises a plurality of conductor patterns, the method comprising:retrieving capacitance information of a respective conductor pattern from a capacitance data store when the capacitance information of the respective conductor pattern is available in the capacitance data store;determining the respective capacitance information of the respective conductor pattern using a field solver and storing the determined respective capacitance information of the respective conductor pattern in the capacitance data store when no capacitance information of the respective conductor pattern is available in the capacitance data store;determining the parasitic capacitance of the electronic circuit layout using the respective capacitance information of the plurality of conductor patterns; and communicating the determined parasitic capacitance of the electronic circuit layout to a user.

2. The computer-implemented method according to claim 1, wherein the capacitance information of the respective conductor pattern is stored in the capacitance data store using a map that maps a corresponding key identifying a respective conductor pattern to the capacitance information of the respective conductor pattern.

3. The computer-implemented method according to claim 2, wherein the respective key comprises an indication of the capacitance type of the respective conductor pattern and an indication of a unique characterization of the respective conductor pattern.

4. The computer-implemented method according to claim 3, wherein the map comprises a hash map,wherein the respective key corresponds to a hash value, andwherein the respective hash value indicates a storage address of the corresponding capacitance information of the respective conductor pattern in the data base.

5. The computer-implemented method according to claim 3 or 4, wherein the pattern indication comprises information on a dimensionality of the respective conductor pattern, on a target metal layer of the respective conductor pattern, and, when applicable, on a neighboring upper metal layer and / or lower metal layer of the respective conductor pattern, andwherein a capacitance indication comprises information on a lateral capacitance type, a top capacitance type, and / or a bottom capacitance type of the respective conductor pattern.

6. The computer-implemented method according to any one of the preceding claims, wherein the capacitance data store comprises a virtual file system.

7. The computer-implemented method according to any one of the preceding claims, wherein the electronic circuit layout comprises electric conductors and electric components, wherein the electric conductors electrically connect the electric components, and wherein the method further comprises:determining a position of the respective electric component and / or a shape of a respective electric conductor using the capacitance information of the respective conductor pattern stored in the capacitance data store; and / or determining the position of the respective electric component and / or the shape of the respective electric conductor using the determined parasitic capacitance of the electronic circuit layout.

8. The computer-implemented method according to any of the preceding claims, further comprising:transmitting the electronic circuit layout to an electronic circuit manufacturing machine.

9. A computer system arranged and configured to execute the acts of the computer-implemented method according to any one of the preceding claims.

10. A computer program product comprising computer program code that, when executed by a computer system, causes the computer system to carry out the method of one of the claims 1 to 8.

11. A computer-readable medium comprising a computer program product including computer program code that, when executed by a computer system, causes the computer system to carry out the method of one of the claims 1 to 8.

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