Metal-assisted chemical etching methods to form through silicon vias

Abstract

Exemplary semiconductor processing methods may include depositing a metal-containing material on a substrate. A layer of silicon-containing material may overlie the substrate. A patterned mask material may overlie the layer of silicon-containing material. The methods may include perforating the metal-containing material to form pores in the metal-containing material. The methods may include submerging the substrate in a first etchant solution to perform a metal-assisted chemical etching of the layer of silicon-containing material. The metal-assisted chemical etching may form one or more features in the layer of silicon-containing material.

Description

PCT / US25 / 21975 28 March 2025 (28.03.2025)PATENT KTS No.: 080042-44025597W001-1488587METAL-ASSISTED CHEMICAL ETCHING METHODS TO FORM THROUGH SILICON VIASTECHNICAL FIELD

[0001] The present technology relates to deposition processes and chambers. More specifically, the present technology relates to methods of forming features in silicon-containing materials.BACKGROUND

[0002] Integrated circuits are made possible by processes which produce intricately patterned material layers on substrate surfaces. Producing patterned material on a substrate requires controlled methods for forming and removing material. Chemical etching is used for a variety of purposes including transferring a pattern in photoresist into underlying layers, thinning layers, or thinning lateral dimensions of features already present on the surface. Often it is desirable to have an etch process that etches one material faster than another facilitating, for example, a pattern transfer process. Such an etch process is said to be selective to the first material. As a result of the diversity of materials, circuits, and processes, etch processes have been developed with a selectivity towards a variety of materials.

[0003] Etch processes may be termed wet or dry based on the materials used in the process. For example, a wet etch may preferentially remove some oxide dielectrics over other dielectrics and materials. However, wet processes may have difficulty penetrating some constrained trenches and also may sometimes deform the remaining material. While wet etch processes may be characterized by high selectivity, wet etch process may not be able to achieve increased depths and / or increased aspect ratios. Dry etches produced in local plasmas formed within the substrate processing region can penetrate more constrained trenches and exhibit less deformation of delicate remaining structures. However, local plasmas may damage the substrate through the production of electric arcs as they discharge. In addition, dry etch process, such as the known Bosch process, tends to introduce etch profile imperfection (e.g., scalloping, micrograss, and / or tradeoff of etch rate with feature size and / or depth (loading effect)).PCT / US25 / 21975 28 March 2025 (28.03.2025)

[0004] Thus, there is a need for improved systems and methods that can be used to produce high quality devices and structures. These and other needs are addressed by the present technology.SUMMARY

[0005] Exemplary semiconductor processing methods may include depositing a metalcontaining material on a substrate. A layer of silicon-containing material may overlie. A patterned mask material may overlie the layer of silicon-containing material. The methods may include perforating the metal-containing material to form pores in the metal-containing material. The methods may include submerging the substrate in a first etchant solution to perform a metal-assisted chemical etching of the layer of silicon-containing material. The metal-assisted chemical etching may form one or more features in the layer of silicon-containing material.

[0006] In embodiments, the metal-containing material may be deposited on the substrate through atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electroless plating, electroplating, or inkjet printing. The metalcontaining material may be or include gold (Au), silver (Ag), or platinum (Pt). The metalcontaining material may be characterized by a thickness of less than or about 100 nm.Perforating the metal-containing material to form pores in the metal-containing material may include contacting the metal-containing material with an inert plasma. The metal-containing material may include two or more metals. Perforating the metal-containing material to form pores in the metal-containing material may include selectively removing at least one of the two or more metals from the metal-containing material. The methods may include stripping the patterned mask material overlying the layer of silicon-containing material. The first etchant solution may include an etchant and an oxidizer. The etchant of the first etchant solution may include hydrogen fluoride (HF) at a concentration of between about 0.2 M and about 50 M. The oxidizer of the first etchant solution may include hydrogen peroxide (H2O2) at a concentration of between about 0.02 M and about 5 M. The one or more features may be characterized by an aspect ratio of greater than or about 15:1. The methods may include, subsequent to submerging the substrate in the first etchant solution to perform the metal-assisted chemical etching of the layer of silicon-containing material, submerging the substrate in a second etchant solution to remove remaining silicon-containing material within the onePCT / US25 / 21975 28 March 2025 (28.03.2025)or more features. An etch rate of the layer of sihcon-containing material may be maintained constant along a depth of the one or more features.

[0007] Some embodiments of the present technology' may encompass semiconductor processing methods. The methods may include depositing a discontinuous metal-containing material on a substrate. A layer of sihcon-containing material may overlie the substrate and a patterned mask material may overlie the layer of silicon-containing material. The methods may include submerging the substrate in a first etchant solution to perform a metal-assisted chemical etching of the layer of silicon-containing material. The metal-assisted chemical etching may form one or more features in the layer of sihcon-containing material.

[0008] In embodiments, portions of the discontinuous metal-containing material may be characterized by an area of greater than or about 0.1 pm2. The discontinuous metalcontaining material may be characterized by a discontinuity of greater than or about 40%. A concentration ratio of an etchant to an oxidizer in the first etchant solution may be between about 2: 1 and about 50:1.

[0009] Some embodiments of the present technology' may encompass semiconductor processing methods. The methods may include depositing a metal-containing material on a substrate. A layer of sihcon-containing material may overlie the substrate and a patterned mask material overlies the layer of silicon-containing material. The methods may include perforating the metal-containing material to form pores in the metal-containing material. The methods may include submerging the substrate in a first etchant solution to perform a metal-assisted chemical etching of the layer of sihcon-containing material. The metal-assisted chemical etching may form one or more features in the layer of sihcon-containing material. The methods may include stripping the metal -containing material from the substrate. The methods may include submerging the substrate in a second etchant solution to remove remaining silicon-containing material within the one or more features.

[0010] In embodiments, the one or more features may be characterized by a depth of greater than or about 3 pm. The second etchant solution may include potassium hydroxide (KOH).

[0011] Such technology' may provide numerous benefits over conventional processing methods. For example, metal-assisted chemical etching may form high aspect ratio, highly uniform features in silicon-containing materials. Additionally, metal-assisted chemical etching may not be limited by profile defects associated with conventional technologies andPCT / US25 / 21975 28 March 2025 (28.03.2025)may be able to process batches of substrates at a single time. These and other embodiments, along with many of their advantages and features, are described in more detail in conjunction with the below description and attached figures.BRIEF DESCRIPTION OF THE DRAWINGS

[0012] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings.

[0013] FIG. 1 shows a top plan view of an exemplary processing system according to some embodiments of the present technology.

[0014] FIG. 2 shows a schematic cross-sectional view of an exemplary plasma system according to some embodiments of the present technology.

[0015] FIG. 3 shows operations of an exemplary method of semiconductor processing according to some embodiments of the present technology.

[0016] FIGS.4A-4G show schematic cross-sectional views of a substrate being processed according to some embodiments of the present technology.

[0017] Several of the figures are included as schematics. It is to be understood that the figures are for illustrative purposes, and are not to be considered of scale unless specifically stated to be of scale. Additionally, as schematics, the figures are provided to aid comprehension and may not include all aspects or information compared to realistic representations, and may include exaggerated material for illustrative purposes.

[0018] In the appended figures, similar components and / or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a letter that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the letter.DETAILED DESCRIPTION

[0019] A through-silicon via (TSV) is a type of VIA (vertical interconnect access) connection used in integrated circuit packaging technology that creates vertical electricalPCT / US25 / 21975 28 March 2025 (28.03.2025)connections between silicon wafers or dies. The vertical connections may be used to interconnect multiple chips, memory, sensors, and other modules. The vertical connections may create smaller, faster, and more power-efficient devices. TSVs may be formed at various intervals during semiconductor processing. For example, via-first TSVs may be fabricated 5 before the individual component (e g., transistors, capacitors, resistors, etc.) are patterned (z.e., front end of line (FEOL)), via-middle TSVs may be fabricated after the individual component is patterned but before the metal layers (z.e., back-end-of-line (BEOL)), and vialast TSVs may be fabricated after (or during) the BEOL process.

[0020] Conventional processes, including Bosch processes, have commonly been used to 10 form TSVs. Bosch processes may include alternating repeatedly between two modes to achieve nearly vertical structures. A first mode may include a standard, nearly isotropic plasma etch. A second mode may include a deposition of a chemically inert passivation layer. By alternating repeatedly between the first mode and the second mode, a feature may be etched into the material with a fairly uniform profile. However, as the feature deepens (and aspect ratio increases), it becomes increasingly difficult to maintain uniform passivation, which may result in an undercut and / or bowing of the feature being etched. Through repetition of the first mode and the second mode, scalloping of the sidewalls defining the feature may result. Additionally, as the feature deepens (and aspect ratio increases), with an etch front being much further from the surface, an etch rate of the material may reduce, 20 causing a loading effect. As such, conventional processes may not currently be able to meet the demands of future devices.

[0021] The present technology may overcome these issues by performing a metal-assisted chemical etching (MACE) to form high aspect ratio features, such as TSVs. The MACE may utilize a metal catalyst on a material, such as silicon-containing materials, such that submersion in an etchant solution including an etchant and an oxidizer may result in a highly uniform, deep feature being etched int the material, such as silicon-containing materials. The MACE may not be limited by a certain depth or aspect ratio, allowing high aspect ratio features to be formed without a loading effect. As such, etch rates may be maintained nearly constant during the MACE. Additionally, instead of processing a single substrate, MACE 30 may allow for the simultaneous processing of numerous substrates, resulting in much higher throughput than conventional processes, such as a Bosch process. The present technology may address issues associated with conventional processes and may serve as a process suitable to meet the demands of present and future devices.PCT / US25 / 21975 28 March 2025 (28.03.2025)

[0022] Although the remaining disclosure will routinely identify specific deposition and etching processes utilizing the disclosed technology, it will be readily understood that the systems and methods are equally applicable to other deposition chambers and etching chambers, as well as processes as may occur in the described chambers. Accordingly, the 5 technology should not be considered to be so limited as for use with these specific deposit! on / etching processes or chambers alone. The disclosure will discuss one possible system and chamber that may be used to perform deposition processes according to embodiments of the present technology before additional details according to embodiments of the present technology are described.10

[0023] FIG. 1 shows a top plan view of one embodiment of a processing system 100 of deposition, etching, baking, and UV treatment chambers according to embodiments. In the figure, a pair of front opening unified pods 102 supply substrates of a variety of sizes that are received by robotic arms 104 and placed into a low pressure holding area 106 before being placed into one of the substrate processing chambers 108a-f, positioned in tandem sections 109a-c. A second robotic arm 110 may be used to transport the substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and back. Each substrate processing chamber 108a-f, can be outfitted to perform a number of substrate processing operations including plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, electroplating, electroless plating, etch (wet or dry), UV20 treatments, pre-clean, degas, orientation, and other substrate processes including, annealing, ashing, etc.

[0024] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, UV treating and / or etching a dielectric or other material on the substrate. In one configuration, two pairs of the processing chambers (e.g, 108c-d and 108e-f) may be used to deposit dielectric material on the substrate, and the third pair of processing chambers (e.g., 108a-b) may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (e.g., 108a-f) may be configured to deposit stacks of alternating dielectric materials on the substrate. Any one or more of the processes described may be carried out in chambers separated from the fabrication system shown in 30 different embodiments. It will be appreciated that additional configurations of deposition, etching, annealing, and UV treatment chambers for dielectric materials are contemplated by system 100.PCT / US25 / 21975 28 March 2025 (28.03.2025)

[0025] FIG. 2 shows a schematic cross-sectional view of an exemplary plasma system 200 according to some embodiments of the present technology. Plasma system 200 may illustrate a pair of processing chambers 108 that may be fitted in one or more of tandem sections 109 described above, and which may include lid stack components according to embodiments of the present technology, and as may be explained further below. The plasma system 200 generally may include a chamber body 202 having sidewalls 212, a bottom wall 216, and an interior sidewall 201 defining a pair of processing regions 220A and 220B. Each of the processing regions 220A-220B may be similarly configured, and may include identical components.

[0026] For example, processing region 220B, the components of which may also be included in processing region 220A, may include a pedestal 228 disposed in the processing region through a passage 222 formed in the bottom wall 216 in the plasma system 200. The pedestal 228 may provide a heater adapted to support a substrate 229 on an exposed surface of the pedestal, such as a body portion. The pedestal 228 may include heating elements 232, for example resistive heating elements, which may heat and control the substrate temperature at a desired process temperature. Pedestal 228 may also be heated by a remote heating element, such as a lamp assembly, or any other heating device.

[0027] The body of pedestal 228 may be coupled by a flange 233 to a stem 226. The stem 226 may electrically couple the pedestal 228 with a power outlet or power box 203. The power box 203 may include a drive system that controls the elevation and movement of the pedestal 228 within the processing region 220B. The stem 226 may also include electrical power interfaces to provide electrical power to the pedestal 228. The power box 203 may also include interfaces for electrical power and temperature indicators, such as a thermocouple interface. The stem 226 may include a base assembly 238 adapted to detachably couple with the power box 203. A circumferential ring 235 is show n above the power box 203. In some embodiments, the circumferential ring 235 may be a shoulder adapted as a mechanical stop or land configured to provide a mechanical interface between the base assembly 238 and the upper surface of the power box 203.

[0028] A rod 230 may be included through a passage 224 formed in the bottom wall 216 of the processing region 220B and may be utilized to position substrate lift pins 261 disposed through the body of pedestal 228. The substrate lift pins 261 may selectively space the substrate 229 from the pedestal to facilitate exchange of the substrate 229 with a robotPCT / US25 / 21975 28 March 2025 (28.03.2025)utilized for transferring the substrate 229 into and out of the processing region 220B through a substrate transfer port 260.

[0029] A chamber lid 204 may be coupled with a top portion of the chamber body 202. The lid 204 may accommodate one or more precursor distribution systems 208 coupled 5 thereto. The precursor distribution system 208 may include a precursor inlet passage 240 which may deliver reactant and cleaning precursors through a dual-channel showerhead 218 into the processing region 220B. The dual-channel showerhead 218 may include an annular base plate 248 having a blocker plate 244 disposed intermediate to a faceplate 246. A radio frequency (“RF”) source 265 may be coupled with the dual-channel showerhead 218, which may power the dual-channel showerhead 218 to facilitate generating a plasma region between the faceplate 246 of the dual-channel showerhead 218 and the pedestal 228. The dualchannel showerhead 218 and / or faceplate 246 may include one or more openings to permit the flow of precursors from the precursor distribution system 208 to the processing regions 220A and / or 220B. In some embodiments, the openings may include at least one of straight15 shaped openings and conical-shaped openings. In some embodiments, the RF source may be coupled with other portions of the chamber body 202, such as the pedestal 228, to facilitate plasma generation. A dielectric isolator 258 may be disposed between the lid 204 and the dual-channel showerhead 218 to prevent conducting RF power to the lid 204. A shadow ring 206 may be disposed on the periphery of the pedestal 228 that engages the pedestal 228. 20

[0030] An optional cooling channel 247 may be formed in the annular base plate 248 of the precursor distribution system 208 to cool the annular base plate 248 during operation. A heat transfer fluid, such as water, ethylene glycol, a gas, or the like, may be circulated through the cooling channel 247 such that the base plate 248 may be maintained at a predefined temperature. A liner assembly 227 may be disposed within the processing region 220B in close proximity to the sidewalls 201, 212 of the chamber body 202 to prevent exposure of the sidewalls 201, 212 to the processing environment within the processing region 220B. The liner assembly 227 may include a circumferential pumping cavity 225, which may be coupled to a pumping system 264 configured to exhaust gases and byproducts from the processing region 220B and control the pressure within the processing region 220B. A plurality of 30 exhaust ports 231 may be formed on the liner assembly 227. The exhaust ports 231 may be configured to allow the flow of gases from the processing region 220B to the circumferential pumping cavity 225 in a manner that promotes processing within the system 200.PCT / US25 / 21975 28 March 2025 (28.03.2025)

[0031] The chamber discussed previously may be used in performing exemplary methods including etching methods. Turning to FIG.3, exemplary operations in a method 300 according to embodiments of the present technology are illustrated. Method 300 may include one or more operations prior to the initiation of the method, including front end processing, 5 deposition, gate formation, etching, polishing, cleaning, or any other operations that may be performed prior to the described operations. The method may include a number of optional operations, which may or may not be specifically associated with some embodiments of methods according to the present technology. For example, many of the operations are described in order to provide a broader scope of the processes performed, but are not critical to the technology, or may be performed by alternative methodology as will be discussed further below. Method 300 may describe operations shown schematically in FIGS. 4A-4G, the illustrations of which will be described in conjunction with the operations of method 300. It is to be understood that the figures illustrate only partial schematic views, and a substrate may contain any number of additional materials and features having a variety of15 characteristics and aspects as illustrated in the figures.

[0032] FIG. 4A illustrates an exemplary structure 400 that may be processed in accordance with method 300. Structure 400 may include a substrate 405. Substrate 405 may be or contain silicon, silicon germanium, or some other semiconductor substrate material. A layer of silicon-containing material 410 may overlie the substrate 405. The layer of silicon- 20 containing material 410 may be any material in which a through silicon via (TSV) may be formed. For example, the layer of silicon-containing material 410 may be silicon, such as amorphous silicon, polysilicon, or a combination thereof. In embodiments, substrate 405 may be a carrier substrate and the layer of silicon-containing material 410 may be a substrate for a subsequent structure. The layer of silicon-containing material 410 may be characterized by a thickness of between about 1 pm and about 100 pm. For example, the layer of silicon- containing material 410 may be characterized by a thickness of greater than or about 1 pm, and may be characterized by a thickness of greater than or about 5 pm, greater than or about 10 pm, greater than or about 25 pm, greater than or about 50 pm, greater than or about 75 pm, greater than or about 100 pm, or more.30

[0033] A mask material 415 may overlie the layer of silicon-containing material 410. The mask material 415 may be any material that allows for selective etching of the layer of silicon-containing material 410. For example, the mask material 415 may be a photoresist, a metal-containing material, a dielectric material, such as another silicon-containing material,PCT / US25 / 21975 28 March 2025 (28.03.2025)or a combination of materials. The mask material 415 may be patterned, using any patterning technique, to form openings 420 in the mask material 415. While FIG. 4 A illustrates a single opening 420, any number of openings 420 may be formed in the mask material 415 across the structure 400. The opening 420 may be characterized by any shape and may dictate the profile that is transferred when etching into the underlying layer of silicon-containing material 410. In embodiments, the opening 420 may be characterized by a circular shape. A critical dimension, or diameter, of the openings 420 may be between about 0.1 pm and about 10 pm. For example, a critical dimension of the openings 420 may be greater than or about 0.2 pm, and may be greater than or about 0.5 pm, greater than or about 1 pm, greater than or about 2 pm, greater than or about 3 pm, greater than or about 4 pm, greater than or about 5 pm, greater than or about 6 pm, greater than or about 7 pm, greater than or about 8 pm, greater than or about 9 pm, greater than or about 10 pm, or more. Conversely, a critical dimension of the openings 420 may be less than or about 10 pm, and may be greater than or about 9 pm, less than or about 8 pm, and may be greater than or about 7 pm, less than or about 6 pm, and may be greater than or about 5 pm, less than or about 4 pm, and may be greater than or about 3 pm, less than or about 2 pm, and may be greater than or about 1 pm, less than or about 0.5 pm, and may be greater than or about 0.2 pm, or less.

[0034] Method 300 may include metal-assisted chemical etching (MACE) operations to form features, such as through silicon vias (TSVs), in silicon-containing materials. In embodiments, method 300, as illustrated in FIG. 4B, may include depositing a metalcontaining material 425 on the substrate 405 at operation 305. As illustrated in FIG. 4C, Method 300 may include perforating the metal-containing material 425 to form apertures 430, or pores, in the metal-containing material 425 at optional operation 310. At operation 315, as illustrated in FIG. 4D, method 300 may include submerging the substrate 405 in a first etchant solution to perform a MACE of the layer of silicon-containing material 410. As illustrated in FIG. 4E, method 300 may include stripping the mask material 415 overlying the layer of silicon-containing material 410 at optional operation 320. At optional operation 325, as illustrated in FIG. 4F, method 300 may include stripping the metal-containing material 425 from the substrate 405. Finally, as illustrated in FIG. 4G, at optional operation 330, method 300 submerging the substrate 405 in a second etchant solution to remove remaining silicon-containing material 410 within the one or more features 435.

[0035] As previously discussed, method 300 may include depositing the metal-containing material 425 on the substrate 405 at operation 305. The metal-containing material 425 mayPCT / US25 / 21975 28 March 2025 (28.03.2025)be deposited using any number of processes. For example, the metal-containing material 425 may be deposited through atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electroless plating, electroplating, or inkjet printing.Additionally, the metal-containing material 425 may be a multi-metal material. As such, the 5 metal-containing material 425 may be deposited as an alloy. Some deposition processes may form a continuous metal-containing material 425, such as the metal-containing material 425 illustrated in FIG. 4B. However, it is also contemplated that the deposition processes may form a discontinuous metal-containing material 425. That is, the metal-containing material 425 may be deposited such that it is already porous, as illustrated in FIG. 4C.

[0036] As illustrated in both FIGS 4B and 4C, the metal-containing material 425 may be deposited on all exposed surfaces. For example, in the exemplary structure 400, the metalcontaining material 425 may be deposited on both the layer of silicon-contaimng material 410 and the mask material 415. However, it is also contemplated that the metal-containing material 425 may be selectively formed on only the layer of silicon-containing material 410 15 and not the mask material 415 or other structures that may be present in structure 400.

[0037] The metal-containing material 425 may be or include any metal useful in MACE of silicon-containing material, such as the layer of silicon-containing material 410. For example, the metal-containing material 425 may be or include gold (Au), silver (Ag), platinum (Pt), copper (Cu), or any other metal material that may serve as a catalyst to etch the 20 layer of silicon-containing material 410. In embodiments, the metal-containing material 425 may be a multi-metal material including a plurality of metals. For example, the metalcontaining material 425 may include two metals, such that one metal may subsequently be removed to form a porous metal -containing material 425. As further discussed below, the metal-containing material 425 including two or more metals may be de-alloyed by selective etching or removal of one or more metals relative to one or more remaining metals in the metal-containing material 425. One exemplary alloyed metal-containing material 425 may be AuCu, where Cu my subsequently be removed to form a porous metal-containing material 425.

[0038] The metal-containing material 425 may be characterized by a thickness of between 30 about 10 nm and about 100 nm. For example, the metal-containing material 425 may be characterized by a thickness of greater than or about 10 nm, and may be characterized by a thickness of greater than or about 20 nm, greater than or about 30 nm, greater than or aboutPCT / US25 / 21975 28 March 2025 (28.03.2025)40 nm, greater than or about 50 nm, greater than or about 60 nm, greater than or about 70 nm, greater than or about 80 nm, greater than or about 90 nm, greater than or about 100 nm, or more. Conversely, the metal-containing material 425 may be characterized by a thickness of less than or about 100 nm, and may be characterized by a thickness of less than or about 90 5 nm, less than or about 80 nm, less than or about 70 nm, less than or about 60 nm, less than or about 50 nm, less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, or less.

[0039] In embodiments, deposition of the metal-containing material 425 may be tuned / optimized such that the metal -containing material 425 is deposited as a perforated or discontinuous layer. As illustrated in FIG. 4C, the metal -containing material 425 may be as- deposited defining apertures 430 in the metal-containing material 425. The apertures 430 may extend from an upper surface of the metal-containing material 425 to a lower surface of the metal-containing material 425 opposite the upper surface of the metal-containing material 425. As such, the apertures 430 in the metal-containing material 425 may expose the layer of 15 silicon-containing material 410 and / or the mask material 415. However, it is also contemplated that metal -containing material 425 may be deposited as a continuous layer, which may ensure complete coverage of the metal-containing material 425 on the layer of silicon-containing material 410.

[0040] If deposited as a continuous layer, the metal-containing material 425 may be 20 perforated or patterned at optional operation 310. As illustrated in FIG. 4C, perforating the metal-containing material 425 may form apertures 430.

[0041] Perforating the metal-containing material 425 to form apertures 430 may include contacting the structure 400, including the metal-containing material 425, with an inert plasma. For example, an inert gas may be provided to a processing region of a semiconductor processing chamber housing the substrate 405. Alternatively, the inert gas may be provided to a remote processing region of the semiconductor processing chamber housing the substrate 405. The remote plasma processing region may be fluidly coupled to the processing region housing the substrate 405. Whether provided to the processing region or the remote processing region, plasma effluents of the inert gas may be formed. The 30 plasma effluents of the inert gas may then be provided to the substrate 405, such that the metal-containing material 425 is bombarded by the plasma effluents of the inert gas. In embodiments, a bias power may be applied during optional operation 310 to increasedPCT / US25 / 21975 28 March 2025 (28.03.2025)directionality and bombardment by the plasma effluents of the inert gas. The bombardment may sputter the metal-containing material 425, which may form the aperture 430 in the metal-containing material 425.

[0042] Alternatively, in embodiments in which the metal-containing material 425 may include two or more metals (z.e., alloyed metal -containing material), one (or less than all the metals) may be selectively removed. For example, various methods (e.g., chemical precipitation, solvent extraction, ion exchange, electrodialysis, adsorption, etc.) may be performed to selectively remove one (or less than all the metals) from a matrix defining the metal-containing material 425 having two or more metals. The resultant structure may be a porous metal-containing material 425 defining one or more apertures 430. While apertures 430 may not be perfectly uniform in such an embodiment, the apertures 430 may still define passageways from the upper surface of the metal-containing material 425 to the lower surface of the metal-containing material 425, such that etchant species in the subsequent MACE may reach the layer of silicon-containing material 410. Deposition and patterning of the metalcontaining material 425 may be configured such that the apertures 430 have adequate dimensions for allowing etchant species to pass through the metal -containing material 425. Additionally, porosity and / or other characteristics of the metal -containing material 425 can be tuned / optimized based on adjusting the alloy composition.

[0043] Whether formed as-deposited during the deposition at operation 305 or formed after deposition at optional operation 310, the metal-containing material 425 defining the apertures 430 may be charactenzed by a critical dimension, such as a diameter or other measurement, of greater than or about 100 nm, and may be may be charactenzed by a critical dimension of greater than or about 150 nm, greater than or about 200 nm, greater than or about 250 nm, greater than or about 300 nm, greater than or about 350 nm, greater than or about 400 nm, greater than or about 450 nm, greater than or about 500 nm, or more. At reduced critical dimensions, the subsequent MACE may randomize, as the metal-containing material 425 may not be large enough to specifically control how the etch proceeds. Conversely, at increased critical dimensions, the MACE be characterized by a reduced etch rate, as an etchant may not be readily able to reach middle portions under the metal -containing material 425. Instead, the etchant may only be able to reach the underlying material at a perimeter of the metal-containing material 425. As such, the metal-containing material 425 defining the apertures 430 may be characterized by a cntical dimension of less than or about 2 pm, and may be characterized by a critical dimension of less than or about 1.5 pm, less than or aboutPCT / US25 / 21975 28 March 2025 (28.03.2025)1 pm, less than or about 900 nm, less than or about 800 nm, less than or about 750 nm, less than or about 700 nm, less than or about 650 nm, less than or about 600 nm, less than or about 550 nm, less than or about 500 nm, or less.

[0044] The metal-containing material 425 defining the apertures 430, or individual portions 5 of the discontinuous metal-containing material 425, may be characterized by an area of greater than or about 0.1 pm2. At reduced areas, the subsequent MACE may randomize and not form a uniform feature in the layer of silicon-containing material 410. As such, the metal-containing material 425 defining the apertures 430 may be characterized by an area of greater than or about 0.2 pm2, and may be characterized by an area of greater than or about 10 0.25 pm2, greater than or about 0.3 pm2, greater than or about 0.35 pm2, greater than or about 0.4 pm2, greater than or about 0.45 pm2, greater than or about 0.5 pm2, greater than or about 0.75 pm2, greater than or about 1 pm2, or more. Additionally, the metal-containing material 425 defining the apertures 430, or individual portions of the discontinuous metal-containing material 425, may be characterized by a discontinuity of greater than or about 40%. Again, at 15 reduced discontinuities, the subsequent MACE may randomize and not form a uniform feature in the layer of silicon-containing material 410. As such, metal-containing material 425 defining the apertures 430 may be characterized by a discontinuity of greater than or about 45%, and may be characterized by a discontinuity of greater than or about 50%, greater than or about 55%, greater than or about 60%, greater than or about 65%, greater than or 20 about 70%, greater than or about 75%, or more.

[0045] At operation 315, method 300 may include submerging the substrate 405 in the first etchant solution. As previously discussed, the first etchant solution may perform MACE of the layer of silicon-containing material 410 on the substrate 405. As illustrated in FIG. 4D, the MACE may form one or more features 435 in the layer of silicon-containing material 410. While FIGS. 4D-4G illustrate the formation of a single feature 435, which may be consistent with opening 420 in the mask material 415, any number of features 435 may be formed in the layer of silicon-containing material 410 across the structure 400.

[0046] The first etchant solution may include an etchant and an oxidizer. The etchant may be any compound or solution operable to etch silicon-containing material. In embodiments, 30 the etchant may be a halogen-containing material, such as a fluorine-containing material.Exemplary fluorine-containing materials may be or include hydrogen fluoride (HF), ammonium fluoride (NH4F), or any other fluorine-containing materials suitable for etchingPCT / US25 / 21975 28 March 2025 (28.03.2025)silicon-containing material. Exemplar}' oxidizers may be or include hydrogen peroxide (H2O2), nitric acid (HNOs), or any other oxidizer.

[0047] In addition to the etchant and the oxidizer, other components may be present in the etchant solution. While the etchant and the oxidizer may be mixed with water (H2O), such as deionized H2O, additional compounds, such as potassium chloride (KC1), potassium hydroxide (KOH), diatomic bromine (Bn), diatomic iodine (I2), sodium iodide (Nal), and / or sodium hydroxide (NaOH), for example, may be included in the first etchant solution.

[0048] During MACE of the layer of silicon-containing material 410, multiple individual reactions may be occurring. For example, at the metal-containing material 425, the oxidizer may be reduced. In the case of H2O2 as the oxidizer, a first reaction may be H2O2 + 2 H+2 H2O + 2 h+. The created holes (h+) are then consumed during the dissolution of the layer of silicon-containing material 410. These holes weaken chemical bonds at the layer of silicon-containing material 410 / first etchant solution interface. As such, dissolution of the layer of silicon-containing material 410 with the etchant takes place. There are several possible reactions via which the dissolution can take place. In the case of HF as the etchant, a second reaction may be: Si + 6 HF + 4 h+— ► SiFe2-+ 6 H+.

[0049] Concentrations of the etchant and the oxidizer may impact the MACE. If a concentration of the oxidizer is too low, chemical bonds in the layer of silicon-containing material 410 may not be sufficiently weakened throughout, resulting in a slower dissolution of the layer of silicon-containing material 410. If a concentration of the oxidizer is too high, chemical bonds in the layer of silicon-containing material 410 may be weakened throughout to an excessive degree, resulting in a faster dissolution of the layer of silicon-containing material 410. Similarly, if a concentration of the etchant is too low, the layer of silicon-containing material 410 may be dissolved at a slower rate. Conversely, if a concentration of the etchant is too high, the layer of silicon-containing material 410 may be dissolved at a faster rate. While an increased rate of dissolution may be preferable, it is also preferable to control the rate of dissolution to maintain control of the MACE.

[0050] In embodiments, a concentration of the etchant may be between about 0.2 M and about 50 M. For example, the etchant may be characterized by a concentration of greater than or about 0.2 M, and may be characterized by a concentration of greater than or about 0.5 M, greater than or about 1 M, greater than or about 2 M, greater than or about 3 M, greater than or about 4 M, greater than or about 5 M, greater than or about 6 M, greater than or aboutPCT / US25 / 21975 28 March 2025 (28.03.2025)7 M, greater than or about 8 M, greater than or about 9 M, greater than or about 10 M, greater than or about 15 M, greater than or about 20 M, greater than or about 25 M, greater than or about 30 M, greater than or about 35 M, greater than or about 40 M, greater than or about 45 M, greater than or about 50 M, or more. Conversely, the concentration of the etchant less than or about 50 M, and may be characterized by a concentration of less than or about 45 M, less than or about 40 M, less than or about 35 M, less than or about 30 M, less than or about 25 M, less than or about 20 M, less than or about 15 M, less than or about 10 M, less than or about 9 M, less than or about 8 M, less than or about 7 M, less than or about 6 M, less than or about 5 M, less than or about 4 M, less than or about 3 M, less than or about 2 M, less than or about 1 M, less than or about 0.5 M, less than or about 0.2 M, or less.

[0051] A concentration of the oxidizer may be between about 0.02 M and about 5 M. For example, the oxidizer may be characterized by a concentration of greater than or about 0.02 M, and may be characterized by a concentration of greater than or about 0.05 M, greater than or about 0.1 M, greater than or about 0.2 M, greater than or about 0.3 M, greater than or about 0.4 M, greater than or about 0.5 M, greater than or about 0.6 M, greater than or about 0.7 M, greater than or about 0.8 M, greater than or about 0.9 M, greater than or about 1 M, greater than or about 1.5 M, greater than or about 2.0 M, greater than or about 2.5 M, greater than or about 3.0 M, greater than or about 3.5 M, greater than or about 4.0 M, greater than or about 4.5 M, greater than or about 5.0 M, or more. Conversely, the concentration of the oxidizer may be less than or about 5.0 M, and may be less than or about 4.5 M, less than or about 4.0 M, less than or about 3.5 M, less than or about 3.0 M, less than or about 2.5 M, less than or about 2.0 M, less than or about 1.5 M, less than or about 1.0 M, less than or about 0.9 M, less than or about 0.8 M, less than or about 0.7 M, less than or about 0.6 M, less than or about 0.5 M, less than or about 0.4 M, less than or about 0.3 M, less than or about 0.2 M, less than or about 0.1 M, less than or about 0.05 M, less than or about 0.02 M, or less.

[0052] As previously discussed, concentrations of the etchant and the oxidizer may impact weakening of chemical bonds in the layer of silicon-containing material 410 and subsequent dissolution of the layer of silicon-containing material 410. While the oxidizer may independently impact weakening of chemical bonds in the layer of silicon-containing material 410 and the etchant may independently impact dissolution of the layer of silicon-containing material 410, a ratio between the etchant and the oxidizer may balance the weakening of chemical bonds and subsequent dissolution. As such, in embodiments, a ratio of the concentration of the etchant to the concentration of the oxidizer, or a concentrationPCT / US25 / 21975 28 March 2025 (28.03.2025)ratio, may be between about 2: 1 and about 50:1. In embodiments, the ratio of the concentration of the etchant to the concentration of the oxidizer may be greater than or about 2 : 1 , and may be greater than or about 4 : 1 , greater than or about 5 : 1 , greater than or about 6 : 1 , greater than or about 7:1, greater than or about 8:1, greater than or about 9:1, greater than or about 10: 1, greater than or about 11:1, greater than or about 12:1, greater than or about 13:1, greater than or about 14: 1, greater than or about 15:1, greater than or about 20: 1, greater than or about 25 : 1 , greater than or about 30:1, greater than or about 35:1, greater than or about 40: 1, greater than or about 45: 1, greater than or about 50: 1, or more. Conversely, the ratio of the concentration of the etchant to the concentration of the oxidizer may be less than or about 50: 1, and may be less than or about 45: 1, less than or about 40: 1, less than or about 35:1, less than or about 30: 1, less than or about 25:1, less than or about 20: 1, less than or about 15:1, less than or about 14:1, less than or about 13:1, less than or about 12: 1, less than or about 11:1, less than or about 10:1, less than or about 9:1, less than or about 8:1, less than or about 7:1, less than or about 6:1, less than or about 5:1, less than or about 4:1, less than or about 2:1, or less.

[0053] A temperature of the first etchant solution may be between about 0 °C and about 150 °C. For example, the temperature of the first etchant solution may be greater than or about 0 °C, and may be greater than or about 10 °C, greater than or about 15 °C, greater than or about 20 °C, greater than or about 25 °C, greater than or about 30 °C, greater than or about 40 °C, greater than or about 50 °C, greater than or about 75 °C, greater than or about 100 °C, greater than or about 125 °C, greater than or about 150 °C, or more. Conversely, the temperature of the first etchant solution may be less than or about 150 °C, and may be less than or about 125 °C, less than or about 100 °C, less than or about 75 °C, less than or about 40 °C, less than or about 50 °C, less than or about 30 °C, less than or about 25 °C, less than or about 20 °C, less than or about 15 °C, less than or about 10 °C, less than or about 5 °C, or less. In embodiments, the temperature of the first etchant solution may be maintained at room temperature, which may simplify method 300.

[0054] An etch rate of the layer of sili con-containing material 410 may be between about 0.1 pm / minute and about 2.0 pm / minute. For example, the etch rate of the layer of silicon-containing material 410 may be greater than or about 0.2 pm / minute, greater than or about 0.4 pm / minute, greater than or about 0.6 pm / minute, greater than or about 0.8 pm / minute, greater than or about 1 pm / minute, greater than or about 1.2 pm / minute, greater than or aboutPCT / US25 / 21975 28 March 2025 (28.03.2025)1.4 pm / minute, greater than or about 1.6 pm / minute, greater than or about 1.8 pm / minute, greater than or about 2 pm / minute, or more. In embodiments, the etch rate of the layer of silicon-containing material 410 may be maintained constant along a depth of the one or more features 435.

[0055] While the etch rate may seem slower than conventional processes, such as a Bosch process, the present technology may be able to process numerous structures, such as structure 400, in a single batch. For example, the present technology, depending on a volume of the first etchant solution, may be able to process greater than or about 2 structures, greater than or about 4 structures, greater than or about two structures, greater than or about 5 structures, greater than or about 10 structures, greater than or about 15 structures, greater than or about 20 structures, greater than or about 25 structures, or more.

[0056] At optional operation 320, and as illustrated in FIG. 4E, method 300 may include stripping the mask material 415 overlying the layer of silicon-containing material 410. While illustrated and discussed as being removed after the MACE at operation 315, it is also contemplated that the mask material 415 may be removed prior to the MACE at operation 315. Since the MACE may selectively etch the layer of silicon-containing material 410 underlying the metal-containing material 425, removal of the mask material 415 prior to the MACE at operation 315 may not impact the MACE or profile of the features 435 etched into the layer of silicon-containing material 410.

[0057] As illustrated in FIG. 4F, after the MACE at operation 315 and, optionally, stripping of the mask material 415 at optional operation 320, method 300 may include stripping the metal-containing material 425 from the substrate 405 at optional operation 325. Stripping the metal-containing material 425 from the substrate 405 may be performed using any of the previously-discussed methods for removing metal (e.g, chemical precipitation, solvent extraction, ion exchange, electrodialysis, adsorption, etc.).

[0058] In embodiments, as illustrated in FIGS. 4D-4F, depending on the structure of the metal-containing material 425 and / or the MACE, a portion of the layer of the silicon-containing material 410 may be present in the features 435. This remaining portion of the layer of the silicon-containing material 410 may be finger-like or referred to as “grass”. In embodiments, one or more of the deposition of the metal-containing material 425 at operation 305, perforating of the metal-containing material 425 at optional operation 310, and / or the MACE at operation 315 may be tuned / optimized to reduce and / or prevent the formation ofPCT / US25 / 21975 28 March 2025 (28.03.2025)this remaining portion of the layer of the sihcon-containing material 410, as illustrated in FIG. 4F. However, if the remaining portion of the layer of the silicon-containing material 410 is present, method 300 may include submerging the substrate 405 in a second etchant solution at optional operation 330.

[0059] As illustrated in FIG. 4G, submerging the substrate 405 in the second etchant solution at optional operation 330 may remove remaining portion of the layer of the sihcon-containing material 410 (i.e., the remaining “grass”). The second etchant solution may be the same, similar to, or include any of the compounds previously discussed with regard to the first etchant solution. In embodiments, the second etchant solution may include KOH.However, without the presence of the metal-containing material 425 and / or the mask material 415, the second etchant solution may non-selectively etch the layer of silicon-containing material. As such, the submersion in the second etchant solution may be brief to ensure only the remaining portion of the layer of the silicon-containing material 410 in the one or more features 435 is removed.

[0060] In embodiments, the one or more features 435, such as those illustrated in FIG. 4G, may be characterized by an aspect ratio, or ratio of length to width / diameter, of greater than or about 15:1, and may be characterized by an aspect ratio of greater than or about 20:1, greater than or about 25:1, greater than or about 30: 1, greater than or about 40: 1, greater than or about 50:1, greater than or about 75:1, greater than or about 100:1, greater than or about 125:1, greater than or about 150:1, greater than or about 200:1, ormore. The one or more features 435 may be characterized by a depth of greater than or about 100 nm, and may be characterized by a depth of greater than or about 200 nm, greater than or about 300 nm, greater than or about 400 nm, greater than or about 500 nm, greater than or about 750 nm, greater than or about 1 pm, greater than or about 1.5 pm, greater than or about 2 pm, greater than or about 2.5 pm, greater than or about 3 pm, greater than or about 3.5 pm, greater than or about 4 pm, greater than or about 4.5 pm, greater than or about 5 pm, greater than or about 10 pm, greater than or about 25 pm, greater than or about 50 pm, greater than or about 75 pm, greater than or about 100 pm, or more.

[0061] In embodiments, method 300 may be performed in a number of semiconductor processing chambers. For example, depositing the metal-containing material 425 on the substrate at operation 305 may be performed in a first semiconductor processing chamber, such as plasma system 200, which as previously discussed may illustrate a pair of processingPCT / US25 / 21975 28 March 2025 (28.03.2025)chambers 108. Perforating the metal-containing matenal 425 at optional operation 310 may be performed in the first semiconductor processing chamber, or the substrate 405 may be transferred to a second semiconductor processing chamber. The substrate may then be transferred to a third semiconductor processing chamber housing the first etchant solution to 5 perform the MACE at operation 315. Another semiconductor processing chamber may be used to perform the stripping of the mask material 415 and the metal-containing material 425 at optional operations 320 and 325, respectively. Finally, another semiconductor processing chamber may house the second etchant solution used for the etching at optional operation 330. While any of the semiconductor processing chambers may be used for multiple operations, it is also contemplated that each semiconductor processing chamber be used for only a single operation.

[0062] The present technology may have numerous benefits compared to conventional processes, such as a Bosch process. For example, the present technology may not be characterized by a loading effect, may maintain a constant etch rate along a depth of the 15 features being etched, may have a high etching selectivity (e.g., relative to the mask material 415 or other exposed materials), may be able to achieve a very high aspect ratio, may not have scalloping issues, and may have very high throughput.

[0063] In the preceding description, for the purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present 20 technology. It will be apparent to one skilled in the art, however, that certain embodiments may be practiced without some of these details, or with additional details.

[0064] Having disclosed several embodiments, it will be recognized by those of skill in the art that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. Additionally, a number of well-known processes and elements have not been described in order to avoid unnecessarily obscuring the present technology. Accordingly, the above description should not be taken as limiting the scope of the technology.

[0065] Where a range of values is provided, it is understood that each intervening value, to the smallest fraction of the unit of the lower limit, unless the context clearly dictates 30 otherwise, between the upper and lower limits of that range is also specifically disclosed.Any narrower range between any stated values or unstated intervening values in a stated range and any other stated or intervening value in that stated range is encompassed. ThePCT / US25 / 21975 28 March 2025 (28.03.2025)upper and lower limits of those smaller ranges may independently be included or excluded in the range, and each range where either, neither, or both limits are included in the smaller ranges is also encompassed within the technology, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included. "About" and / or “approximately” as used herein when referring to a measurable value such as an amount, a temporal duration, and the like, encompasses variations of ±20% or ±10%, ±5%, or ±0.1% from the specified value, as such variations are appropriate to in the context of the systems, devices, circuits, methods, and other implementations described herein. “Substantially” as used herein when referring to a measurable value such as an amount, a temporal duration, a physical attribute (such as frequency), and the like, also encompasses variations of ±20% or ±10%, ±5%, or ±0.1% from the specified value, as such variations are appropriate to in the context of the systems, devices, circuits, methods, and other implementations described herein.

[0066] As used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural references unless the context clearly dictates otherwise. Thus, for example, reference to “a layer” includes a plurality of such layer, and reference to “the precursor” includes reference to one or more precursors and equivalents thereof known to those skilled in the art, and so forth.

[0067] Also, the words “comprise(s)”, “comprising”, “contain(s)”, “containing”, “include(s)”, and “including”, when used in this specification and in the following claims, are intended to specify the presence of stated features, integers, components, or operations, but they do not preclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

Claims

PCT / US25 / 21975 28 March 2025 (28.03.2025)CLAIMS:

1. A semiconductor processing method comprising:depositing a metal-containing material on a substrate, wherein a layer of silicon-containing material overlies the substrate and a patterned mask material overlies the layer of silicon-containing material;perforating the metal -containing material to form pores in the metal -containing material; andsubmerging the substrate in a first etchant solution to perform a metal-assisted chemical etching of the layer of silicon-containing material, wherein the metal-assisted chemical etching forms one or more features in the layer of silicon-containing material.

2. The semiconductor processing method of claim 1, wherein the metalcontaining material is deposited on the substrate through atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electroless plating, electroplating, or inkjet printing.

3. The semiconductor processing method of claim 1, wherein the metalcontaining material comprises gold (Au), silver (Ag), or platinum (Pt).

4. The semiconductor processing method of claim 1, wherein the metalcontaining material is characterized by a thickness of less than or about 100 nm.

5. The semiconductor processing method of claim 1, wherein perforating the metal-containing material to form pores in the metal-containing material comprises contacting the metal-containing material with an inert plasma.

6. The semiconductor processing method of claim 1, wherein:the metal-containing material comprises two or more metals, and perforating the metal -containing material to form pores in the metalcontaining material comprises selectively removing at least one of the two or more metals from the metal-containing material.

7. The semiconductor processing method of claim 1, further comprising:stripping the patterned mask material overlying the layer of silicon-containing material.PCT / US25 / 21975 28 March 2025 (28.03.2025)8. The semiconductor processing method of claim 1, wherein the first etchant solution comprises an etchant and an oxidizer.

9. The semiconductor processing method of claim 8, wherein the etchant of the first etchant solution comprises hydrogen fluoride (HF) at a concentration of between about 0.2 M and about 50 M.

10. The semiconductor processing method of claim 8, wherein the oxidizer of the first etchant solution comprises hydrogen peroxide (H2O2) at a concentration of between about 0.02 M and about 5 M.

11. The semiconductor processing method of claim 1, wherein the one or more features are characterized by an aspect ratio of greater than or about 15:1.

12. The semiconductor processing method of claim 1, further comprising: subsequent to submerging the substrate in the first etchant solution to perform the metal-assisted chemical etching of the layer of silicon-containing material, submerging the substrate in a second etchant solution to remove remaining silicon-containing material within the one or more features.

13. The semiconductor processing method of claim 1, wherein an etch rate of the layer of silicon-containing material is maintained constant along a depth of the one or more features.

14. A semiconductor processing method comprising:depositing a discontinuous metal-containing material on a substrate, wherein a layer of silicon-containing material overlies the substrate and a patterned mask material overlies the layer of silicon-containing material; andsubmerging the substrate in a first etchant solution to perform a metal-assisted chemical etching of the layer of silicon-containing material, wherein the metal-assisted chemical etching forms one or more features in the layer of silicon-containing material.

15. The semiconductor processing method of claim 14, wherein portions of the discontinuous metal-containing material are characterized by an area of greater than or about 0.1 pm2.PCT / US25 / 21975 28 March 2025 (28.03.2025)16. The semiconductor processing method of claim 14, wherein the discontinuous metal-containing material is characterized by a discontinuity of greater than or about 40%.

17. The semiconductor processing method of claim 14, wherein a 5 concentration ratio of an etchant to an oxidizer in the first etchant solution is between about 2:1 and about 50:1.

18. A semiconductor processing method comprising:depositing a metal-containing material on a substrate, wherein a layer of silicon-containing material overlies the substrate and a patterned mask material overlies the 10 layer of silicon-containing material;perforating the metal -containing material to form pores in the metal - containing material;submerging the substrate in a first etchant solution to perform a metal-assisted chemical etching of the layer of silicon-containing material, wherein the metal-assisted chemical etching forms one or more features in the layer of silicon-containing material;stripping the metal-containing material from the substrate; and submerging the substrate in a second etchant solution to remove remaining silicon-containing material within the one or more features.

19. The semiconductor processing method of claim 18, wherein the one or 20 more features are characterized by a depth of greater than or about 3 pm.

20. The semiconductor processing method of claim 18, wherein the second etchant solution comprises potassium hydroxide (KOH).

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