Selective deposition onto doped si and SIGE for inner spacer formation in gate-all-around (GAA) device

Abstract

Described is a method of forming a semiconductor device which includes selectively removing a plurality of semiconductor material layers from a film stack on a substrate to form a plurality of openings adjacent to a plurality of channel layers. The film stack includes the plurality of channel layers and the plurality of semiconductor material layers alternatingly arranged and extending between a source / drain (S / D) epitaxial (epi) layer and doped source / drain (S / D) epitaxial (epi) liner on the substrate. The film stack is pre-cleaned to remove oxides and form a plurality of reduced channel layers and a reduced doped S / D epi liner. The substrate is exposed to an inhibitor compound to passivate the reduced channel layers selectively over oxidized surfaces of the doped S / D epi liner. An inner spacer is formed on the non-passivated surfaces of the doped S / D epi liner.

Description

Attorney Docket No.: 44027828WO01 PATENT1SELECTIVE DEPOSITION ONTO DOPED SI AND SIGE FOR INNER SPACER FORMATION IN GATE-ALL-AROUND (GAA) DEVICETECHNICAL FIELD

[0001] Embodiments of the present disclosure generally pertain to the field of semiconductor devices and semiconductor device manufacturing. More particularly, embodiments of the present disclosure relate to forming an inner spacer in transistors, e.g., gate-all-around devices (GAA), field-effect transistors (FinFETs), and complementary field effect transistors (CFETs).BACKGROUND

[0002] Integrated circuits have evolved into complex devices that can include millions of transistors, capacitors, and resistors on a single chip. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.

[0003] The transistor is a key component of most integrated circuits. Since the drive current, and therefore speed, of a transistor is proportional to the gate width of the transistor, faster transistors generally require larger gate width. Thus, there is a tradeoff between transistor size and speed, and "fin" field-effect transistors (FinFETs) have been developed to address the conflicting goals of a transistor having maximum drive current and minimum size. FinFETs are characterized by a fin-shaped channel region that greatly increases the size of the transistor without significantly increasing the footprint of the transistor and are now being applied in many integrated circuits. FinFETs, however, have their own drawbacks.

[0004] Gate-all-around (GAA) FETs provide design flexibility, low operational voltage, high drive currents, high computational speed, and excellent performance within a smaller footprint area. In a GAA nanosheet structure, an inner spacer may be introduced to improve parasitic capacitance between source / drain (S / D) epitaxial layers and metal gates. This structure, however, causes a challenge in fabrication of high-quality defect free source / drain (S / D) epitaxial layers, especially in p-type FET devices where silicon germanium (SiGe) source / drain (S / D) epitaxial layers typically increaseAttorney Docket No.: 44027828WO01 PATENT2strain in silicon (Si) channel layers. In the presence of inner spacer layers (e.g., silicon nitride), however the grown epitaxial layers are defective and there is no strain in the film.

[0005] Thus, there is a need in the art for devices and methods of manufacture to produce defect-free epaxial growth of source / drain epitaxial layers and form high-quality inner spacers in transistor structures.SUMMARY

[0006] Embodiments of the disclosure are directed to methods of forming a semiconductor device. In one or more embodiments, a method of forming a semiconductor device comprises: exposing a substrate to an inhibitor compound to selectively passivate surfaces of a plurality of channel layers over surfaces of a doped source / drain epitaxial (epi) liner, the inhibitor compound comprising one or more of a silanol, an alcohol, an alkyne, or an alkene; and forming an inner spacer on the doped S / D epi liner.

[0007] Further embodiments of the disclosure are directed to methods of forming a semiconductor device. In one or more embodiments, a method of forming a semiconductor device comprises: selectively removing a plurality of semiconductor material layers from a film stack on a substrate to form a plurality of openings adjacent a plurality of channel layers, the film stack comprising the plurality of channel layers and the plurality of semiconductor material layers alternatingly arranged and extending between a source / drain (S / D) epitaxial (epi) layer and doped source / drain (S / D) epitaxial (epi) liner on the substrate; pre-cleaning a film stack on a substrate to remove oxides and form a plurality of reduced channel layers and a reduced doped S / D epi liner; selectively forming an oxide on a portion of the reduced doped S / D epi liner to form an oxidized doped S / D epi liner; exposing the substrate to an inhibitor compound to passivate the reduced channel layers and the reduced doped S / D epi liner; and forming an inner spacer on the doped S / D epi liner.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] So that the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarizedAttorney Docket No.: 44027828WO01 PATENT3above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope.

[0009] FIG. 1 illustrates a process flow diagram of a method of forming a 3D DRAM device according to one or more embodiments;

[0010] FIG. 2A illustrates a schematic cross-sectional view of a portion of a substrate being processed according to the method of one or more embodiments;

[0011] FIG. 2B illustrates a schematic cross-sectional view of a portion of a substrate being processed according to the method of one or more embodiments;

[0012] FIG. 2C illustrates a schematic cross-sectional view of a portion of a substrate being processed according to the method of one or more embodiments; and

[0013] FIG. 3 illustrates a cluster tool according to one or more embodiments.

[0014] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.DETAILED DESCRIPTION

[0015] Before describing several exemplary embodiments of the disclosure, it is to be understood that the disclosure is not limited to the details of construction or process steps set forth in the following description. The disclosure is capable of other embodiments and of being practiced or being carried out in various ways.

[0016] The term "about" as used herein means approximately or nearly and in the context of a numerical value or range set forth means a variation of ±15% or less, of the numerical value. For example, a value differing by ±14%, ±10%, ±5%, ±2%, ±1%, ±0.5%, or ±0.1% would satisfy the definition of about.

[0017] In the following description, numerous specific details, such as specific materials, chemistries, dimensions of the elements, etc. are set forth in order to provide thorough understanding of one or more of the embodiments of the present disclosure. It will be apparent, however, to one of ordinary skill in the art that the one or more embodiments of the present disclosure may be practiced without these specific details.Attorney Docket No.: 44027828WO01 PATENT4In other instances, semiconductor fabrication processes, techniques, materials, equipment, etc., have not been described in great detail to avoid unnecessarily obscuring this description. Those of ordinary skill in the art, with the included description, will be able to implement appropriate functionality without undue experimentation.

[0018] While certain exemplary embodiments of the disclosure are described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative and not restrictive of the current disclosure, and that this disclosure is not restricted to the specific constructions and arrangements shown and described because modifications may occur to those ordinarily skilled in the art.

[0019] As used in this specification and the appended claims, the terms "precursor", "reactant", "reactive gas", and the like are used interchangeably to refer to any gaseous species that can react with the substrate surface.

[0020] A "substrate" as used herein, refers to any substrate or material surface formed on a substrate upon which film processing is performed during a fabrication process. For example, a substrate surface on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxides, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, without limitation, semiconductor wafers. Substrates may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the film processing steps disclosed may also be performed on an under-layer formed on the substrate as disclosed in more detail below, and the term "substrate surface" is intended to include such under-layer as the context indicates. Thus, for example, where a film / layer or partial film / layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0021] According to one or more embodiments, the term "on", with respect to a film or a layer of a film, includes the film or layer being directly on a surface, for example, a substrate surface, as well as there being one or more underlayers between the film orAttorney Docket No.: 44027828WO01 PATENT5layer and the surface, for example the substrate surface. Thus, in one or more embodiments, the phrase "on the substrate surface" is intended to include one or more underlayers. In other embodiments, the phrase "directly on" refers to a layer or a film that is in contact with a surface, for example, a substrate surface, with no intervening layers. Thus, the phrase "a layer directly on the substrate surface" refers to a layer in direct contact with the substrate surface with no layers in between.

[0022] One or more of the layers deposited on the substrate or substrate surface are continuous. As used herein, the term "continuous" refers to a layer that covers an entire exposed surface without gaps or bare spots that reveal material underlying the deposited layer. A continuous layer may have gaps or bare spots with a surface area less than about 15% or less than about 10% of the total surface area of the layer.

[0023] As used herein, the term "epitaxy" refers to a type of crystal growth or material deposition in which new crystalline layers are formed with one or more well-defined orientations with respect to a crystalline seed layer. The deposited crystalline film is called an epitaxial layer.

[0024] Transistors are circuit components or elements that are often formed on semiconductor devices. Depending upon the circuit design, in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements, transistors are formed on a semiconductor device. Generally, a transistor includes a gate formed between source and drain regions. In one or more embodiments, the source and drain regions include a doped region of a substrate and exhibit a doping profile suitable for a particular application. The gate is positioned over the channel region and includes a gate dielectric interposed between a gate electrode and the channel region in the substrate.

[0025] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. Enhancement mode field effect transistors generally display very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by an electric field in the device, which is generated by a voltage difference between the body and the gate of the device. The FET’s three terminals are source (S), through which the carriers enter the channel; drain (D), through which the carriers leave the channel; and gate (G), the terminal that modulates the channel conductivity. Conventionally, entering the channel at the source (S) is designated Is and currentAttorney Docket No.: 44027828WO01 PATENT6entering the channel at the drain (D) is designated ID. Drain-to-source voltage is designated VDS. By applying voltage to gate (G), the current entering the channel at the drain (i.e., ID) can be controlled.

[0026] The metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate, whose voltage determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage is used for amplifying or switching electronic signals. A MOSFET is based on the modulation of charge concentration by a metal-oxide-semiconductor (MOS) capacitance between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer. Compared to the MOS capacitor, the MOSFET includes two additional terminals (source and drain), each connected to individual highly doped regions that are separated by the body region. These regions can be either p or n type, but they are both of the same type, and of opposite type to the body region. The source and drain (unlike the body) are highly doped as signified by a "+" sign after the type of doping.

[0027] If the MOSFET is an n-channel or nMOS FET, then the source and drain are n+ regions and the body is a p region. If the MOSFET is a p-channel or pMOS FET, then the source and drain are p+ regions and the body is a n region. The source is so named because it is the source of the charge carriers (electrons for n-channel, holes for p-channel) that flow through the channel; similarly, the drain is where the charge carriers leave the channel.

[0028] As used herein, the term "fin field-effect transistor (FinFET)" refers to a MOSFET transistor built on a substrate where the gate is placed on two or three sides of the channel, forming a double- or triple-gate structure. FinFET devices have been given the generic name FinFETs because the channel region forms a "fin" on the substrate. FinFET devices have fast switching times and high current density.

[0029] As used herein, the term “complementary field-effect transistor (CFET)” refers to a three-dimensional stacked architecture where an n-type and a p-type MOSFET are placed vertically, allowing for high transistor density and improved performance in microchips.

[0030] As used herein, the term "gate-all-around (GAA)" or "gate-all-around transistor" is used to refer to an electronic device, e.g., a transistor, in which the gateAttorney Docket No.: 44027828WO01 PATENT7material surrounds the channel region on all sides. The channel region of a GAA transistor may include nanowires or nano-slabs or nano-sheets, bar-shaped channels, or other suitable channel configurations. In one or more embodiments, the channel region of a GAA device has multiple horizontal nanowires or horizontal bars vertically spaced, making the GAA transistor a stacked horizontal gate-all-around (hGAA) transistor.

[0031] One example of gate-all-around (GAA) technology is complementary field effect transistor (CFET). As used herein, the term "complementary field-effect transistor (CFET)" refers to a transistor that includes NMOS FET devices and PMOS FET devices stacked on each other. Each of the NMOS FET devices and the PMOS FET devices that form the CFET are GAA transistors or hGAA transistors. CFET transistors have increased on-chip device density and reduced area consumption when compared to GAA transistors.

[0032] As used herein, the term "nanowire" refers to a nanostructure, with a diameter on the order of a nanometer (10-9meters). Nanowires can also be defined as the ratio of the length to width being greater than 1000. Alternatively, nanowires can be defined as structures having a thickness or diameter constrained to tens of nanometers or less and an unconstrained length. Nanowires are used in transistors and some laser applications, and, in one or more embodiments, are made of semiconducting materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPU, GPU, MPU, and volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. As used herein, the term "nanosheet" refers to a two-dimensional nanostructure with a thickness in a scale ranging from about 0.1 nm to about 1000 nm.

[0033] As used herein, the term "3D NAND" refers to a type of electronic (solid-state) non-volatile computer storage memory in which the memory cells are stacked in multiple layers. 3D NAND memory generally includes a plurality of memory cells that include floating-gate transistors. Traditionally, 3D NAND memory cells include a plurality of NAND memory structures arranged in three dimensions around a bit line.

[0034] As used herein, the term "dynamic random-access memory" or "DRAM" refers to a memory cell that stores a datum bit by storing a packet of charge (i.e., a binary one), or no charge (i.e., a binary zero) on a capacitor. The charge is gated ontoAttorney Docket No.: 44027828WO01 PATENT8the capacitor via an access transistor and sensed by turning on the same transistor and looking at the voltage perturbation created by dumping the charge packet on the interconnect line on the transistor output. Thus, a single DRAM cell is made of one transistor and one capacitor.

[0035] As used herein, the term "front-end-of-line (FEOL)" refers to the processes where individual transistors are created on a wafer, while the term "back-end-of-line (BEOL)" refers to the subsequent steps of deposition of metallization and insulation layers that connect the transistors to form an integrated circuit. FEOL builds the fundamental components, including the transistor gates, within the wafer’s substrate, whereas BEOL adds multiple layers of metal interconnects and dielectrics to wire these transistors together for computing.

[0036] As used herein, the term "non-transitory computer-readable medium" refers to a physical data storage device, such as, but not limited to, a hard drive or RAM, that stores computer instructions or data in a tangible form and retains the data even when power is removed.

[0037] Transistor device structures include a planar structure, a fin field effect transistor (finFET) structure, a gate all around (GAA) structure, and a complementary field-effect transistor (CFET). Logic gate performance is often related to the characteristics of the materials used as well as the thickness and area of the structural layers. As some gate characteristics are adjusted to accommodate device scaling, however, performance and reliability challenges arise. To achieve a node-to-node performance benefit, the drive-current of logic transistors needs to be improved. For gate-all-around PMOS, a compressive channel stress improves hole mobility with higher hole mobility reducing channel resistance leading to lower device resistance and higher drive-current. Typically, compressive channel stress may be incorporated using silicon germanium (SiGe) at the source and the drain, where higher germanium (Ge) concentration results in an increase in the channel stress.

[0038] Gate-all-around (GAA) FETs provide design flexibility, low operational voltage, high drive currents, high computational speed, and excellent performance within a smaller footprint area. In a GAA nanosheet structure, an inner spacer may be introduced to improve parasitic capacitance between source / drain (S / D) epitaxial layers and metal gates. This structure, however, causes a challenge in fabrication of high-Attorney Docket No.: 44027828WO01 PATENT9quality defect free source / drain (S / D) epitaxial layers, especially in p-type FET devices where silicon germanium (SiGe) source / drain (S / D) epitaxial layers typically increase strain in silicon (Si) channel layers. In the presence of inner spacer layers (e.g., silicon nitride), however the grown epitaxial layers are defective and there is no strain in the film.

[0039] One or more embodiments provide a method of manufacturing a transistor device, e.g., gate-all-around devices (GAA), field-effect transistors (FinFETs), and complementary field effect transistors (CFETs), where the inner spacer is formed very late in the process flow so that the source / drain epitaxial layer has strain. Selective deposition is used to advantageously deposit a dielectric material, e.g., SiO, SiON, SiOCN, SiN, and other IOW-K materials, onto doped, e.g., boron- or phosphorus-doped, silicon (Si) or silicon germanium (SiGe) surfaces while inhibiting growth on undoped silicon (Si) surfaces. The method of one or more embodiments includes removal of native surface oxides, controlled re-oxidation, inhibitor molecule application, and selective dielectric deposition to form an inner spacer. The inhibitor may be advantageously selected from one or more of silanols, organic alcohols, alkynes, or alkenes.

[0040] In one or more embodiments, native oxides are stripped from undoped and boron- or phosphorus-doped silicon (Si) and silicon germanium (SiGe) (1 % to 99% Ge). A controlled re-oxidation is then performed, where the boron- or phosphorus-doped silicon (Si) and silicon germanium (SiGe) re-oxidize faster than the undoped silicon (Si) (and undoped silicon germanium (SiGe)). Without intending to be bound by theory, the difference in this oxidation rate provides the lever for chemically distinguishing the surfaces, ultimately providing selectivity. In one or more embodiments, a vapor-phase inhibitor, e.g., a silanol, an organic alcohol, an alkyne, or an alkene, is applied to the substrate(s) to bind to and block film growth on H-terminated surfaces, in this case the non-oxidized, undoped, hydrogen-terminated Si and SiGe. Atomic layer dielectric deposition of the inner spacer layer proceeds on the boron- or phosphorus-doped silicon (Si) and silicon germanium (SiGe), while deposition is inhibited on undoped silicon (Si) (and some undoped silicon germanium (SiGe)) surfaces, producing selective growth that enables an inner spacer last (ISL) scheme for gate-all-around (GAA) transistors).Attorney Docket No.: 44027828WO01 PATENT10

[0041] Although the disclosure will routinely identify specific GAA devices, and components thereof, it will be readily understood that the device and methods are equally applicable to other transistor and memory devices, orientations thereof, as processes for forming such devices. Accordingly, the technology should not be considered to be so limited as for use with these specific devices or methods alone.

[0042] In one or more embodiments, metal deposition and other processes can be carried out in an isolated environment (e.g., a cluster process tool). Accordingly, some embodiments of the disclosure provide integrated tool systems with related process modules to implement the methods.

[0043] The embodiments of the disclosure are described by way of the Figures, which illustrate devices (e.g., GAA, FinFET, and CFET) and processes for forming devices in accordance with one or more embodiments of the disclosure. The processes shown are merely illustrative possible uses for the disclosed processes, and the skilled artisan will recognize that the disclosed processes are not limited to the illustrated applications.

[0044] FIG. 1 illustrates a process flow diagram of a method 100 of forming a transistor device according to one or more embodiments. More specifically, FIG. 1 depicts a process flow diagram of a method 100 of forming an inner spacer in a semiconductor structure 200 forming a portion of a horizontally stacked gate-all-around field-effect transistor (GAA FET) nanosheet structure, according to one or more embodiments of the present disclosure. In the method 100, an inner spacer is formed last in the process.

[0045] The method 100 is described below with respect to FIGS. 2A to 2C, which depict the stages of fabrication of semiconductor structures and transistor structures in accordance with some embodiments of the present disclosure. FIGS. 2A, 2B, and 2C are cross-sectional views of a transistor structure (e.g., GAA, FET, CFET) according to one or more embodiments. The method 100 may be part of a multi-step fabrication process of a semiconductor device. Accordingly, the method 100 may be performed in any suitable process chamber coupled to a cluster tool. The cluster tool may include process chambers for fabricating a semiconductor device, such as chambers configured for etching, deposition, physical vapor deposition (PVD), chemical vaporAttorney Docket No.: 44027828WO01 PATENT11deposition (CVD), oxidation, or any other suitable chamber used for the fabrication of a semiconductor device.

[0046] The method 100 of forming the transistor structure or semiconductor structure 200 begins at operation 101 , by providing a substrate 208 having a top surface 207 (as illustrated in FIG. 2A). In some embodiments, the substrate 208 may be a bulk semiconductor substrate. As used herein, the term "bulk semiconductor substrate" refers to a substrate in which the entirety of the substrate is comprised of a semiconductor material. The bulk semiconductor substrate may comprise any suitable semiconducting material and / or combinations of semiconducting materials for forming a semiconductor structure. For example, the semiconducting layer may comprise one or more materials such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or non-patterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconducting materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 208 comprises a semiconductor material, e.g., silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 208 comprises one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although a few examples of materials from which the substrate may be formed are described herein, any material that may serve as a foundation upon which passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) may be built falls within the spirit and scope of the present disclosure.

[0047] In some embodiments, the semiconductor material may be a doped material, such as n-doped silicon (n-Si), or p-doped silicon (p-Si). In some embodiments, the substrate may be doped using any suitable process such as an ion implantation process. As used herein, the term "n-type" refers to semiconductors that are created by doping an intrinsic semiconductor with an electron donor element during manufacture. The term n-type comes from the negative charge of the electron. In n-type semiconductors, electrons are the majority carriers and holes are the minority carriers.Attorney Docket No.: 44027828WO01 PATENT12As used herein, the term "p-type" refers to the positive charge of a well (or hole). As opposed to n-type semiconductors, p-type semiconductors have a larger hole concentration than electron concentration. In p-type semiconductors, holes are the majority carriers and electrons are the minority carriers. The dopant can be any suitable dopant known to the skilled artisan. In one or more embodiments, the dopant comprises a Group lll-V element. In one or more embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or combinations thereof. In some embodiments, the substrate may be doped to provide a high dose of dopant at a first location of the top surface 207 of the substrate 208 in order to prevent parasitic bottom device turn on. In one or more embodiments, a superlattice structure 202 is formed atop the first location of the top surface 207 of the substrate 208. For example, in some embodiments, the top surface 207 of the substrate 208 may have a dopant density about 1018atoms / cm3to about 1019atoms / cm3.

[0048] Referring to FIG. 1 and FIG. 2A, in one or more embodiments, at least one superlattice structure 202 of firm stack is formed atop the top surface 207 of the substrate 208. The superlattice structure 202 may comprise a plurality of semiconductor material layers 206 and a corresponding plurality of channel layers 204 alternatingly arranged in a plurality of stacked pairs. In one or more embodiments, the plurality of semiconductor material layers 206 and a corresponding plurality of channel layers 204 of the superlattice structure 202 extend between two source / drain (S / D) epitaxial (epi) layers 210 on the substrate 208 such that a first end of each of the plurality of semiconductor material layers 206 and each of the plurality of channel layers 204 forms one sidewall of the source / drain (S / D) epitaxial (epi) layer 210 and a second end of each of the plurality of semiconductor material layers 206 and each of the plurality of channel layers 204 forms the opposing second sidewall of the source / drain (S / D) epitaxial (epi) layer 210. The source / drain (S / D) epitaxial (epi) layer 210 has a bottom that may, in one or more embodiments, be formed within the substrate 208.

[0049] In one or more embodiments the plurality of stacked groups of layers of the superlattice structure 202 comprise, consist essentially of, or consist of silicon (Si), germanium (Ge), silicon germanium (SiGe), or indium gallium zinc oxide (IGZO). In some embodiments, the plurality of semiconductor material layers 206 comprise, consist essentially of, or consist of silicon germanium (SiGe), and the plurality ofAttorney Docket No.: 44027828WO01 PATENT13channel layers 204 comprise, consist essentially of, or consist of silicon (Si) or indium gallium zinc oxide (IGZO). The plurality of semiconductor material layers 206 may be formed of silicon germanium (SiGe) with a ratio of germanium (Ge) ranging between about 0% or about 5% and about 90%, for example, about 25%. In some embodiments, the germanium concentration is in a range of from 0% to 25% germanium.

[0050] In one or more embodiments, the plurality of semiconductor material layers 206 and corresponding plurality of channel layers 204 can comprise any number of lattice matched material pairs suitable for forming a superlattice structure 202. For the sake of simplicity, the drawings illustrate only 3 pairs of lattice matched material pairs, but any suitable number is possible. In some embodiments, the plurality of semiconductor material layers 206 and corresponding plurality of channel layers 204 comprise from about 2 to about 50 pairs of lattice matched materials.

[0051] In one or more embodiments, the thickness of the plurality of semiconductor material layers 206 and the plurality of channel layers 204 are independently in the range of from about 2 nm to about 50 nm, in the range of from about 3 nm to about 20 nm, or in a range of from about 2nm to about 15 nm. In one or more embodiments, the fin-shaped superlattice structure 202 may have a width of between about 6 nm and about 200 nm. A pitch between adjacent dummy gate structures 214 may be between about 40 nm and about 80 nm.

[0052] In one or more embodiments, the plurality of channel layers 204 may be doped with a dopant. The dopant can be any suitable dopant known to the skilled artisan. In one or more embodiments, the dopant comprises a Group lll-V element. In one or more embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or combinations thereof. The doping concentration of the plurality of channel layers 204 may be in a range of from 1e14 cm-3to 1e19 cm-3. In other embodiments, the plurality of channel layers 204 are not doped with a dopant.

[0053] The semiconductor structure 200 shown in FIG. 2A includes the fin-superlattice structure 202 including a stack of alternating semiconductor material layers 206 and channel layers 204 epitaxially grown on the substrate 208. The semiconductor structure 200 further includes the source / drain (S / D) epitaxial (epi) layer 210 andAttorney Docket No.: 44027828WO01 PATENT14source / drain (S / D) epitaxial (epi) liners 212 in contact with the S / D epi layer 210 and on both sides of the superlattice structure 202.

[0054] Referring to FIG. 2A, in one or more embodiments, a dummy gate structure 214 is formed and patterned over the superlattice structure 202. The dummy gate structure 214 defines the channel region of the transistor device. The dummy gate structure 214 may be formed using any suitable conventional deposition and patterning process known in the art. The dummy gate structure 214 may comprise any suitable material. In some embodiments, the dummy gate structure 214 comprises one or more of a dummy gate metal layer and a dummy gate polysilicon layer.

[0055] In one or more embodiments, the dummy gate structure 214 interfaces with the S / D epi layer 210 via a dummy oxide layer 216. A gate spacer 218 may be formed over the dummy gate structure 214 and above the fin-shaped superlattice 202. In one or more embodiments, the gate spacer 218 may be formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma enhanced atomic layer deposition, plasma enhanced chemical vapor deposition or low-pressure chemical vapor deposition.

[0056] In one or more embodiments, the gate spacer 218 is a conformal layer. As used herein, the term "conformal" means that the gate spacer 218 adapts to the contours of a feature or a layer. Conformality of a layer is typically quantified by a ratio of the average thickness of a layer deposited on the sidewalls of a feature to the average thickness of the same deposited layer on the field, or upper surface, of the substrate. As used herein, a layer that is "conformally deposited" refers to a layer where the thickness is about the same throughout. A layer which is conformal varies in thickness by less than or equal to about 5%, 2%, 1%, or 0.5%. In one or more embodiments, the deposited gate spacer 218 has a conformality greater than 90%, or greater than 91%, or greater than 92%, or greater than 93%, or greater than 94%, or greater than 95%, or greater than 96%, or greater than 97%, or greater than 98%, or greater than 99%.

[0057] In a p-type MOS (p-MOS) device region of the semiconductor structure 200, the S / D epi layer 210 may be formed of epitaxially grown silicon germanium (SiGe) with a ratio of germanium (Ge) ranging between about 0% or about 10% and about 25% or about 50%, doped with p-type dopants such as boron (B) or gallium (Ga), with aAttorney Docket No.: 44027828WO01 PATENT15concentration of between about 1019cm-3and 5 x 1021cm-3, depending upon the desired conductive characteristic of the S / D epi layer 210.

[0058] In an n-type MOS (N-MOS) device region of the semiconductor structure 200, the S / D epi layer 210 may be formed of epitaxially grown silicon (Si) doped with n-type dopants such as phosphorus (P), arsenic (As), or antimony (Sb), with a concentration of between about 1019cm-3and 5 x 1021cm-3, depending upon the desired conductive characteristic of the S / D epi layer 210.

[0059] In one or more embodiments, the S / D epi liners 212 may be formed of silicon germanium (SiGe) with a ratio of germanium (Ge) ranging between about 0% or about 5% and about 25% or about 30%, for example, about 10%, lightly doped with p-type dopants such as boron (B) or gallium (Ga) in a p-MOS region, or n-type dopants such as phosphorus (P), arsenic (As), or antimony (Sb) in an n-MOS region, with a concentration of between about 1 x 1018cm-3and 5 x 1021cm-3, depending upon the desired conductive characteristic of the S / D epi liners 212.

[0060] In one or more embodiments, the S / D epi layers 210 and the S / D epi liners 212 are formed before an inner spacer (e.g., silicon nitride (Si3N4)) between the S / D epi layers 210 and a metal gate (between adjacent channel layers 204) is formed. Therefore, in the p-type transistor region, there is channel strain during epitaxial growth of the S / D epi layers 210, thus forming defect-free S / D epi layers 210 and the S / D epi liners 212.

[0061] In one or more embodiments, the dummy gate structure 214 may be formed of polycrystalline silicon (Si). The dummy oxide layer 216 may be formed of polycrystalline silicon oxide (SiOx).

[0062] The gate spacers 218 may be formed of any suitable dielectric material. As used herein, the term "dielectric material" refers to a layer of material that is an electrical insulator that can be polarized in an electric field. In one or more embodiments, the gate spacers 218 comprise one or more of silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boride (SiB), and silicon boron nitride (SiBN). In some embodiments, the gate spacers 218 include a low-k dielectric material. In some embodiments, the IOW-K dielectric material has a k-value less than 7 or less than 5 or less than 2. In at least some embodiments, the gate spacers 218 include oxides, carbon doped oxides, porous silicon dioxide, carbides, oxycarbides,Attorney Docket No.: 44027828WO01 PATENT16nitrides, oxynitrides, oxycarbonitrides, polymers, phosphosilicate glass, fluorosilicate (SiOF) glass, organosilicate glass (SiOCH), or any combinations thereof. In at least some embodiments, the gate spacers 218 may be selected from one or more of silicon oxynitride (SiOCN), silicon oxycarbide (SiOC), silicon oxyboronitride (SiBCN), or silicon oxide (SiOx).

[0063] Referring to FIG. 1 , the method 100 proceeds with operation 104, in which a selective etch process is performed to selectively remove the semiconductor material layers 206 to form cavities 220 between adjacent channel layers 204, as illustrated in FIG. 2B. In one or more embodiments, the semiconductor material layers 206 are removed by any suitable wet etch process or dry etch process. In one or more embodiments, the etching uses a wet etch process, such as diluted hydrofluoric acid (DHF). In one or more embodiments, a dry etch process is used. In some embodiments, the dry etch process may include a conventional plasma etch, or a remote plasma-assisted dry etch process, In the etch process of one or more embodiments, the device is exposed to H2, NF3, and / or NH3 plasma species, e.g., plasma-excited hydrogen and fluorine species. For example, in some embodiments, the device may undergo simultaneous exposure to H2, NF3, and NH3 plasma. The etch process of one or more embodiments may be performed in any suitable chamber, which may be integrated into one of a variety of multi-processing platforms. In one or more embodiments, a wet etch process may be used which includes a hydrofluoric (HF) acid last process, in which HF etching of surface is performed that leaves surface hydrogen-terminated. Specifically, in a wet etch process using hydrofluoric (HF) acid, exposed surfaces 204S of the channel layers 204 (e.g., silicon (Si)) and exposed surfaces 212S of the S / D epi liners 212 (e.g., silicon germanium (SiGe)) are left hydrogen (H)-terminated. After exposure to ambient air, the exposed surfaces 204S, 212S may be oxidized and hydroxyl (OH)-terminated.

[0064] Alternatively, any other liquid-based etch process may be employed. In some embodiments, the process comprises a sublimation etch. The etch process can be plasma or thermally based. The plasma processes can be any suitable plasma (e.g., conductively coupled plasma, inductively coupled plasma, microwave plasma). For example, in one or more embodiments, the semiconductor material layers 206 may be exposed to H2, NF3, and / or NH3 plasma species, e.g., plasma-excited hydrogen andAttorney Docket No.: 44027828WO01 PATENT17fluorine species. The etch process may be plasma or thermally based. The plasma etch process can use any suitable plasma (for example, conductively coupled plasma, inductively coupled plasma, or microwave plasma) known to the skilled artisan.

[0065] Referring to FIG. 1 , at operation 106, a queue time (Q-time) controlled preclean process is performed to reduce the hydroxyl (OH)-terminated surfaces 204S (e.g., silicon (Si)) and the hydroxyl (OH)-terminated surfaces 212S (e.g., silicon germanium (SiGe)). The pre-clean process includes a cleaning process using a dilute hydrofluoric acid (dHF) performed in a first processing chamber, such as the processing chamber 420 shown in FIG. 3.

[0066] In one or more embodiments, the cleaning process may be performed in a dilute HF (dHF) process. In some embodiments, the dHF used in the cleaning process may have a dilution ratio of about 100:1 for about 1 minute. By the cleaning process, the exposed surfaces 204S of the channel layers 204 (e.g., silicon (Si)) and the exposed surfaces 212S of the S / D epi liners 212 (e.g., silicon germanium (SiGe)) may be reduced and hydrogen (H)-terminated. Subsequently, the surfaces 204S of the channel layers 204 (e.g., silicon (Si)) and the surfaces 212S of the S / D epi liners 212 (e.g., silicon germanium (SiGe)) are exposed to ambient air for a queue time (Q-time). Since germanium (Ge) oxidates faster in air than silicon (Si), the hydrogen (H)-terminated surfaces 212S of the S / D epi liners 312 (e.g., silicon germanium (SiGe)) become at least partially oxidized and hydroxyl (OH)-terminated, while the exposed surfaces 204S of the channel layers 204 (e.g., silicon (Si)) remain hydrogen (H)-terminated. The Q time may be controlled such that only the exposed surfaces 212S of the S / D epi liners 212 (e.g., silicon germanium (SiGe)) are oxidized by a desired amount and may be between about 1 minute and about 240 minutes.

[0067] In one or more embodiments, alternative or additional to the Q-time controlled pre-clean process operation 106, a directional oxidation process is performed to oxidize the exposed surfaces 212S of the S / D epi liners 212 (e.g., silicon germanium (SiGe)) selectively over the exposed surface 204S of the channel layers 204 (e.g., silicon (Si)), in operation 108. By the directional oxidation process of one or more embodiments, the exposed surfaces 212S of the S / D epi liners 212 (e.g., silicon germanium (SiGe)) become hydroxyl (OH)-terminated.Attorney Docket No.: 44027828WO01 PATENT18

[0068] In one or more embodiments, the selective oxidation process may be a plasma treatment process, such as a rapid thermal anneal (RPO) or decoupled plasma plus (DPX+) process, performed in a second processing chamber, such as the processing chambers 420, 422, 424, 426, 428, and 430 shown in FIG. 3.

[0069] In one or more embodiments, when the controlled re-oxidation is performed, the boron- or phosphorus-doped silicon (Si) and silicon germanium (SiGe) (e.g., the exposed surfaces 212S of the S / D epi liners 212) re-oxidize faster than the undoped silicon (Si) of the channel layers 204. Accordingly, in one or more embodiments, after the pre-clean operation, the inhibitor binds more strongly to silicon (Si) versus silicon germanium (SiGe).

[0070] In other alternative embodiments, a controlled re-oxidation is unnecessary because during operation 106, the boron- or phosphorus-doped silicon (Si) and silicon germanium (SiGe) (e.g., the exposed surfaces 212S of the S / D epi liners 212) are not effectively reduced during the queue time (Q-time) controlled pre-clean process. In such embodiments, the oxides are selectively removed from the undoped surfaces (e.g., undoped silicon (Si) of the channel layers 204) while the oxide remains on the boron-or phosphorus-doped silicon (Si) and silicon germanium (SiGe) surfaces (e.g., the exposed surfaces 212S of the S / D epi liners 212.

[0071] In one or more embodiments, alternative or additional to the Q-time controlled pre-clean process of operation 106, a selective removal process is performed to remove silicon oxide (SiOx) on the surface 204S of the channel layers 204 (e.g., silicon (Si)) selectively over silicon germanium oxide (SiGeOx) on the surfaces 212S of the S / D epi liners 212 (e.g., silicon germanium (SiGe)), in operation 110. By the selective removal process, the hydroxyl (OH)-terminated surface 204S of the channel layers 204 (e.g., silicon (Si)) become hydrogen (H)-terminated, while the hydroxyl (OH)-terminated surfaces 212S of the S / D epi liners 212 (e.g., silicon germanium (SiGe)) remain hydroxyl (OH)-terminated.

[0072] In one or more embodiments, the selective removal process may include any appropriate dry anisotropic etching or wet etching process, performed in a second processing chamber, such as the processing chamber 420 shown in FIG. 3.

[0073] In one or more embodiments, at operation 112, an inhibitor application process is performed to passivate the hydrogen (H)-terminated surface 204S of theAttorney Docket No.: 44027828WO01 PATENT19channel layers 204 (e.g., silicon (Si)) selectively over the hydroxyl (OH)-terminated surfaces 212S of the S / D epi liners 212 (e.g., silicon germanium (SiGe)) and exposed surfaces 218S of the gate spacers 218 (e.g., silicon oxide (SiOx)). In one or more embodiments, the inhibitor application process may include applying one or more inhibitors to the hydrogen (H)-terminated surfaces 204S of the channel layers 204 (e.g., silicon (Si)), the at least partially hydroxyl (OH)-terminated surfaces 212S of the S / D epi liners 212 (e.g., silicon germanium (SiGe)), and the exposed surfaces 218S of the gate spacers 218 (e.g., silicon oxide (SiOx)).

[0074] In one or more embodiments, the inhibitors are any suitable inhibitor compound. In one or more embodiments, the inhibitor may be advantageously selected from one or more of silanols, organic alcohols, alkynes, or alkenes. In some embodiments, the inhibitor is one or more of a silanols, an organic alcohol, an alkyne-containing compound, an acetylene-containing compound, an alkene-containing compound, and an ethylene-containing compound.

[0075] In some embodiments, the inhibitor may be any suitable silanol. As used herein, the term "silanol" refers to chemical compounds that contain silicon-hydroxyl group (Si-OH). In one or more embodiments, the silanol has the general formula (I)R2RLSi-R3OH

[0076] 0 where R1, R2, and R3are independently selected from hydrogen (H), a saturated or unsaturated alkyl having from 1 to 24 carbon atoms, and a saturated or unsaturated aryl having from 1 to 24 carbon atoms.

[0077] In some embodiments, the inhibitor may be any suitable organic alcohol. As used herein, the term "organic alcohol" refers to a compound that contains a hydroxyl group (-OH) bonded to a carbon atom. In one or more embodiments, the organic alcohol has the general formula (II)Attorney Docket No.: 44027828WO01 PATENT20

[0078] where R1, R2, and R3are independently selected from hydrogen (H), a saturated or unsaturated alkyl having from 1 to 24 carbon atoms, and a saturated or unsaturated aryl having from 1 to 24 carbon atoms.

[0079] In some embodiments, the inhibitor may be any suitable alkyne-containing compound. As used herein, the term "alkyne-containing compound" refers to chemical compounds that contain unsaturated hydrocarbons containing at least one carboncarbon triple bond. In one or more embodiments, the alkyne-containing compound has the general formula (III)

[0080] where R4and R5are independently selected from hydrogen (H), a saturated or unsaturated alkyl having from 1 to 24 carbon atoms, and a saturated or unsaturated aryl having from 1 to 24 carbon atoms.

[0081] In some embodiments, the inhibitor may be any suitable acetylene-containing compound. As used herein, the term "acetylene-containing compound" refers to chemical compounds that contain unsaturated hydrocarbons containing at least one carbon-carbon triple bond between two hydrogens (HC=CH).

[0082] In some embodiments, the inhibitor may be any suitable alkene-containing compound. As used herein, the term "alkene-containing compound" refers to chemical compounds that contain at least one carbon-carbon double bond. In one or more embodiments, the alkyne-containing compound has the general formula (IV)

[0083] where R1, R2, R3, and R4are independently selected fromAttorney Docket No.: 44027828WO01 PATENT21hydrogen (H), a saturated or unsaturated alkyl having from 1 to 24 carbon atoms, and a saturated or unsaturated aryl having from 1 to 24 carbon atoms.

[0084] In further embodiments, the inhibitor may be any suitable ethylene-containing compounds. As used herein, the term "ethylene-containing compound" refers to chemical compounds that contain at least one carbon-carbon double bond between two hydrogens (H2C=CH2).

[0085] As used herein, the term "alkyl" or "alk," alone or as part of another group, includes both straight and branched chain hydrocarbons, as well as cyclic hydrocarbons, containing 1 to 24 carbons, or containing 1 to 12 carbon atoms, or containing 1 to 18 carbon atoms, or containing 6 to 18 carbon atoms in the normal chain, such as methyl, ethyl, propyl, isopropyl, butyl, t-butyl, isobutyl, pentyl, hexyl, isohexyl, heptyl, 4,4-dimethylpentyl, octyl, 2,2,4-trimethyl-pentyl, nonyl, decyl, undecyl, dodecyl, the various branched chain isomers thereof, and the like. Such groups may optionally include up to 1 to 4 substituents. The alkyl may be substituted or unsubstituted.

[0086] The term "cyclic alkyl” as used herein includes all alkyl groups that include a ring having from 3 to 24 carbon atoms, or from 3 to 18 carbon atoms, or from 3 to 12 carbon atoms.

[0087] The alkyl groups, including cyclic alkyl groups, may optionally include up to 1 to 4 substituents such as halo, for example F, Br, Cl, or I, or CF3, alkyl, alkoxy, aryl, aryloxy, aryl(aryl) or diaryl, arylalkyl, arylalkyloxy, alkenyl, cycloalkyl, cycloalkylalkyl, cycloalkylalkyloxy, amino, hydroxy, hydroxyalkyl, acyl, heteroaryl, heteroaryloxy, heteroarylalkyl, heteroarylalkoxy, aryloxyalkyl, alkylthio, arylalkylthio, aryloxyaryl, alkylamido, alkanoylamino, arylcarbonylamino, nitro, cyano, thiol, haloalkyl, trihaloalkyl, and / or alkylthio, and the like.

[0088] As used herein, the term "alkene" or "alkenyl" refers to straight or branched chain radicals of 1 to 24 carbons, or containing 1 to 12 carbon atoms, or containing 1 to 18 carbon atoms, or containing 6 to 18 carbon atoms in the normal chain, which include one to six double bonds in the normal chain, such as vinyl, 2-propenyl, 3-butenyl, 2-butenyl, 4-pentenyl, 3-pentenyl, 2-hexenyl, 3-hexenyl, 2-heptenyl, 3-heptenyl, 4-heptenyl, 3-octenyl, 3-nonenyl, 4-decenyl, 3-undecenyl, 4-dodecenyl, 4,8,12-tetradecatrienyl, and the like, and which may be optionally substituted with 1 to 4 substituents, namely, halogen, haloalkyl, alkyl, alkoxy, alkenyl, alkynyl, aryl, arylalkyl,Attorney Docket No.: 44027828WO01 PATENT22cycloalkyl, amino, hydroxy, heteroaryl, cycloheteroalkyl, alkanoylamino, alkylamido, arylcarbonyl-amino, nitro, cyano, thiol, alkylthio, and / or any of the alkyl substituents set out herein.

[0089] As used herein, the term "alkynyl" refers to straight or branched chain radicals of 1 to 24 carbons, or containing 1 to 12 carbon atoms, or containing 1 to 18 carbon atoms, or containing 6 to 18 carbon atoms in the normal chain, which include one triple bond in the normal chain, such as 2-propynyl, 3-butynyl, 2-butynyl, 4-pentynyl, 3-pentynyl, 2-hexynyl, 3-hexynyl, 2-heptynyl, 3-heptynyl, 4-heptynyl, 3-octynyl, 3-nonynyl, 4-decynyl, 3-undecynyl, 4-dodecynyl, and the like, and which may be optionally substituted with 1 to 4 substituents, namely, halogen, haloalkyl, alkyl, alkoxy, alkenyl, alkynyl, aryl, arylalkyl, cycloalkyl, amino, heteroaryl, cycloheteroalkyl, hydroxy, alkanoylamino, alkylamido, arylcarbonylamino, nitro, cyano, thiol, and / or alkylthio, and / or any of the alkyl substituents set out herein.

[0090] As used herein, the term "aryl" refers to monocyclic and bicyclic aromatic groups containing 6 to 10 carbons in the ring portion (such as phenyl, biphenyl or naphthyl, including 1 -naphthyl and 2-naphthyl) and may optionally include 1 to 3 additional rings fused to a carbocyclic ring or a heterocyclic ring (such as aryl, cycloalkyl, heteroaryl, or cycloheteroalkyl rings). The aryl group may be optionally substituted through available carbon atoms with 1 , 2, or 3 substituents, for example, hydrogen, halo, haloalkyl, alkyl, haloalkyl, alkoxy, haloalkoxy, alkenyl, trifluoromethyl, trifluoromethoxy, alkynyl, and the like.

[0091] The term "halogen" or "halo" as used herein alone or as part of another group refers to chlorine, bromine, fluorine, and iodine, as well as CF3.

[0092] In one or more embodiments, the inhibitors may selectively bind to the hydrogen (H)-terminated surfaces 204S of the channel layers 204 (e.g., silicon (Si)), but not to oxides (the at least partially hydroxyl (OH)-terminated surfaces 212S of the S / D epi liners 212 (e.g., silicon germanium (SiGe) and the exposed surfaces 218S of the gate spacers 218 (e.g., silicon oxide (SiOx))).

[0093] In one or more embodiments, a ratio of a deposition rate of the inhibitors on to the hydrogen (H)-terminated surfaces 204S of the channel layers to the oxides may be about 10:1 or greater, 100:1 or greater, or 1000:1 or greater. In one or more embodiments, substantially no inhibitor compound is deposited on the oxides.Attorney Docket No.: 44027828WO01 PATENT23

[0094] The inhibitor application process of operation 112 may be performed by any suitable deposition technique, such as chemical vapor deposition (CVD), or plasma enhanced chemical vapor deposition (PECVD) process, atomic layer deposition (ALD), or plasma enhanced atomic layer deposition (PEALD) process based on, for example, a hydrocarbon gas or mixture of hydrocarbon gases, in a third processing chamber, such as the processing chamber 424, 426, 428, or 430 shown in FIG. 3.

[0095] In one or more embodiments, the inhibitor application process of operation 112 may be performed using a soak period of between about 1 minutes and about 90 minutes, such as between about 30 minutes and about 75 minutes, for example, about 60 minutes, at a temperature of between about 100 °C and about 500 °C, such as between about 200 °C and about 400 °C, or between about 200 °C and about 300 °C, for example about 250 °C a chamber pressure of between about 1 Torr and about 10 Torr, such as between about 1 Torr and about 5 Torr, or between about 1 Torr and about 3 Torr, for example about 3 Torr, and with a purge / pump (p / p) duration of between about 10 minutes and about 20 minutes, such as between about 12 minutes and about 18 minutes, or between about 1 minutes and about 60 minutes, for example, about 15 minutes.

[0096] With reference to FIG. 1 and FIG. 2C, at operation 114, a selective deposition process is performed to selectively deposit inner spacers 222 on the non-passivated oxide surfaces 212S of the S / D epi liners 212 (e.g., silicon germanium (SiGe)) within the cavities 230 and the non-passivated surfaces 218S of the gate spacer 218 (e.g., silicon oxide (SiO2)), and not on the passivated surfaces 204S of the channel layers 204 (e.g., silicon (Si)), as shown in FIG. 2C. The inner spacers 222 may comprise any suitable material. In one or more embodiments, the inner spacers 222 may be formed of silicon nitride (SisN4), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), other IOW-K materials, or combinations thereof.

[0097] In one or more embodiments, the inner spacers 222 are a conformal layer. In one or more embodiments, the deposited inner spacers 222 have a conformality greater than 90%, or greater than 91%, or greater than 92%, or greater than 93%, or greater than 94%, or greater than 95%, or greater than 96%, or greater than 97%, or greater than 98%, or greater than 99%.

[0098] In one or more embodiments, selective deposition is used to advantageouslyAttorney Docket No.: 44027828WO01 PATENT24deposit inner spacers 222, onto doped, e.g., boron- or phosphorus-doped, silicon (Si) or silicon germanium (SiGe) surfaces while inhibiting growth on undoped channel layers 204 surfaces.

[0099] In one or more embodiments, the selective deposition process of operation 114 may be performed by a PECVD process in a fourth processing chamber, such as the processing chamber 424, 426, 428, or 430 shown in FIG. 3.

[0100] In the deposition process of one or more embodiments, the inner spacers 222 may be deposited by a thermal process using silicon-containing precursor. The selectivity in the selective deposition may arise from differences in nucleation of the passivated surface 204S of the channel layers 204 (e.g., silicon (Si)) and nonpassivated oxide surfaces (the exposed surfaces 212S of the S / D epi liners 212 and the exposed surfaces 218S of the gate spacer 218), and thus the inner spacers 222 may be formed selectively on the oxide surfaces. A ratio of a deposition rate of the inner spacers 222 on the non-passivated oxide surfaces (the exposed surfaces 212S of the S / D epi liners 212 and the exposed surfaces 218S of the gate spacer 218) and the passivated surface 204S of the channel layers 204 e.g., silicon (Si)) may be about 6:1.

[0101] The silicon-containing precursor may be any suitable silicon-containing compound. In one or more embodiments, the silicon-containing precursor may be silane (SiH4), dichlorosilane (DCS, SiH2Cl2), hexachlorodisilane (HCDS), 1 ,3-Diethoxy-1 ,3-dimethyl-1 ,3-disilacyclobutane (AME), or organosiliconprecursor, such as bis(trimethylsilyl)methane (BTMSM, [(CH3)3Si]2CH2), methyltriethoxysilane (MTES, CH3Si(OC2Hs)3), dimethoxydimethylsilane (DMDMDS, Si(OCH3)2(CH3)2), methyltrimethoxysilane (MTMS, CH3Si(OCH3)3), trimethylsilane (3MS), tetramethylcyclotetrasiloxane (TMCTS), diethoxymethylsilane (DEMS), alpha-terpinene (ATRP), or silicon bromide (SiB4).

[0102] The selective deposition may be performed at any suitable flow rate, at any suitable chamber pressure, and at any suitable power. In one or more embodiments, the selective deposition may be performed at a flow rate of between about 10 seem and about 2000 seem, at a chamber pressure of between about 0.5 Torr and about 10 Torr, at an RF power of between about 500 W and about 6000 W.

[0103] With reference to FIG. 1 , at operation 116, a densification process is performed to densify the inner spacers 222. The densification process may include aAttorney Docket No.: 44027828WO01 PATENT25plasma treatment or a radical based process. The plasma treatment may use a capacitively coupled plasma (CCP) or an inductively coupled plasma (ICP) process in a fifth processing chamber, such as the processing chamber 422 shown in FIG. 3. In the radical based treatment process, the semiconductor structure is soaked in a gas such as hydrogen (H2) or helium (He). A cycle of the inhibitor application in operation 112 and the selective deposition process in operation 114 may be continued as needed to fill the cavities 220 with the inner spacers 222 of a desired thickness of between about 1 nm and about 15 nm, for example, between about 4 nm and about 6 nm.

[0104] The embodiments described herein provide methods for forming high quality inner spacers formed last in the process, in a horizontally stacked gate-all-around fieldeffect transistor (GAA FET) nanosheet structure. Since the inner spacers (e.g., silicon nitride (Si3N4)) are formed after source / drain (S / D) epitaxial layers (e.g., silicon germanium (SiGe)), there is no strain in silicon (Si) channel layers during deposition of S / D epitaxial layers.

[0105] The methods include a queue time (Q-time) controlled pre-cleaning, inhibitor application to selectivity passivate silicon (Si) surfaces, and depositing low-k dielectric material selectively on non-passivated silicon germanium (SiGe) surfaces but not on the passivated silicon (Si) surfaces. The Q-time controlled pre-cleaning may be replaced by selective oxidation of silicon germanium (SiGe) surfaces, or selective removal of silicon oxide (SiOx) over silicon germanium oxide (SiGeOx).

[0106] Additional embodiments of the disclosure are directed to a processing tool or a cluster tool 400 for the formation of the GAA devices, FinFETs, CFETS, and methods described, as shown in FIG. 3. A variety of multi-processing platforms may be utilized. FIG. 3 illustrates a schematic top-view diagram of an example of a multi-chamber processing system, e.g., a cluster tool 400, according to embodiments of the present disclosure. The cluster tool 400 generally includes a factory interface 402, load lock chambers 404, 406, transfer chambers 408, 410 with respective transfer robots 412, 414, holding chambers 416, 418, and processing chambers 420, 422, 424, 426, 428, 430. As detailed herein, wafers in the cluster tool 400 can be processed in and transferred between the various chambers without exposing the wafers to an ambient environment exterior to the cluster tool 400 (e.g., an atmospheric ambient environment such as may be present in a fab). For example, the wafers can be processed in andAttorney Docket No.: 44027828WO01 PATENT26transferred between the various chambers in a low pressure (e.g., less than or equal to about 300 Torr) or vacuum environment without breaking the low pressure or vacuum environment between various processes performed on the wafers in the cluster tool 400. Accordingly, the cluster tool 400 may provide for an integrated solution for some processing of wafers, e.g., semiconductor substrates.

[0107] In the illustrated example of FIG. 3, the factory interface 402 includes a docking station 440 and factory interface robots 442 to facilitate transfer of wafers. The docking station 440 is configured to accept one or more front opening unified pods (FOUPs) 444. In some examples, each factory interface robot 442 generally comprises a blade 448 disposed on one end of the respective factory interface robot 442 configured to transfer the wafers from the factory interface 402 to the load lock chambers 404, 406.

[0108] The load lock chambers 404, 406 have respective ports 450, 452 coupled to the factory interface 402 and respective ports 454, 456 coupled to the transfer chamber 408. The transfer chamber 408 further has respective ports 458, 460 coupled to the holding chambers 416, 418 and respective ports 462, 464 coupled to processing chambers 420, 422. Similarly, the transfer chamber 410 has respective ports 466, 468 coupled to the holding chambers 416, 418 and respective ports 470, 472, 474, 476 coupled to processing chambers 424, 426, 428, 430. The ports 454, 456, 458, 460, 462, 464, 466, 468, 470, 472, 474, 476 can be, for example, slit valve openings with slit valves for passing wafers therethrough by the transfer robots 412, 414 and for providing a seal between respective chambers to prevent a gas from passing between the respective chambers. Generally, any port is open for transferring a wafer therethrough. Otherwise, the port is closed.

[0109] The load lock chambers 404, 406, transfer chambers 408, 410, holding chambers 416, 418, and processing chambers 420, 422, 424, 426, 428, 430 may be fluidly coupled to a gas and pressure control system (not specifically illustrated). The gas and pressure control system can include one or more gas pumps (e.g., turbo pumps, cryo-pumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. In operation, a factory interface robot 442 transfers a wafer from a FOUP 444 through a port 450 or 452 to a load lock chamber 404 or 406. The gas and pressure control system then pumps down the load lock chamber 404 orAttorney Docket No.: 44027828WO01 PATENT27406. The gas and pressure control system further maintains transfer chambers 408, 410 and holding chambers 416, 418 with an interior low pressure or vacuum environment (which may include an inert gas). Hence, the pumping down of the load lock chamber 404 or 406 facilitates passing the wafer between, for example, the atmospheric environment of the factory interface 402 and the low pressure or vacuum environment of the transfer chamber 408.

[0110] With the wafer in the load lock chamber 404 or 406 that has been pumped down, the transfer robot 412 transfers the wafer from the load lock chamber 404 or 406 into the transfer chamber 408 through port 454 or 456. The transfer robot 412 is then capable of transferring the wafer to and / or between any of the processing chambers 420, 422 through the respective ports 462, 464 for processing and the holding chambers 416, 418 through the respective ports 458, 460 for holding to await further transfer. Similarly, the transfer robot 414 is capable of accessing the wafer in the holding chamber 416 or 418 through the port 466 or 468 and is capable of transferring the wafer to and / or between any of the processing chambers 424, 426, 428, 430 through the respective ports 470, 472, 474, 476 for processing and the holding chambers 416, 418 through the respective ports 466, 468 for holding to await further transfer. The transfer and holding of the wafer within and among the various chambers can be in the low pressure or vacuum environment provided by the gas and pressure control system.

[0111] The processing chambers 420, 422, 424, 426, 428, 430 can be any appropriate chamber for processing a wafer. In some embodiments, the processing chamber 420 can be capable of performing an annealing process, the processing chamber 422 can be capable of performing a cleaning process, and the processing chambers 424, 426, 428, 430 can be capable of performing epitaxial growth processes. In some examples, the processing chamber 422 can be capable of performing a cleaning process, the processing chamber 420 can be capable of performing an etch process, and the processing chambers 424, 426, 428, 430 can be capable of performing respective epitaxial growth processes. The processing chamber 422 may be a preclean chamber. The processing chamber 420 may be an etch chamber.

[0112] A system controller 490 is coupled to the cluster tool 400 for controlling the cluster tool 400 or components thereof. For example, the system controller 490 may control the operation of the cluster tool 400 using a direct control of the chambers 404,Attorney Docket No.: 44027828WO01 PATENT28406, 408, 416, 418, 410, 420, 422, 424, 426, 428, 430 of the cluster tool 400 or by controlling controllers associated with the chambers 404, 406, 408, 416, 418, 410, 420, 422, 424, 426, 428, 430. In operation, the system controller 490 enables data collection and feedback from the respective chambers to coordinate performance of the cluster tool 400.

[0113] The system controller 490 generally includes a central processing unit (CPU) 492, memory 494, and support circuits 496. The CPU 492 may be one of any form of a general-purpose processor that can be used in an industrial setting. The memory 494, or non-transitory computer-readable medium, is accessible by the CPU 492 and may be one or more of memory such as random-access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote. The support circuits 496 are coupled to the CPU 492 and may comprise cache, clock circuits, input / output subsystems, power supplies, and the like. The various methods disclosed herein may generally be implemented under the control of the CPU 492 by the CPU 492 executing computer instruction code stored in the memory 494 (or in memory of a particular process chamber) as, for example, a software routine. When the computer instruction code is executed by the CPU 492, the CPU 492 controls the chambers to perform processes in accordance with the various methods.

[0114] Other processing systems can be in other configurations. For example, more or fewer processing chambers may be coupled to a transfer apparatus. In the illustrated example, the transfer apparatus includes the transfer chambers 408, 410 and the holding chambers 416, 418. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as a transfer apparatus in a processing system.

[0115] In one or more embodiments, a processing tool comprises: a central transfer station comprising a robot configured to move a wafer; a plurality of process stations, each process station connected to the central transfer station and providing a processing region separated from processing regions of adjacent process stations; and a controller connected to the central transfer station and the plurality of process stations, the controller configured to activate the robot to move the wafer between process stations, and to control a process occurring in each of the process stations.

[0116] In one or more embodiments, a processing tool comprises: a central transferAttorney Docket No.: 44027828WO01 PATENT29station comprising a robot configured to move a wafer; a plurality of process stations, each process station connected to the central transfer station and providing a processing region separated from processing regions of adjacent process stations; and a controller connected to the central transfer station and the plurality of process stations, the controller configured to activate the robot to move the wafer between process stations, and to control a process occurring in each of the process stations.

[0117] The use of the terms "a" and "an" and "the" and similar referents in the context of describing the materials and methods discussed herein (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicate herein or clearly contradicted by context. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., "such as") provided herein, is intended merely to better illuminate the materials and methods and does not pose a limitation on the scope unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0118] Reference throughout this specification to "one embodiment," "certain embodiments," "some embodiments", "one or more embodiments", or "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of the phrases such as "in one or more embodiments," "in certain embodiments," "in one embodiment", or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0119] Although the disclosure herein has been described with reference to particular embodiments, those skilled in the art will understand that the embodimentsAttorney Docket No.: 44027828WO01 PATENT30described are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the method and apparatus of the present disclosure without departing from the spirit and scope of the disclosure. Thus, the present disclosure can include modifications and variations that are within the scope of the appended claims and their equivalents.

Claims

Attorney Docket No.: 44027828WO01 PATENT31What is claimed is:

1. A method of forming a semiconductor device, the method comprising:selectively removing a plurality of semiconductor material layers from a film stack on a substrate to form a plurality of openings adjacent a plurality of channel layers, the film stack comprising the plurality of channel layers and the plurality of semiconductor material layers alternatingly arranged and extending between a source / drain (S / D) epitaxial (epi) layer and doped source / drain (S / D) epitaxial (epi) liner on the substrate;pre-cleaning the film stack to remove oxides and form a plurality of reduced channel layers and a reduced doped source / drain (S / D) epitaxial (epi) liner;selectively forming an oxide on the doped source / drain (S / D) epitaxial (epi) liner to form an oxidized doped source / drain (S / D) epitaxial (epi) liner; exposing the substrate to an inhibitor compound to selectively passivate surfaces of the plurality of channel layers over surfaces of the doped source / drain (S / D) epitaxial (epi) liner, the inhibitor compound comprising one or more of a silanol, an alcohol, an alkyne, or an alkene; andforming an inner spacer on the doped S / D epi liner.

2. The method of claim 1 , where the plurality of channel layers comprise silicon (Si) and have a hydrogen-terminated surface.

3. The method of claim 1 , wherein the doped S / D epi liner comprises silicon germanium (SiGe) having a germanium concentration in a range of from greater than 0% to 25 %.

4. The method of claim 3, wherein the doped S / D epi liner is doped with a dopant comprising one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), or antimony (Sb).

5. The method of claim 1 , wherein the film stack is a superlattice structure.Attorney Docket No.: 44027828WO01 PATENT326. The method of claim 1 , wherein the semiconductor device comprises a transistor selected from the group consisting of a gate-all-around (GAA), a field-effect transistor (FinFETs), and complementary field effect transistor (CFETs).

7. The method of claim 1 , wherein the inner spacer comprises one or more of silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), or a IOW-K material.

8. The method of claim 1 , further comprising densifying the inner spacer.

9. A method of forming a semiconductor device, the method comprising:selectively removing a plurality of semiconductor material layers from a film stack on a substrate to form a plurality of openings adjacent a plurality of channel layers, the film stack comprising the plurality of channel layers and the plurality of semiconductor material layers alternatingly arranged and extending between a source / drain (S / D) epitaxial (epi) layer and doped source / drain (S / D) epitaxial (epi) liner on the substrate;pre-cleaning the film stack on the substrate to selectively remove oxides and form a plurality of reduced channel layers while retaining oxides on the doped S / D epi liner;exposing the substrate to an inhibitor compound to passivate surfaces of the plurality of channel layers over the doped source / drain (S / D) epitaxial (epi) liner with retained oxides; andforming an inner spacer on non-passivated surfaces of the oxidized doped S / D epi liner.

10. The method of claim 9, wherein the semiconductor device comprises a transistor selected from the group consisting of a gate-all-around (GAA), a field-effect transistor (FinFETs), and complementary field effect transistor (CFETs).Attorney Docket No.: 44027828WO01 PATENT3311.The method of claim 9, where the plurality of channel layers comprise silicon (Si) and the plurality of semiconductor material layers comprise silicon germanium (SiGe).

12. The method of claim 9, wherein the doped S / D epi liner comprises silicon germanium (SiGe) have a germanium concentration in a range of from greater than 0% to 25 %.

13. The method of claim 12, wherein the doped S / D epi liner is doped with a dopant.

14. The method of claim 13, wherein the dopant comprises one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), or antimony (Sb).

15. The method of claim 9, wherein the inhibitor compound comprises one or more of a silanol, an alcohol, an alkyne, or an alkene.

16. The method of claim 9, wherein the inner spacer comprises one or more of silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), or a IOW-K material.

17. The method of claim 9, further comprising densifying the inner spacer.

18. The method of claim 9, wherein the film stack is a superlattice structure.

19. The method of claim 9, wherein the reduced channel layers comprise hydrogentermination.

20. The method of claim 9, further comprising selectively depositing a second inner spacer on a gate spacer on a top surface of the film stack.

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