Photonic-electronic digital-to-analog and analog-to-digital converter

Abstract

A photonic computing system comprising a modulator array configured to provide integrated digital-to-analog converter (DAC) functionality; a phase-change material (PCM)-based DAC that is integrated within the modulator array, wherein the PCM-based DAC comprises a first set of one or more PCM elements; a photodetector array configured to provide integrated analog-to-digital converter (ADC) functionality; a PCM-based ADC that is integrated within the photodetector array, wherein the PCM-based ADC comprises a second set of one or more PCM elements; and a photonic computing core coupled between the modulator array and the photodetector array.

Description

PHOTONIC-ELECTRONIC DIGTTAL-TO-ANALOG AND ANALOG-TO-DIGITAL CONVERTERTECHNICAL FIELD

[0001] Various embodiments of the present disclosure relate to a digital-to-analog converter (DAC) / analog-to-digital converter (ADC) system, and more particularly, direct transformation between optical / photonic / analog and digital electronic domains.BACKGROUND

[0002] The growing demands of photonic computing and optical communications have highlighted critical efficiency bottlenecks in conventional digital-to-analog converter (DAC) architectures. For example, traditional photonic interfaces may comprise separate DAC and modulator components that introduce significant power overhead in a range of approximately 5-15 pj per bit conversion and may result in conversion stages that consume substantial power as well as introduce latency that limits overall system performance. Applicant has identified many technical shortcomings associated with existing DAC systems. For example, existing approaches for improving DAC efficiency, such as by optimizing electronic circuits or improving modulator designs, maintain separate digital-to-analog conversion and optical modulation.BRIEF SUMMARY

[0003] Various embodiments described herein relate to an integrated conversion system that enables direct transformation between optical / photonic / analog and digital electronic domains.

[0004] According to some embodiments, a photonic computing system comprises a modulator array configured to provide integrated digital-to-analog converter (DAC) functionality; a phasechange material (PCM)-based DAC that is integrated within the modulator array, wherein the PCM-based DAC comprises a first set of one or more PCM elements; a photodetector array configured to provide integrated analog-to-digital converter (ADC) functionality; a PCM-based ADC that is integrated within the photodetector array, wherein the PCM-based ADC comprises a second set of one or more PCM elements; and a photonic computing core coupled between the modulator array and the photodetector array.

[0005] In some embodiments, the PCM-based DAC comprises a PCM-based weightedelement array that is configured to convert digital inputs to optical signals in accordance with one or more optical losses. In some embodiments, the PCM-based weighted element array is configured to provide binary-weighted attenuation by switching between amorphous and crystalline states. In some embodiments, the PCM-based ADC is configured to provide temporal accumulation by the photodetector array accumulating charge over one or more cycles before readout. In some embodiments, the photonic computing core comprises one or more of on-chip one-dimensional lens arrays, splitters, micro-ring resonators, or integrated photodetectors.

[0006] According to some embodiments, an integrated photodetector-analog-to-digital converter (ADC) structure comprises a splitter configured to (i) receive an optical signal and (ii) divide the optical signal into a plurality of parallel paths; a plurality of loss inducers coupled to the splitter, wherein a loss inducer of the plurality of loss inducers is (i) configured in a path of the plurality of parallel paths and (ii) configured to provide a selected level of optical attenuation; and a plurality of photodetectors, wherein a photodetector of the plurality of photodetectors is (i) coupled the loss inducer of the plurality of loss inducers and (ii) configured to generate a digital electronic output.

[0007] In some embodiments, the optical signal comprises an n-bit analog signal, and the splitter is configured to convert the n-bit analog signal to an n-bit digital electronic output. In some embodiments, the plurality of loss inducers comprises non-volatile phase-change material (PCM) configured to induce a plurality of quantized loss levels. In some embodiments, the non-volatile PCM is configured to induce a plurality of loss levels from a range of approximately -4dB to -9.2dB across the plurality of parallel paths. In some embodiments, the plurality of photodetectors are configured to generate a digital output pattern by generating a plurality of digital electronic outputs based on a threshold.

[0008] According to some embodiments, an integrated DAC-modulator structure comprises a plurality of loss-inducing elements that are arranged in a cascaded configuration, wherein (i) a loss-inducing element of the plurality of loss-inducing elements (a) comprises phase-change material (PCM), and (b) is configured to provide a binary-scaled loss value that corresponds to a bit position of a digital electronic input, and (ii) the plurality of loss-inducing elements are configured to convert an n-bit digital electronic input into an n-bit optical output; and a control interface that is configured to selectively activate the plurality of loss-inducing elements in accordance with a plurality of bits corresponding to an n-bit digital electronic input.

[0009] In some embodiments, the plurality of loss-inducing elements comprise a first loss element with a loss of 2dB, a second loss element with a loss of 4dB, a third loss element with a loss of 8dB, and a fourth loss element with a loss of 16dB . In some embodiments, the loss-inducing element comprises a PCM spiral waveguide structure, and the PCM spiral waveguide structure comprises one or more paths that provide one or more optical delays. In some embodiments, the plurality of loss-inducing elements are configured as an AND gate or an OR gate that processes a most-significant bit (MSB) electronic input and a least-significant bit (LSB) electronic input. In some embodiments, the AND gate or the OR gate comprises an electronic-photonic domain interface that is configured to convert the MSB electronic input or the LSB electronic input to an optical signal with an attenuation level that corresponds to the MSB electronic input or the LSB electronic input.BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments incorporating teachings of the present disclosure are shown and described with respect to the figures presented herein.

[0011] FIG. 1 A is a schematic diagram of an example digital-to-optical conversion subsystem.

[0012] FIG. IB is a schematic diagram of an example optical-to-digital conversion subsystem.

[0013] FIG. 2 is an example photonic computing architecture in accordance with some embodiments of the present disclosure.

[0014] FIG. 3 is a schematic diagram of an example integrated photodetector-ADC structure in accordance with some embodiments of the present disclosure.

[0015] FIG. 4 is a data flow diagram of an example phase change material (PCM)-based photonic ADC in accordance with some embodiments of the present disclosure.

[0016] FIG. 5 is a schematic diagram of an example integrated DAC-modulator structure in accordance with some embodiments of the present disclosure.

[0017] FIG. 6 is an example 4-bit PCM-based weighted optical attenuator array in accordance with some embodiments of the present disclosure.

[0018] FIG. 7 is an example PCM spiral waveguide design in accordance with some embodiments of the present disclosure.

[0019] FIG. 8A is a dataflow diagram of an example AND gate DAC design with 2-input configurations in accordance with some embodiments of the present disclosure.

[0020] FIG. 8B is a dataflow diagram of an example OR gate DAC design with 2-input configurations in accordance with some embodiments of the present disclosure.

[0021] FIG. 9 is a diagram of example PCM-based weighted element array in accordance with some embodiments of the present disclosure.

[0022] FIG. 10 is waveforms of example inputs and output of an OR gate DAC in accordance with some embodiments of the present disclosure.DETAILED DESCRIPTION

[0023] Various embodiments of the present disclosure now will be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the disclosure are shown. Indeed, the disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. The term “or” is used herein in both the alternative and conjunctive sense, unless otherwise indicated. The terms “illustrative,” “example,” and “exemplary” are used to be examples with no indication of quality level. Like numbers refer to like elements throughout.General Overview and Example Technical Improvements

[0024] As described above, there are many technical shortcomings associated with existing digital-to-analog converter (DAC) and / or analog-to-digital converter (ADC) systems. Traditional interface systems between photonic / analog / optical and electronic / digital domains may comprise multiple DAC / ADC components and conversions between electronic and photonic domains. As a result, power and latency overhead may be introduced by separate DAC, modulator, and ADC components.

[0025] FIG. 1A is a schematic diagram of an example digital-to-optical conversion subsystem 100A. The digital-to-optical conversion subsystem 100A comprises a DAC 102 (comprising a resistor network that is coupled to an operational amplifier) that converts digital electronic signals 104 (from the electronic domain 106A) to analog electronic signals 108. The digital-to-optical conversion subsystem 100A further comprises an optical modulator 110 that converts the analog electronic signals 108 to unprocessed / unfiltered optical / photonic signals 112. The unprocessed / unfiltered optical / photonic signals 112 are further processed in a photonic domain114 via photonic computing hardware 116 that is configured to perform operations (e.g., joint transform correlator (JTC) and / or photonic tensor core (PTC)) on the unprocessed / unfiltered optical / photonic signals 112 to generate processed / filtered optical / photonic signals 118 with a desired gain (e.g., 8 dB).

[0026] FIG. IB is a schematic diagram of an example optical-to-digital conversion subsystem 100B. The optical-to-digital conversion subsystem 100B comprises a photodetector 120 that converts processed / filtered optical / photonic signals 118 to analog electronic signals 122. The optical-to-digital conversion subsystem 100B further comprises an ADC 124 (comprising a 2-bit priority decoder circuit with reference voltage comparators) that converts (e.g., digitizes) the analog electronic signals 122 to digital electronic signals 126 in the electronic domain 106B.

[0027] A photonic computing system may comprise an architecture that integrates electronic and optical domains through individual DAC and ADC components, such as the digital-to-optical conversion subsystem 100A and the optical-to-digital conversion subsystem 100B depicted in FIG.1A and FIG. IB, respectively. However, such a multi-component approach may result in high power consumption, reduced speed, and creates conversion bottlenecks (e.g., associated with multi-domain conversions between electronic and photonic domains).

[0028] Accordingly, various embodiments of the present disclosure integrate DAC and ADC components into unified elements, thereby reducing energy consumption, increasing conversion speed, and eliminating conventional system bottlenecks. In some embodiments, a photonic computing system comprises phase-change material (PCM)-based components that enable efficient domain conversion while significantly reducing power consumption compared to traditional approaches. PCMs may offer unique advantages by leveraging their ability to switch between amorphous and crystalline states, enabling persistent changes in optical properties that may reduce and / or eliminate continuous power consumption. Thus, by leveraging PCM properties to achieve direct digital-to-optical conversion, power consumption may be potentially reduced, for example, by approximately 70% while maintaining high-speed operation above 4 GHz. Applications of some embodiments of the present disclosure include, but are not limited to, highspeed data conversion for artificial intelligence (AI) / machine learning (ML), signal processing, data communications, and mixed-signal systems, offering significant advantages over conventional conversion methods.Example System Architecture

[0029] FIG. 2 is an example photonic computing architecture 200 in accordance with some embodiments of the present disclosure. The photonic computing architecture 200 comprises integrated DAC and ADC components via PCM-based DAC 202 and PCM-based ADC 204. The PCM-based DAC 202 may comprise a first set of one or more PCM elements that are integrated and / or incorporated within a modulator array 206 to provide integrated DAC functionality with reduced (e.g., approximately 70%) power consumption compared to conventional DACs.

[0030] The PCM-based ADC 204 may comprise a second set of one or more PCM elements that are integrated and / or incorporated within a photodetector array 208 that comprises high-speed (e.g., greater than approximately 40 GHz) photodetectors to provide integrated ADC functionality that may achieve a 90% power reduction over conventional ADCs. The photonic computing architecture 200 further comprises photonic computing core 210, which comprises components, such as on-chip one-dimensional lens arrays, splitters, micro-ring resonators, and / or integrated photodetectors for signal processing.

[0031] Accordingly, the photonic computing architecture 200 integrates DAC and ADC components for efficient photonic computing interfaces. Such integrated structures may reduce or obviate intermediate conversion steps while maintaining high accuracy and speed. In some embodiments, the PCM-based DAC comprises a PCM-based weighted element array that directly converts digital inputs to optical signals through precisely controlled optical losses. The PCM-based weighted element array may provide binary-weighted attenuation (e.g., lx, 2x, 4x) when switched between amorphous and crystalline states, thereby obviating separate DAC and modulator components through single-step conversion. For example, arranged in a monolithic silicon photonic platform with integrated heaters for thermal control, a system comprising the photonic computing architecture 200 may comprise 16 distinct optical levels for 4-bit resolution at 30 GHz switching speeds. The PCM array’s non-volatile nature may reduce or remove static power consumption while maintaining linearity across the input range.

[0032] The PCM-based ADC 204 may be configured to provide a temporal accumulation where photodetectors (of the photodetector array 208) accumulate charge over one or more cycles before readout, which may reduce ADC sampling frequency significantly (e.g., approximately 16x) while maintaining throughput through capacitive element integration. For example, capacitive elements may be integrated with the photodetectors to store accumulated charge frommultiple optical pulses. The accumulated charge may then be read out in a conversion cycle. Such an approach may particularly benefit neural networks where partial sum accumulation is performed, as the accumulated optical signals may be converted to digital form in fewer conversion cycles. The PCM-based ADC 204 may also incorporate optimized transimpedance amplifiers (TIAs) and comparators for signal integrity at reduced sampling rates while interfacing with the photonic computing core 210 to minimize conversion overhead.

[0033] According to various embodiments of the present disclosure, an integrated photonic memory architecture comprises PCM-based multi-state memory. In some embodiments, a PCM-based weighted element array converts digital inputs into binary numbers through optical losses (e.g., 2dB, 4dB, 8dB, and 16dB). In some embodiments, PCM elements within the PCM-based weighted element array are configured to switch between amorphous and crystalline states to provide binary-weighted attenuation. The amorphous state of the PCM may exhibit higher optical absorption, resulting in greater signal attenuation, while the crystalline state may exhibit lower optical absorption, resulting in reduced signal attenuation.

[0034] The PCM-based weighted element array may function as a programmable randomaccess memory (P-RAM) with electro-thermal writing and ultra-fast optical reading (e g., in picoseconds). For example, state switching may be achieved through thermal control, such as via integrated heaters that apply controlled heating pulses to transition the PCM between states. By selectively switching individual PCM elements between these states, the PCM-based weighted element array may provide programmable binary-weighted attenuation levels (e.g., 1 x, 2*, 4*, 8x) that correspond to bit positions in a digital input. The non-volatile nature of the PCM states may allow the attenuation configuration to persist without continuous power application. Accordingly, the integrated photonic memory architecture may provide (a) high efficiency (e.g., operating at approximately 30GHz) with low power consumption, and (b) improved performance metrics including and extremely low insertion loss. The integrated photonic memory architecture may also be lOOx more effective compared to conventional DAC and ADC, thereby making it highly suitable for next-generation photonic computing applications.

[0035] In some embodiments, the integrated photonic memory architecture employs engineered materials and structures to induce precisely controlled optical losses, enabling weightbased conversion. For example, the integrated photonic memory architecture may comprise (a) PCM-based loss-inducing elements for binary weighted conversion, (b) hybrid structures thatcombine multiple materials and geometries for optimized performance, and (c) parallel and cascaded loss implementations for scalability and precision.

[0036] FIG. 3 is a schematic diagram of an example integrated photodetector-ADC structure 300 in accordance with some embodiments of the present disclosure. The integrated photodetector-ADC structure 300 comprises a plurality of loss inducers 304 (e.g., with different PCM-induced losses) that are configured to convert an w-bit optic / photonic / analog signal 302 to an / / -bit digital electronic output 306. The / / -bit optic / photonic / analog signal 302 is split through a lx2nSplitter 304 into a plurality paths corresponding to the plurality of loss inducers 304 and then provided through a plurality of photodetectors 308 to generate a digital electronic output 310.

[0037] FIG. 4 is a data flow diagram of an example PCM-based photonic ADC 400 in accordance with some embodiments of the present disclosure. The PCM-based photonic ADC 400 may comprise non-volatile PCM that is configured to induce quantized loss levels. An analog, photonic, and / or optical input signal 402 is split into four paths comprising non-volatile PCM 404 with various PCM-induced losses (-4dB to -9.2dB). Each path is associated with a photodetector of a plurality of photodetectors 406 that generate a plurality of digital electronic outputs 408. In some embodiments, the plurality of photodetectors 406 are configured to generate a digital output pattern through threshold-based detection. Each photodetector may be configured to compare its received optical power against a predetermined threshold (e.g., 30pW) and generate a binary output based on whether the received power exceeds the threshold. For example, when the optical power at a photodetector exceeds a 30pW threshold, the photodetector may output a logical high value (e.g., “1”), and when the optical power falls below the threshold, the photodetector may output a logical low value (e.g., “0”). The combination of binary outputs from the plurality of photodetectors 406 creates a digital output pattern (e.g., “1111,” “0111,” “0011,” and “0001”) that corresponds to the analog input level, thereby creating a 2 -bit digital output. Accordingly, a PCM-based design may obviate complex electronic ADC circuitry, thereby improving power efficiency and conversion speed.

[0038] FIG. 5 is a schematic diagram of an example integrated DAC-modulator structure 500 in accordance with some embodiments of the present disclosure. The integrated DAC-modulator structure 500 comprises a plurality of loss-inducing material 504 that are connected in series and / or cascaded and are used to convert z?-bit digital electronic input 502 into analog electronic input 506 that is modulated into / / -bit optic / photonic / analog output 508. In some embodiments, the integratedDAC-modulator structure 500 comprises a control interface that is configured to selectively activate the plurality of loss-inducing material 504 in accordance with a plurality of bits corresponding to the / / -bit digital electronic input 502. The control interface may receive the / / -bit digital electronic input 502 and generate control signals that selectively enable or bypass individual loss-inducing elements based on the binary value of each bit position. For example, when a bit is set to a logical high value, the control interface may activate the corresponding loss-inducing element to apply its associated attenuation level, and when a bit is set to a logical low value, the control interface may bypass or deactivate the corresponding loss-inducing element. Such selective activation may enable direct conversion from digital electronic inputs to modulated optical outputs with attenuation levels that correspond to digital input values.

[0039] FIG. 6 is an example 4-bit PCM-based weighted optical attenuator array 600 in accordance with some embodiments of the present disclosure. The 4-bit PCM-based weighted optical attenuator array 600 comprises binary-scaled loss elements 602 comprising a plurality of loss values. A first binary-scaled loss element 602A representing bit 0 comprises a loss of 2dB, a second binary-scaled loss element 602B representing bit 1 comprises a loss of 4dB, a third binary-scaled loss element 602C representing bit 2 comprises a loss of 8 dB, and a fourth binary-scaled loss element 602D representing bit 3 comprises a loss of 16 dB.

[0040] FIG. 7 is an example PCM spiral waveguide design 700 in accordance with some embodiments of the present disclosure. The PCM spiral waveguide design 700 comprises an integrated PCM spiral waveguide structure comprising PCM, where different sections or parallel paths comprising anand an-i provide specific optical delays (weights) for signals. In some embodiments, the an-i path is used to implement true time delay for temporal signal processing.

[0041] FIG. 8A is a dataflow diagram of an example AND gate DAC design 800A with 2-input configurations in accordance with some embodiments of the present disclosure.

[0042] FIG. 8B is a dataflow diagram of an example OR gate DAC design 800B with 2-input configurations in accordance with some embodiments of the present disclosure.

[0043] The DAC designs 800A and 800B comprise electronic-photonic domain interfaces for processing most-significant bit (MSB) electronic inputs 802A, 802B and least-significant-bit (LSB) electronic inputs 804 A, 804B. An electronic-photonic domain interface may be configured to convert digital electronic inputs to optical signals with attenuation levels that correspond to the bit significance of each input. An electronic-photonic domain interface may apply binary-weightedattenuation such that the MSB path receives a first attenuation level and the LSB path receives a second attenuation level that is scaled relative to the first attenuation level. The resulting optical signals may be combined to produce an output optical signal with an amplitude that corresponds to the combined digital input value.

[0044] The MSB electronic inputs 802A and 802B, representing a binary sequence “1100,” and the LSB electronic inputs 804A and 804B, representing a binary sequence of “1010,” are converted to corresponding optical signals with different attenuation levels. Referring to FIG. 8A, the MSB electronic input 802A is converted to optical signal 810A with attenuation level 806A and LSB electronic input 804A is converted to optical signal 812A with attenuation level 808A. According to FIG. 8B, the MSB electronic input 802B is converted to optical signal 810B with attenuation level 806B and LSB electronic input 804B is converted to optical signal 812B with attenuation level 808B.

[0045] In some embodiments, the AND gate and OR gate configurations depicted in FIGS. 8A and 8B process MSB and LSB inputs through an electronic-photonic domain interface to achieve different logical combining functions. In an AND gate configuration, optical output may comprise a logical high value when both the MSB and LSB inputs are at logical high values, with the output attenuated when either input is at a logical low value. In an OR gate configuration, the optical output may comprise a logical high value when either the MSB or LSB input comprises a logical high value, with the output attenuated when both inputs comprise logical low values. The electronic-photonic domain interface may implement such logical functions by selectively applying attenuation based on the input bit states. For example, the electronic-photonic domain interface may convert an MSB electronic input to a first optical signal with a first attenuation level and convert an LSB electronic input to a second optical signal with a second attenuation level, where the attenuation levels are determined by the logical gate configuration and the binary weight of each input position. By doing so, direct conversion from multi-bit digital electronic inputs to weighted optical outputs may be provided through an integrated gate-based DAC structure.

[0046] FIG. 9 is a diagram of example PCM-based weighted element array 900 in accordance with some embodiments of the present disclosure. An example dynamic signal response is depicted of the PCM-based weighted element array 900 implemented as of an OR gate DAC operating at 1550nm wavelength.

[0047] FIG. 10 are waveforms of inputs and output of a PCM-based weighted element array implemented as an OR gate DAC in accordance with some embodiments of the present disclosure.

[0048] In some embodiments, an element array weight-loss inducing system provides direct data conversion between photonic and digital domains. In some embodiments, the element array weight-loss inducing system comprises one or more weight-loss elements, wherein the one or more weight-loss elements comprise phase change materials. In some embodiments, the one or more weight-loss elements are arranged in parallel and / or cascaded configurations. In some embodiments, the element array weight-loss inducing system comprises one or more of an integrated photodetector-ADC structure or an integrated DAC-modulator structure.Conclusion

[0049] It should be understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application.

[0050] Many modifications and other embodiments of the present disclosure set forth herein will come to mind to one skilled in the art to which the present disclosures pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the present disclosure is not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claim concepts. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.Examples

[0051] Some embodiments of the present disclosure may be implemented by one or more computing devices, entities, and / or systems described herein to perform one or more example operations, such as those outlined below. The examples are provided for explanatory purposes. Although the examples outline a particular sequence of steps / operations, each sequence may be altered without departing from the scope of the present disclosure. For example, some of the steps / operations may be performed in parallel or in a different sequence that does not materially impact the function of the various examples. In other examples, different components of anexample device or system that implements a particular example may perform functions at substantially the same time or in a specific sequence.

[0052] Moreover, although the examples may outline a system or computing entity with respect to one or more steps / operations, each operation may be performed by any one or combination of computing devices, entities, and / or systems described herein. For example, a computing system may comprise a single computing entity that is configured to perform all of the steps / operations of a particular example. In addition, or alternatively, a computing system may comprise multiple dedicated computing entities that are respectively configured to perform one or more of the steps / operations of a particular example. By way of example, the multiple dedicated computing entities may coordinate to perform all of the steps / operations of a particular example.

[0053] Example 1. A photonic computing system comprising: a modulator array configured to provide integrated digital-to-analog converter (DAC) functionality; a phase-change material (PCM)-based DAC that is incorporated within the modulator array, wherein the PCM-based DAC comprises a first set of one or more PCM elements; a photodetector array configured to provide integrated analog-to-digital converter (ADC) functionality; a PCM-based ADC that is integrated within the photodetector array, wherein the PCM-based ADC comprises a second set of one or more PCM elements; and a photonic computing core coupled between the modulator array and the photodetector array.

[0054] Example 2. The photonic computing system of example 1, wherein the PCM-based DAC comprises a PCM-based weighted element array that is configured to convert digital inputs to optical signals in accordance with one or more optical losses.

[0055] Example 3. The photonic computing system of example 2, wherein the PCM-based weighted element array is configured to provide binary -weighted attenuation by switching between amorphous and crystalline states.

[0056] Example 4. The photonic computing system of example 1, wherein the PCM-based ADC is configured to provide temporal accumulation by the photodetector array accumulating charge over one or more cycles before readout.

[0057] Example 5. The photonic computing system of example 1, wherein the photonic computing core comprises one or more of on-chip one-dimensional lens arrays, splitters, microring resonators, or integrated photodetectors.

[0058] Example 6. An integrated photodetector-analog-to-digital converter (ADC) structure comprising: a splitter configured to (i) receive an optical signal and (ii) divide the optical signal into a plurality of parallel paths; a plurality of loss inducers coupled to the splitter, wherein a loss inducer of the plurality of loss inducers is (i) configured in a path of the plurality of parallel paths and (ii) configured to provide a selected level of optical attenuation; and a plurality of photodetectors, wherein a photodetector of the plurality of photodetectors is (i) coupled the loss inducer of the plurality of loss inducers and (ii) configured to generate a digital electronic output.

[0059] Example 7. The integrated photodetector-ADC structure of example 6, wherein: (i) the optical signal comprises an n-bit analog signal, and (ii) the splitter is configured to convert the n-bit analog signal to an n-bit digital electronic output.

[0060] Example 8. The integrated photodetector-ADC structure of example 6, wherein the plurality of loss inducers comprises non-volatile phase-change material (PCM) configured to induce a plurality of quantized loss levels.

[0061] Example 9. The integrated photodetector-ADC structure of example 8, wherein the non-volatile PCM is configured to induce a plurality of loss levels from a range of approximately -4dB to -9.2dB across the plurality of parallel paths.

[0062] Example 10. The integrated photodetector-ADC structure of example 6, wherein the plurality of photodetectors are configured to generate a digital output pattern by generating a plurality of digital electronic outputs based on a threshold.

[0063] Example 11. An integrated DAC-modulator structure comprising: a plurality of lossinducing elements that are arranged in a cascaded configuration, wherein: (i) a loss-inducing element of the plurality of loss-inducing elements (a) comprises phase-change material (PCM), and (b) is configured to provide a binary-scaled loss value that corresponds to a bit position of a digital electronic input, and (ii) the plurality of loss-inducing elements are configured to convert an n-bit digital electronic input into an n-bit optical output; and a control interface that is configured to selectively activate the plurality of loss-inducing elements in accordance with a plurality of bits corresponding to an n-bit digital electronic input.

[0064] Example 12. The integrated DAC-modulator structure of example 11, wherein the plurality of loss-inducing elements comprise a first loss element with a loss of 2dB, a second loss element with a loss of 4dB, a third loss element with a loss of 8dB, and a fourth loss element with a loss of 16dB.

[0065] Example 13. The integrated DAC-modulator structure of example 11, wherein: (i) the loss-inducing element comprises a PCM spiral waveguide structure, and (ii) the PCM spiral waveguide structure comprises one or more paths that provide one or more optical delays.

[0066] Example 14. The integrated DAC-modulator structure of example 11, wherein the plurality of loss-inducing elements are configured as an AND gate or an OR gate that processes a most-significant bit (MSB) electronic input and a least-significant bit (LSB) electronic input.

[0067] Example 15. The integrated DAC-modulator structure of example 14, wherein the AND gate or the OR gate comprises an electronic-photonic domain interface that is configured to convert the MSB electronic input or the LSB electronic input to an optical signal with an attenuation level that corresponds to the MSB electronic input or the LSB electronic input.

Claims

CLAIMSWhat is claimed is:

1. A photonic computing system comprising:a modulator array configured to provide integrated digital-to-analog converter (DAC) functionality;a phase-change material (PCM)-based DAC that is integrated within the modulator array, wherein the PCM-based DAC comprises a first set of one or more PCM elements;a photodetector array configured to provide integrated analog-to-digital converter (ADC) functionality;a PCM-based ADC that is integrated within the photodetector array, wherein the PCM-based ADC comprises a second set of one or more PCM elements; anda photonic computing core coupled between the modulator array and the photodetector array.

2. The photonic computing system of claim 1, wherein the PCM-based DAC comprises a PCM-based weighted element array that is configured to convert digital inputs to optical signals in accordance with one or more optical losses.

3. The photonic computing system of claim 2, wherein the PCM-based weighted element array is configured to provide binary-weighted attenuation by switching between amorphous and crystalline states.

4. The photonic computing system of claim 1, wherein the PCM-based ADC is configured to provide temporal accumulation by the photodetector array accumulating charge over one or more cycles before readout.

5. The photonic computing system of claim 1, wherein the photonic computing core comprises one or more of on-chip one-dimensional lens arrays, splitters, micro-ring resonators, or integrated photodetectors.

6. An integrated photodetector-analog-to-digital converter (ADC) structure comprising:a splitter configured to (i) receive an optical signal and (ii) divide the optical signal into a plurality of parallel paths;a plurality of loss inducers coupled to the splitter, wherein a loss inducer of the plurality of loss inducers is (i) configured in a path of the plurality of parallel paths and (ii) configured to provide a selected level of optical attenuation; anda plurality of photodetectors, wherein a photodetector of the plurality of photodetectors is (i) coupled the loss inducer of the plurality of loss inducers and (ii) configured to generate a digital electronic output.

7. The integrated photodetector-ADC structure of claim 6, wherein:(i) the optical signal comprises an n-bit analog signal, and(ii) the splitter is configured to convert the n-bit analog signal to an n-bit digital electronic output.

8. The integrated photodetector-ADC structure of claim 6, wherein the plurality of loss inducers comprises non-volatile phase-change material (PCM) configured to induce a plurality of quantized loss levels.

9. The integrated photodetector-ADC structure of claim 8, wherein the non-volatile PCM is configured to induce a plurality of loss levels from a range of approximately -4dB to -9.2dB across the plurality of parallel paths.

10. The integrated photodetector-ADC structure of claim 6, wherein the plurality of photodetectors are configured to generate a digital output pattern by generating a plurality of digital electronic outputs based on a threshold.

11. An integrated DAC -modulator structure comprising:a plurality of loss-inducing elements that are arranged in a cascaded configuration, wherein:(i) a loss-inducing element of the plurality of loss-inducing elements (a) comprises phase-change material (PCM), and (b) is configured to provide a binary-scaled loss value that corresponds to a bit position of a digital electronic input, and(ii) the plurality of loss-inducing elements are configured to convert an n-bit digital electronic input into an n-bit optical output; anda control interface that is configured to selectively activate the plurality of loss-inducing elements in accordance with a plurality of bits corresponding to an n-bit digital electronic input.

12. The integrated DAC-modulator structure of claim 11, wherein the plurality of loss-inducing elements comprise a first loss element with a loss of 2dB, a second loss element with a loss of 4dB, a third loss element with a loss of 8dB, and a fourth loss element with a loss of 16dB.

13. The integrated DAC-modulator structure of claim 11, wherein:(i) the loss-inducing element comprises a PCM spiral waveguide structure, and(ii) the PCM spiral waveguide structure comprises one or more paths that provide one or more optical delays.

14. The integrated DAC-modulator structure of claim 11, wherein the plurality of loss-inducing elements are configured as an AND gate or an OR gate that processes a most-significant bit (MSB) electronic input and a least-significant bit (LSB) electronic input.

15. The integrated DAC-modulator structure of claim 14, wherein the AND gate or the OR gate comprises an electronic-photonic domain interface that is configured to convert the MSB electronic input or the LSB electronic input to an optical signal with an attenuation level that corresponds to the MSB electronic input or the LSB electronic input.

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