Coaxial test socket and printed circuit board interfaces for testing integrated circuit chips

Abstract

A test socket assembly for coupling an integrated circuit (IC) chip to a first printed circuit board (PCB) and to a second PCB is provided. The test socket assembly includes a bottom conductive body defining a first plurality of cavities extending from a first surface to a second surface, a top conductive body defining a second plurality of cavities extending from a third surface to a fourth surface, a bottom signal probe disposed in a first signal cavity of the first plurality of cavities, a bottom ground probe disposed in a first ground cavity of the first plurality of cavities, a top signal probe disposed in a second signal cavity of the second plurality of cavities, and a top ground probe disposed in a second ground cavity of the second plurality of cavities.

Description

S1AIP79370PC00(39717-146)1SYSTEMS AND METHODS FOR COAXIAL TEST SOCKET AND PRINTED CIRCUIT BOARD INTERFACES FOR TESTING PACKAGE- ON-PACKAGE INTEGRATED CIRCUIT CHIPSCROSS-REFERENCE TO RELATED APPLICATION

[0001] The present application claims priority to US Provisional Patent Application No. 63 / 777,209, filed 25 March 2025, which is incorporated herein by reference in its entirety.BACKGROUND

[0002] The embodiments described herein relate generally to electrical interconnects and, more particularly, to interfaces for coaxial test sockets and printed circuit boards (PCBs) for testing package-on-package (PoP) integrated circuit (1C) chips.

[0003] In the electronics and semiconductor industries, systems used to test 1C semiconductor chips often include test sockets. A test socket is disposed on a PCB, or “load board,” and may include a socket body and one or more probes (i.e., electrical contacts or pins) that electrically connect the IC chip to the PCB. Test sockets generally must meet various electrical and mechanical performance thresholds to adequately test a given IC chip. For example, the test socket should maintain signal integrity, such as a desired error rate or signal-to-noise ratio, at a desired data transfer rate for the IC under test. Current test sockets generally maintain signal integrity up to a data transfer rate of about 30 gigabits per second. However, some applications, such as 5G telecommunications or artificial intelligence, may require higher rates of data transfer. A test socket capable of maintaining signal integrity at higher data transfer rates is therefore desirable.BRIEF SUMMARY

[0004] In one aspect, a test socket assembly for coupling an integrated circuit (IC) chip to a first printed circuit board (PCB) and to a second PCB is provided. The test socket assembly includes a bottom conductive body having a first surface configured to face the first PCB and a second surface configured to face the IC chip. TheS1A1P79370PC00(39717-146)2bottom conductive body defines a first plurality of cavities extending from the first surface to the second surface. The test socket assembly further includes a top conductive body having a third surface configured to face the 1C chip and a fourth surface configured to face the second PCB. The top conductive body defines a second plurality of cavities extending from the third surface to the fourth surface. The test socket assembly further includes a bottom signal probe disposed in a first signal cavity of the first plurality of cavities. The bottom signal probe is configured to electrically connect to a signal conductor of the first PCB and to a first signal pad of the 1C chip. The test socket assembly further includes a bottom ground probe disposed in a first ground cavity of the first plurality of cavities. The bottom ground probe is configured to electrically connect to a ground conductor of the first PCB and to a first ground pad of the 1C chip. The test socket assembly further includes a top signal probe disposed in a second signal cavity of the second plurality of cavities. The signal probe is configured to electrically connect to a signal conductor of the second PCB and to a second signal pad of the 1C chip. The test socket assembly further includes a top ground probe disposed in a second ground cavity of the second plurality of cavities. The ground probe configured to electrically connect to a ground conductor of the second PCB and to a second ground pad of the 1C chip.

[0005] In another aspect, a method for manufacturing a test socket assembly for coupling an 1C chip to a first PCB and to a second PCB is provided. The method includes forming a bottom conductive body having a first surface configured to face the first PCB and a second surface configured to face the 1C chip, the bottom conductive body defining a first plurality of cavities extending from the first surface to the second surface. The method further includes forming a top conductive body having a third surface configured to face the 1C chip and a fourth surface configured to face the second PCB, the top conductive body defining a second plurality of cavities extending from the third surface to the fourth surface. The method further includes positioning a bottom signal probe in a first signal cavity of the first plurality of cavities, the bottom signal probe configured to electrically connect to a signal conductor of the first PCB and to a first signal pad of the 1C chip. The method further includes positioning a bottom ground probe in a first ground cavity of the first plurality of cavities, the bottom ground probe configured to electrically connect to a ground conductor of the first PCB and to a first ground pad of theS1A1P79370PC00(39717-146)31C chip. The method further includes positioning a top signal probe in a second signal cavity of the second plurality of cavities, the top signal probe configured to electrically connect to a signal conductor of the second PCB and to a second signal pad of the 1C chip. The method further includes positioning a top ground probe in a second ground cavity of the second plurality of cavities, the top ground probe configured to electrically connect to a ground conductor of the second PCB and to a second ground pad of the 1C chip.

[0006] In another aspect, a test assembly is provided. The test assembly includes a first printed circuit board PCB, a second PCB, and a test socket assembly for coupling an 1C chip to the first PCB and to the second PCB. The test socket assembly includes a bottom conductive body having a first surface configured to face the first PCB and a second surface configured to face the 1C chip. The bottom conductive body defines a first plurality of cavities extending from the first surface to the second surface. The test socket assembly further includes a top conductive body having a third surface configured to face the 1C chip and a fourth surface configured to face the second PCB. The top conductive body defines a second plurality of cavities extending from the third surface to the fourth surface. The test socket assembly further includes a bottom signal probe disposed in a first signal cavity of the first plurality of cavities. The bottom signal probe is configured to electrically connect to a signal conductor of the first PCB and to a first signal pad of the 1C chip. The test socket assembly further includes a bottom ground probe disposed in a first ground cavity of the first plurality of cavities. The bottom ground probe is configured to electrically connect to a ground conductor of the first PCB and to a first ground pad of the 1C chip. The test socket assembly further includes a top signal probe disposed in a second signal cavity of the second plurality of cavities. The signal probe is configured to electrically connect to a signal conductor of the second PCB and to a second signal pad of the 1C chip. The test socket assembly further includes a top ground probe disposed in a second ground cavity of the second plurality of cavities. The ground probe configured to electrically connect to a ground conductor of the second PCB and to a second ground pad of the 1C chip.S1AIP79370PC00(39717-146)4BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIGS. 1-6B show example embodiments of the systems and methods described herein.

[0008] FIG. 1 is a cross-sectional view of an example test assembly including an example test socket;

[0009] FIG. 2 is a cross-sectional view of another example test assembly;

[0010] FIG. 3 is a cross-sectional view of another example test assembly;

[0011] FIG. 4 is a cross-sectional view of an example socket body for use in the example test assemblies shown in FIGS. 1 and 2;

[0012] FIG. 5 is a cross-sectional view of another example test assembly;

[0013] FIG. 6A is a flowchart of an example method for manufacturing a test socket assembly; and

[0014] FIG. 6B is a continuation of the flowchart shown in FIG. 6A. DETAILED DESCRIPTION

[0015] In the following specification and the claims, reference will be made to a number of terms, which shall be defined to have the following meanings.

[0016] The singular forms “a,” “an,” and “the” include plural references unless the context clearly dictates otherwise.

[0017] Approximating language, as used herein throughout the specification and claims, is applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about,” “approximately,” andS1A1P79370PC00(39717-146)5“substantially,” is not to be limited to the precise value specified. In at least some instances, the approximating language may correspond to the precision of an instrument for measuring the value. Here and throughout the specification and claims, range limitations are combined and interchanged, such ranges are identified and include all the sub-ranges contained therein unless context or language indicates otherwise.

[0018] The disclosed systems and methods include a test socket assembly for coupling an integrated circuit (1C) chip to at least one printed circuit board (PCB), for example, to facilitate testing of the 1C chip using the PCB. In some example embodiments, the 1C chip is a “package-on-package” (PoP) 1C chip having contact pads on two sides (e.g., top and bottom), and the test socket assembly is configured to couple the 1C chip to two PCBs or other external circuits located on opposite sides (e.g., above and below) the 1C chip. For example, during use, the 1C chip may be placed onto a bottom test socket that is connected to a first PCB, and then a top test socket connected to a second PCB may be placed onto the bottom socket to hold the 1C chip between the top and bottom test sockets. As described in further detail below, both the bottom test socket and top test socket utilize coaxial structures for signal transmission between the 1C chip and respective PCBs, which enables a use of higher frequency signals for communication between the 1C chip and the PCBs.

[0019] The test sockets include a conductive body having a first surface facing the corresponding PCB and a second surface facing the 1C chip. The conductive body defines one or more signal cavities and one or more ground cavities, each extending from the first surface to the second surface. The test sockets further include one or more signal probes each disposed in one of the signal cavities, such that the signal probes and signal cavities form a coaxial structure within the conductive body. These signal probes are configured to electrically connect to a signal conductor of the corresponding PCB and to a signal pad of the 1C chip, for example, to enable a transmission of electrical signals between the PCBs and the 1C chip.

[0020] The test sockets further include one or more ground probes each disposed in one of the ground cavities. These ground probes are configured to electrically connect to a ground conductor of the corresponding PCB and to a ground padS1A1P79370PC00(39717-146)6of the 1C chip to enable an electrical connection of respective grounds of the PCB and 1C chip. The ground probe is further electrically connected, either directly or indirectly, to the conductive body, enabling the conductive body to function as a coaxial shielding for the signal probe and enabling the test socket to achieve improved electrical performance on parameters such as, for example, a higher data transfer rate between the 1C chip and multiple (e.g., top and bottom) PCBs or other external circuits.

[0021] The conductive body of each test socket may also define one or more power cavities extending from the first surface to the second surface, and in which a power probe may be disposed. Likewise, the power probe is configured to electrically connect to a power conductor of the corresponding PCB and to a power pad of the 1C chip. The ground probe is configured to be electrically connected to the conductive body.

[0022] FIG. 1 is a cross-sectional view of an example test assembly 100 including a test socket 102, a PCB 104, and an integrated circuit (1C) chip 106. In some embodiments, test socket 102 is configured to enable a communicative coupling of 1C chip 106 chip to PCB 104 for testing 1C chip 106. As described in further detail below, test socket 102 provides for the transmission of electrical signals and electrical power between PCB 104 and 1C chip 106 and a connection of respective electrical grounds of PCB 104 and 1C chip 106.

[0023] Test socket 102 includes a conductive body 108 (sometimes referred to herein as a “bottom conductive body”), a signal probe 110, a ground probe 112, and a power probe 114. Conductive body 108 has a first surface 116 disposed adjacent to PCB 104 and a second surface 118 disposed adjacent to 1C chip 106.Conductive body 108 is electrically conductive, and includes a conductive material such as, for example, aluminum, magnesium, titanium, zirconium, copper, iron, or an alloy including one or more thereof. Conductive body 108 includes a plurality of cavities, including a signal cavity 120 extending from a first signal opening 122 at first surface 116 to a second signal opening 124 at second surface 118, a ground cavity 126 extending from a first ground opening 128 at first surface 116 to a second ground opening 130 at second surface 118, and a power cavity 132 extending from a first power opening 134 at first surface 116 to a second power opening 136 at second surface 118. In someS1A1P79370PC00(39717-146)7embodiments, conductive body 108 includes a plurality of signal cavities 120, ground cavities 126, and / or power cavities 132. In certain embodiments, a distance between any two of signal probe 110, ground probe 112, and power probe 114 is greater than about 0.5 millimeters center to center.

[0024] Signal probe 110 is located within signal cavity 120, and is configured to contact and electrically connect to a signal conductor 138 disposed on a substrate 140 of PCB 104 and to a signal pad 142 of 1C chip 106 to enable a transmission of electrical signals between PCB 104 and 1C chip 106. Signal probe 110 may include a single conductive piece or may include multiple components. For example, in some embodiments, signal probe 110 is a spring probe. Signal probe 110 is electrically insulated from conductive body 108. For example, in certain embodiments, signal probe 110 or signal cavity 120 may include an electrically insulative coating (not shown). In such embodiments, the insulative coating may be, for example, an anodic film generated on the metal, a polytetrafluoroethylene (PTFE) coating, a combination thereof, or another coating or sealing material. For example, in some such embodiments, the coating includes an anodized aluminum layer having a thickness of greater than about 0.02 millimeters and a PTFE sealing layer having a thickness of greater than about 0.001 millimeters. In some embodiments, signal probe 110 includes one or more insulation members 144 disposed on signal probe 110. While two insulation members 144 are shown, there may be more or less than two insulation members 144 on signal probe 110. Insulation members 144 may be rings that wrap around a portion of a circumference of the outside surface of signal probe 110 or may wrap around the entirety of a circumference of the outside surface of signal probe 110. Accordingly, insulation members 144 may be annular in shape. In some embodiments signal cavity 120 widens at second signal opening 124 to form a signal counterbore 146. In such embodiments, signal counterbore 146 is shaped to receive at least a portion of signal pad 142 without causing signal pad 142 to contact conductive body 108.

[0025] Signal probe 110 and signal cavity 120 together form a coaxial transmission line. Accordingly, signal probe 110, signal cavity 120, insulation members 144, and signal counterbore 146 may be shaped and sized to achieve desired electricalS1A1P79370PC00(39717-146)8properties such as, for example, achieving a constant impedance, reducing reflection or distortion of electrical signals, reducing insertion loss and return loss, achieving a desired characteristic impedance, and / or reducing crosstalk.

[0026] Ground probe 112 is located within ground cavity 126, and is configured to contact and electrically connect to a ground conductor 148 of PCB 104 and a ground pad 150 of 1C chip 106 to electrically connect respective grounds of PCB 104 and 1C chip 106. Ground probe is further electrically connected to conductive body 108. For example, as shown in FIG. 1, ground probe 112 may contact conductive body 108. Because no insulation separates ground probe 112 and conductive body 108, ground probe 112 and conductive body 108 are electrically connected when placed in contact. As described in further detail below, in some embodiments, test socket 102 includes additional features for improving the electrical connection between ground probe 112 and conductive body 108. Like signal probe 110, ground probe 112 may include a single conductive piece or include multiple components. For example, in some embodiments, ground probe 112 is a spring probe. In some embodiments ground cavity 126 widens at second ground opening 130 to form a ground counterbore 152, which may be similar in structure to signal counterbore 146.

[0027] Power probe 114 is located within power cavity 132, and is configured to contact and electrically connect to a power conductor 154 of PCB 104 and a power pad 156 of 1C chip 106 to provide power to 1C chip 106 from PCB 104. Like signal probe 110 and ground probe 112, power probe 114 may include a single conductive piece or include multiple components. For example, in some embodiments, power probe 114 is a spring probe. Like signal probe 110, power probe 114 is electrically insulated from conductive body 108. For example, in certain embodiments, power probe 114 may include an electrically insulative coating (not shown) and / or insulation members similar to insulation members 144. In some embodiments power cavity 132 widens at second power opening 136 to form a power counterbore 158, which may be similar in structure to signal counterbore 146 and / or ground counterbore 152.

[0028] Conductive body 108 is electrically connected to ground conductor 148 of PCB 104 at least through ground probe 112. In some embodiments,S1A1P79370PC00(39717-146)9conductive body 108 is directly electrically connected to ground conductor 148. For example, conductive body 108 may be configured to contact ground conductor 148 when installed, and / or test socket 102 may include additional components for electrically connecting conductive body 108 to ground conductor 148.

[0029] As shown in FIG. 1, in certain embodiments, signal pads 142, ground pads 150, and power pads 156 may also be located on a top side of 1C chip 106. As described in further detail below, these pads located on the top side of 1C chip 106 may be used to connect 1C chip 106 to a portion of a test socket assembly that is located above 1C chip 106.

[0030] FIG. 2 is a cross-sectional view of another example test assembly 200. Test assembly includes a bottom portion 202, which generally functions similarly to test socket 102 described above with respect to FIG. 1. Test assembly 200 further includes a top portion 204 configured to be positioned with respect to bottom portion 202 such that 1C chip 106 is received and retained between bottom portion 202 and top portion 204. For example, during use, 1C chip 106 may be placed onto bottom portion 202 and then top portion 204 may be placed onto bottom portion 202 covering 1C chip 106.

[0031] Bottom portion 202 includes conductive body 108, one or more signal probes 110, and one or more ground probes 112, which generally function as described with respect to FIG. 1.

[0032] Top portion 204 includes a top conductive body 206, one or more top signal probes 208, and one or more top ground probes 210. Top conductive body 206 includes a third surface 212 adjacent to 1C chip 106 and a fourth surface 214 adjacent to a top PCB 216. Like PCB 104, top PCB 216 includes one or more conductors (not shown). Top signal probes 208 are configured to connect signal pads 142 located on a top side of 1C chip 106 to corresponding (e.g., signal) conductors of top PCB 216, and top ground probes 210 are configured to connect ground pads 150 located on a top side of 1C chip 106 to corresponding (e.g., ground) conductors of top PCB 216. Top conductive body 206 includes one or more cavities, similar to signal cavities 120 orS1A1P79370PC00(39717-146)10ground cavities 126, through which top signal probes 208 and top ground probes 210 extend. Thus, top signal probes 208 and top conductive body 206 form coaxial transmission lines similar to those formed by signal probe 110 and bottom conductive body 108.

[0033] Bottom conductive body 108 and top conductive body 206 are configured to receive 1C chip 106 between second surface 118 and third surface 212. For example, during use, 1C chip 106 may be placed onto and at least partially retained by bottom portion 202. Once, 1C chip 106 is placed onto bottom portion 202, top portion 204 may be placed onto bottom portion 202 and 1C chip 106 so that 1C chip 106 is held between bottom portion 202 and top portion 204. In this state, bottom signal probes 110, top signal probes 208, bottom ground probes 112, and top ground probes 210 are electrically connected to respective signal pads 142 or ground pads 150 of 1C chip 106.

[0034] In certain embodiments, top portion 204 further includes one or more top power probes, similar to power probes 114, which extend from power pads 156 located on a top side of 1C chip 106 to corresponding (e.g., power) conductors of top PCB 216. In such embodiments, these top power probes extend trough respective cavities of top conductive body 206.

[0035] In some embodiments, top portion 204 further includes a cooling structure 218 (e.g. a heat sink). In some such embodiments, cooling structure 218 is attached to and may retain in place other components of top portion 204, such as top conductive body 206 and / or top PCB 216.

[0036] FIG. 3 is a cross-sectional view of another test assembly 300. Test assembly 300 includes a test socket 302 and 1C chip 106, which generally functions as described with respect to FIG. 1. In some embodiments, test socket 302 may be used to implement bottom portion 202 and / or top portion 204 of test assembly 200 described with respect to FIG. 2. Test socket 302 includes a socket body 304 and probes 306. Probes 306 function similarly to signal probes 110, ground probes 112, and / or power probes 114.S1A1P79370PC00(39717-146)11

[0037] Socket body 304 includes an upper portion 308, a middle portion 310, and a lower portion 313. Upper portion 308, middle portion 310, and lower portion 312 are attached and together form a shape similar to that of conductive body 108, and thus socket body 304 functions similarly to conductive body 108. Upper portion 308 and lower portion 312 are formed from an electrically insulative material, such as composite plastic, and middle portion 310 is formed from a conductive material such as metal. Middle portion 310 therefore provides coaxial shielding of probes 306, and upper portion 308 and lower portion 312 insulate middle portion 310 from the surrounding environment.

[0038] FIG. 4 is a cross-sectional view of a socket body 400, which generally functions similarly to conductive body 108 described above with respect to FIG. 1. In some embodiments, socket body 400 may be used to implement bottom conductive body 108 and / or top conductive body 206 of test assembly 200 described with respect to FIG. 2. Socket body 400 includes a metal body 402 and an insulation layer 404 coating at least a portion of an external surface of metal body 402. Metal body 402 provides coaxial shielding of probes extending through socket body 400, and insulation layer 404 insulates metal body 402 from the surrounding environment.

[0039] FIG. 5 is a cross-sectional view of another test assembly 500. Test assembly 500 includes test socket 102 and 1C chip 106, which generally function as described with respect to FIG. 1. As shown in FIG. 2, in some embodiments, test socket 102 includes a first dielectric epoxy retainer 502 and a second dielectric epoxy retainer 504. First dielectric epoxy retainer 502 is positioned in signal cavity 120 near first signal opening 122, and second dielectric epoxy retainer 504 is positioned in signal cavity 120 near second signal opening 124, such that first dielectric epoxy retainer 502 and second dielectric epoxy retainer 504 each retain signal probe 110 with respect to conductive body 108 at an opposite respective end of signal probe 110. First dielectric epoxy retainer 502 and / or second dielectric epoxy retainer 504 may be shaped, sized, and or include a material selected to achieve desired electrical properties such as, for example, achieving a constant impedance, reducing reflection or distortion of electrical signals, reducing insertion loss and return loss, achieving a desired characteristic impedance, and / or reducing crosstalk.S1A1P79370PC00(39717-146)12

[0040] FIGS. 6A and 6B depict a method 600 for manufacturing a test socket assembly (such as test assembly 200). In the example embodiment, method 600 includes forming 602 a bottom conductive body (such as conductive body 108) having a first surface (such as first surface 116) configured to face a first PCB (such as PCB 104) and a second surface (such as second surface 118) configured to face an 1C chip (such as 1C chip 106). The bottom conductive body defines a first plurality of cavities extending from the first surface to the second surface.

[0041] Method 600 further includes forming 604 a top conductive body (such as top conductive body 206) having a third surface (such as third surface 212) configured to face the 1C chip and a fourth surface (such as fourth surface 214) configured to face a second PCB (such as top PCB 216). The top conductive body defines a second plurality of cavities extending from the third surface to the fourth surface.

[0042] Method 600 further includes positioning 606 a bottom signal probe (such as signal probe 110) in a first signal cavity (such as signal cavity 120) of the first plurality of cavities. The bottom signal probe is configured to electrically connect to a signal conductor of the first PCB and to a first signal pad of the 1C chip.

[0043] Method 600 further includes positioning 608 a bottom ground probe (such as ground probe 112) in a first ground cavity (such as ground cavity 126) of the first plurality of cavities. The bottom ground probe is configured to electrically connect to a ground conductor of the first PCB and to a first ground pad of the 1C chip.

[0044] Method 600 further includes positioning 610 a top signal probe (such as top signal probe 208) in a second signal cavity of the second plurality of cavities. The top signal probe is configured to electrically connect to a signal conductor of the second PCB and to a second signal pad of the 1C chip.

[0045] Method 600 further includes positioning 612 a top ground probe (such as top ground probe 210) in a second ground cavity of the second plurality of cavities. The top ground probe is configured to electrically connect to a ground conductor of the second PCB and to a second ground pad of the 1C chip.S1A1P79370PC00(39717-146)13

[0046] In certain embodiments, the bottom conductive body and the top conductive body are configured to receive the 1C chip between the second surface and the third surface.

[0047] In some embodiments, at least one of the bottom signal probe, the bottom ground probe, the top signal probe, or the top ground probe includes a spring probe.

[0048] In certain embodiments, method 600 further includes positioning a bottom power probe (such as power probe 114) in a first power cavity (such as power cavity 132) of the first plurality of cavities. The bottom power probe is configured to electrically connect to a power conductor of the first PCB and to a first power pad of the 1C chip.

[0049] In some such embodiments, method 600 further includes positioning a top power probe in a second power cavity of the second plurality of cavities. The top power probe is configured to electrically connect a power conductor of the second PCB and to a second power pad of the 1C chip.

[0050] In certain embodiments, at least one of the bottom conductive body or the top conductive body includes a metal body (such as metal body 402) and an insulation layer (such as insulation layer 404) coating the metal body.

[0051] In some embodiments, method 600 further includes positioning a first dielectric epoxy retainer (such as first dielectric epoxy retainer 502 or second dielectric epoxy retainer 504) in the first signal cavity. The first dielectric epoxy retainer configured to retain the bottom signal probe in position with respect to the bottom conductive body.

[0052] In certain such embodiments, method 600 further includes positioning a second dielectric epoxy retainer (such as first dielectric epoxy retainer 502 or second dielectric epoxy retainer 504) in the second signal cavity. The second dielectric epoxy retainer configured to retain the top signal probe in position with respect to the top conductive body.S1A1P79370PC00(39717-146)14

[0053] Example embodiments of methods and systems for coaxial test socket and PCB interfaces are described above in detail. The methods and systems are not limited to the specific embodiments described herein, but rather, components of systems and / or steps of the methods may be used independently and separately from other components and / or steps described herein. Accordingly, the example embodiments can be implemented and used in connection with many other applications not specifically described herein.

[0054] Technical effects of the systems and methods described herein include at least one of: (a) improved signal integrity for a coaxial test socket including a bottom socket body and a top socket body by improving electrical coupling between the socket bodies and an electrical ground; and (b) increased data transfer rates for a coaxial test socket including a bottom socket body and a top socket body by improving electrical coupling between the socket bodies and an electrical ground.

[0055] Although specific features of various embodiments of the disclosure may be shown in some drawings and not in others, this is for convenience only. In accordance with the principles of the disclosure, any feature of a drawing may be referenced and / or claimed in combination with any feature of any other drawing.

[0056] This written description uses examples to disclose various embodiments, including the best mode, and also to enable any person skilled in the art to practice the disclosure, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the disclosure is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims.

Claims

S1A1P79370PC00(39717-146)15WHAT IS CLAIMED IS:

1. A test socket assembly for coupling an integrated circuit (1C) chip to a first printed circuit board (PCB) and to a second PCB, said test socket assembly comprising:a bottom conductive body having a first surface configured to face the first PCB and a second surface configured to face the 1C chip, said bottom conductive body defining a first plurality of cavities extending from the first surface to the second surface;a top conductive body having a third surface configured to face the 1C chip and a fourth surface configured to face the second PCB, said top conductive body defining a second plurality of cavities extending from the third surface to the fourth surface;a bottom signal probe disposed in a first signal cavity of the first plurality of cavities, said bottom signal probe configured to electrically connect to a signal conductor of the first PCB and to a first signal pad of the 1C chip;a bottom ground probe disposed in a first ground cavity of the first plurality of cavities, said bottom ground probe configured to electrically connect to a ground conductor of the first PCB and to a first ground pad of the 1C chip;a top signal probe disposed in a second signal cavity of the second plurality of cavities, said top signal probe configured to electrically connect to a signal conductor of the second PCB and to a second signal pad of the 1C chip; anda top ground probe disposed in a second ground cavity of the second plurality of cavities, said top ground probe configured to electrically connect to a ground conductor of the second PCB and to a second ground pad of the 1C chip.

2. The test socket assembly of Claim 1, wherein said bottom conductive body and said top conductive body are configured to receive the 1C chip between the second surface and the third surface.S1A1P79370PC00(39717-146)163. The test socket assembly of Claim 1, wherein at least one of said bottom signal probe, said bottom ground probe, said top signal probe, and / or said top ground probe comprises a spring probe.

4. The test socket assembly of Claim 1, further comprising a bottom power probe disposed in a first power cavity of the first plurality of cavities, said bottom power probe configured to electrically connect to a power conductor of the first PCB and to a first power pad of the 1C chip.

5. The test socket assembly of Claim 4, further comprising a top power probe disposed in a second power cavity of the second plurality of cavities, said top power probe configured to electrically connect a power conductor of the second PCB and to a second power pad of the 1C chip.

6. The test socket assembly of Claim 1, wherein at least one of said bottom conductive body and / or said top conductive body comprises a metal body and an insulation layer coating said metal body.

7. The test socket assembly of Claim 1, further comprising a first dielectric epoxy retainer disposed in the first signal cavity and configured to retain said bottom signal probe in position with respect to said bottom conductive body.

8. The test socket assembly of Claim 7, further comprising a second dielectric epoxy retainer disposed in the second signal cavity and configured to retain said top signal probe in position with respect to said top conductive body.

9. A method for manufacturing a test socket assembly for coupling an integrated circuit (1C) chip to a first printed circuit board (PCB) and to a second PCB, said method comprising:forming a bottom conductive body having a first surface configured to face the first PCB and a second surface configured to face the 1C chip, the bottom conductive body defining a first plurality of cavities extending from the first surface to the second surface;forming a top conductive body having a third surface configured to face the 1C chip and a fourth surface configured to face the second PCB, the top conductiveS1A1P79370PC00(39717-146)17body defining a second plurality of cavities extending from the third surface to the fourth surface;positioning a bottom signal probe in a first signal cavity of the first plurality of cavities, the bottom signal probe configured to electrically connect to a signal conductor of the first PCB and to a first signal pad of the 1C chip;positioning a bottom ground probe in a first ground cavity of the first plurality of cavities, the bottom ground probe configured to electrically connect to a ground conductor of the first PCB and to a first ground pad of the 1C chip;positioning a top signal probe in a second signal cavity of the second plurality of cavities, the top signal probe configured to electrically connect to a signal conductor of the second PCB and to a second signal pad of the 1C chip; and positioning a top ground probe in a second ground cavity of the second plurality of cavities, the top ground probe configured to electrically connect to a ground conductor of the second PCB and to a second ground pad of the 1C chip.

10. The method of Claim 9, wherein the bottom conductive body and the top conductive body are configured to receive the 1C chip between the second surface and the third surface.

11. The method of Claim 9, wherein at least one of the bottom signal probe, the bottom ground probe, the top signal probe, and / or the top ground probe includes a spring probe.

12. The method of Claim 9, further comprising positioning a bottom power probe in a first power cavity of the first plurality of cavities, the bottom power probe configured to electrically connect to a power conductor of the first PCB and to a first power pad of the 1C chip.

13. The method of Claim 12, further comprising positioning a top power probe in a second power cavity of the second plurality of cavities, the top power probe configured to electrically connect a power conductor of the second PCB and to a second power pad of the 1C chip.S1A1P79370PC00(39717-146)1814. The method of Claim 9, wherein at least one of the bottom conductive body and / or the top conductive body comprises a metal body and an insulation layer coating the metal body.

15. The method of Claim 9, further comprising positioning a first dielectric epoxy retainer in the first signal cavity, the first dielectric epoxy retainer configured to retain the bottom signal probe in position with respect to the bottom conductive body.

16. The method of Claim 15, further comprising positioning a second dielectric epoxy retainer in the second signal cavity, the second dielectric epoxy retainer configured to retain the top signal probe in position with respect to the top conductive body.

17. A test assembly comprising:a first printed circuit board (PCB);a second PCB; andtest socket assembly for coupling an integrated circuit (1C) chip to said first PCB and to said second PCB, said test socket assembly comprising:a bottom conductive body having a first surface configured to face said first PCB and a second surface configured to face the 1C chip, said bottom conductive body defining a first plurality of cavities extending from the first surface to the second surface;a top conductive body having a third surface configured to face the 1C chip and a fourth surface configured to face said second PCB, said top conductive body defining a second plurality of cavities extending from the third surface to the fourth surface;a bottom signal probe disposed in a first signal cavity of the first plurality of cavities, said bottom signal probe configured to electrically connect to a signal conductor of said first PCB and to a first signal pad of the 1C chip;S1A1P79370PC00(39717-146)19a bottom ground probe disposed in a first ground cavity of the first plurality of cavities, said bottom ground probe configured to electrically connect to a ground conductor of said first PCB and to a first ground pad of the 1C chip;a top signal probe disposed in a second signal cavity of the second plurality of cavities, said top signal probe configured to electrically connect to a signal conductor of said second PCB and to a second signal pad of the 1C chip; anda top ground probe disposed in a second ground cavity of the second plurality of cavities, said top ground probe configured to electrically connect to a ground conductor of said second PCB and to a second ground pad of the 1C chip.

18. The test assembly of Claim 17, wherein said bottom conductive body and said top conductive body are configured to receive the 1C chip between the second surface and the third surface.

19. The test assembly of Claim 17, wherein at least one of said bottom signal probe, said bottom ground probe, said top signal probe, and / or said top ground probe comprises a spring probe.

20. The test assembly of Claim 17, further comprising: a bottom power probe disposed in a first power cavity of the first plurality of cavities, said bottom power probe configured to electrically connect to a power conductor of said first PCB and to a first power pad of the 1C chip; anda top power probe disposed in a second power cavity of the second plurality of cavities, said top power probe configured to electrically connect a power conductor of said second PCB and to a second power pad of the 1C chip.

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