Scalable high photon energy radiation detector with dual mode readout integrated circuit

Abstract

An imaging sensor may include a plurality of sensor pixels formed on a substrate, an individual sensor pixel comprising: a local integrated readout circuit comprising a photodetector element, a sensing layer formed over the local integrated readout circuit and electrically connected with the local integrated readout circuit via a conductive contact region formed within a major surface of the local integrated readout circuit, wherein the local integrated readout circuit is configured to generate: a first sensor signal using first electric charge carriers generated in the sensing layer in response to absorption of an ionizing electromagnetic radiation, and a second sensor signal using second electric charge carriers generated by the photodetector element in response to absorption of a non-ionizing electromagnetic radiation.

Description

UCRUZ.002WO PATENTSCALABLE HIGH PHOTON ENERGY RADIATION DETECTOR WITH DUAL MODE READOUT INTEGRATED CIRCUITINCORPORATION BY REFERENCE

[0001] This application claims benefit under 35 U.S.C. §119(e) of U.S. Provisional Patent Application No. 63 / 779,703, entitled “SCALABLE HIGH PHOTON ENERGY RADIATION DETECTOR WITH DUAL MODE READOUT INTEGRATED CIRCUIT” filed on March 28, 2025, and U.S. Provisional Patent Application No. 63 / 846673, entitled “SCALABLE HIGH PHOTON ENERGY RADIATION DETECTOR WITH DUAL MODE READOUT INTEGRATED CIRCUIT” filed on July 18, 2025, which are hereby incorporated by reference herein in their entirety.BACKGROUNDField

[0002] This disclosure relates to the field of integrated electromagnetic radiation detectors and in particular design and fabrication of scalable electromagnetic sensors formed by a plurality of active pixels including a sensing layer interfaced with a local integrated readout circuit and configured to detect ionizing and non-ionizing electromagnetic radiations.Description of Related Art

[0003] As is well known, X-ray imaging systems are abundantly employed, for example, to image fractures in human bones, for security at airports, as well as for scientific research experiments. Years ago, film was positioned with respect to the object to be imaged to capture the x-rays and record the images. Today, electronic detectors are employed. More generally, various imaging systems use a sensor panel comprising an array of active detector pixels to detect electromagnetic radiation that carries information pertaining to material and structural properties of a body. Some of these imaging systems may use large area detectors configured to detect ionizing electromagnetic radiation, such as X-ray radiation, by converting the ionizing to a plurality of electrical signals each generated by an active detector pixel. Such imaging systems may enable high-resolution, high-fidelity capture of internal structures withexceptional precision. By using many small, discrete pixels, the detector can measure variations in the electromagnetic radiation, e.g., X-ray intensity, across a fine grid, producing images with spatial detail and contrast.SUMMARY

[0004] In some aspects, the techniques described herein relate to an imaging sensor panel including: a plurality of sensor pixels formed on a substrate, an individual sensor pixel including: a local integrated readout circuit including a photodetector element; a sensing layer formed over the local integrated readout circuit and electrically connected with the local integrated readout circuit via a conductive contact region formed within a major surface of the local integrated readout circuit, wherein the local integrated readout circuit is configured to generate: a first sensor signal using first electric charge carriers generated in the sensing layer in response to absorption of an ionizing electromagnetic radiation, and a second sensor signal using second electric charge earners generated by the photodetector element in response to absorption of a non-ionizing electromagnetic radiation.

[0005] In some aspects, the techniques described herein relate to an imaging pixel including a local integrated readout circuit including: a conductive contact region electrically in contact with a sensing layer formed over the imaging pixel; a detector element configured to generate a photocurrent in response to receiving a second radiation having a wavelength within a second spectral range via the sensing layer; and wherein the local integrated readout circuit is configured to receive: first electric charge carriers from the sensing layer via the conductive contact region and generate a first sensor signal based on the first electric charge carriers; and second electric charge carriers from the detector element and generate sensor signals using the received charge and generate a second sensor signal based on the second electric charge earners; andBRIEF DESCRIPTION OF THE DRAWINGS

[0006] The systems, methods, and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below.

[0007] FIG. 1 schematically illustrates a cross-sectional view of a sensor or detector configured to generate sensor signals in response to receiving electromagnetic radiation having wavelength within a high energy wavelength range (e.g., X-ray or Gammaray) and a low energy wavelength range (e.g., visible, infrared, or ultraviolet).

[0008] FIG. 2A schematically illustrates a side cross-sectional view of a sensor element or pixel with an integrated local readout circuit that can be an example implementation of the detector shown in FIG. 1.

[0009] FIG. 2B schematically illustrates a side cross-sectional view of a sensor element or pixel with an integrated local readout circuit that can be another example implementation of the detector shown in FIG. 1.

[0010] FIG. 2C schematically illustrates a side cross-sectional view of a sensor element or pixel with an integrated local readout circuit that can be another example implementation of the detector shown in FIG. 1.

[0011] FIG. 2D schematically illustrates a side cross-sectional view of a sensor element or pixel with an integrated local readout circuit that can be another example implementation of the detector shown in FIG. 1.

[0012] FIG. 3A schematically illustrates an example sensor tile comprising a sensor die comprising an array of sensors pixels where each sensor pixel is configured to detect ionizing and non-ionizing electromagnetic radiation.

[0013] FIG 3B schematically illustrates al local integrated readout circuit of an individual sensor pixel of the sensor tile shown in FIG. 3A.

[0014] FIG. 4A schematically illustrates a cross section of three sensor pixels of a detector configured to directly detect ionizing electromagnetic radiation using a sensing layer and non-ionizing electromagnetic radiation using a photodetector element (e.g., a photodiode).

[0015] FIG. 4B schematically illustrates a top-view of an example macro-pixel comprising four pixels configured to detect ionizing electromagnetic radiation (e.g., X-ray) and non-ionizing electromagnetic radiation (e.g., in visible and near-infrared wavelength ranges).

[0016] FIG. 4C schematically illustrates a cross-sectional view of a section of the macro-pixel shown in FIG. 4B depicting a co-planar integrated local readout circuit comprising a photodiode, and a sensing layer formed on or over a portion of the integrated local readout circuit.

[0017] FIG. 5A schematically illustrates an example of a sensor die comprising a plurality of sensor pixels.

[0018] FIG. 5B schematically illustrates a wafer 504 comprising five sensor dies.

[0019] FIG. 5C schematically illustrates two sensor tiles having different dimensions.

[0020] FIG. 6A schematically illustrates a top-view of an example sensor panel formed by connecting six sensor tiles

[0021] FIG. 6B schematically illustrates a three-dimensional view of another example sensor panel comprising eight sensor tiles.

[0022] FIG. 7 schematically illustrates a three-dimensional view of a region of a sensor tile depicting formation of a sensing layer over a readout integrated circuit comprising a plurality of integrated local integrated readout circuits.

[0023] FIG. 8 schematically illustrates an imaging system comprising a sensor tile, intermediate circuit module, a mainboard and a computing system.

[0024] FIG. 9 is a block diagram illustrating an example process that may be used to design and fabricate a detector system comprising a sensor panel, one or more intermediate circuit modules, and at least one mother board.

[0025] FIG. 10A is a circuit diagram illustrating electrical connection between a pixel column comprising N pixels and a downstream amplifier via a column link and two sample-and-hold (S&H) amplifiers SHI, SH2.

[0026] FIG. 10B shows results of calculations performed to evaluate linearity of pixel response and capacitive loading of pixel waveform for pixels in a sensor panel or sensor tile. The top panel shows temporal variations of the control signals and pixel output waveforms. The bottom panel shows calculated temporal variations of photocurrent and output voltage readout from a pixel depicting a time interval within which the response is linear.

[0027] FIG. 11 is a block diagram schematically illustrating a scanning circuit configured to scan the horizontal and vertical axes (row and columns), simplifying the row / column decoder and enabling partial readouts through token manipulation. The top panel (a) shows a horizonal toke chain

[0028] FIG. 12A shows the timing of various control signals provided to readout circuit (e.g., the integrated local readout circuit shown in FIG. 3B) for detection of ionizing radiation in direct conversion mode where charge carriers are received from the sensing layer.

[0029] FIG. 12B shows the timing of various control signals provided to readout circuit (e.g., the integrated local readout circuit shown in FIG. 3B) for detection of non-ionizing electromagnetic radiation (or indirect detection of ionizing radiation) using photocurrent received from a photodiode.

[0030] FIG. 13 shows the simulated complete pixel chain in direct mode demonstrating high (99.99%) linearity in pixel response over the full output range of 2 V.

[0031] FIG. 14 shows the simulation results of electrical current provided to 256 pixel columns (e.g., in one or more sensor tiles) indicating power consumption by the corresponding readout circuits during different operational phases of the readout circuit depicted by the control signals SH_SIG and SH_RST.

[0032] FIG. 15 shows the output buffer waveforms for pixels originating at the 0,0 and max X,Y positions in a sensor tile, showing a settling time of 20 ns for readout across the array.

[0033] FIG. 16A is a schematic diagram illustrating an example imaging system 1 comprising one or more of the sensor pixels, sensor tiles, and sensor panels described above.

[0034] FIG. 16B is a schematic diagram illustrating electrical connection between the intermediate circuit modules, the sensor panel and the main (mother) board imaging system shown in FIG. 16A.DETAILED DESCRIPTION

[0035] High performance large area electromagnetic detectors are useful in many applications including but not limited to imaging (e.g.. medical imaging, structural characterization, and the like). Scaling to obtain a large area pixelated electromagnetic detector, in particular, for detecting ionizing electromagnetic radiation such as X-ray, without degrading its sensitivity and low-noise performance is a challenging task.

[0036] An X-ray imaging system based on an array of active detector pixels can enable high-resolution, high-fidelity capture of internal structures with exceptional precision. By using many, e.g., an array of, small and discrete active pixels, the imaging system can measure variations in X-ray intensity across a fine grid, producing images with superior spatial detail. This pixel-based approach also supports advanced image-processing techniques, such as noise reduction, dynamic range enhancement, and real-time reconstruction, which can improve diagnostic accuracy across medical, industrial, and security applications.Additionally , active pixel arrays allow for faster acquisition and lower radiation doses, since they are more sensitive and efficient at capturing X-ray photons, ultimately resulting in safer and more accurate imaging.

[0037] In some cases, scaling the detection area (e.g., increasing the areal size) of an X-ray imaging sensor comprising an array of detectors based on existing sensor technologies may reduce the signal-to-noise ratio (SNR) and amplitude of the corresponding sensor signals. Moreover, for various applications, it can be beneficial if an X-ray imaging sensor can also detect and image non-ionizing electromagnetic radiation, e.g., in the visible and infrared wavelength range. Some of the active sensor pixels and sensor tiles disclosed herein, however, can be used to form high-performance large area and modular sensor panels for detection and imagining both ionizing and non-ionizing electromagnetic radiation. These modular sensor panels can be scaled according to characteristics of an imaging system with negligible or without a penalty on the quality (e.g., SNR and amplitude) of the sensor signals generated by the sensor panel. In some cases, an ionizing electromagnetic radiation can have a photon energy greater 10 eV and non-ionizing electromagnetic radiation can have a photon energy less than 10 eV.

[0038] In some implementations, an electromagnetic imaging system may comprise a sensor panel configured to generate a plurality of sensor signals indicative of a power or intensity of electromagnetic radiation received at different regions or segments (e.g., different sensor pixels) of the sensor panel. In some cases, electromagnetic radiation can have wavelengths in X-ray, Gamma-Ray, visible, and infrared (e.g., near infrared) spectral ranges. In some implementations, the sensor panel may comprise a plurality of sensor tiles stitched, connected, or otherwise combined together to form a large detection area. In some implementations, a sensor tile may include a plurality of sensor pixels (e.g., active sensor pixels), with different sensor pixels (e.g., each sensor pixel) generating a corresponding sensor signal of the plurality of sensor signals. In certain implementations, the number of sensor pixels in the sensor tile and the size of the individual sensor pixels may be selected such that the resulting plurality of sensor signals enables generation of a high-resolution image or provides high-resolution information regarding the structure or composition of a body, structure, or an object imaged using the sensor panel.

[0039] In some implementations, a sensor pixel, herein referred to as pixel, may be configured to generate a sensor signal indicative of an intensity and / or power of radiationreceived by a sensitive area (e.g., a surface area) of the pixel. In some embodiments, individual pixels disclosed below may comprise a sensing layer integrated (e.g., directly integrated or hybridized) with an underlying local integrated readout circuit, where the sensing layer converts electromagnetic radiation to electric charge carriers, and the local integrated readout circuit generates a low noise sensor signal using the electric charge carriers generated within the sensing layer. In some cases, the electric charge carriers, herein referred to as charge carriers, may comprise electrons and holes. In some cases, the sensing layer is directly formed on a portion of the local integrated readout circuit to reduce or minimize an electric path between the sensing layer and the local integrated readout circuit. Advantageously, formation of the sensing media (e.g., layer) on the local integrated readout circuit may reduce charge earner loss and noise associated with an electrical path between sensing layer and the local integrated readout circuit. In some cases, the sensing layer may be configured for direct detection of X-rays and / or Gamma-rays. For example, the sensing layer may comprise a material (e.g., a photoconductive material) configured to generate electrons and / or holes upon being irradiated by X-ray (or Gamma-ray) radiation. In some cases, the sensing layer may comprise amorphous selenium (a-Se).

[0040] In some cases, the sensing layer may be configured to transmit electromagnetic radiation incident on the sensing layer having wavelengths in a transparency window of the sensing layer to allow illumination of a portion of a local integrated readout circuit and / or a photodiode below the sensing layer by the incident electromagnetic radiation. In some cases, the transparency window of the sensing layer may comprise a near infrared (NIR) spectral range, a visible (VIS) spectral range or another spectral range (e.g., a soft ultraviolet range). Advantageously, when the sensing layer is configured to transmit incident radiation in the near-IR spectral range and absorb incident radiation comprising high-energy photons (e.g., X-ray, Gamma rays, and / or hard ultraviolet), the sensor pixel can detect both near-IR and high photon energy radiation.

[0041] In some embodiments, a pixel may include a detector element (e.g., a photodiode) configured to detect electromagnetic radiation comprising wavelengths within one or more of a visible wavelength range and a near infrared range, or a combination thereof. In some cases, the detector element may be included in the local integrated readout circuit. In some embodiments, a pixel may include a detector element (e.g., a photodiode) configured todetect electromagnetic radiation within an ultraviolet (UV) wavelength range (e.g., soft-UV or from 120 nm to 380 nm).

[0042] In some cases, the local integrated readout circuit of a pixel may comprise a single-mode or a multimode local integrated readout circuit. In some cases, the single-mode local integrated readout circuit may be configured to generate sensor signals based on charge carriers received from the sensing layer. In some cases, the multi-mode local integrated readout circuit can be a dual-mode readout circuit configured to switchably generate sensor signals based on charge carriers received from the sensing layer and a detector element. In some cases, the multi-mode local integrated readout circuit may be configured to operate in at least two different modes where a first mode generates first sensor signals associated with absorption of radiation having wavelengths in a first spectral range (e.g.. ionizing electromagnetic radiation such as X-ray) by the sensing layer and a second sensor signal associated with absorption of radiation having wavelengths in a second spectral range (e.g., visible, near infrared, soft-UV or a combination thereof) by the detector element (e.g., photodetector or photodiode).

[0043] In some embodiments, the multimode local integrated readout circuit may generate the first sensor signals based on charge carriers received from the sensing layer and a photocurrent and / or photovoltage generated by the photodiode upon receiving secondary radiation generated in the sensing layer by an ionizing radiation. In some such embodiments, the a first signal can be generated during a first period (using the sensing layer), a second signal can be generated during a second period (using the photodiode), and a processing circuit may use the first and the second signals to generate an output signal. In some cases, the output signal can be indicative of intensity of an ionizing radiation that may have caused the generation of the first signal (via direct charge generation in the sensing layer) and the second signal (e.g., based on detection of a secondary radiation emitted by the sensing layer). In some examples, the sensing layer may comprise a halide perovskite that can function as both a direct conversion sensing layer (e.g., directly converting ionizing radiation into charge carriers) and as a scintillator (e.g., converting ionizing radiation into secondary non-ionizing electromagnetic radiation). In various implementations, dual mode operation may allow detecting X-ray, VIS, NIR, and soft-UV radiation using a single pixel. Advantageously, in some cases, dual mode operation may allow detection of an ionizing radiation (e.g., X-ray) using a combination of sensor signals generated by direct charge generation and scintillation by a single sensing layer.

[0044] In some implementations, the sensing layer may be configured to generate light (photons) having wavelengths that are detectable by a photodiode, in response to absorption of the high-energy photons. In these implementations, the multimode local integrated readout circuit may be configured to generate a first sensing signal using a first photocurrent received from the photodiode in response to being illuminated by light generated by the sensing layer, and a second signal using a second photocurrent received from the photodiode in response to illumination of the photodiode by radiation (e.g., near-IR) radiation transmitted through the sensing layer.

[0045] In some embodiments, a pixel may be configured to detect the high-energy photons based on charge carriers generated in the sensing layer (direct detection) and VIS / NIR photons based on photocurrents generated by a photodiode. In some embodiments, a pixel may be configured to detect both high-energy photons and VIS / NIR photons based on photocurrents generated by the photodiode.

[0046] In some cases, the local integrated readout circuit may comprise a complementary metal oxide semiconductor (CMOS) circuit fabricated (e.g., monolithically fabricated) on a substrate.

[0047] In some implementations, a sensor panel may comprise a scalable hybrid sensor platform formed by a plurality of sensor tiles and configured to detect one or both a high energy electromagnetic radiation (e.g., ionizing radiation such as X-ray, Gamma-ray, or the like) and a low energy electromagnetic radiation (e.g., non-ionizing electromagnetic radiation such as ultraviolet, visible, and / or near infrared). In some cases, a sensor tile may include three edges (connector-free edges) configured to be interfaced with adjacent tiles and a fourth edge configured to be electrically connected to a processing circuit (e.g., a field programmable gate array or another circuit).

[0048] In some cases, a sensor tile may comprise a sensor die comprising the local integrated readout circuits and a sensing layer (e.g., a patterned sensor layer) deposited, fabricated, or otherwise formed thereon, and a printed circuit board (PCB) electrically and mechanically connected to the sensor die. In some designs, the sensing layer and the local integrated readout circuit may form a stack (e.g., a vertical stack formed along a direction normal to a major surface of the sensor substrate).

[0049] In some such cases, the sensor panel or the corresponding sensor panel may comprise X-ray (or Gamma-ray) photoconductor stack directly deposited on CMOS readoutarray. In some cases, the sensor panel formed by multiple sensor tiles can have an expandable and modular detector area (e.g., by adding, removing, rearranging the sensor tiles). In some examples, a sensor panel can be integrated and / or electrically connected to camera electronics.

[0050] In various implementations, the sensor panels and sensor tiles can include a readout integrated circuit (ROICs) comprising a plurality of local integrated readout circuits (at pixel level) configured to interface with a sensing layer to provide:• Versatility: individual local integrated readout circuits may support both X-ray (or Gamma-ray) and VisNIR detection modes.• Scalable Active Area• Micron scale X-ray (or Gamma-ray) resolution• Video Frame rates• High X-ray QE using a-Se direct detection layers• Flexible Modular System Design• Allow 90 nm low noise Stitchable CMOS manufacturing• Three-side tileable readout floorplan for micron scale pixel detectors.

[0051] In one embodiment, a sensor tile may comprise a CMOS-based (ROIC) comprising the plurality of local integrated readout circuits and a sensing layer formed on or over the ROIC. In some cases, the ROIC may comprise an application specific integrated circuit (ASIC). In some embodiments, the sensor tile may comprise an active pixel sensor (APS). In some embodiments, a scalable image sensor, herein referred to as a sensor panel, may be formed using a plurality of sensor tiles. Individual sensor tiles and thereby the scalable image sensor may be configured to directly detect X-ray radiation based on charge carriers generated in the sensing layer and VIS -NIR radiation based using photodetectors integrated with the ROIC. In some examples, sensor tile may comprise a plurality of pixels each comprising a local integrated readout circuit. An individual local integrated readout circuit may comprise, for example, six transistors and can be configured to operate in two detection modes: 1) electron collection from pinned photodiode in response to receiving VIS -NIR radiation, 2) hole or electron collection from the sensing layer (e.g.. a directly hybridized amorphous selenium layer) in response to receiving X-ray radiation. In some cases, an individual pixel can have an area from 5x5 pm2to 7x7 pm2, from 7x7 pm2to 10x10 pm2, from 10x10 pm2to 15x15 pm2, from 15x15 pm2to 20x20 pm2, or any ranges formed by these values, e.g., from 5x5 pm2to 20x20 pm2, or, possibly larger or smaller areas.

[0052] FIG. 1 schematically illustrates a cross-sectional view of a sensor or detector 100 configured to generate a sensor signal in response to receiving electromagnetic radiation having wavelengths within a high energy wavelength range (e.g.. X-ray or Gammaray) and, in some cases, a sensor signal in response to receiving electromagnetic radiation having wavelengths within a low energy wavelength range (e.g., visible, infrared, or ultraviolet). In some embodiment, the detector 100 may comprise a sensing layer 102 and a readout circuit 112 configured to receive charge carriers (e.g., electrons and / or hole) generated in the sensing layer 102, light transmitted through the sensing layer 102 and / or directly received light (e.g., light received through an opening formed in the sensing layer 102). In some cases, the readout circuit 112 may receive light generated in the sensing layer 102. In some embodiments, the readout circuit 112 may comprise a first circuit block 112a that is in electric contact with the sensing layer 102 to receive charge carriers generated within the sensing layer and generate a first sensor signal 116 using the received charge carriers. In some embodiments, the readout circuit 112 may comprise a second circuit block 112b configured to convert light transmitted via the sensing layer 102, directly received light, and, in some cases, light generated in the sensing layer 102, to a second sensor signal 118. For example, the second circuit block 112b may comprise a photosensor (e.g., a photodiode) configured to convert light having a wavelength within one or more of a visible, or infrared (e.g., near infrared) wavelength range into an electrical signal, the second sensor signal 118. In some cases, the photosensor (e.g., a photodiode) may be configured to convert light having a wavelength within an ultraviolet wavelength range (e.g., soft UV) to the second sensor signal 118.

[0053] In some embodiments, the readout circuit 112 can be a planar and / or integrated circuit (e.g., a CMOS integrated circuit) and the sensor layer 102 may be formed on a major surface of the readout circuit 112 comprising a conductive region (e.g., a conductive pad) of the first circuit block 112a.

[0054] In some embodiments, the detector 100 can be a pixel of an imaging sensor (e.g., an APS) comprising a plurality of pixels (e.g., substantially identical pixels). In some such embodiment, the readout circuit 112 may comprise a local integrated readout circuit also referred to as APS cell. In some cases, the APS cell may comprise a pixel circuit and a photosensor. In some embodiments, the sensing layer 102 can be a portion of a larger sensing layer formed on or over a plurality of the APS cells to form the plurality of pixels.

[0055] In some embodiments, high energy electromagnetic radiation 104 incident on the sensing layer 102 may interact with the sensing layer 102 to generate charge carriers 109 via a photogeneration process 108 and the charge carriers may drift toward an electric interface between the sensing layer 102 and the first circuit block 112a by an electric field 114. In some cases, the electric interface between the sensing layer 102 and the first circuit block 112a may comprise a conductive pixel region or conductive pixel pad 209 formed on a top layer of the readout circuit 112. In some cases, the conductive pixel pad 209 may comprise a conductive region (e.g., a metallic or highly doped region) formed at or near a major surface of the readout circuit 112. In some cases, the readout circuit 112 may comprise a top insulation layer 211 (e.g., a dielectric layer) and the conductive pixel pad 209 may comprise a conductive region (e.g., a metallic or highly doped region) formed within the top insulating layer. In some cases, the top layer 211 can be a thin non-conductive layer comprising polyimide layer, another polymer or composite material.

[0056] In some cases, a top conductive layer 207 may be formed on a major surface of the sensing layer 102 opposite to the interface between the sensing layer 102 and the readout circuit 112. In some cases, the electric field 114 may be established in the sensing layer 102 by applying a voltage between the conductive layer 207 (also referred to as top electrode layer 207) and the conductive pixel pad 209 (also referred to as bottom electrode). In some cases, the electric field 114 may be configured to drive charge earners of the same type that are generated in a portion of the sensing layer 102 above the readout circuit 112 toward the conductive pixel pad 209. As such, in some cases, where the sensing layer 102 is a large continuous layer formed over multiple readout circuits (e.g., local readout circuits), the electric field 114 may be configured to drive charge carriers of the same type that are generated above each readout circuit toward the respective conductive pixel pad 209 and thereby provide some level of charge transport isolation between neighboring readout circuits. In some implementations, the pixel pad 209 may include multiple conductive segments separated by dielectric regions. In certain examples, these conductive segments may be arranged in a matrix configuration (e.g., a 2x2, 3x3, 4x4, 5x5, an NxN matrix, or a matrix having non-equal numbers of rows and columns). In some cases, the magnitude of the electric field 114 can be from 3 to 5 V / pm, 5 to 10 V / pm, 10 to 15 V / pm, or any range formed by these values or larger or smaller values. In some cases, the top conductive layer 207 may comprise a transparent conductive layer such a thin gold layer or transparent conductive oxide (e.g., ITO,Fluorine-Doped Tin Oxide, FTO, aluminum-Doped Zinc Oxide, AZO, Gallium-Doped Zinc Oxide, GZO, or the like). In some cases, the top conductive layer 207 may comprise a metal that has good adhesion sensing layer.

[0057] In some cases, the thickness of the sensing layer 102 between the top conductive layer 207 and the conductive pad 209, along a direction normal to a major surface of the readout circuit 112, can be from 30 microns to 50 microns, from 50 microns to 70 microns, from 70 microns to 100 microns, from 100 microns to 150 microns, from 150 microns to 200 microns, or any ranges formed by the values, e.g.. from 30 to 200 microns, or larger or smaller values.

[0058] Upon receiving the photogenerated charge carriers 109 at the electric interface (conductive pad 209), the first circuit block 112a may generate the first sensor signal 116 indicative of absorption of the high energy electromagnetic radiation 104 in the sensing layer 102. In some examples, the first sensor signal can be proportional to the intensity and / or power or the incident high energy electromagnetic radiation 104 or a number of high energy photons absorbed by the sensing layer 102.

[0059] In some embodiments, high energy electromagnetic radiation 104 incident on the sensing layer 102 may interact with the sensing layer 102 to generate light 106 (e.g., low energy electromagnetic radiation) through a scintillation process 110 and the light may be transmitted to a light sensor or light detection element of the second circuit block 112b. Upon receiving the light from the sensing layer 102, the second circuit block 112b may generate the second sensor signal 118 indicative of absorption of the high energy electromagnetic radiation 104 in the sensing layer 102. In some examples, the second sensor signal 118 can be proportional to the intensity and / or power or the incident high energy electromagnetic radiation 104 or a number of high energy photons absorbed by the sensing layer 102.

[0060] In some embodiments, low energy electromagnetic radiation 105 incident on the sensing layer 102 may be transmitted to a light sensor or a light detection element of the second circuit block 112b. Upon receiving the low energy electromagnetic radiation 105 via the sensing layer 102, the second circuit block 112b may generate the second sensor signal 118 indicative of absorption of the low energy electromagnetic radiation 105 by the light sensor or the light detection element. In some examples, the second sensor signal 118 can be proportional to the intensity and / or power or the low energy electromagnetic radiation 105 or a number of low energy photons absorbed by the light sensor or the light detection element. In some cases,the first and second circuit blocks 112a, 112b, can be controllably activated during different operational modes of the corresponding pixel. In some examples, the first sensor signal 116 may be generated in a first operational mode and the second sensor signal 118 may be generated in a second operational mode. In some cases, the first and second sensor signals 116, 118, may be generated during two different periods and a processing circuit may use them to generate an output signal indicative of a characteristic of an ionizing radiation absorbed in the sensing layer 102 during the two different periods. In some cases, the tope electrode layer 207 may not extend over a region or section of the sensing layer 102 directly above the second circuit block 112b or directly above the light sensor or a light detection element in the second circuit block 112b.

[0061] FIG.2A schematically illustrates a side cross-sectional view of a sensor unit or pixel 200 that can be an example implementation of the detector 100. The sensor unit 200 may comprise a sensing layer 102a formed on or over a local integrated readout circuit 204 (e.g., an APS cell). In some cases, the local integrated readout circuit 204 can be a multimode (e.g., dual mode) readout circuit. In some cases, the local integrated readout circuit 204 may comprise a first circuit layer 203, and a second circuit layer 205 formed between the first circuit layer 203 and the sensing layer 102a. In some examples, the second circuit layer 205 can be formed on the first circuit layer 203. In some cases, the first circuit layer 203 may comprise a p-type substrate. In some embodiments, the first circuit layer may comprise a photosensor 208 configured to convert light received from the sensing layer 102a. Light received by the photosensor 208 may comprise low energy light 106 generated within the sensing layer 102a (e.g., as a result of absorption of high energy electromagnetic radiation) or low energy light 105 received via the sensing layer 102a from a medium above the sensing layer 102a. In some embodiments, the photosensor 208 may comprise a photodiode comprising a PN junction. In some examples, the PN junction may comprise a p-doped region formed in an n-doped well formed in the first circuit layer. In some cases, photosensor 208 can be a pinned photodiode comprising a pinned layer, a charge collection region, and transfer gate.

[0062] In some cases, the local integrated readout circuit may comprise a CMOS circuit formed in the second circuit layer 205 and electrically connected the photosensor 208 (e.g., a photodiode) formed in the first circuit layer

[0063] In some embodiments, the second circuit layer 205 may comprise a conductive contact pad 209, also referred to as pixel pad or bottom electrode, that is electrically in contactwith the sensing layer 102a. In some cases, the conductive pixel pad 209 can be a conductive region formed in the second circuit layer 205. In some cases, the second circuit layer 205 may comprise a top layer 211 (e.g., a dielectric layer) within which the conductive contact pad 209 is formed. In some embodiments, a top electrode layer 207 may be disposed on or over the sensing layer 102a. In some cases, a voltage may be applied between the top electrode layer 207 and the conductive pixel pad 209 (bottom electrode) to generate an electric filed within the sensing layer 102a. In some cases, the second circuit layer 205 may further comprise a metal-insulator-metal capacitor (MIMCAP) 206 electrically connected to the sensing layer 102a, e.g., via the conductive contact pad 209. In some such cases, the MIMCAP 206 may be configured to receive and store electric charge generated in the sensing layer 102a, e.g., as a result of absorption of a high energy electromagnetic radiation 104. In some embodiments, the MIMCAP 206 can be electrically connected to a first circuit block of the local integrated readout circuit 204 and the photosensor 208 can be electrically connected to a second circuit block of the local integrated readout circuit 204. In some examples, the MIMCAP 206 may comprise two metal plates separated by an insulating layer, forming a parallel plate capacitor. In some cases, one of the two metal plates may be in electrical contact with the sensing layer 102 to allow the MIMCAP 206 to receive charge carriers generated in the sensing layer in response to absorption of high-energy photons in the sensing layer.

[0064] In some cases, the electronic circuitry of the local integrated readout circuit 204 may be formed in the second circuit layer 205, the first circuit layer 203, or both.

[0065] In some embodiments, the local integrated readout circuit of a sensor unit or pixel may comprise a co-planar CMOS circuit formed in a single circuit layer. In some such embodiments, the single circuit layer may comprise a photosensor (e.g., the photodiode) formed in a region that may partially surround the CMOS circuit. The CMOS circuit may comprise a MIMCAP and a top conductive contact pad.

[0066] FIG. 2B schematically illustrates a side cross-sectional view of a sensor unit 202 that can be another example implementation of the detector 100. The sensor unit 202 may comprise one or more features described above with respect to the sensor unit 200. In some cases, the sensing layer 102b of the sensor unit 202 may comprise a through-hole 210 formed above the photosensor 208 such that the photosensor 208 can directly receive low energy light 105 from a medium above the sensing layer 102b via the through-hole 210.

[0067] In some embodiments, the sensor units 200, 202, each can be a pixel (e.g., an active pixel) of an imaging sensor (e.g., an APS) comprising a plurality of pixels (e.g., substantially identical pixels). In some such embodiments, the local integrated readout circuit 204 may comprise an APS cell. In some embodiments, the sensing layers 102a, 102b, can be a portion of a larger sensing layer formed on or over a plurality of the APS cells to form the plurality of pixels. In some embodiments, the sensing layers 102a. 102b, shown in FIGS 2A and 2B can be portions of a continuous sensing layer form over a plurality of integrated local readout circuits. In some embodiments, the sensing layers 102a. 102b, each can be a segment of a segmented (e.g., patterned) sensing layer.

[0068] In various implementations, the sensing layers 102, 102a, and 102b, may comprise selenium (e.g., amorphous selenium), or another material configured to generate charge carriers upon interaction with high-energy and / or ionizing photons. In various implementations, the sensing layers 102, 102a, and 102b, may comprise Cesium iodide (CsI) and or gadolinium oxysulfide (GOS or Gd2C>2S:Tb), that can convert X-ray energy into visible or near- visible light, through scintillation.

[0069] In some embodiments, the sensing layers 102, 102a, and 102b, may comprise a material (e.g., a Halide Perovskite) with dual capabilities as a charge detector and a scintillator to combine the benefits of both detection mechanisms in a single detector or sensor. In some cases, the sensing layers 102, 102a, and 102b, may comprise a material with high effective atomic number (Zeff), such as thalliumchloride (T1C1).

[0070] In some embodiments, the sensing layers 102, 102a, and 102b, may comprise multiple sublayers each having a different composition, or at least one different characteristic (e.g., density, doping, and the like). In some cases, a characteristic (e.g., doping) of the sublayers can be graded (e.g., along a vertical direction normal to a major surface of the sensing layer).

[0071] In some cases, the sensor units 200, 202, may comprise a hybrid detector configured to generate electricals signal in response to receiving electromagnetic radiation having wavelengths within the Gamma-ray and / or X-ray spectral region and another spectral region comprising one or more of the ultraviolet UV region, visible (VIS) region, and infrared (IR) region.

[0072] In some embodiments, the local integrated readout circuit 204 can be a section or block of a larger CMOS readout array. In some such embodiments, the sensing layers102a, 102b, can be a portion of a larger sensing layer formed (e.g., directly deposited) on or over the CMOS readout array.

[0073] In some embodiments, the readout circuit 112 or the local integrated readout circuit 204 may be configured to generate a sensor signal by integrating electrons or holes generated as a result of absorption electromagnetic radiation. In some embodiments, the readout circuit 112 or the local integrated readout circuit 204, may be configured to operate in two different modes: 1) generating a sensor signal based on charge carriers of the same type collected from the sensing layer 102a. 2) generating a sensor signal based on charge carriers collected from the photosensor 208. In some cases, the type of charge carries collected from the sensing layer 102a may be determined based on the direction of the electric field 114 established in the sensing layer. For example, the readout circuit 112 or the local integrated readout circuit 204, may be configured to operate in two different modes: 1) a hole integration mode or 2) an electron integration mode. In some embodiments, the dual mode operation enables detection at multiple photon energies simultaneously in electron integration mode or in close temporal coincidence by viewing the same target in hole collection mode, then switching to electron collection mode within a few frames of imaging operation.

[0074] In some embodiments, a bottom charge blocking layer 215 may be formed between the sensing layer 102, 102a, 102b and a corresponding local integrated readout circuit (e.g., between the sensing layer and conductive contact pad of the local integrated). The bottom charge blocking layer 215 may be configured to block charge carriers driven by the electric field 114, established in the sensing layer toward the conductive contact pad 209. In some embodiments, a top charge blocking layer 213 may be formed between the sensing layer 102, 102a, 102b and top electrode layer 207. The top charge blocking layer 213 may be configured to block charge carriers driven by the electric field 114 toward the top electrode layer 207. For example, when the electric field 114 is configured to drive holes toward the conductive contact pad 209 and the electrons toward the top electrode, the bottom charge blocking layer 215 may comprise a hole blocking layer and the top charge blocking layer 213 may comprise an electron blocking layer.

[0075] In some cases, the detector 100 or sensor units 200, 202, may comprise a direct hybrid X-ray detector configured to generate sensor signals based on photogenerated charge (e.g., holes or electrons) confined in a pixel by an electric field (e.g., an electric field >10V7pm) within the sensing layer 102 (or 102a, 102b). The electric field may be generatedby applying a DC voltage between the top electrode layer 207 and conductive pad 209. In some cases, the voltage applied across the sensing layer can be from 200 volts to 500 volts, from 500 volts to 2000 volts, from 2000 volts to 3000 volts, or any ranges formed by these values, e.g., 200 to 3000 volts, or possibly larger or smaller values.

[0076] In some cases, a thickness of the conductive layer 102 may be configured to allow transmission of radiation having wavelengths within the transparency window of the sensing layer.

[0077] In some embodiments, charge carriers generated as a result of interaction between X-ray radiation and the sensing layer 102 may be collected and stored in a holding capacitor (e.g., in the MIMCAP 206) and can be subsequently converted to a voltage and / or a sensor signal.

[0078] In some cases, the readout circuit 112 and the sensor units 200, 202, may be configured to collect charge carriers over an integration period and convert the integrated charge to a voltage and / or sensor signal.

[0079] In some cases, the detector 100 or sensor units 200, 202, may be used to form a multi-energy direct hybrid APS comprising a pixel array with large scalable active area, capable of coplanar electron and hole integration and detection of a wide photon energy range including X-ray, gamma scintillation, Cherenkov UV, visible, and near IR. In some cases, the hybrid APS can be an imaging array comprising a sensing layer directly applied and hybridized to a CMOS active pixel sensor. In some cases, the sensing layer may comprise one or both of a photoconductive and a scintillating material. In some cases, the sensing layer may comprise a thin scintillating layer disposed on or over a thick photorefractive layer.

[0080] FIG. 2C schematically illustrates a side cross-sectional view of a sensor element or pixel with an integrated local readout circuit that can be another example implementation of the detector shown in FIG. 1. FIG.2D schematically illustrates a side cross-sectional view of a sensor element or pixel with an integrated local readout circuit that can be another example implementation of the detector shown in FIG. 1. In some cases, the sensor elements or pixels shown in FIGS. 2C and 2D, may comprise one or more features described above with respect to the FIGS. 2A and 2B. In some examples, the sensor elements or pixels shown in FIGS. 2C and 2D, may comprise a specific electric connection between the MIM CAP 206 and the photosensor 208, e.g., via controllable electrical paths. In some cases, the controllable electrical paths may comprise one or more transistors.

[0081] FIG. 3A schematically illustrates an example sensor tile 300 comprising a sensor die 322. In some cases, the sensor die 322 may comprise an array of sensors pixels 324 (e.g., an array or matrix of sensor pixels also referred to as a pixel array). In some cases, a sensor pixel 303 (herein referred to as a pixel) may comprise a local integrated readout circuit 301 and a sensing layer region 102-1 in electric communication with the local integrated readout circuit 301. In some cases, the sensor tile 300 may comprise a ROIC comprising a plurality of local integrated readout circuits. In some cases, the local integrated readout circuit 301 can be a circuit segment of the ROIC. In some examples, the ROIC may comprise an integrated and / or monolithic circuit (e.g., a CMOS circuit) such an ASIC. In some cases, the sensing layer region 102-1 can be a portion of a sensing layer formed on or over the ASIC that is located above the local integrated readout circuit 301. In some cases, the sensing layer may comprise a continuous layer extending over all or a portion of the local integrated readout circuits in the sensor tile 303. In some cases, the sensing layer may comprise a patterned layer and / or a segmented layer. In some cases, the sensing layer may comprise a layer comprising electrically isolated regions and the sensing layer region 102-1 can be one of the electrically isolated regions on or above the local integrated readout circuit 301. In some cases, an individual segment or an individual electrically isolated region may cover a single local integrated readout circuit. In some cases, an individual segment or an individual electrically isolated region may cover multiple local integrated readout circuits. In some such cases, two segments of the sensing layer may be separated by a gap over a region of the sensor tile comprising bond pads to provide access to the bond pads.

[0082] In some cases, the sensing layer may comprise a sensing material that generates a charge carrier upon receiving electromagnetic radiation having wavelength within a characteristic sensing bandwidth of the sensing material. In some cases, the characteristic bandwidth may comprise one or both X-ray or Gamma-ray wavelengths (or frequencies).

[0083] In some embodiments, an individual local integrated readout circuit of the ROIC can be in optical and / or electrical communication with the sensing layer to receive charge carriers and light from the sensing layer. In some cases, the patterned sensing layer may comprise a plurality of electrically isolated sections, where an individual section is electrically connected to an individual local integrated readout circuit. In some cases, the local integrated readout circuit may be in electrical connection or communication with the sensing layer (or a segment or region of the sensing layer) via a conductive pad formed at or near a major surfaceof the local integrated readout circuit. In some cases, the local integrated readout circuit may be capacitively coupled to the sensing layer (or a segment or region of the sensing layer) via a capacitor (e.g.. a MIMCAP). Advantageously, forming the sensing layer on the local readout circuits may improve or increase the amplitude and / or signal-to-noise ratio of a sensor signal generated by an individual pixel (e.g., by reducing a length of the electrical path between the sensing layer, where electron / holes are formed, and the input of the local integrated readout circuit).

[0084] In some such cases, the sensor die 322 may additionally comprise one or more electronic circuits, herein referred to tile processing circuit 326, electrically connected to the some, most, or all of the pixels 324 of the sensor die 324. In some embodiments, the tile processing circuit 326 may comprise electronic circuitry configured to receive sensor signals from the different row and columns of the array of pixels 324 in the sensor die 322. For example, the tile processing circuit 326 may be configured to scan different columns and rows of in the pixel array 324 to receive sensor signals generated by individual pixels. Additionally, in some cases, the tile processing circuit 326 may comprise an amplification circuit (e.g., amplify the sensor signals), a timing circuit (e.g., control pixel scanning), and / or an input / output interfacing circuit (e.g., to control data communication with another circuit such as an analog-to-digital converter or an intermediate processing module).

[0085] In some cases, the pixels 324 and the tile processing circuit 326 may be formed on or over a common substrate. In some embodiments, the sensor tile 300 may further comprise a tile terminal 328. The tile may comprise an electric interface region or section including electrical circuits and interconnect structures configured to electrically connect the sensor tile 300 to a control and / or signal processing circuit. In some cases, the tile terminal 328 may comprise a PCB electrically connected to the sensor die 322 and / or the substrate on or over which the pixels 324 and the tile processing circuit 326 are formed. In some such cases, the pixel array 324 may be formed within a first region of a substrate and the tile processing circuit 326 may be formed in a second region of the substate, e.g., near an edge of the substrate, and electrically connected to the first region. In some cases, the first and second regions can be rectangular regions. In some cases, the PCB may be electrically connected to an electronic circuit of the substrate via one or more conductive contact pads, conductive vias, solder balls, or the like. The PCB may comprise an electrical connector (e.g., a ribbon connector) and may be configured to provide electric connection between the electronic circuits of the sensor dieand another circuit, e.g., an analog-to digital converter (ADC). Tn some cases, the PCB may include additional electronic circuits configured to process signals received from the sensor die prior to transmission to the connector. In some cases, the PCB may be further configured to provide a bias voltage to the sensor die (e.g., based on a signal received via the connector). In some cases, the electronic circuits of the substrate or an electronic circuit formed on the PCB may comprise a column scanner, a column amplifier, a timing circuit, an input / output (I / O) circuit, other types of electronic circuits or any combination thereof.

[0086] In some embodiments, a number of pixels in the senor tile 300 (in the pixel array 324) can be from 1 to 10 Mega pixels, from 10 to 30 Mega pixels, from 30 to 50 Mega pixels, from 50 to 70 Mega pixels, or any ranges formed by these values for example, from 1 to 70 Mega pixel, or possibly larger or smaller values. In some embodiments, the sensor tile 300 may have a rectangular shape with dimensions ranging, for example, from 5 cm x 10 cm to 20 cm x 40 cm. In one example design, a sensor tile may have a detector area greater than 11cm by 23cm and 67 Mega pixels. In various implementations, a pixel of the sensor tile 300 can have a sensitive area of from 5x5 microns to 15x15 microns, or larger or smaller. However, the designs are not limited to these examples, and a pixel or tile may have other sensitive areas or dimensions.

[0087] In some implementations, the local integrated readout circuit of a pixel may comprise multiple transistors (e.g., CMOS transistors) configured to receive and, in some cases, accumulate or integrate, electric charge (electron and / or holes) generated in the sensor layer and output a sensor signal dependent on, e.g., proportional, to received and / or accumulated electric charge. In some cases, a number of transistors (e.g., CMOS transistors) in the local integrated readout circuit can be from 2 to 4, 4 to 6, 6 to 8, 8 to 10 or any ranges formed by these values, for example, from 4 to 10, or possibly larger or smaller values. In some cases, the electric charge in the sensing layer may be generated by absorption of electromagnetic radiation in the sensing layer. In some cases, a voltage (e.g., a DC voltage) may be applied across the sensing layer to separate electrons and holes generated in response to absorption of electromagnetic radiation. In some such cases, the sensing layer may be vertically extended between two electrodes (e.g., formed on opposing major surfaces of the sensing layer), and the voltage may be applied between the two electrodes by a voltage control circuit. In some cases, a single voltage control circuit may provide the voltage to a plurality of pixels (e.g., pixels in the same tile). In some cases, the voltage control circuit can be electricallyconnected to the sensor tile 300 via the tile terminal 328. In some cases, the voltage applied on the sensing layer can be from 100 to 500 volts, from 500 to 1000 volts, from 1000 to 1500 volts from 1500 to 2000 volts or any ranges formed by these values, for example, from 500 to 2000 volts or possibly larger or smaller values. In some cases, the voltage applied on the sensing layer may be configured based on the thickness of the sensing layer to and electric field greater than or equal to 5 V / micrometer, greater than or equal to 10 V / micrometer, or greater than or equal to 15 V / micrometer.

[0088] In some examples, the sensor tile 300 and the pixels therein may be configured to detect photons having energies from 0.1 to 10 kilo electron-volts (keV), from 10 to 25 keV, from 25 to 50 keV, from 50 to 70 keV, from 70 to 100 keV, from 100 to 130 keV, from 130 keV to 150 keV, for example, from 50 to 150 keV, or possibly any ranges formed by these values or larger or smaller values.

[0089] In some embodiments, the sensor die 322 may include two lateral edges and two longitudinal edges. In certain implementations, the tile processing circuit 326 may be positioned near one of the lateral edges. The pixel array 324 may comprise pixel columns extending longitudinally between a lateral edge 323b and the tile processing circuit 326, and pixel rows extending between the two longitudinal edges 323a and 323c. In some cases, the lateral edge 323b and the longitudinal edges 323a and 323c, collectively referred to as tiling edges, may not include any electrical connectors and can be configured to permit the sensor tile to connect to three adjacent sensor tiles (e.g., sensor tiles substantially identical to the sensor tile 300). For example, the sensor tile 300 may interface with another sensor tile along the lateral edge 323b, and with two additional sensor tiles along the longitudinal edges 323a and 323c.

[0090] FIG 3B schematically illustrates an individual local integrated readout circuit 301 (e.g.. circuitry of a local integrated readout circuit) configured to generate a sensor signal indicative of generation of one or more charge carriers (e.g., electrons or holes) in a sensing layer region 102-1 or a photocurrent (or photocharge) generated by a photodiode (DI) 302, which may be included in the local integrated readout circuit 301. In some embodiments, the local integrated readout circuit 301 may be controlled to generate a first sensor signal indicative of generation of one or more charge carriers in the sensing layer region 102-1 during a first operational mode and generate a second sensor signal indicative of the photocurrent generated by the photodiode (DI) 302, during a second operational mode. In some cases, thephotodiode (DI) 302 can be a pinned photodiode. Tn some examples, the photodiode (DI) 302 may be configured to detect light having wavelength within visible range, near infrared range, a portion of ultraviolet range (e.g.. from 350 nm to 400 nm) or combination thereof. In some examples, the photodiode (DI) 302 may be configured to detect photons having energies less than 10 eV.

[0091] In some cases, the sensing layer region 102-1 can be electrically connected to the local integrated readout circuit 301. In some embodiments, the local integrated readout circuit 301 may be electrically connected to the sensing layer region 102-1 via a conductive contact pad 309 (or a conductive region of a of the local integrated readout circuit 301). In some examples, the sensing layer region 102-1 may comprise a thin film comprising a-Se and configured to generate electrons and holes in response to absorbing X-ray (or in some cases gamma ray) radiation.

[0092] In some embodiments, the photodiode (DI) may be configured to generate photocurrent (or photovoltage) upon receiving visible light (having wavelengths from 400 nm to 750 nm) and / or near infrared light (e.g., from 750 nm to 1700 micrometers), and in some cases, ultraviolet (UV) light (e.g., soft UV having wavelengths from 190 nm-400 nm) or any combination of wavelengths or wavelength ranges in one or more of these spectral regions.

[0093] In some embodiments, the photodiode (DI) may be positioned below the sensing layer region 102-1 and may be configured to receive light from or through sensing layer region 102-1. For example, the photodiode (DI) may receive light generated by sensing layer region 102-1 in response to receiving and / or absorbing X-ray, Gamma-ray, or hard ultraviolet radiation, or may receive light from a surrounding environment transmitted through sensing layer region 102-1. In some embodiments, the sensing layer region 102-1 may be configured to transmit at least a portion of the visible, infrared, or near-infrared radiation or any combination wavelength from these spectral regions that is incident on the sensing layer region 102-1. In some such embodiments, the sensing layer region 102-1 may comprise an opening (e.g., through hole) above or near the photodiode (DI) layer to allow visible, infrared, or near-infrared radiation or any combination thereof to become directly incident on the photodiode (DI) without interacting or substantially interacting with the sensing layer.

[0094] As described above, in some cases, an electric field (e.g. a strong electric field greater than 10 V / pm) is established or applied across the sensing layer region 102-1 to separate electrons and holes generated in the sensing layer region 102-1 and drive the electronsor the holes toward the conductive pad electrically connected to the local integrated readout circuit 301 via the capacitor 309.

[0095] The local integrated readout circuit 301 shown in FIG. 3B comprises six transistors M1-M6. First and second transistors Ml 306 and M2 308 may be used to switch between two operational modes (e.g., based on electric charge received from the sensing layer region 102-1 or from the photodiode (DI)). In some embodiments, the first transistor Ml 306 may be turned ON and the second transistor M2 308 may be turned OFF to receive charge carriers from the sensing layer region 102-1 and to generate a sensor signal indicative direct conversion of charge earners within the sensing layer region 102-1, e.g., as a result of absorption of high energy electromagnetic radiation. In some embodiments, the first transistor Ml 306 may be turned OFF and the second transistor M2 308 may be turned ON to receive photocurrent from the photodiode (DI) 302 and to generate a sensor signal indicative of detection of low energy electromagnetic radiation. In some cases, the first and second transistors Ml 306, M2 308. may switched using first and second transistor control signals TXP, TXN, respectively.

[0096] In some cases, the local integrated readout circuit 301 may comprise a third transistor M3 310 that may be activated by a third control signal BIN2_SEL to blend the electric charge of 4 pixels in a 2x2 matrix to enable fast scanning. For example, the third control signal BIN2_SEL can be a global binning control that may cause the third transistor M3310 to combine the detected electrical charge detected by the pixel 301 with those detected by three other pixels within an integration period. In some examples, the pixel 301 and the three other pixels may comprise of four adjacent pixels, e.g., arranged in a 2x2 grid. The number of pixels binned can be more or less in other designs.

[0097] In some cases, the local integrated readout circuit 301 may comprise a fourth transistor M4312 that may be activated by a fourth control signal VREF_PIX to reset the charge in a storage or integration capacitor Cl 320. In some cases, the local integrated readout circuit 301 may comprise a diode D2 304 configured to protect the electronic components in case a defect in the sensing layer region 102-1 causes the high voltage applied to the sensing layer region 102-1 to become shorted to the local integrated readout circuit 301. In some cases, the local integrated readout circuit 301 may comprise fifth transistor M5 314 serving as a follower transistor configured to generate a sensor signal in response to receiving a signal (e.g., a voltage) from the sense node 307. In some cases, the local integrated readoutcircuit 301 may comprise a sixth transistor M6 316 configured to connect the output of the fifth transistor M5314 to a column link 321, upon receiving a ROW control signal and thereby transmit the sensor signal to the tile processing circuit 326 via the column link 321.

[0098] In some cases, the electric charge received from the sensing layer region 102-1 may be collected by a holding capacitor (CO) 318 and then converted to a voltage. In some such cases, absorption of an ionizing electromagnetic radiation in the sensing layer region 102-1 may generate electrons and holes and the electric field established in the sensing layer region 102-1 may drive charge carriers of the same type (e.g., electrons or holes) toward the conductive pixel pad 209. When the transistor Ml 306 is ON (activated) the charge carriers may flow from the conductive pixel pad 209 to the transistor Ml 306 via the contact node 305. When the transistor Ml 306 is OFF (deactivated) the charge carriers may flow from the conductive pixel pad 209 to the holding capacitor (CO) via the contact node 305. In some cases, the holding capacitor (CO) 318 can be a MIM capacitor (e.g., the MIMCA 206 in FIGS 2A, 2B, 2C. or 2D).

[0099] In some cases, a direct conversion mode, where charge carriers are received from the sensing layer region 102-1, may comprise a hole collection mode and a photodiode mode may comprise an electron collection mode. In some cases, the electron collection mode may differ from hole collection mode in that the photodiode (DI) may be used for storing charge storage, which is then transferred to the integration capacitor, while in the hole collection mode, the capacitor directly stores the charge. As such, the dual mode local integrated readout circuit 301 may be controlled to operate in the hole collection mode to detect radiation having wavelength in X-ray and / or gamma ray range, during a first period, and to operate in the electron collection mode to detect radiation having wavelength in visible and / or near infrared wavelength, during a second period. Thus, the local integrated readout circuit may detect radiation having different wavelengths in close temporal coincidence.

[0100] In some implementations, the local integrated readout circuit may be controlled to simultaneously receive charge from the photodiode (DI) and sensing layer region 102-1. For example, in some cases, transistor Ml and M2 may be both turned on (e.g., by simultaneously providing control signals TXP and TXN to Ml and M2, respectively).

[0101] In some cases, the sensing layer region 102-1 may comprise both charge transport and Cerenkov photon emission properties to allow for both direct (based on electric charge generated by the high-energy photons) and indirect (based on visible or near IR photonsgenerated by the high-energy photons). In some cases, the sensing layer may comprise a scintillating material configured to generate visible (or near IR radiation) in response to absorbing X-ray, gamma ray (or generally a high-energy photon) and the local integrated readout circuit may be configured to detect visible (and / or infrared) radiation and generate a sensor signal corresponding to the detected visible radiation (and / or infrared).

[0102] In some embodiments, the sensing layer may be configured to generate charge carriers or visible / near-IR radiation in response to absorbing ultra-violet (UV) radiation. As such, in some cases, the senor tiles and panels described above may be used to detect UV radiation by secondary emission by the sensing layer.

[0103] FIG. 4A schematically illustrates a cross section of three sensor pixels of a detector each configured to directly detect ionizing electromagnetic radiation using a sensing layer 102 and non-ionizing electromagnetic radiation using a photodetector element, e.g., a photodiode (not shown). In this example configuration, the pixels may comprise a sensing layer 102, a top electrode layer 207 formed on or above the sensing layer 102, and a charge blocking layer 215 formed between the readout integrated circuit ROIC (e.g., a CMOS ROIC) and the sensing layer 102. In some cases, the sensing layer 102 may comprise selenium (e.g., amorphous selenium), cesium iodide, Gadolinium oxysulfide, a halide perovskite, or another material configured to generate charge carriers upon absorbing high energy electromagnetic radiation. In some cases, a charge blocking layer 215 may be formed between the sensing layer 102 and the local integrated readout circuit 403 (e.g., between the sensing layer 102 and the local integrated readout circuit 403). In some cases, a top layer 211 of the circuit 403 may comprise conductive regions, segments, or pads separated and electrically isolated by insulation, dielectric, or otherwise charge blocking regions. In some examples, the top layer 211 may comprise a scratch protection layer that has been thinned to match a contact metal pad and expose the metal surface.

[0104] In some cases, an individual pixel may comprise a conductive pixel pad 209 serving as bottom electrode. In some cases, the conductive pixel pad 209 may be configured to confine the electric field and charge carriers inside the sensing layer 102 such that the charge carriers generated as a result of absorption of high energy electromagnetic radiation 104 above an individual local integrated readout circuit are collected by the local integrated readout circuit via the conductive pad 209. Advantageously, the blocking layer 404 with the conductive pads therein may provide electrical isolation between adjacent pixels of a sensor tile (or panel),thereby reducing or eliminating pixel-to-pixel cross-talk such that sensor signals generated by individual local integrated readout circuits remain associated with the respective volume of the sensing layer 102 (e.g.. substantially above the respective area or the ROIC 403). In some embodiments, an individual local integrated readout circuit may comprise a capacitor 406 electrically connected to a conductive pixel pad 209 of the blocking layer 404. In some cases, the local integrated readout circuit may comprise an n-region 410 formed within a p-well (or p-layer) 411 and the capacitor 406 can be connected between the conductive region 209 and the n-region 410. In some cases, electrical charge stored in the capacitor 406 can be substantially equal or proportional to electric charge generated in a volume of the sensing layer 102 as a result of absorption of the high energy electromagnetic radiation 104. In some embodiments, at least a portion (e.g., a dielectric region) of the blocking layer 404 may comprise a material configured to transmit low energy electromagnetic radiation 105 (e.g., having wavelengths within soft UV, VIS, or IR region or any combination thereof), such that a photodiode of the ROIC can receive the low energy electromagnetic radiation 105.

[0105] In some embodiments, a plurality of pixels may be combined to form a macro-pixel. In some cases, an individual pixel may comprise direct sensing region (indicated by dashed line) configured to generate charge carriers in respond to absorbing ionizing electromagnetic radiation and a photodiode that partially surrounds the direct sensing region. The photodiode can be configured to detect non-ionizing electromagnetic radiation (e.g., in VIC, NIR, soft-UV and a combination thereof) via a transparent layer formed on or above the photodiode. In some cases, the macro-pixel section may comprise one or more local integrated readout circuits formed with the photodiode in a common co-planar circuit layer (e.g., a CMOS circuit layer). In some cases, the transparent layer may be formed over a portion of the circuit layer comprising the photodiode and the sensing layer may be formed over a portion of the circuit layer comprising a conductive contact pad electrically connected to a local integrated readout circuit. In some cases, the local integrated readout circuit of an individual pixel may be electrically connected to the corresponding sensing layer (or sensing layer segment) via one or more conductive contact pad segments.

[0106] In some cases, the conductive contact pad of an individual pixel may comprise multiple conductive contact pad segments that can be arranged as a matrix (e.g., a 2x2, 3x3, 4x4, 5x5, an NxN matrix, or a matrix having non-equal numbers of rows and columns).

[0107] FIG. 4B schematically illustrates a top-view of an example macro-pixel comprising a four pixels. In one example, the sensing layer of each pixel may be connected to the corresponding local integrated circuit nine contact pads (e.g., arranged as a 3 by 3 matrix) and an L-shape photodiode. In some cases, the pixels may be configured to detect ionizing electromagnetic radiation (e.g., X-ray) based on charge carriers received from a sensing layer 102 and the L-shape photodiode may be configured to detect non-ionizing electromagnetic radiation (e.g., in visible and near-infrared wavelength ranges). In some cases, each pixel of the macro-pixel can be a LxL square shape pixels, where L can be from 5 to 15 microns. In some example L can be 7 microns.

[0108] FIG. 4C schematically illustrates a cross-sectional view of a section of the macro-pixel shown in FIG. 4B depicting a co-planar integrated local readout circuit 405 comprising a photodiode 408 (e.g., one of the four photodiodes in FIG. 4B), a sensing layer 102 formed on or over a portion of the integrated local readout circuit 405, and a transparent layer 407 formed one or over the photodiode 408. In some cases, the photodiode 408 can be a pinned photodiode. In some cases, one or more MIMCAPs 406 may be embedded in a layer between the sensing layer 102 and the integrated local readout circuit 405.

[0109] FIG. 5A schematically illustrates an example of a sensor die 322 comprising a plurality of sensor pixels (referred to as pixels). In some implementations, the pixels may be arranged as columns separated by a column spacing, where each column comprises a one-dimensional array of sensor pixels extended from a first longitudinal edge (e.g., a tiling edge) of the sensor die to a tile processing circuit 326 formed near a second longitudinal edge of the sensor substrate. In some cases, the tile processing circuit 326 circuit may be electrically connected to the individual columns to receive sensor signals from the pixels in the column. In some examples, the number of columns in a sensor tile can be from 100 to 200. from 200 to 300, from 300 to 400. or any range formed by these values, e.g., from 100 to 400 or, possibly, larger or smaller. The inset shows a 5X stepper reticle mask layout 502 for large die stitching.

[0110] FIG. 5B schematically illustrates a wafer 504 comprising five sensor dies. In some cases, an individual sensor die may comprise a pixel array and a tile processing circuit. In some cases, the wafer 504 may comprise five ROIC segments where an individual ROIC segment comprises an array or local integrated readout circuits and a tile processing circuit. In some cases, the wafer 504 may comprise a sensing layer formed on or over the ROIC segmentsto form the sensor dies. Tn some embodiments, the sensing layer may be formed on a sensor die or on a ROIC segment, after separating (dicing) the sensor die from the wafer.

[0111] FIG. 5C schematically illustrates two sensor tiles having different lateral dimensions (e.g., lengths and widths in a plane normal to vertical direction). In some cases, an individual one of the two sensor tiles may be fabricated by connecting and / or attaching a tile terminal 328 to a sensor die 322.

[0112] In some designs, a single mask may be used to fabricate tiles having different lateral sizes (e.g., different lengths and / or different widths).

[0113] In some implementations, multiple tiles (e.g., separately fabricated tiles) may be combined to form a sensor panel to provide a larger detector area (sensing area). In some cases, tiles having different lateral dimensions may be fabricated based on the arrangement / architecture described above with respect to FIGS. 3A-3B. Advantageously, the proposed tiled-based design and architecture allow formation of a scalable detector area having a desired shape and / or dimension by fabricating and using multiple tiles having the same or different dimensions / shapes (e.g., a unified design methodology) and stitching the titles to form a sensor panel having the desired shape and / or dimension. In some cases, the sensor panel, which may comprise one or more tiles, can be used in a modular camera. In some implementations, a tile may have a detector area having a width and / or length from 1 to 5 centimeters, from 5 to 10 centimeters, from 10 to 25 centimeters, from 25 to 30 centimeters, or any ranges formed by these values, e.g., from 1 to 30 centimeters, or possibly larger or smaller sizes.

[0114] FIG. 6A schematically illustrates a top-view of an example sensor panel 600 formed by connecting six sensor tiles (e.g., six substantially identical sensor tiles) arranged as a 2 by 3 matrix. In some cases, the sensor panel 600 may be fabricated by stitching six individual sensor tiles via their connector- free edges such that the corresponding tile terminals (PCB sections) are positioned at outer edges of the sensor panel 600. In some cases, individual tile terminals may be connected, bonded, or otherwise electrically attached to individual intermediate circuit modules (not shown), e.g., via ribbon connectors. In some embodiments, an individual sensor tile may comprise multiple identical self-contained pixel array blocks called sensor slices. In some cases, an individual sensor slice may comprise bonding pads for readout out of the sensor signals by the pixels of within the sensor slice. In the example shown in FIG. 6A, each sensor tile comprises six slices.

[0115] FIG. 6B schematically illustrates a three-dimensional view of another example sensor panel 610 comprising eight sensor tiles (e.g., eight substantially identical sensor tiles) arranged as a 2 by 4 matrix.

[0116] FIG. 7 schematically illustrates a three-dimensional view of a region of a sensor tile depicting formation of a sensing layer (e.g., amorphous selenium layer, comprise amorphous selenium, cesium iodide, or Gadolinium oxysulfide, or other material comprising scintillating and / or photo-to-change conversion properties) over a ROIC 403 (e.g., CMOS ROIC) comprising a plurality of integrated local integrated readout circuits. In some implementations, the sensing layer may be directly formed on or over the local integrated readout circuits by deposition of a sensor material (e.g., selenium) on local integrated readout circuits via a mask 702 (e.g., a shadow mask). In some other designs, a sensing layer (e.g., a segmented sensing layer) may be formed photolithographically by depositing a layer of sensing material on or over the local integrated readout circuits, depositing a photoresist (PR) layer on the sensing layer, photolithographically patterning the PR layer (e.g., using a photolithographic mask), and etching the sensing layer. In some implementations, a portion of the sensing layer 102 on or above a local integrated readout circuit and the local integrated readout circuit may form a vertical stack. In some cases, a vertical separation between the sensing layer 102 and the ROIC 403 can be 20 micrometers (microns) or less, 15 microns or less, 10 microns or less, 5 microns or less, 2 microns or less, 1 micron or less, 0.5 micron or less or any range formed by any of these values, e.g., from 20 microns to 0.5 microns, or possibly larger or smaller. In some cases, an intermediate layer between the sensing layer 102 and the ROIC 403 may provide electrical connection between the sensing layer 102 and the individual local integrated readout circuits. In some cases, the intermediate region may comprise a conductive material or at least a conductive region (e.g., a plurality of conductive pads). In some cases, the sensing layer 102 may be directly in contact with the a portion of the ROIC, for example, with a conductive pads 209 of a local integrated readout circuit.

[0117] In some embodiments, a sensing layer may be physical pressed upon a top major surface of a ROIC using pressure from X-ray transparent foam compression. In some such cases, an airgap may exist between the sensing layer and the ROIC.

[0118] In some implementations, thickness (t_se) of the amorphous selenium layer along a vertical direction can be from 30 to 50 microns, from 50 to 100 microns, from 100 to 150 microns, from 150 microns to 200 microns, or any range formed by these values, e.g.,from 30 to 200 microns, or possibly larger or smaller values. In some cases, t_se may be determined based at least in part on the wavelength range and / or energy range of the electromagnetic waves detected by the sensor. The vertical direction can be perpendicular to a major surface of a wafer on which the local integrated readout circuits are fabricated.

[0119] In some embodiments, an opening may be formed in the sensing layer 102 to allow some radiation (e.g., visible or near-IR) radiation to become incident on the photodiode and / or a region of the local integrated readout circuit under the sensing layer without interacting with the sensing layer 102.

[0120] In some embodiments, a conductive layer may be formed on a top surface of the sensing layer to allow generating an electric field in the sensing layer by applying a voltage across the sensing layer.

[0121] FIG.8 schematically illustrates an imaging system 800 comprising a sensor tile 300 (e.g., a sensor die 322 connected to a tile terminal 328), an intermediate module 804, a main board 806 and a computing system 808. In some cases, the tile terminal 328 may receive sensor signals from individual columns of the sensor tile (e.g., from the ROIC of the sensor tile) and provide the sensor signals, in some cases, e.g., after initial processing, to the interface module 804. The interface circuit module 804 may process (or further process) the sensor signals received from the sensor die (e.g., via the PCB) to generate intermediate signals 805 and provide the intermediate signals to a main board 806 (e.g., a mother board). In some cases, the interface module 804 may comprise a plurality of ADS devices configured to receive analog senor signals from the sensor tile 300, generate corresponding digital signals, herein referred to as the intermediate signals 805, and transmit the intermediate signals to the main board 806. In some cases, interface module 804 may comprise a power management circuit and one or more driver circuits. In some cases, the main board 806 may be configured to process the intermediate signals 805 to generate an output signal 807 carrying information indicative of an amount, amplitude and / or intensity of radiation received by individual pixels of the sensor tile 300. In some cases, the main board 806 can be an FPGA board comprising an ADC interface 806a, a data grabber and processing circuit 806b, a PCI express interface 806e, a Double Data Rate (DDR) circuit 806c, and a sequencer 806d. In certain embodiments, the output signal 807 may be transmitted to a computing system 808 (e.g., a personal computer) configured to process the output signal 807 and generate an image signal corresponding to an image of an object illuminated by an electromagnetic source operating at a specified spectralrange. Tn some cases, the spectral ranges can be high energy spectral range (e.g., X-ray) or a low energy spectral range (e.g., VIS, NIR). In some embodiments, the computing system 808 may transmit the image signal to a display system that generates an image comprising an intensity distribution of electromagnetic radiation having one or more wavelengths within, for example, the X-ray, Gamma-ray, UV, VIS, or NIR range, over the sensitive area of the sensor tile 300. In some cases, the image signal may comprise a hybrid image signal including two overlapping images, each formed based on radiation detected within a different wavelength range. In some cases, the computing system 808 may comprise a non-transitory memory storing machine readable instructions and a hardware processor configured to execute the machine-readable instructions to process the output signal 807 to generate the image signal.

[0122] In some embodiments, the imaging system 800 may comprise a high voltage (HV) module 810 configured to provide a DC voltage to a sensor tile 300 to generate an electric field in the sensor layer therein. In some cases, the high voltage (HV) module 810 may operate under control of the computing system 808.

[0123] FIG. 9 is a block diagram illustrating an example process that may be used to design and fabricate a detector system comprising a sensor panel, one or more intermediate circuit modules, and at least one mother board. In some cases, the one or more intermediate circuit modules may be integrated with the mother board. In some cases, the sensor panel may comprise one or more one sensor tiles. In some cases, the at least one sensor tile may comprise one or more features described above with respect to FIGS 1, 2A / 2B, 3, 4, and 7, and the interface module and a mother board may comprise one or more features described above with respect to FIG. 8.

[0124] In some embodiments, the design and fabrication of the sensor panel may comprise multiple steps or phases including: design and fabrication of individual sensor tiles, design and fabrication of the intermediate circuit modules and the at least one motherboard, assembly of the sensor tile using the sensor panels, integration and / or connection of the motherboard, intermediate circuit modules and the sensor panel, camera software integration with the mother board, connecting the motherboard to a computing system. In some cases, the motherboard and the software integrated therein may be used to test individual sensor panels separately prior to deployment of all sensor panels for image generation across the entire sensor panel.

[0125] In some implementations, the fabrication process may begin with providing a wafer and fabricating one or more ROICs, where an individual ROIC may comprise an array of local integrated readout circuits of an individual sensor die. In some cases, a ROIC or one or more local integrated readout circuits therein may be electrically tested to verify their performance. In some embodiments, the wafer may be diced to singulate a single ROIC and form (e.g., depositing) a sensing layer (e.g.. a-Se layer) on or over the ROIC to form a sensor die. In some cases, the sensing layer may be patterned to separate segments of the sensing layer deposited on or above different local integrated readout circuits. For example, after fabricating a plurality of ROICs over a wafer, the wafer may be diced to separate a CMOS die, and a layer of a-Se (or another photoconductive X-ray detector materials) may be patterned directly onto the surface of the CMOS die.

[0126] In some embodiments, the sensing layer may be formed (e.g., deposited) over the wafer on two or more ROICs to form multiple sensor dies prior to separating the sensor dies from the wafer.

[0127] In some cases, e.g., concurrently with fabrication of the ROICs, title processing circuits electronic may be fabricated (e.g., monolithically fabricated) on the wafer. In some cases, an individual tile processing circuit can be electrically connected to an individual ROIC. For example, a tile processing circuit can be electrically connected to multiple columns of the ROIC. As such, the resulting sensor die may comprise an integrated circuit comprising the ROIC, the patterned sensing layer thereon, and tile processing circuit. In some embodiments, the fabrication process may further comprise fabricating tile terminals (e.g., PCBs) and connecting individual tile terminals to individual sensor dies to form individual sensor tiles. In some embodiments, the process described above may be used to fabricate two or more sensor tiles.

[0128] In some implementations, the process may further comprise fabricating and / or providing at least one intermediate circuit module and at least one mother board, connecting the intermediate circuit to an individual sensor tile and to the mother board to test the performance of the sensor tile.

[0129] In some cases, multiple sensor tiles may be connected to assemble a sensor panel. In some such cases, the sensor panel may be formed after separately testing the corresponding sensor tile using the same or different intermediate circuits. In some other cases,the individual sensor tiles of the sensor panel may be tested after forming the sensor panel, using the same or different intermediate circuits.

[0130] In some cases, each sensor tile may be electrically connected to an intermediate circuit module. In some cases, the intermediate circuit module may comprise an analog-to-digital converter (ADC). In some cases, the intermediate circuit module may comprise a PCB. In some embodiments, individual intermediate circuit modules may be connected to a camera readout electronics bus on a motherboard, to form a standalone detector.

[0131] In some embodiments, a sensor panel may comprise multiple sensor tiles aligned and attached to each other along three tiling edges, with the fourth edge used to connect the individual sensor tiles to individual intermediate circuit modules. In some cases, the sensor panel may comprise a backplate on or over which the sensor tiles may be mounted or disposed. In some cases, the individual intermediate circuit modules may be connected to a main board (e.g., a motherboard).

[0132] In some cases, the ROIC tile of a sensor tile may comprise an Application Specific Integrated Circuit (ASIC). In some cases, the ASIC may be designed such that it can be manufactured using a specified CMOS semiconductor manufacturing process. In some cases, the specified CMOS semiconductor manufacturing process may comprise a process tailored for read-out integrated circuits (ROICs) used in imaging and focal plane array (FPA) applications. In some examples, the specified CMOS semiconductor manufacturing process may be tailored for high-density pixel level metal pads for contact with photoconductive detector layers. In some embodiments, the specified CMOS semiconductor manufacturing process may comprise a mask reticle set designed to fabricate a die with variable dimensions based on a two-dimensional reticle pattern stitching technology. In some examples, the specified CMOS semiconductor manufacturing process may comprise the Skywater S90LN 90-nm process. In some cases, the stitching mask may support sensor tiles having different dimensions and different number of pixels. In some examples, the dimensions of a sensor tile can be from 25 mm x 25 mm to 140 mm x 140 mm. In one example, the dimensions of a sensor tile can be 28.67 mm x 28.67 mm. In another example, dimensions of a sensor tile can be 136 mm x 136 mm. In some examples, the number of pixels in a sensor tile may comprise from 4096 x 4096 pixels to 19456 x 19456 pixels. In some cases, the stitchable mask design may enable customization of a sensor die size, and thereby a sensor tile size, for a specificapplication without the need for a new mask set and thereby eliminating the Non-Recurring Engineering (NRE) cost for the new mask set.

[0133] In some embodiments, the readout ASIC may comprise an edge pixel layout configured for three-side close tiling.

[0134] In some cases, the modular design and fabrication shown in FIG. 9 may allow fabrication of sensor panels with customized fields of view (FOVs) for a wide range of applications.

[0135] In various implementations, a sensor panel can be as small as 3 cm x 3 cm to modules for a large-area sensor panel configured for clinical chest X-ray.

[0136] FIG. 10A is a circuit diagram illustrating electrical connection between a pixel column comprising N pixels and a downstream amplifier via a column link 321 and two sample-and-hold (S&H) amplifiers SHI, SH2. In some embodiments, a first S&H amplifier, SHI, may be configured to receive and store a signal level of a pixel in the pixel column, and a second S&H amplifier, SH2, may be configured to receive and store a reset level of the same pixel, after an exposure period of the pixel. In some embodiments, a downstream amplifier may be configured to subtract the reset and signal values to remove noise (e.g., kTC noise, fixed-pattern noise, and the like). In some cases, the downstream amplifier may comprise a differential amplifier or correlated double sampling (CDS) amplifier. In one embodiment, a tile processing circuit may be configured to sequentially extract signals from the column link 321. In some cases, a sensor signal and a reset signal may be routed from the column link 321 to SHI and SH2, respectively. SHI and SH2, may sample and store the instantaneous voltages to preserve the corresponding voltage levels for subsequent processing. The held voltages from the two S&H amplifiers are then provided to the downstream amplifier 1002. The downstream amplifier 1002 may process (e.g., subtract) the two stored voltages to produce a conditioned output voltage suitable for further analog processing or digitization, enabling accurate and low-noise extraction of pixel information from both columns.

[0137] FIG. 10B shows results of calculations performed to evaluate linearity of pixel response and capacitive loading of pixel waveform for pixels in a sensor panel or sensor tile. The top panel shows temporal variations of: a first control signal provided to SHI (to activate SHI), a reset signal sent to a pixel (to reset the pixel), a second control signal provided to SH2 (to activate SH2), and pixel output waveforms (e.g., output by the downstream amplifier 1002) for three pixels (pixel Nos. 1, 4096, and 8193) in a sensor panel. The bottompanel shows calculated temporal variations of photocurrent and output voltage readout from a pixel depicting a time interval within which the response is linear.

[0138] In some embodiments, row and column selection and readout within the sensor tile and / or sensor panel, may be controlled by a scanning circuit (e.g., a scanning circuit of the tile processing circuit). In some cases, the scanning circuit may comprise an x-y scanning circuit. In some embodiments, the scanning circuit may comprise a token-based scanning circuit in which a row token propagates sequentially through a chain of row-driver cells to assert a corresponding row-select signal for an active row while a column token propagates through column readout cells to grant exclusive access to a shared column bus, such that only the column holding the token samples or forwards data at a given time; upon receipt of the row token, the selected row couples pixel outputs to respective column lines, where the token-enabled column readout cell operates its sample-and-hold and / or correlated-double- sampling front end to acquire the pixel signal and, after completing acquisition or transmission to downstream circuitry, passes the column token to a next column cell, while completion of the row cycle triggers hand-off of the row token to a next row, thereby providing deterministic, collision-free, and low-power arbitration for sequential extraction of pixel signals across the array and compatibility with asynchronous / event-driven or mixed readout modes.

[0139] FIG. 11 is a block diagram schematically illustrating a scanning circuit configured to scan the horizontal and vertical axes (row and columns), simplifying the row / column decoder and enabling partial readouts through token manipulation. The top panel (a) shows a horizonal toke chain and a bottom panel (b) shows vertical toke chain. In some cases, both the horizontal (for column selection) and vertical (for pixel addressing) token chains may use shift register elements, with token cells built around a D-latch that changes state on the rising edge of TK_ADV_... command. In some cases, horizontal tokens may enable analog readout by driving common horizontal lines, VOUTP and VOUTN, while vertical tokens may connect the internal analog voltage to the local column line for pixel readout. In some embodiments, buffering may be implemented every M rows and columns to boost clock edges, allowing for adaptation in line / column numbers. In some cases, M can be from 10 to 15 from 15 to 20 or other values. In some cases, in a normal mode, even and odd token cells can be connected to different clock phases, while in a binning mode, even token cells can be active.

[0140] FIG. 12A shows the integration timing for direct conversion mode where charge is received from the sensing layer (when M2 is OFF and Ml is ON). With reference to FIG 3B, in the direct conversion mode, the second control signal (TXN) can be at a low (off) level to disconnect the photodiode (DI) 302, the first control signal (TXP) can be at a high (on) level to connect the sensing layer region 102-1 to the sense node 307 of the source-follower stage (the fifth transistor M5 314). In this case, Capacitors CO and Cl are shorted to form a larger storage capacitor (e.g., a 40 fF capacitor). In some cases, in direct conversion mode, the reset voltage VREF_PIX (the fourth control signal) may be set to 1 V, and during integration, the voltage on contact node 305 (labeled PAD) may rise due to charge earners received from sensing layer region 102-1. During readout, a row control signal may switch the sixth transistor M6316 to connect the fifth transistor M5 314 to the common column link 321, and to transmit the sensor signal to a corresponding double sample-and-hold circuit. A pulse on SH_SIG may save the signal, and the RSTB signal may reset the pixel storage capacitor to VREF, with SH_RST sampling the reset level. In some cases, SH (SIG and RST) signals are applied at the column amplifier level. In some cases, RSTB may be applied to transistor M4312 in FIG. 3B. For the hole collection mode, the signal may be accumulated in CO 318 and the Cl 320 capacitors can be involved when the transistor Ml 306 is ON (activated by the signal TXP) to transfer charge to the node 307.

[0141] Fig. 12B shows the integration timing for the photodiode mode, where charge is received from the photodiode (DI) 302 (when M2 is ON and Ml is OFF). With reference to FIG 3B, in the direct conversion mode, the second control signal (TXN) can be at a high (on) level to connect the photodiode (DI) 302 to the sense node 307 and the first control signal (TXP) can be at a low (off) level to disconnect the sensing layer region 102-1 from the sense node 307. During readout, the RSTB signal may pull the pixel signal to 3.3 V - Vt (~2.2 V), and SH_RST samples the reset level. A pulse on TXN may transfer charge from the photodiode to Cl, and a pulse on SH_SIG samples the signal. As described earlier, the photodiode mode may differ from the direct conversion mode in that the photodiode (DI) 302 is used both for converting photons to charge carriers (e.g., photocurrent) and storing the resulting charge carriers and then providing the stored charge carriers to the integration capacitor Cl 320, while in direct conversion, the integrating capacitor Cl 320. in some cases, capacitor CO 318, directly stores the charge.

[0142] In some embodiments, the readout timing sequence is controlled by the user (e.g., through user interface) with 11 externally driven signals, including row and column pulses (TK INIT COL, TK INIT ROW, TK ADV COL. TK ADV ROW), pixel control signals (RST, TXN, TXP), and S&H pulses (SH SIG, SH RST). Global controls (GLOBAL and BIN2 SEL) manage reset and binning modes. Partial readout is supported by pre-advancing tokens to specific rows. The ASIC uses token-based chains for efficient row and column selection, simplifying decoder complexity, and improving pixel readout. Horizontal tokens control the column Sample and Hold (S&H) amplifiers to facilitate analog signal readout. The token advancement is managed by the TK ADV COL command, with initialization handled by TK INIT COL. Buffers are inserted every 16 columns to maintain signal integrity, and alternating clock phases help prevent racing conditions. In binning mode, odd tokens are deactivated, grouping pixels into 2x2 blocks and doubling the readout speed. Horizontal tokens output pseudodifferential signals to ensure high signal fidelity during readout. Vertical tokens manage row-level selection, connecting pixels to column lines. Advancement occurs via the TK ADV ROW command, with initialization performed by TK INIT ROW. Similarly to the horizontal chain, buffers are inserted every 16 rows, and partial readout is supported by pre advancing tokens to target rows. The vertical chain processes one row per token advancement, aligning with the slower analog readout process.

[0143] In some embodiments, the modular system design described above, e.g., fabricating individual sensor tiles and sticking them to form a sensor panel, may enable fabrication of sensor panels with large areas exceeding 20 cm x 30 cm, and with resolutions surpassing 100 megapixels per sensor tile. In some cases, yield of CMOS fabrication and digital pipeline data rates may impose practical limitations on certain performance parameters of the sensor panel. Table 1 shows calculated RC time constants, readout times and frame rates for sensor panels formed by stitching sensor tiles for different values or stiches along a long edges of the sensor tiles, number of pixels in the sensor panel and the size of the sensor panel. The calculated data in Table 1 is obtained by partial-layout simulation of the pixel readout chain, including the pixel front-end, S&H circuits, output buffers, and digital token chains. Simulations are performed across seven process comers including ff 0C, ss 50C, fs 30C, sf 30C, ff ht 50, and ss It 0C.Table 1Total readout Frame Frame # Y axis Size Y RC Total readoutPixel time per row Rate rate 2x2 stitches (mm) (microsecond) time per row (s)Binning 2x2 (s) (f / s) (f / s) 1 2048 14.34 0.02 6.57E-06 3.37E-06 74.3 290.0 2 3072 21.50 0.04 6.78E-06 3.58E-06 48.0 182.0 3 4096 28.67 0.07 7.07E-06 3.87E-06 34.5 126.1 4 5120 35.84 0.10 7.45E-06 4.25E-06 26.2 91.9 5 6144 43.01 0.15 7.91E-06 4.71E-06 20.6 69.16 7168 50.18 0.21 8.46E-06 5.26E-06 16.5 53.1 7 8192 57.34 0.27 9.08E-06 5.88E-06 13.4 41.5 8 9216 64.51 0.34 9.80E-06 6.60E-06 11.1 32.99 10240 71.68 0.42 1.06E-05 7.39E-06 9.2 26.4 10 11264 78.85 0.51 1.15E-05 8.28E-06 7.7 21.5 11 12288 86.02 0.60 1.24E-05 9.24E-06 6.5 17.6 12 13312 93.18 0.71 1.35E-05 1.03E-05 5.6 14.613 14336 100.35 0.82 1.46E-05 1.14E-05 4.8 12.2

[0144] The data in Table 1 suggests that sensor tiles between having active areas from 50 mm x 50 mm to 64 mm x 64 mm may provide better performance for certain applications. In some cases, simulation results confirm the feasibility of achieving frame rates surpassing 30 fps with 2x2 binning and up to 9216 rows of pixels.

[0145] Fig. 13 shows the simulated complete pixel chain in direct mode demonstrating high (99.99%) linearity in pixel response over the full output range of 2 V. At the testbench level, acquisitions were performed using the sequencing defined in FIG. 12A and for a limited FOV of 10 x 10 pixels. By moving the limited FOV around the pixel array, the entire design may be validated.

[0146] FIG. 14 shows the simulation results of electrical current provided to 256 pixel columns (e.g., in one or more sensor tiles) indicating power consumption by the corresponding readout circuits during different operational phases of the readout circuit depicted by the control signals SH_SIG and SH_RST. In some cases, during a column readout in direct mode, either SH RST or SH SIG, the consumed power can be 33 mW for a block of 256 columns or 128 pW / col, e.g., for a worst-case scenario. Simulation results are shown in FIG. 14. During idle time, the power is reduced to 16.6 mW or 64 pW / column. The performance of the column output amplifier was also evaluated resulting in a phase margin greater than 45°, an open loop gain exceeding 40 dB, a rise and fall time less than 15 ns, a noise level below 200 pV, and idle current less than 1 mA.

[0147] FIG. 15 shows the output buffer waveforms for pixels originating at the 0,0 and max X,Y positions in a sensor tile, showing a settling time of 20 ns for readout across the array.

[0148] Noise simulations were also performed including thermal, kTC, and aliasing and saw low noise performance for both electron and hole integration modes. In direct and photodiode modes, the maximum noise registered was 163.8 e- and 83.3 e- respectively.

[0149] Table 2 summarizes the performance parameters of full well, gain, and noise of an individual pixel for both direct and indirect modes. Noise simulations are performed for the complete pixel chain including thermal, kTC, and aliasing noise.Table 2Parameter Minimum Tvpical Maximum Full well (direct mode) |ke~'| 452.7 559.7 678.1 Full well (indirect mode) [ke~] 154.7 191.3 231.7 Gain (direct anxfe) [pV / e ~] 3.7 4.1 4.5Gain (indirect mode) [pV / e~] 10.8 11,9 13.2Noise (direct mode) [e~] 122.7 142.6 163.8Noise (mdireei. mode) [e~[ 40.6 60.4 83.3

[0150] Table 3. Noise calculations for electron and hole collection modes.Table 3Calculation Target Minimum Value Maximum Value PNoise 535.7 uV rms 898.3 uV rmsPHoise_e- <35 21.43 e- rms 35.93 e- rmsPNoise 553.7 uV rms 603.6 uV rms PHoiseJiole <120 110.7 e- rms 120.7 e- rmsOutRage 2041 2.497

[0151] Table 4. Readout IC Performance Calculations. Calculated values for the analog circuit.Table 4Calculation Target Minimum Value Maximum Value PM >45 45.07 Degree 70.73 Degreegain Ik >40 45.99 dB 46.01 dBGainBwP > 80 M 77.4 MHz 124.6 MHzRise < 20 n 10.55 ns 14.76 nsFall < 20 n 12.93 ns 15.6 nsCalculation Target Minimum Value Maximum ValueNoise < 200 u 119.9 uV 193.2 uVIdle_cur < 1 m 633.5 uA 743.5 uApeak_cur > 500 u 886.6 uA 5.358 mAmax_drive > 500 u 109.4 u 4.271 m

[0152] Some of the simulation results validate the robustness and scalability of the pixel architecture described above for fabricating large-area, high resolution flat panel imagers supporting both direct X-ray photoconductor hole / electron and in-direct X-ray to VIS -NIR electron detection modes, hi some cases, the sensor panels fabricated by stitching the sensor panels described above can meet requirements for noise, charge-to-voltage conversion gain, and high frame rate while maintaining modest power dissipation and acceptable environmental operating margins. In some cases, the RIOC can support frame rates exceeding 30 fps for vertical dimensions of up to 9216 rows when 2x2 binning is enabled. Power simulations show efficient column-level readout. In some cases, dynamic power consumption can be lower than 128 pW / col and idle power can be 64 pW / col or lower. The output buffer allows rapid signal handling with a settling time of less than 20 ns, noise below 200 pV, phase margin exceeding 45°, and open-loop gain greater than 40 dB. In some cases, the column output amplifier may consume less than 1 mA of quiescent current, which can be suitable for low-power imaging arrays.

[0153] In some cases, sensor operation in direct hole integration mode, the pixel chain may exhibit a wide output swing of 2 V with high linearity across the dynamic range. The full well capacity can reach to 678.1 ke . while the input-referred noise may range from 122.7 to 163.8 e", which can yield a practical dynamic range greater than or equal to 70 dB. The charge conversion gain in this mode may have an average around 4.1 pV / e", which can be suitable for large signals (e.g., typical in a-Se detectors) with large dynamic range. In some case, operation in indirect electron integration mode, the interaction capacitor (e.g., Cl 320) may be designed to allow for greater charge-to-voltage gain, e.g., greater than or equal to 11.9 pV / e". In some cases, the noise floor may be low, ranging from 40.6 to 83.3 e", allowing better signal-to-noise contrast under low-signal or photon-limited conditions.

[0154] FIG. 16A is a schematic diagram illustrating an example imaging system 1600 comprising one or more of the sensor pixels, sensor tiles, and sensor panels described above. In some embodiments, the imaging system 1600 may comprise one or more featuresdescribed above with respect to the imaging system 800. Tn some embodiments, imaging system 1600 may comprise a sensor panel 1602, a main board 1608 (e.g., a mother board) and one or more intermediate circuit modules 1606-1, 1606-2, electrically connected between the sensor panel 1602 and the main board 1608. In some embodiments, the intermediate circuit modules 1606-1... 1606-N may receive analog sensor signals from the sensor panel 1602, generate one or more digital signals using the analog sensor signals, and provide the digital data signals to the main board 1608. The main board 1608 may process the digital signals to generate an image signal that can be provided to a computing system 1620 and displayed by a display of the computing system 1620 or a display connected to the computing system 1620. In some embodiments, an intermediate circuit module may be electrically connected to one or both the main board 1608 and the sensor panel 1602 by ribbon cables and connectors (e.g., flat flexible cable). In some embodiments, an intermediate circuit module may be electrically connected to one or both the main board 1608 and the sensor panel 1602 via a solder bond. In some embodiments, a shielding plate 1603 may be positioned between the sensor panel 1602 and the main board 1608 to protect the main board 1608 from high energy or ionizing radiation incident on the sensor panel. In some examples, the sensor panel may be mounted or otherwise mechanically connected to the shielding plate 1603. In some cases, the sensor panel 1602 can be a tiled sensor panel comprising a plurality of sensor tiles stitched together (e.g., similar to the sensor panels shown in FIGS. 6A and 6B).

[0155] In some embodiments, the sensor panel 1602, the main board 1608 (e.g., a motherboard), and the intermediate circuit modules 1606-1 and 1606-2 may be housed within an enclosure 1601. In some embodiments, the enclosure may be formed from a material, or coated with a layer, configured to absorb ionizing electromagnetic radiation, thereby protecting the components of the imaging system contained therein from such radiation. In some embodiments, a face or panel of the enclosure 1601, which is positioned to face the sensor panel 1602, may include a window 1611 configured to permit transmission of ionizing electromagnetic radiation, thereby allowing such radiation to illuminate the sensor panel (e.g., the sensitive layer of the sensor plane). In certain cases, the window 1611 may additionally be configured to transmit non-ionizing electromagnetic radiation (e.g., visible or infrared light) toward the sensor panel 1602. In some embodiments, the window 1611 may comprise a carbon light shield. In some embodiments, the window 1611 may comprise a beryllium. In some embodiments, the window 1611 may comprise a molded X-ray transparent polymers.

[0156] FIG.16B is a schematic diagram illustrating electrical connection between the intermediate circuit modules 1606-1...1606-N, the sensor panel 1602 and the main (mother) board imaging system 1600. Also shown is an individual sensor tile 1615 to an individual intermediate circuit module 1606-1 by a ribbon connector 1604-1. In some cases, the individual sensor tile 1615 may be connected to the main board 1608 by a second ribbon connector 1604-2.Example Embodiments

[0157] Additional embodiments, features, and variations of the disclosure are described in the following clauses:Group 1

[0158] Clause 1. An imaging sensor panel comprising: a plurality of sensor pixels formed on a sensor die, an individual sensor pixel comprising: a local integrated readout circuit (ROIC); and a sensing layer formed over the local readout circuit to form a vertical stack; wherein a vertical separation between the sensing layer and the local ROIC, along a direction perpendicular to a major surface of the sensor die, is 2 microns or smaller; and wherein the ROIC is configured to generate a first sensor signal in response to absorption of a first radiation having a wavelength within a first spectral range, by the sensing layer.

[0159] Clause 2. The imaging sensor panel of clause 1, wherein the first radiation comprises X-ray radiation or gamma radiation.

[0160] Clause 3. The imaging sensor panel of any one of clauses 1-2, wherein the ROIC is configured to generate the first sensor signal using charge carriers generated in the sensing layer in response to absorption of the first radiation.

[0161] Clause 4. The imaging sensor panel of any one of clauses 1-3 wherein the sensing layer comprises amorphous selenium, cesium iodide, or Gadolinium oxysulfide.

[0162] Clause 5. The imaging sensor panel of any one of clauses 1-4, wherein the sensor pixel further comprises a photodiode wherein the ROIC is further configured to generate a second sensor signal in response to absorption of a second radiation having a wavelength within a second spectral range by the photodiode.

[0163] Clause 6. The imaging sensor panel of any one of clauses 1-5, wherein the second spectral range comprises one or both visible and near infrared wavelength ranges.

[0164] Clause 7. The imaging sensor panel of any one of clauses 1-5, wherein the ROIC is configured to operate in a first mode to detect the first radiation or operate in a second mode to detect the second radiation.

[0165] Clause 8. The imaging sensor panel of any one of clauses 1-7, wherein the ROIC is configured to operate in the first mode during a first period to detect the first radiation and operate in the second mode during a second period to detect the second radiation.

[0166] Clause 9. The imaging sensor panel of any one of clauses 1-8, wherein the second radiation is generated by the sensing layer in response to absorption of the first radiation.

[0167] Clause 10. The imaging sensor panel of any one of clauses l-9e, wherein the second radiation comprises Cerenkov photon emission.

[0168] Clause 11. The imaging sensor panel of any one of clauses 1-10, comprising a first sensor tile comprising a first plurality of sensor pixels formed on first senor die and a second sensor tile comprising a second plurality of sensor pixels formed on a second sensor die.

[0169] Clause 12. The imaging sensor panel of any one of clauses 1-11, where the first sensor die further comprises a first electronic circuit.

[0170] Clause 13. The imaging sensor panel of any one of the 1-12, where the first sensor tile further comprises a printed circuit board.Group 2

[0171] Clause 1. A readout pixel comprising: a sensing layer configured to generate charge carriers or photons in response to receiving a first radiation having a wavelength within a first spectral range; a photodiode configured to generate a photocurrent in response to receiving a second radiation having a wavelength within a second spectral range; and a local integrated readout circuit (ROIC) configured to receive charge or current generated by one or both the sensing layer and the photodiode and generate sensor signals using the received charge, wherein the sensing layer is formed over the local readout circuit to form a vertical stack.

[0172] Clause 2. The readout pixel of clause 1, wherein the first spectral range comprises one or more of X-ray radiation, gamma radiation, and ultraviolet radiation.

[0173] Clause 3. The readout pixel of any one of clauses 1-2, wherein the second spectral range comprises one or more of visible light and infrared light.

[0174] Clause 4. The readout pixel of any one of clauses 1-3, wherein sensing layer is configured to generate the second radiation in response to receiving the first radiation.

[0175] Clause 5. The readout pixel of any one of clauses 1-3, wherein the second radiation is incident on and transmitted through the sensing layer.

[0176] Clause 6. The imaging sensor panel of any one of clauses 1-5, wherein the ROIC is configured to operate in a first mode to detect the first radiation or operate in a second mode to detect the second radiation.

[0177] Clause 7. The imaging sensor panel of any one of clauses 1-6, wherein the ROIC is configured to operate in the first mode during a first period to detect the first radiation and operate in the second mode during a second period to detect the second radiation.Group 3

[0178] Clause 1. An imaging sensor panel comprising: a plurality of sensor pixels formed on a substrate, an individual sensor pixel comprising: a local integrated readout circuit comprising a photodetector element; a sensing layer formed over the local integrated readout circuit and electrically connected with the local integrated readout circuit via a conductive contact region formed within a major surface of the local integrated readout circuit, wherein the local integrated readout circuit is configured to generate: a first sensor signal using first electric charge carriers generated in the sensing layer in response to absorption of an ionizing electromagnetic radiation, and a second sensor signal using second electric charge carriers generated by the photodetector element in response to absorption of a non-ionizing electromagnetic radiation.

[0179] Clause 2. The imaging sensor panel of clause 1. wherein the sensing layer comprises a direct-conversion photoconductive sensing layer configured to generate electronhole pairs in response to absorption of the ionizing electromagnetic radiation.

[0180] Clause 3. The imaging sensor panel of any one of clauses 1-2, wherein a vertical separation between the sensing layer and the major surface of the local integrated readout circuit, along a direction perpendicular to the major surface, is less than 2 microns.

[0181] Clause 4. The imaging sensor panel of clause 1, wherein the sensing layer is formed on the major surface of the local integrated readout circuit.

[0182] Clause 5. The imaging sensor panel of any one of clauses 1-4, wherein the ionizing electromagnetic radiation comprises X-ray or gamma-ray.

[0183] Clause 6. The imaging sensor panel of any one of clauses 1-6, wherein the ionizing electromagnetic radiation has a photon energy from 30 eV to 100 keV.

[0184] Clause 7. The imaging sensor panel of clause 1, wherein the non-ionizing electromagnetic radiation has a photon energy from 0.5 eV to 10 eV.

[0185] Clause 8. The imaging sensor panel of any one of clauses 1-7, wherein the nonionizing electromagnetic radiation comprise one or more of visible light, soft-ultraviolet light, and near-infrared light.

[0186] Clause 9. The imaging sensor panel of clause 8, wherein the non-ionizing electromagnetic radiation comprises light having wavelengths within one or both visible and near infrared wavelength ranges.

[0187] Clause 10. The imaging sensor panel of any one of clauses 1-9, wherein the sensing layer comprises amorphous selenium.

[0188] Clause 11. The imaging sensor panel of any one of clauses 1-10, wherein the sensing layer comprises a Halide Perovskite.

[0189] Clause 12. The imaging sensor panel of any one of clauses 1-11, wherein the sensing layer comprises a material configured to generate light wavelength within one or more of ultraviolet, visible, and infrared wavelength ranges, upon absorbing the ionizing electromagnetic radiation.

[0190] Clause 13. The imaging sensor panel of clause 12, wherein the sensing layer comprises cesium iodide (CsI) or gadolinium oxysulfide (GadOx).

[0191] Clause 14. The imaging sensor panel of any one of clauses 1-13, wherein the photodetector element comprises a photodiode.

[0192] Clause 15. The imaging sensor panel of clause 14, wherein the photodiode comprises a pinned photodiode.

[0193] Clause 16. The imaging sensor panel of clause 15, wherein the photodiode comprises an n-doped region formed in a p-doped well integrated with the local integrated readout circuit.

[0194] Clause 17. The imaging sensor panel of any one of clauses 1-16, wherein the photodetector element is configured to receive the non-ionizing electromagnetic radiation from a medium above the sensing layer via the sensing layer.

[0195] Clause 18. The imaging sensor panel of any one of clauses 1-17, wherein the photodetector element is configured to receive the non-ionizing electromagnetic radiation from a medium above the sensing layer via a through-hole formed in the sensing layer.

[0196] Clause 19. The imaging sensor panel of any one of clauses 1-18, wherein the non-ionizing electromagnetic radiation is generated in the sensing layer in response to interaction between the ionizing electromagnetic radiation and the sensing layer.

[0197] Clause 20. The imaging sensor panel of clause 19, wherein the non-ionizing electromagnetic radiation comprises Cerenkov photon emission.

[0198] Clause 21. The imaging sensor panel of any one of clauses 1-20, wherein the non-ionizing electromagnetic radiation is received via the sensing layer from a source outside of the sensing layer.

[0199] Clause 22. The imaging sensor panel of any one of clauses 1-21, wherein the local integrated readout circuit comprises a capacitor connected to the conductive contact region.

[0200] Clause 23. The imaging sensor panel of clause 22, wherein the capacitor comprises a metal-insulator-metal capacitor.

[0201] Clause 24. The imaging sensor panel of any one of clauses 1-23, wherein the sensing layer is formed over another local integrated readout circuit of the imaging sensor panel and is electrically connected to a second conductive contact region formed within the major surface of the local integrated readout circuit, wherein the conductive contact region is electrically isolated from the second conductive contact region.

[0202] Clause 25. The imaging sensor panel of any one of clauses 1-24, wherein the individual sensor pixel further comprises a top electrode layer vertically separated from the conductive contact region by the sensing layer.

[0203] Clause 26. The imaging sensor panel of clause 25. wherein the first electric charge carriers drift toward the conductive contact region under an electric field established between the top electrode layer and the conductive contact region in the sensing layer.

[0204] Clause 27. The imaging sensor panel of any one of clauses 1-26, wherein the local integrated readout circuit is configured to switch between a first mode that generates the first sensor signal and a second mode that generates the second sensor signal.

[0205] Clause 28. The imaging sensor panel of clause 27, wherein the first sensor signal is generated based on holes collected from the sensing layer.-M-

[0206] Clause 29. The imaging sensor panel of clause 27, wherein the first sensor signal is generated based on electrons collected from the sensing layer.

[0207] Clause 30. The imaging sensor panel of clause 27, wherein the second sensor signal is generated based on one or both electrons and holes collected from the photodetector

[0208] Clause 31. The imaging sensor panel of clause 1, wherein the local integrated readout circuit comprises six transistors.

[0209] Clause 32. The imaging sensor panel of clause 27, wherein the local integrated readout circuit comprises a first mode-transistor and a second mode-transistor configured to be controlled to switch operation of the local integrated readout circuit between the first and second modes.

[0210] Clause 33. The imaging sensor panel of clause 32, wherein the first modetransistor is configured to controllably establish electric connection between a sense node of the local integrated readout circuit and a capacitor connected to the sensing layer.

[0211] Clause 34. The imaging sensor panel of clause 32, wherein the second modetransistor is configured to controllably establish electric connection between a sense node of the local integrated readout circuit and the photodetector element.

[0212] Clause 35. The imaging sensor panel of clause 32, wherein the local integrated readout circuit further comprises a binning transistor, a reset transistor, a source-follower transistor and a row-select transistor.

[0213] Clause 36. The imaging sensor panel of any one of clauses 1-35, wherein the individual sensor pixel comprises a charge blocking layer formed between the sensing layer and the conductive contact region.

[0214] Clause 37. The imaging sensor panel of clause 25, wherein the individual sensor pixel comprises a charge blocking layer formed between the top electrode layer and sensing layer.

[0215] Clause 38. The imaging sensor panel of any one of clauses 1-37, comprising a first sensor tile having a first plurality of sensor pixels electrically connected to a first terminal, and a second sensor tile having a second plurality of sensor pixels electrically connected to a second terminal, wherein the first and second terminals are individually configured to electrically connect the pixels of the respective sensor tiles to one or more electronic circuits.

[0216] Clause 39. The imaging sensor panel of clause 38, wherein each of the first and second sensor tiles includes three connector-free edges, and wherein the first and second sensor tiles are interfaced along a pair of their respective connector-free edges.

[0217] Clause 40. The imaging sensor panel of clause 38, where the first sensor tile further comprises a first electronic circuit configured to receive sensor signals from the first plurality of sensor pixels.

[0218] Clause 41. The imaging sensor panel of clause 38, wherein the first sensor tile further comprises a tile terminal configured to electrically connect the first electronic circuit to another circuit.

[0219] Clause 42. An imaging system comprising: the sensor panel of clause 38; an intermediate circuit module electrically connected to the first and second sensor tiles; and computing system electrically connected to the intermediate circuit module, wherein the intermediate circuit module comprises an analog-to-digital converter.

[0219] Clause 43. The imaging sensor panel of any one of clauses 1-42 wherein the local integrated readout circuit is configured to generate the first sensor signal during a first period and generate the second sensor signal during a second period different from the first period.

[0219] Clause 44. The imaging sensor panel of any one of clauses 1-43 wherein the local integrated readout circuit is configured to generate an output signal based on the first and second sensor signals.

[0220] Clause 45. An imaging pixel comprising a local integrated readout circuit comprising: a conductive contact region electrically in contact with a sensing layer formed over the imaging pixel; a detector element configured to generate a photocurrent in response to receiving a second radiation having a wavelength within a second spectral range via the sensing layer; and wherein the local integrated readout circuit is configured to receive: first electric charge carriers from the sensing layer via the conductive contact region and generate a first sensor signal based on the first electric charge carriers; and second electric charge carriers from the detector element and generate sensor signals using the received charge and generate a second sensor signal based on the second electric charge carriers; and

[0221] Clause 46. The imaging pixel of clause 45, wherein the first charge carriers comprise holes and the second electric charge carriers comprise electrons.

[0222] Clause 47. The imaging pixel of any one of clauses 45-46, wherein the first spectral range comprises one or more of X-ray radiation, gamma radiation, and deep-ultraviolet radiation.

[0223] Clause 48. The imaging pixel of any one of clauses 45-47, wherein the second spectral range comprises one or more of visible and infrared range.

[0224] Clause 49. The imaging pixel of any one of clauses 45-48. wherein the sensing layer is configured to generate the second radiation in response to receiving the first radiation.

[0225] Clause 50. The imaging pixel of any one of clauses 45-49, wherein the local integrated readout circuit is configured to operate in a first mode to detect the first radiation or operate in a second mode to detect the second radiation.

[0226] Clause 51. The imaging pixel of clause 50, wherein the local integrated readout circuit is configured to operate in the first mode during a first period to detect the first radiation and operate in the second mode during a second period to detect the second radiation, wherein the first and second periods are non-overlapping.Terminology

[0227] Although systems and methods of image-based or video-based human recognition are disclosed with reference to preferred embodiments, other embodiments will be apparent to those of ordinary skill in the art from the disclosure herein. Moreover, the embodiments described have been presented by way of example only, and are not intended to limit the scope of the inventions. Rather, a skilled artisan will recognize from the disclosure herein a wide number of alternatives for the exact ordering of the image processing steps. Other arrangements, configurations, and combinations of the embodiments disclosed herein will be apparent to a skilled artisan in view of the disclosure herein and are within the spirit and scope of the inventions as defined by the claims and their equivalents.

[0228] Any combination of features described in these appendices can be implemented in combination with aspects described above. Moreover, any combination of features described in two or more of the appendices can be implemented together. As a non-limiting example, any of the features recited in the summary of certain aspects included in one of the appendices can be combined with any of the features recited in the summary of certain aspects included in one or more of the other appendices, as appropriate.

[0229] Reference to any prior art in this specification is not, and should not be taken as, an acknowledgement or any form of suggestion that the prior art forms part of the common general knowledge in the field of endeavor in any country in the world.

[0230] Where reference is used herein to directional terms such as ‘up’, ‘down’, ‘forward’, ‘rearward’, ‘horizontal’, ‘vertical’ etc., those terms refer to when the apparatus is in a typical in-use position and are used to show and / or describe relative directions or orientations.

[0231] Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise”, “comprising”, and the like, are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense, that is to say, in the sense of “including, but not limited to”.

[0232] The terms “approximately,” “about,” and “substantially” as used herein represent an amount close to the stated amount that still performs a desired function or achieves a desired result. For example, in some embodiments, as the context may permit, the terms “approximately”, “about”, and “substantially” may refer to an amount that is within less than or equal to 10% of, within less than or equal to 5% of, and within less than or equal to 1% of the stated amount.

[0233] The disclosed apparatus and systems may also be said broadly to consist in the parts, elements and features referred to or indicated in the specification of the application, individually or collectively, in any or all combinations of two or more of said parts, elements or features.

[0234] Depending on the embodiment, certain acts, events, or functions of any of the algorithms, methods, or processes described herein can be performed in a different sequence, can be added, merged, or left out altogether (for example, not all described acts or events are necessary for the practice of the algorithms). Moreover, in certain embodiments, acts or events can be performed concurrently, for example, through multi-threaded processing, interrupt processing, or multiple processors or processor cores or on other parallel architectures, rather than sequentially.

[0235] It should be noted that various changes and modifications to the presently preferred embodiments described herein will be apparent to those skilled in the art. Such changes and modifications may be made without departing from the spirit and scope of the disclosed apparatus and systems and without diminishing its attendant advantages. For instance, various components may be repositioned as desired. It is therefore intended that suchchanges and modifications be included within the scope of the disclosed apparatus and systems. Moreover, not all of the features, aspects and advantages are necessarily required to practice the disclosed apparatus and systems.

[0236] Conditional language used herein, such as, among others, “can,” “could,” “might,” “may,” “e.g.,” “for example,” “such as” and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and / or states. Unless the context clearly requires otherwise, throughout the disclosure, the words “comprise,” “comprising,” “include,” “including,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The words “coupled” or connected”, as generally used in this disclosure, refer to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above.” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application.

[0237] Where the context permits, words in this disclosure using the singular or plural number may also include the plural or singular number, respectively. The words “or” in reference to a list of two or more items, is intended to cover all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. All numerical values provided herein are intended to include similar values within a measurement error.

Claims

WHAT TS CLAIMED TS1. An imaging sensor panel comprising:a plurality of sensor pixels formed on a substrate, an individual sensor pixel comprising:a local integrated readout circuit comprising a photodetector element; a sensing layer formed over the local integrated readout circuit and electrically connected with the local integrated readout circuit via a conductive contact region formed within a major surface of the local integrated readout circuit,wherein the local integrated readout circuit is configured to generate:a first sensor signal using first electric charge carriers generated in the sensing layer in response to absorption of an ionizing electromagnetic radiation, anda second sensor signal using second electric charge carriers generated by the photodetector element in response to absorption of a non-ionizing electromagnetic radiation.

2. The imaging sensor panel of claim 1, wherein the sensing layer comprises a direct-conversion photoconductive sensing layer configured to generate electron-hole pairs in response to absorption of the ionizing electromagnetic radiation.

3. The imaging sensor panel of claim 1, wherein a vertical separation between the sensing layer and the major surface of the local integrated readout circuit, along a direction perpendicular to the major surface, is less than 2 microns.

4. The imaging sensor panel of claim 1, wherein the sensing layer is formed on the major surface of the local integrated readout circuit.

5. The imaging sensor panel of claim 1, wherein the ionizing electromagnetic radiation comprises X-ray or gamma-ray.

6. The imaging sensor panel of claim 1, wherein the ionizing electromagnetic radiation has a photon energy from 30 eV to 100 keV.

7. The imaging sensor panel of claim 1, wherein the non-ionizing electromagnetic radiation has a photon energy from 0.5 eV to 10 eV.

8. The imaging sensor panel of claim 1, wherein the non-ionizing electromagnetic radiation comprises one or more of visible light, soft-ultraviolet light, and near- infrared light.

9. The imaging sensor panel of claim 8, wherein the non-ionizing electromagnetic radiation comprises light having wavelengths within one or both visible and near-infrared wavelength ranges.

10. The imaging sensor panel of claim 1, wherein the sensing layer comprises amorphous selenium.

11. The imaging sensor panel of claim 1, wherein the sensing layer comprises a Halide Perovskite.

12. The imaging sensor panel of claim 1, wherein the sensing layer comprises a material configured to generate light wavelength within one or more of ultraviolet, visible, and infrared wavelength ranges, upon absorbing the ionizing electromagnetic radiation.

13. The imaging sensor panel of claim 12, wherein the sensing layer comprises cesium iodide (CsI) or gadolinium oxy sulfide (GadOx).

14. The imaging sensor panel of claim 1, wherein the photodetector element comprises a photodiode.

15. The imaging sensor panel of claim 14, wherein the photodiode comprises a pinned photodiode.

16. The imaging sensor panel of claim 15, wherein the photodiode comprises an n-doped region formed in a p-doped well integrated with the local integrated readout circuit.

17. The imaging sensor panel of claim 1, wherein the photodetector element is configured to receive the non-ionizing electromagnetic radiation from a medium above the sensing layer via the sensing layer.

18. The imaging sensor panel of claim 1, wherein the photodetector element is configured to receive the non-ionizing electromagnetic radiation from a medium above the sensing layer via a through-hole formed in the sensing layer.

19. The imaging sensor panel of claim 1, wherein the non-ionizing electromagnetic radiation is generated in the sensing layer in response to interaction between the ionizing electromagnetic radiation and the sensing layer.

20. The imaging sensor panel of claim 19, wherein the non-ionizing electromagnetic radiation comprises Cerenkov photon emission.

21. The imaging sensor panel of claim 1, wherein the non-ionizing electromagnetic radiation is received via the sensing layer from a source outside of the sensing layer.

22. The imaging sensor panel of claim 1, wherein the local integrated readout circuit comprises a capacitor connected to the conductive contact region.

23. The imaging sensor panel of claim 22, wherein the capacitor comprises a metalinsulator-metal capacitor.

24. The imaging sensor panel of claim 1, wherein the sensing layer is formed over another local integrated readout circuit of the imaging sensor panel and is electrically connected to a second conductive contact region formed within the major surface of the local integrated readout circuit, wherein the conductive contact region is electrically isolated from the second conductive contact region.

25. The imaging sensor panel of claim 1, wherein the individual sensor pixel further comprises a top electrode layer vertically separated from the conductive contact region by the sensing layer.

26. The imaging sensor panel of claim 25, wherein the first electric charge carriers drift toward the conductive contact region under an electric field established between the top electrode layer and the conductive contact region in the sensing layer.

27. The imaging sensor panel of claim 1, wherein the local integrated readout circuit is configured to switch between a first mode that generates the first sensor signal and a second mode that generates the second sensor signal.

28. The imaging sensor panel of claim 27, wherein the first sensor signal is generated based on holes collected from the sensing layer.

29. The imaging sensor panel of claim 27, wherein the first sensor signal is generated based on electrons collected from the sensing layer.

30. The imaging sensor panel of claim 27, wherein the second sensor signal is generated based on one or both electrons and holes collected from the photodetector31. The imaging sensor panel of claim 1, wherein the local integrated readout circuit comprises six transistors.

32. The imaging sensor panel of claim 27, wherein the local integrated readout circuit comprises a first mode-transistor and a second mode-transistor configured to be controlled to switch operation of the local integrated readout circuit between the first and second modes.

33. The imaging sensor panel of claim 32, wherein the first mode-transistor is configured to controllably establish electric connection between a sense node of the local integrated readout circuit and a capacitor connected to the sensing layer.

34. The imaging sensor panel of claim 32, wherein the second mode-transistor is configured to controllably establish electric connection between a sense node of the local integrated readout circuit and the photodetector element.

35. The imaging sensor panel of claim 32, wherein the local integrated readout circuit further comprises a binning transistor, a reset transistor, a source-follower transistor and a row-select transistor.

36. The imaging sensor panel of claim 1, wherein the individual sensor pixel comprises a charge blocking layer formed between the sensing layer and the conductive contact region.

37. The imaging sensor panel of claim 25, wherein the individual sensor pixel comprises a charge blocking layer formed between the top electrode layer and sensing layer.

38. The imaging sensor panel of claim 1, comprising a first sensor tile having a first plurality of sensor pixels electrically connected to a first terminal, and a second sensor tile having a second plurality of sensor pixels electrically connected to a second terminal, wherein the first and second terminals are individually configured to electrically connect the pixels of the respective sensor tiles to one or more electronic circuits.

39. The imaging sensor panel of claim 38, wherein each of the first and second sensor tiles includes three connector-free edges, and wherein the first and second sensor tiles are interfaced along a pair of their respective connector-free edges.

40. The imaging sensor panel of claim 38. where the first sensor tile further comprises a first electronic circuit configured to receive sensor signals from the first plurality of sensor pixels.

41. The imaging sensor panel of claim 38, wherein the first sensor tile further comprises a tile terminal configured to electrically connect the first electronic circuit to another circuit.

42. An imaging system comprising:the sensor panel of claim 38;an intermediate circuit module electrically connected to the first and second sensor tiles; andcomputing system electrically connected to the intermediate circuit module, wherein the intermediate circuit module comprises an analog-to-digital converter.

43. An imaging pixel comprising a local integrated readout circuit comprising:a conductive contact region electrically in contact with a sensing layer formed over the imaging pixel;a detector element configured to generate a photocurrent in response to receiving a second radiation having a wavelength within a second spectral range via the sensing layer; andwherein the local integrated readout circuit is configured to receive:first electric charge carriers from the sensing layer via the conductive contact region and generate a first sensor signal based on the first electric charge carriers; andsecond electric charge carriers from the detector element and generate sensor signals using the received charge and generate a second sensor signal based on the second electric charge carriers; and44. The imaging pixel of claim 43, wherein the first charge carriers comprise holes and the second electric charge carriers comprise electrons.

45. The imaging pixel of claim 43, wherein the first spectral range comprises one or more of X-ray radiation, gamma radiation, and deep-ultraviolet radiation.

46. The imaging pixel of claim 43, wherein the second spectral range comprises one or more of visible and infrared range.

47. The imaging pixel of claim 43, wherein the sensing layer is configured to generate the second radiation in response to receiving the first radiation.

48. The imaging pixel of claim 43, wherein the local integrated readout circuit is configured to operate in a first mode to detect the first radiation or operate in a second mode to detect the second radiation.

49. The imaging pixel of claim 48, wherein the local integrated readout circuit is configured to operate in the first mode during a first period to detect the first radiation and operate in the second mode during a second period to detect the second radiation, wherein the first and second periods are non-overlapping.

Images