Display panel, display apparatus and driving method

Abstract

A display panel (100), a display apparatus (200) and a driving method, which relate to the technical field of display. The display panel (100) comprises: a pixel array (10), which comprises M display sub-regions sequentially arranged along a first direction, wherein M≥3, and M is an integer; N gating circuits (20), which are alternately arranged with the M display sub-regions along the first direction in sequence, wherein N=M-1, the N gating circuits (20) are configured to control, in response to a received control signal, the M display sub-regions to form two display regions, and the number of display sub-regions included in the two display regions is less than or equal to M; and a driving circuit (30), which is electrically connected to the M display sub-regions, wherein the driving circuit (30) is configured to output a first data signal and a second data signal to the two display regions, respectively.

Description

Display panel, display device and driving method Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel, display device, and driving method. Background Technology

[0002] With the increasing trend of entertainment-oriented in-vehicle displays, they often integrate office, entertainment, and leisure functions. As the screen size of in-vehicle displays increases, the number of users is also gradually increasing from a single person to multiple people. Therefore, in order to meet the different usage scenarios and the diverse needs of multiple users, the partitioned driving method of in-vehicle displays has become particularly important. Summary of the Invention

[0003] This disclosure provides a display panel, a display device, and a driving method.

[0004] According to a first aspect, this disclosure provides a display panel, comprising: a pixel array including M display sub-regions arranged sequentially along a first direction, where M ≥ 3 and M is an integer; N gating circuits arranged alternately with the M display sub-regions along the first direction, where N = M-1, the N gating circuits being configured to control the M display sub-regions to form two display areas in response to a received control signal, the number of display sub-regions included in the two display areas being less than or equal to M; and a driving circuit electrically connected to the M display sub-regions, the driving circuit being configured to output a first data signal and a second data signal to the two display areas respectively.

[0005] According to a second aspect, this disclosure provides a display device, including: a display panel provided in the embodiments of this disclosure; and a main control unit configured to output image data to the display panel; wherein the display panel is further configured to display a first data signal and a second data signal obtained based on the image data.

[0006] According to a third aspect, this disclosure provides a driving method, comprising: responding to a received control signal, controlling M display sub-regions included in a pixel array to form two display areas through N gating circuits, wherein the number of display sub-regions included in the two display areas is less than or equal to M, M≥3, M is an integer, and N=M-1; and outputting a first data signal and a second data signal to the two display areas respectively, so as to drive the two display areas to display a first screen and a second screen based on the first data signal and the second data signal respectively; wherein the N gating circuits and the M display sub-regions are arranged alternately in sequence. Attached Figure Description

[0007] Figure 1 shows a schematic diagram of the structure of a display panel according to an embodiment of the present disclosure;

[0008] Figures 2A and 2B show schematic diagrams of the display screen of the display panel according to an embodiment of the present disclosure;

[0009] Figure 3 shows a schematic diagram of the structure of a display panel according to another embodiment of the present disclosure;

[0010] Figure 4 shows a schematic diagram of the structure of a display panel according to another embodiment of the present disclosure;

[0011] Figure 5 shows a schematic diagram of the structure of a display panel according to another embodiment of the present disclosure;

[0012] Figure 6 shows a schematic diagram of the structure of a display panel according to another embodiment of the present disclosure;

[0013] Figure 7 shows a schematic diagram of the structure of a scanning unit according to an embodiment of the present disclosure;

[0014] Figure 8 shows a timing diagram of the drive signals according to an embodiment of the present disclosure;

[0015] Figure 9 shows a schematic diagram of the structure of a display device according to an embodiment of the present disclosure;

[0016] Figure 10 shows a schematic diagram of a display device according to another embodiment of the present disclosure; and

[0017] Figure 11 shows a schematic flowchart of a driving method according to an embodiment of the present disclosure. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. In the following description, some specific embodiments are for descriptive purposes only and should not be construed as limiting this disclosure in any way, but are merely examples of embodiments of this disclosure. Conventional structures or constructions will be omitted where they may cause confusion in understanding this disclosure. It should be noted that the shapes and dimensions of the components in the figures do not reflect actual size and proportion, but are only schematic representations of the contents of the embodiments of this disclosure.

[0019] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning as understood by those skilled in the art. The terms "first," "second," and similar words used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0020] Furthermore, in the description of the embodiments disclosed herein, the terms "connected to" or "linked" can refer to a direct connection between two components, or to a connection between two components via one or more other components, wherein the connection method is electrical connection or electrical coupling. Additionally, the two components can also be connected or coupled via wired or wireless means.

[0021] Figure 1 shows a schematic diagram of the structure of a display panel according to an embodiment of the present disclosure.

[0022] As shown in Figure 1, the display panel 100 includes a pixel array 10, N gating circuits 20 and a driving circuit 30.

[0023] In this embodiment of the disclosure, the pixel array 10 includes M display sub-regions 1_1, 1_2, ..., 1_M-1, 1_M arranged sequentially along the first direction D1, where M ≥ 3 and M is an integer.

[0024] For example, pixel array 10 includes multiple pixel units that can be arranged in an array, wherein a row of pixel units includes multiple pixel units arranged along a first direction D1 or a third direction D3, and a column of pixel units includes multiple pixel units arranged along a second direction D2. For example, a pixel unit can be a pixel, and each pixel includes multiple light-emitting units. After the light-emitting elements in pixel array 10 are lit, display panel 100 displays an image. For example, display panel 100 can be an active matrix organic light-emitting diode (AMOLED) panel, and the light-emitting element is an OLED.

[0025] Each display sub-area may include multiple columns of pixel units. The number of columns of pixel units in each of the M display sub-areas may be equal or unequal. The number of rows of pixel units in the M display sub-areas is the same.

[0026] In this embodiment of the disclosure, the N selection circuits 20 may include selection circuits 2_1, 2_2, ..., 2_N-1, 2_N. The N selection circuits 2_1, 2_2, ..., 2_N-1, 2_N and the M display sub-regions 1_1, 1_2, ..., 1_M-1, 1_M are arranged alternately along the first direction D1, where N = M-1. For example, each selection circuit has a display sub-region adjacent to each other on opposite sides along the first direction D1. The M display sub-regions can be considered to include the first display sub-region 1_1 to the Mth display sub-region 1_M arranged sequentially along the first direction D1, wherein the second display sub-region to the (M-1)th display sub-region has a selection circuit adjacent to each other on opposite sides along the first direction D1.

[0027] For example, M display sub-regions 1_1, 1_2, ..., 1_M-1, 1_M are spaced apart from N gating circuits 20. Understandably, the N gating circuits 20 divide the pixel array 10 into M display sub-regions, such that a gating circuit is provided in the m-th and (m+1)-th display sub-regions, where 1 ≤ m < M. Correspondingly, the N gating circuits can be considered to include gating circuits 2_1 to 2_N arranged sequentially along the first direction D1, where a display sub-region is provided in the n-th and (n+1)-th gating circuits, where 1 ≤ n < N.

[0028] For example, in an embodiment of this disclosure, in response to a received control signal, N gating circuits 20 control M display sub-areas to form two display areas, wherein the number of display sub-areas included in the two display areas is less than or equal to M.

[0029] The gating circuit controls the switching between connected and disconnected states for the two display sub-areas located on either side of the gating circuit. In the connected state, the two display sub-areas on either side of the gating circuit can receive data signals from the same data line or scan signals from the same scan line. In the disconnected state, the two display sub-areas on either side of the gating circuit require data signals from two separate data lines or scan signals from two separate scan lines. In response to the received scan and data signals, the light-emitting elements of the pixel units in the display sub-areas emit light, thereby displaying the image.

[0030] For example, among the N gating circuits 20, one gating circuit controls the two display sub-areas located on both sides to be in a disconnected state, and the remaining N-1 gating circuits all control the two display sub-areas located on both sides to be in a connected state. In this case, the M display sub-areas form two display sub-areas. For example, the nth gating circuit controls the mth display sub-area and the (m+1)th display sub-area to be in a disconnected state, where m=n. The 1st to (n-1)th gating circuits and the (n+1)th to Nth gating circuits all control the two display sub-areas located on both sides of their respective sides to be in a connected state. In this case, the 1st to mth display sub-areas form one display area, and the (m+1)th to Mth display sub-areas form another display area.

[0031] For example, when the gating circuit controls the two display sub-areas located on both sides to be in an open state, the gating circuit can be considered to be in a first state. When the gating circuit controls the two display sub-areas located on both sides to be in a connected state, the gating circuit can be considered to be in a second state. When only one of the N gating circuits is in the first state, the number of display sub-areas included in the two display areas is equal to M. When multiple of the N gating circuits are in the first state, the number of display sub-areas included in the two display areas is less than M.

[0032] For example, the nth selection circuit is in the first state, and the 1st to (n-1)th selection circuits and the (n+1)th to Nth selection circuits are in the second state. At this time, the 1st to mth display sub-area forms a display area, and the (m+1)th to Mth display sub-area forms a display area. The two display areas include M display sub-areas.

[0033] For example, the nth and (n+2)th gating circuits are in the first state, and the 1st to (n-1)th and (n+3)th to (N)th gating circuits are in the second state. At this time, the 1st to (m)th display sub-area form a display area, and the (m+3)th to (M)th display sub-area form a display area. The two display areas include M-2 display sub-areas, where m = n.

[0034] It should be noted that the number of display areas that can be formed by M display sub-regions is related to the number of write start points for data signals or scan signals in the M display sub-regions. A write start point can be the position where a data line writes a data signal or the position where a scan line writes a scan signal. For example, if the display panel 100 has two write start points for data signals, then a display sub-region connected to both write start points can be written with data signals, thus displaying an image. A display sub-region located between two gating circuits in their first state is not connected to any write start point, therefore it cannot be written with data signals and thus does not display an image. The position of the write start point can be related to the gating circuit; for example, for display sub-regions located on either side of a gating circuit, a single write start point can only write the corresponding signal to the display sub-region located on one side.

[0035] In this embodiment of the disclosure, the driving circuit 30 is electrically connected to M display sub-areas 1_1, 1_2, ..., 1_M-1, 1_M, and the driving circuit 30 outputs a first data signal and a second data signal to the two display areas respectively.

[0036] For example, the driving circuit 30 can be a display driver integrated circuit (DDIC), which may include a timing controller, a data driving circuit, and a gate driving circuit. The timing controller drives the data driving circuit to send data signals to the pixel array 10 and drives the gate driving circuit to send scan signals to the pixel array 10, causing the light-emitting elements of the pixel array 10 to emit light. The driving circuit 30 can also be a touch and display driver integration circuit (TDDIC), which can send data circuit signals and scan signals to the pixel array 10 based on the received touch signal indicating a touch command, causing the light-emitting elements of the pixel array 10 to emit light based on the touch command.

[0037] For example, if the multiple display sub-regions included in each of the two display areas are in a sequentially connected state, the driving circuit 30 can provide a first data signal and a second data signal to the multiple display sub-regions included in each of the two display areas respectively.

[0038] For example, multiple display sub-areas belonging to the same display area can have data signals provided by the same data line and scan signals provided by multiple scan lines respectively. When multiple scan signals scan multiple display sub-areas sequentially, a single data line provides data signals sequentially to multiple display sub-areas belonging to the same display area along the first direction D1.

[0039] For example, multiple display sub-regions belonging to the same display area can have their scanning signals provided by the same scan line and their data signals provided by multiple data lines respectively. When the scan signal sequentially scans multiple display sub-regions along the first direction D1, multiple data lines provide data signals to each of the multiple display sub-regions belonging to the same display area.

[0040] In this embodiment, by controlling N gating circuits to switch between a first state and a second state using control signals, the switching between connected and disconnected states of M display sub-regions can be achieved, thus allowing the pixel array 10 to form different display areas. The two display areas can be provided with different data signals by the driving circuit 30, enabling each area to independently display different images, thereby achieving partitioned display. Furthermore, controlling the gating circuits located at different positions to be in the first state can change the size of the display area, thereby meeting different display size requirements.

[0041] The two display areas of the display panel 100 are schematically illustrated with reference to Figures 1, 2A, and 2B. Figures 2A and 2B show schematic diagrams of the display screen of the display panel according to an embodiment of the present disclosure.

[0042] Figure 2A shows the first display area A1 and the second display area A2 of the display panel's display area AA. Figure 2B shows the first display area A3 and the second display area A4 of the display panel's display area AA. The size of the first display area A1 is different from the size of the first display area A3, and the size of the second display area A2 is different from the size of the second display area A4.

[0043] The following is an illustrative example using M=3 and N=2. The pixel array includes three display sub-regions 1_1, 1_2, and 1_3, and two selection circuits, including selection circuits 2_1 and 2_2. The three display sub-regions 1_1, 1_2, and 1_3, and the two selection circuits 2_1 and 2_2 are arranged alternately along a first direction. Display sub-regions 1_1 and 1_2 are located on both sides of selection circuit 2_1, and display sub-regions 1_2 and 1_3 are located on both sides of selection circuit 2_2.

[0044] For example, the display panel has a first display mode and a second display mode.

[0045] In the first display mode, the gating circuit 2_1 is in the second state and the gating circuit 2_2 is in the first state. At this time, the display sub-area 1_1 and the display sub-area 1_2 can form the first display area A1, and the display sub-area 1_3 can form the second display area A2.

[0046] For example, the driving circuit can provide a first data signal to the display sub-area included in the first display area A1, and the driving circuit can provide a second data signal to the display sub-area included in the second display area A2. The first display area A1 and the second display area A2 can be used to display different display images respectively, thereby realizing partitioned display.

[0047] In this embodiment of the disclosure, the first data signal is used to drive the first display area A1 to refresh the screen at a first display frequency, and the second data signal is used to drive the second display area A2 to refresh the screen at a second display frequency.

[0048] The first display frequency and the second display frequency can be the same or different. For example, the first display frequency can be 120Hz, and the second display frequency can be 60Hz. In this case, the display screen of the first display area A1 can be refreshed at 120Hz, and the display screen of the second display area A2 can be refreshed at 60Hz, thereby realizing the zoned frequency conversion display of the display panel.

[0049] In the second display mode, the gating circuit 2_1 is in the first state and the gating circuit 2_2 is in the second state. At this time, the display sub-area 1_1 can form the first display area A3, and the display sub-area 1_2 and the display sub-area 1_3 can form the second display area A4.

[0050] For example, the driving circuit can provide a first data signal to the display sub-area included in the first display area A3, and the driving circuit can provide a second data signal to the display sub-area included in the second display area A4. The first display area A3 and the second display area A4 can be used to display different display images respectively, thereby realizing partitioned display. In addition, the display images of the first display area A3 and the second display area A4 can also be refreshed at different display frequencies.

[0051] In this embodiment of the disclosure, during the display process of the display panel, the display mode of the display panel can be switched from a first display mode to a second display mode, or from a second display mode to a first display mode, thereby changing the display ratio of the partitioned display of the display panel.

[0052] For example, the second display area A2 formed by display sub-area 1_3 can be a 3:2 display screen, and the second display area A4 formed by display sub-area 1_2 and display sub-area 1_3 can be a 16:9 display screen. By changing the state of the two gating circuits, the display ratio of the display area can be changed to meet different user display needs.

[0053] In some embodiments, during the process of the gating circuit located between two display areas switching from an open state to an open state, the driving circuit controls the initialization of the first data signal and the second data signal.

[0054] For example, during the process of the display panel switching from the first display mode to the second display mode, in response to the gating circuit 2_2 located between the first display area A1 and the second display area A2 switching from an open state to an open state, the drive circuit controls the initialization of the first data signal and the second data signal. During the process of the gating circuit 2_2 switching from an open state to an open state, the gating circuit 2_1 also switches from an open state to an open state, and the three display sub-areas form the first display area A3 and the second display area A4.

[0055] The start time of the data signal initialization process can be earlier than the time when the gating circuit 2_2 switches from the disconnected state to the connected state, and earlier than the time when the gating circuit 2_1 also switches from the connected state to the disconnected state. The end time of the data signal initialization process can be later than the time when the gating circuit 2_2 switches from the disconnected state to the connected state, and later than the time when the gating circuit 2_1 also switches from the connected state to the disconnected state.

[0056] In this embodiment, the initialization process includes resetting the data voltage of the first data signal and the data voltage of the second data signal, so that the first display area A1 no longer displays an image based on the first data signal, and the second display area A1 no longer displays an image based on the second data signal. After initialization, the driving circuit provides new first data signals and new second data signals to the first display area A3 and the second display area A4, respectively.

[0057] For example, the initialization process may include setting the data voltages of both the first and second data signals to the data voltages corresponding to a black screen. In this case, the display panel displays a black screen. The initialization process may also include setting the data lines transmitting the first and second data signals to a high-impedance state (Hi-Z). In this case, the display panel receives the data signal, but the display screen does not refresh.

[0058] For example, the initialization process could involve controlling the data line to output a black screen and then setting it to a high-impedance state. After initializing the data signals transmitted on the data line, new first data signals and new second data signals are then provided via the data line.

[0059] In this embodiment of the disclosure, when the display mode of the display panel changes, the boundary line between the first display area and the second display area will change. By initializing the first data signal and the second data signal, the display screen of the display panel can be initialized, thereby avoiding display abnormalities due to changes in the boundary line between the two display areas.

[0060] Figure 3 shows a schematic diagram of the structure of a display panel according to another embodiment of the present disclosure.

[0061] As shown in Figure 3, the driving circuit 30 is electrically connected to M display sub-areas 1_1, 1_2, ..., 1_M-1, 1_M and N gating circuits 2_1, 2_2, ..., 2_N-1, 2_N via multiple data lines DL_1, ..., DL_P. The driving circuit 30 is also electrically connected to the N gating circuits 2_1, 2_2, ..., 2_N-1, 2_N via N signal lines SL_1, ..., SL_N.

[0062] In this embodiment of the disclosure, multiple data lines are arranged along a second direction D2 that intersects with the first direction D1, and extend along the first direction D1. For example, the first direction D1 is perpendicular to the second direction D2. Pixel rows in the pixel array 10 include multiple pixel units arranged along the first direction D1, so each data line can be electrically connected to the multiple pixel units included in a pixel row in the pixel array 10.

[0063] In this embodiment of the disclosure, each data line is electrically connected sequentially to the M display sub-regions 1_1, 1_2, ..., 1_M-1, 1_M and the N gating circuits 2_1, 2_2, ..., 2_N-1, 2_N, based on the arrangement of M display sub-regions 1_1, 1_2, ..., 1_M-1, 1_M and the N gating circuits 2_1, 2_2, ..., 2_N-1, 2_N. The M display sub-regions 1_1, 1_2, ..., 1_M-1, 1_M and the N gating circuits 2_1, 2_2, ..., 2_N-1, 2_N are arranged alternately in sequence, so the data line is alternately connected to the M display sub-regions 1_1, 1_2, ..., 1_M-1, 1_M and the N gating circuits 2_1, 2_2, ..., 2_N-1, 2_N in sequence. For example, the data cable is connected in sequence to display sub-area 1_1, gating circuit 2_1, display sub-area 1_2, gating circuit 2_2, ..., gating circuit 2_N-1, display sub-area 1_M-1, gating circuit 2_N, display sub-area 1_M.

[0064] In this embodiment of the disclosure, the number of multiple data lines can be the same as the number of pixel rows included in the pixel array 10. For example, the pixel array 10 includes P pixel rows, and multiple data lines DL_1, ... DL_P are electrically connected to the P pixel rows respectively. The driving circuit 30 provides data signals to the P pixel rows respectively via the P data lines.

[0065] In this embodiment, the driving circuit 30 provides control signals to N gating circuits via signal lines SL_1, ... SL_N. The gating circuits can control the transmission state of data signals on the data lines based on the received control signals. For example, the control signal controls the first gating circuit 2_1 to be in a second state. In this state, the first display sub-area 1_1 and the second display sub-area 1_2 are connected via a data line, and the first display sub-area 1_1 and the second display sub-area 1_2 belong to the same display area. The driving circuit 30 can then provide first data signals to the first display sub-area 1_1 and the second display sub-area 1_2 sequentially via this data line. Alternatively, the control signal controls the first gating circuit 2_1 to be in a first state. In this state, the data line connecting the first display sub-area 1_1 and the second display sub-area 1_2 is in an open-circuit state, and two sub-lines electrically connected to the first display sub-area 1_1 and the second display sub-area 1_2 can be formed respectively. The first display sub-area 1_1 and the second display sub-area 1_2 belong to different display areas. The driving circuit 30 can provide the first data signal and the second data signal to the first display sub-area 1_1 and the second display sub-area 1_2 respectively via two sub-lines.

[0066] In some embodiments, the driving circuit 30 outputs a first data signal to M display sub-regions along a first direction D1, and outputs a second data signal to the M display sub-regions along a third direction D3 opposite to the first direction D1. For example, the first direction D1 and the third direction D3 can be 180 degrees apart. The driving circuit 30 can provide the first data signal and the second data signal to the M display sub-regions, starting from both ends of the pixel row in the pixel array 10 and moving towards the middle.

[0067] In this embodiment of the disclosure, under the control of N control signals from N signal lines, at least one of the N gating circuits is in an open state. The gating circuit in the open state is used to block the transmission of the first data signal along the first direction D1 and to block the transmission of the second data signal along the third direction D3.

[0068] In this embodiment of the disclosure, the gate circuit in the disconnected state can block the transmission path of the first data signal and the second data signal, thereby preventing the first data signal and the second data signal from being written into the same pixel unit.

[0069] For example, when only the nth gating circuit is in the off state among the N gating circuits, the nth gating circuit can block the transmission of the first data signal along the first direction D1 to the (m+1)th display sub-area, and block the transmission of the second data signal along the third direction D3 to the mth display sub-area. At this time, the 1st to the mth display sub-area form a display area, and the (m+1)th to the Mth display sub-area form a display area, where m = n. The driving circuit 30 can sequentially output the first data signal along the first direction D1 to the 1st to the mth display sub-area via the data line, and sequentially output the second data signal along the third direction D3 to the Mth to the (m+1)th display sub-area via the data line.

[0070] For example, when the nth and (n+2th)th gating circuits in the N gating circuits are in an open state, the nth gating circuit can block the transmission of the first data signal along the first direction D1 to the (m+1th)th display sub-area, and the (n+2th)th gating circuit can block the transmission of the second data signal along the third direction D3 to the (m+2th)th display sub-area. At this time, the first to the mth display sub-areas form a display area, and the (m+3)th to the Mth display sub-areas form another display area. The driving circuit 30 can sequentially output the first data signal along the first direction D1 to the first to the mth display sub-areas via data lines, and sequentially output the second data signal along the third direction D3 to the Mth to the (m+3th)th display sub-areas via data lines.

[0071] In this embodiment, by controlling N gating circuits to switch between a first state and a second state using control signals, the transmission path of the driving circuit 30 transmitting the first data signal along the first direction D1 and the transmission path of the driving circuit 30 transmitting the second data signal along the third direction D3 can be controlled. This allows the driving circuit 30 to output two data signals to two display areas in different directions. Using the gating circuits in the first state avoids the two data signals being written into the same pixel circuit in different directions, thus preventing display abnormalities.

[0072] Figure 4 shows a schematic diagram of the structure of a display panel according to another embodiment of the present disclosure.

[0073] As shown in Figure 4, the driving circuit 30 includes a first data unit 31 and a second data unit 32.

[0074] In this embodiment, the first data unit 31 is electrically connected to M display sub-regions via multiple data lines DL_1, ... DL_P. The first data unit 31 outputs a first data signal to a first display region in the two display regions via the multiple data lines DL_1, ... DL_P. The second data unit 32 is electrically connected to the M display sub-regions via multiple data lines DL_1, ... DL_P. The second data unit 32 outputs a second data signal to a second display region in the two display regions via the multiple data lines DL_1, ... DL_P.

[0075] In this embodiment of the present disclosure, the first data unit 31 and the second data unit 32 are disposed opposite to each other on both sides of the pixel array 10 along the first direction D1, and the two ends of each data line are electrically connected to the first data unit 31 and the second data unit 32 respectively.

[0076] In this embodiment, since the two ends of the data line are electrically connected to the first data unit 31 and the second data unit 32 respectively, the first data unit 31 can provide a first data signal to M display sub-areas via the data line along a first direction D1, and the first data unit 32 can provide a second data signal to the M display sub-areas via the data line along a third direction D3. In this case, the first data signal and the second data signal can be transmitted simultaneously on a single data line, and the transmission paths of the first data signal and the second data signal are blocked by a gating circuit.

[0077] In this embodiment of the disclosure, the first data unit 31 and the second data unit 32 can transmit different data signals to M display sub-areas via data lines in two directions, respectively. The transmission path of the data signals on the data lines is blocked by the gating circuit to isolate the transmission areas of the first data signal and the second data signal, thereby realizing the partition driving and partition display of the pixel array 10.

[0078] Figure 5 shows a schematic diagram of the structure of a display panel according to another embodiment of the present disclosure.

[0079] As shown in Figure 5, the nth gating circuit among the N gating circuits includes multiple first transistors T1 arranged along the second direction D2, where 1 ≤ n ≤ N, and n is an integer. Each data line includes M data sub-lines, and the mth data sub-line is electrically connected to the mth display sub-area among the M display sub-areas, where 1 ≤ m ≤ M, and m is an integer. The driving circuit 30 may also include a control unit 33.

[0080] In this embodiment of the disclosure, the control terminals of the plurality of first transistors T1 included in the nth gating circuit are all electrically connected to the nth signal line among the N signal lines. The first terminals of the plurality of first transistors T1 are electrically connected to the mth data sub-line of each of the plurality of data lines. The second terminals of the plurality of first transistors T1 are electrically connected to the (m+1)th data sub-line of each of the plurality of data lines, where m = n.

[0081] It should be noted that the source and drain of the switching transistor used in the embodiments of this disclosure are symmetrical, so their source and drain can be interchanged. In the embodiments of this disclosure, according to their function, the gate can be called the control electrode, one of the source and drain can be called the first electrode, and the other of the source and drain can be called the second electrode. In the following examples, an N-type thin-film transistor is used as an example for description. Those skilled in the art will understand that the embodiments of this disclosure can obviously be applied to the case where the switching transistor is a P-type thin-film transistor.

[0082] In this embodiment, the number of signal lines is the same as the number of gating circuits. The control unit 33 is electrically connected to N gating circuits via N signal lines to output control signals to the N gating circuits via the N signal lines. The number of first transistors T1 included in each gating circuit is the same as the number of data lines.

[0083] Each gating circuit includes multiple first transistors T1 whose control electrodes are all electrically connected to the same signal line to receive the same control signal. Therefore, the multiple first transistors T1 in a single gating circuit can be simultaneously in an on state or simultaneously in an off state based on the control signal.

[0084] For example, the first transistor T1 is an N-type transistor. When the control signal output by the control unit 33 is high, the first transistor T1 is in the on state. When the control signal output by the control unit 33 is low, the first transistor T1 is in the off state.

[0085] In this embodiment of the disclosure, the number of first transistors T1 included in each gating circuit is the same as the number of data lines. Each data line can be electrically connected to one of the first transistors T1 in the multiple gating circuits. For example, data line DL_1 can be electrically connected to the pixel units in the first pixel rows of each of the M display sub-regions and the first first transistor T1 in the N gating circuits. The first transistor T1 connected to data line DL_1 is used to connect or disconnect the pixel units in the first pixel rows of the M display sub-regions.

[0086] In this embodiment of the disclosure, the m-th data sub-line of data line DL_1 is electrically connected to the m-th display sub-area, and the (m+1)-th data sub-line of data line DL_1 is electrically connected to the (m+1)-th display sub-area. The first terminal of the first transistor T1 in the n-th gating circuit is electrically connected to the m-th data sub-line of data line DL_1, and the second terminal of the first transistor T1 is electrically connected to the (m+1)-th data sub-line of data line DL_1, where m = n.

[0087] When the first transistor T1 is in the ON state, its first electrode is connected to the m-th and (m+1)-th data sub-lines of data line DL_1, forming a continuous data line. When the first transistor T1 is in the OFF state, its first electrode is disconnected from the m-th and (m+1)-th data sub-lines of data line DL_1, forming two disconnected data lines.

[0088] In this embodiment of the disclosure, the first end of the first data sub-line L1 of each of the P data lines is electrically connected to the first data unit 31, the second end of the first data sub-line L1 of each of the P data lines is electrically connected to the first electrode of each of the P first transistors T1 in the first gating circuit, and the first end of the second data sub-line L2 of each of the P data lines is electrically connected to the second electrode of each of the P first transistors T1 in the first gating circuit.

[0089] For example, the first data unit 31 can provide a first data signal to the first row pixel circuit in the first display sub-area 1_1 via the first data sub-line L1 in data line DL_1. When the first transistor T1 is in the on state in the first gating circuit, the first data unit 31 can provide a first data signal to the first row pixel circuit in the second display sub-area 1_2 via the first data sub-line L1 and the second data sub-line L2 in data line DL_1. Similarly, when the first transistor T1 is in the on state in the first gating circuit to the nth gating circuit, the first data unit 31 can provide a first data signal to the first row pixel circuit in the mth display sub-area 1_m via the first data sub-line L1 to the mth data sub-line Lm in data line DL_1, where m = n.

[0090] In this embodiment of the disclosure, the second end of the Mth data sub-line LM of each of the P data lines is electrically connected to the second data unit 32, the first end of the Mth data sub-line LM of each of the P data lines is electrically connected to the second pole of the P first transistors T1 in the Nth gating circuit, and the second end of the M-1th data sub-line LM-1 of each of the P data lines is electrically connected to the first pole of the P first transistors T1 in the Nth gating circuit.

[0091] For example, the second data unit 32 can provide a second data signal to the first row pixel circuit in the Mth display sub-area 1_M via the Mth data sub-line LM in data line DL_1. When the first transistor T1 is in the on state in the Nth gating circuit, the second data unit 32 can provide a first data signal to the first row pixel circuit in the M-1th display sub-area 1_M-1 via the Mth data sub-line LM and the (M-1)th data sub-line LM-1 in data line DL_1. Similarly, when the first transistor T1 is in the on state in the Nth to nth gating circuits, the second data unit 32 can provide a second data signal to the first row pixel circuit in the mth display sub-area 1_m via the Mth data sub-line LM to the mth data sub-line Lm in data line DL_1, where M = N+1.

[0092] In this embodiment of the disclosure, under the control of the control signal from the nth signal line, the nth gating circuit controls the mth data sub-line and the (m+1)th data sub-line to be in a disconnected state, or the nth gating circuit controls the mth data sub-line and the (m+1)th data sub-line to be in a connected state.

[0093] For example, when the control signal from the nth signal line is high, the nth gating circuit controls the mth data sub-line and the (m+1)th data sub-line to be in a connected state. When the mth data sub-line and the (m+1)th data sub-line are in a connected state, the mth display sub-area and the (m+1)th display sub-area can be supplied with data line signals by the same data line, allowing the mth display sub-area and the (m+1)th display sub-area to form the same display area.

[0094] For example, when the control signal from the nth signal line is low, the nth gating circuit controls the mth data sub-line and the (m+1)th data sub-line to be disconnected. When the mth data sub-line and the (m+1)th data sub-line are disconnected, the mth display sub-area and the (m+1)th display sub-area can be supplied with data signals by different data lines. Thus, the mth display sub-area and the (m+1)th display sub-area form different display areas.

[0095] In this embodiment of the disclosure, the control unit 33 can drive the control unit in the circuit 30 that has a general-purpose input / output (GPIO) port. The control unit 33 can be electrically connected to the control electrode of the first transistor T1 of each of the N gating circuits via the GPIO port through signal lines SL_1, SL_2, ..., SL_N-1, SL_N.

[0096] In this embodiment of the disclosure, the first transistors included in the N gating circuits can divide the data line into M data sub-lines, and the M data sub-lines are used to provide data signals to M display sub-areas respectively. The N gating circuits can control the connection or disconnection of the M data sub-lines, and control each data line to form two independent sub-lines connected to the first data unit 31 and the second data unit 32 respectively. The two data sub-lines are electrically connected to the display sub-areas in the two display areas respectively, to provide the first data signal and the second data signal, thereby realizing zoned display.

[0097] Figure 6 shows a schematic diagram of the structure of a display panel according to another embodiment of the present disclosure.

[0098] As shown in Figure 6, the driving circuit 30 also includes a first scanning unit 34 and a second scanning unit 35.

[0099] In this embodiment of the present disclosure, the first scanning unit 34 and the second scanning unit 35 are electrically connected to N display sub-regions out of M display sub-regions, respectively. The first scanning unit 34 is electrically connected to the first display sub-region 1_1 to the (M-1)th display sub-region 1_M-1 out of the M display sub-regions, and outputs a first scanning signal to the first display sub-region 1_1 to the (M-1)th display sub-region 1_M-1. The second scanning unit 35 is electrically connected to the second display sub-region 1_2 to the Mth display sub-region 1_M out of the M display sub-regions, and outputs a second scanning signal to the second display sub-region 1_2 to the Mth display sub-region 1_M.

[0100] In this embodiment, the first scanning unit 34 and the second scanning unit 35 can provide scanning signals to the display sub-regions in the two display areas respectively. For example, the first scanning unit 34 can provide a first scanning signal to the first display area, and the second scanning unit 35 can provide a second scanning signal to the second display area. Based on the first and second states of N gating circuits, M display sub-regions can form two display areas. For example, the two display areas can be a first display area and a second display area, where the first display sub-region 1_1 belongs to the first display area, the Mth display sub-region 1_M belongs to the second display area, and the second display sub-region 1_2 and the (M-1)th display sub-region 1_M-1 can belong to either the first or the second display area.

[0101] In this case, when the second display sub-area 1_2 and the (M-1)th display sub-area 1_M-1 belong to the first display area, the first scanning unit 34 provides a first scanning signal to the first display sub-area 1_1 to the (M-1)th display sub-area 1_M-1. When the second display sub-area 1_2 and the (M-1)th display sub-area 1_M-1 belong to the second display area, the second scanning unit 35 provides a second scanning signal to the second display sub-area 1_2 to the (M)th display sub-area 1_M.

[0102] In this embodiment of the present disclosure, the display sub-area where the first data unit 31 provides the first data signal is consistent with the display sub-area where the first scanning unit 34 provides the first scan signal. The display sub-area where the second data unit 32 provides the second data signal is consistent with the display sub-area where the second scanning unit 35 provides the second scan signal.

[0103] For example, when only the nth selection circuit among the N selection circuits is in the off state, the first display sub-region to the mth display sub-region form the first display area, and the (m+1)th display sub-region to the Mth display sub-region form the second display area, where m = n. In this case, the first scanning unit 34 can provide a first scanning signal to the first display sub-region to the mth display sub-region, and the first data unit 31 can provide a first data signal to the first display sub-region to the mth display sub-region. The second scanning unit 35 can provide a second scanning signal to the (m+1)th display sub-region to the Mth display sub-region, and the second data unit 32 can provide a second data signal to the (m+1)th display sub-region to the Mth display sub-region.

[0104] In this embodiment of the present disclosure, the first scanning unit 34 may provide the first scanning signal sequentially from the first display sub-region to the m-th display sub-region, or it may provide the first scanning signal sequentially from the m-th display sub-region to the first display sub-region. The second scanning unit 35 may provide the second scanning signal sequentially from the (m+1)-th display sub-region to the M-th display sub-region, or it may provide the second scanning signal sequentially from the M-th display sub-region to the (m+1)-th display sub-region.

[0105] For example, when the first scanning unit 34 sequentially provides the first scanning signal along the first direction D1 to the first display sub-area and then to the m-th display sub-area, the first data unit 31 also sequentially provides the first data signal along the first direction D1 to the first display sub-area and then to the m-th display sub-area. Similarly, when the first scanning unit 34 sequentially provides the first scanning signal along the third direction D2 to the m-th display sub-area and then to the first display sub-area, the first data unit 31 also sequentially provides the first data signal along the third direction D3 to the m-th display sub-area and then to the first display sub-area.

[0106] In this embodiment, the first scanning unit 34 and the first data unit 31 can form a first driving unit, which drives a display sub-area in the first display area to display an image. The second scanning unit 35 and the second data unit 32 can form a second driving unit, which drives a display sub-area in the second display area to display an image.

[0107] In some embodiments, the driving circuit 30 is electrically connected to M display sub-regions via a plurality of scan lines GL1_1, ..., GL_Q. The plurality of scan lines GL1_1, ..., GL_Q are arranged along a first direction D1 and extend along a second direction D2 that intersects the first direction D1.

[0108] In this embodiment, the number of multiple scan lines GL1_1, ..., GL_Q is the same as the number of pixel columns in the pixel array 10. Each display sub-region may include multiple pixel columns, and each scan unit is electrically connected to multiple pixel columns in the display sub-region via multiple scan lines.

[0109] In this embodiment, the scan line connected to the m-th display sub-region 1_m is connected to the first scan unit 34 and the second scan unit 35, where 1 < m < M. The scan line connected to the first display sub-region 1_1 is connected to the first scan unit 34, and the scan line connected to the M-th display sub-region 1_M is connected to the second scan unit 35.

[0110] In this embodiment of the disclosure, the first display sub-region 1_1 may be provided with a first scan signal solely by the first scanning unit 34, therefore the scan lines connected to the first display sub-region 1_1 may be connected solely to the first scanning unit 34. The Mth display sub-region 1_M may be provided with a second scan signal solely by the second scanning unit 35, therefore the scan lines connected to the Mth display sub-region 1_M are connected to the second scanning unit 35. The second display sub-region 1_2 to the (M-1)th display sub-region 1_M-1 may be provided with a first scan signal by the first scanning unit 34 or a second scan signal by the second scanning unit 35, therefore the scan lines connected to the second display sub-region 1_2 to the (M-1)th display sub-region 1_M-1 may be electrically connected to the first scanning unit 34 and the second scanning unit 35.

[0111] For example, a scan line electrically connected to the second display sub-area 1_2 has a first branch and a second branch. The first branch can be electrically connected to the first scanning unit 34, and the second branch can be electrically connected to the second scanning unit 35. For example, when the second display sub-area 1_2 and the first display sub-area 1_1 belong to the same display area, the second display sub-area 1_2 receives a first scan signal from the first scanning unit 34. When the second display sub-area 1_2 and the first display sub-area 1_1 belong to different display areas, the second display sub-area 1_2 receives a second scan signal from the second scanning unit 35.

[0112] In this embodiment, the scan lines connected to the second display sub-regions 1_2 to the (M-1)th display sub-regions 1_M-1 are shared by the first scanning unit 34 and the second scanning unit 35. Therefore, both the first scanning unit 34 and the second scanning unit 35 can provide scan signals to the second display sub-regions 1_2 to the (M-1)th display sub-regions 1_M-1. Thus, during the partitioned display process controlled by the gating circuit, any one of the second display sub-regions 1_2 to the (M-1)th display sub-regions 1_M-1 can form either a first display area or a second display area. The first scanning unit 34 and the second scanning unit 35 provided in this disclosure can provide scan signals to two display areas with different display ratios, thereby achieving partitioned display.

[0113] Figure 7 shows a schematic diagram of the structure of a scanning unit according to an embodiment of the present disclosure.

[0114] As shown in Figure 7, the first scanning unit 34 includes N first scanning subunits 34_1, 34_2, ..., 34_N. The second scanning unit 35 includes N second scanning subunits 35_1, 35_2, ..., 35_N.

[0115] In this embodiment of the present disclosure, N first scanning sub-units 34_1, 34_2, ..., 34_N output first scanning signals to the first display sub-area to the (M-1)th display sub-area, respectively. N second scanning sub-units 35_1, 35_2, ..., 35_N output second scanning signals to the second display sub-area to the Mth display sub-area, respectively.

[0116] In this embodiment, the nth gating circuit includes at least one of a second transistor T2 and a third transistor T3. The control electrode of the second transistor T2 is electrically connected to the nth signal line among the N signal lines, the first electrode of the second transistor T2 is electrically connected to the nth first scanning sub-unit, and the second electrode of the second transistor T2 is electrically connected to the (n+1)th first scanning sub-unit, where 1 < n < N. The control electrode of the third transistor T3 is electrically connected to the nth signal line, the first electrode of the third transistor T3 is electrically connected to the (n-1)th second scanning sub-unit, and the second electrode of the third transistor is electrically connected to the nth second scanning sub-unit.

[0117] In this embodiment of the present disclosure, the first scanning subunit 34_1 can provide a first scanning signal to the first display sub-area, and the second scanning subunit 35_N can provide a second scanning signal to the Mth display sub-area. The first scanning subunit 34_n can provide a first scanning signal to the nth display sub-area, and the second scanning subunit 35_n-1 can provide a second scanning signal to the nth display sub-area.

[0118] In this embodiment of the disclosure, the first scanning unit 34 may include a plurality of cascaded shift registers, each shift register providing a scanning signal to a column of pixels. Each of the N first scanning subunits 34_1, 34_2, ..., 34_N may include at least two cascaded shift registers. The shift registers between two adjacent first scanning subunits are electrically connected via a second transistor T2, and the cascading relationship between the shift registers of two adjacent first scanning subunits is controlled by the second transistor T2.

[0119] For example, when the second transistor T2 is turned on, the nth first scan subunit is electrically connected to form a cascade relationship with the (n+1)th first scan subunit. The shift register in the (n+1)th first scan subunit that is connected to the nth first scan subunit can be driven by the signal output by the nth first scan subunit, so that the (n+1)th first scan subunit outputs a scan signal.

[0120] For example, when the second transistor T2 is off, the electrical connection between the nth first scan sub-unit and the (n+1)th first scan sub-unit is broken. At this time, the nth first scan sub-unit and the (n+1)th first scan sub-unit are driven by different signals and output scan signals respectively.

[0121] In this embodiment of the disclosure, the second scanning unit 35 may include a plurality of cascaded shift registers, each shift register providing a scanning signal to a column of pixels. Each of the N second scanning subunits 35_1, 35_2, ..., 35_N may include at least two cascaded shift registers. The shift registers between two adjacent second scanning subunits are electrically connected via a third transistor T3, and the cascading relationship between the shift registers of two adjacent second scanning subunits is controlled by the third transistor T3.

[0122] For example, when the third transistor T3 is turned on, the nth second scan sub-unit is electrically connected to form a cascade relationship with the (n+1)th second scan sub-unit. The shift register in the (n+1)th second scan sub-unit that is connected to the nth second scan sub-unit can be driven by the signal output from the nth second scan sub-unit, thereby the (n+1)th second scan sub-unit outputs a scan signal.

[0123] For example, when the third transistor T3 is off, the electrical connection between the nth second scan sub-unit and the (n+1)th second scan sub-unit is broken. At this time, the nth second scan sub-unit and the (n+1)th second scan sub-unit are driven by different signals and output scan signals respectively.

[0124] In this embodiment of the disclosure, since the first scanning unit 34 is used to provide a first scanning signal to the first display sub-area to the (M-1)th display sub-area, and the second scanning unit 35 is used to provide a second scanning signal to the second display sub-area to the (M)th display sub-area, the first gating circuit 2_1 only includes the second transistor T2, the Nth gating circuit 2_N only includes the third transistor T3, and the second gating circuit 2_2 to the (N-1)th gating circuit 2_N-1 all include the second transistor T2 and the third transistor T3.

[0125] In this embodiment of the disclosure, the control electrodes of the first transistor T1, the second transistor T2, and the third transistor T3 included in the same gating circuit are all electrically connected to the same signal line. Therefore, the on-state or off-state of the first transistor T1, the second transistor T2, and the third transistor T3 included in the same gating circuit is consistent.

[0126] For example, when multiple first transistors T1 in the nth gating circuit 2_n are in the off state, the second transistor T2 and the third transistor T3 are also in the off state. At this time, the mth display sub-region is disconnected from the (m+1)th display sub-region, the first scanning sub-unit 34_n is also disconnected from the first scanning sub-unit 34_n+1, and the second scanning sub-unit 35_n-1 is also disconnected from the second scanning sub-unit 35_n, where m = n.

[0127] In this configuration, the first display sub-area to the m-th display sub-area form a first display area. First scanning sub-units 34_1 to 34_n provide first scanning signals to the first display sub-area to the m-th display sub-area, respectively. First data unit 31 provides first data signals to the first display sub-area to the m-th display sub-area. The (m+1)-M-th display sub-area form a second display area. Second scanning sub-units 35_n to 35_N provide second scanning signals to the (m+1)-M-th display sub-area, respectively. Second data unit 32 provides second data signals to the (m+1)-M-th display sub-area. This achieves regional display of the display panel 100.

[0128] In this embodiment, the display sub-region is located in the display area AA of the display panel 100, therefore the first transistor T1 is also located in the display area AA of the display panel 100. The first scanning unit 34 and the second scanning unit 35 are located in the non-display area of ​​the display panel 100, therefore the second transistor T2 and the third transistor T3 are also located in the non-display area of ​​the display panel 100.

[0129] In some embodiments, the driving circuit 30 is electrically connected to N first scanning sub-units via N first start lines GSTV1, and the driving circuit is electrically connected to N second scanning sub-units via N second start lines GSTV2. For example, the timing controller in the driving circuit 30 can be electrically connected to the N first scanning sub-units via the N first start lines GSTV1, and can provide a first start signal to the N first scanning sub-units via the N first start lines GSTV1. The timing controller in the driving circuit 30 can also be electrically connected to the N second scanning sub-units via the N second start lines GSTV2, and can provide a second start signal to the N second scanning sub-units via the N second start lines GSTV2.

[0130] In this embodiment of the present disclosure, under the control of N gating circuits, any one of the N first scanning sub-units can be used as the first-level first scanning sub-unit in a cascaded plurality of first scanning sub-units. Therefore, any one of the N first scanning sub-units requires a first start signal provided by the first start line GSTV1. Under the control of N gating circuits, any one of the N second scanning sub-units can be used as the first-level second scanning sub-unit in a cascaded plurality of second scanning sub-units. Therefore, any one of the N second scanning sub-units requires a second start signal provided by the second start line GSTV2.

[0131] For example, when the nth gating circuit 2_n is in the first state and all remaining gating circuits are in the second state, a cascaded relationship is established between the first scanning subunit 34_1 and the first scanning subunit 34_n, and a cascaded relationship is also established between the second scanning subunit 35_n and the second scanning subunit 35_N, where m = n. In this case, the first start line GSTV1, electrically connected to the first scanning subunit 34_1, provides a first start signal to the first scanning subunit 34_1, or the first start line GSTV1, electrically connected to the first scanning subunit 34_n, provides a first start signal to the first scanning subunit 34_n. In this case, the second start line GSTV2, electrically connected to the second scanning subunit 35_n, provides a second start signal to the second scanning subunit 35_n, or the second start line GSTV2, electrically connected to the second scanning subunit 35_N, provides a second start signal to the second scanning subunit 35_N.

[0132] It should be noted that when the nth gating circuit 2_n is in the first state and the remaining gating circuits are all in the second state, the first scanning sub-unit 34_n+1 to the first scanning sub-unit 34_N are also cascaded, and the second scanning sub-unit 35_1 and the second scanning sub-unit 35_n-1 are also cascaded.

[0133] Since the first scanning subunit 34_1 is used to provide a first scanning signal to the first display sub-area 1_1 in the first display area, a plurality of first scanning subunits that form a cascade relationship with the first scanning subunit 34_1 are used to provide a first scanning signal to the first display area. The first start line GSTV1 does not provide a first start signal to any of the first scanning subunits from the first scanning subunit 34_n+1 to the first scanning subunit 34_N.

[0134] Since the second scanning subunit 35_N is used to provide the second scanning signal to the Mth display sub-area 1_M in the second display area, a plurality of second scanning subunits that are cascaded with the second scanning subunit 35_N are used to provide the second scanning signal to the second display area. The second start line GSTV2 does not provide the second start signal to any of the second scanning subunits 35_1 and 35_n-1.

[0135] For example, when the nth gating circuit 2_n is in the first state and all remaining gating circuits are in the second state, the first start line GSTV1, electrically connected to the first scanning sub-unit 34_n, provides a first start signal to the first scanning sub-unit 34_n, and the second start line GSTV2, electrically connected to the second scanning sub-unit 35_n, provides a second start signal to the second scanning sub-unit 35_n. In this case, the first scanning unit 34 can sequentially scan multiple pixel columns in the first display area along the third direction D3, and the second scanning unit 35 can sequentially scan multiple pixel columns in the second display area along the first direction D1.

[0136] In this embodiment of the present disclosure, under the control of the control signal from the nth signal line, the nth gating circuit controls the nth first scanning subunit and the (n+1)th first scanning subunit to be in a disconnected state, or the nth gating circuit controls the nth first scanning subunit and the (n+1)th first scanning subunit to be in a connected state.

[0137] Under the control of the control signal from the nth signal line, the nth gating circuit controls the (n-1)th second scanning sub-unit to be in a disconnected state with the nth second scanning sub-unit, or the nth gating circuit controls the (n-1)th second scanning sub-unit to be in a connected state with the nth second scanning sub-unit.

[0138] In this embodiment of the present disclosure, when the nth first scanning sub-unit and the (n+1)th first scanning sub-unit are in a connected state, the two display sub-areas connected to the nth first scanning sub-unit and the (n+1)th first scanning sub-unit form the same display area. When the (n-1)th second scanning sub-unit and the nth second scanning sub-unit are in a connected state, the two display sub-areas connected to the (n-1)th second scanning sub-unit and the nth second scanning sub-unit form the same display area.

[0139] For example, when the control signal from the nth signal line is high, the nth gating circuit controls the mth data sub-line and the (m+1)th data sub-line to be in a connected state, and the nth gating circuit also controls the nth first scan sub-unit and the (n+1)th first scan sub-unit to be in a cascaded state. At this time, the mth display sub-area and the (m+1)th display sub-area form the same display area. When the nth first scan sub-unit and the (n+1)th first scan sub-unit are cascaded with the first scan sub-unit 34_1, the nth first scan sub-unit and the (n+1)th first scan sub-unit provide first scan signals to the mth display sub-area and the (m+1)th display sub-area, respectively. The same data line formed by the mth data sub-line and the (m+1)th data sub-line can provide first data signals to the mth display sub-area and the (m+1)th display sub-area.

[0140] For example, when the control signal from the nth signal line is high, the nth gating circuit also controls the (n-1)th second scan sub-unit to be cascaded with the nth second scan sub-unit. At this time, the mth display sub-area and the (m+1)th display sub-area form the same display area. When the (n-1)th and nth second scan sub-units are cascaded with the Nth second scan sub-unit, the (n-1)th and nth second scan sub-units provide second scan signals to the mth and (m+1)th display sub-areas, respectively. The same data line formed by the mth and (m+1)th data sub-lines can provide second data signals to the mth and (m+1)th display sub-areas.

[0141] For example, when the control signal from the nth signal line is low, the nth gating circuit controls the mth data sub-line and the (m+1)th data sub-line to be disconnected. The nth gating circuit also controls the nth first scan sub-unit and the (n+1)th first scan sub-unit to be disconnected. The nth gating circuit also controls the (n-1)th second scan sub-unit and the nth second scan sub-unit to be disconnected.

[0142] In this configuration, the first scanning sub-unit to the nth first scanning sub-unit can be cascaded together, and the mth display sub-area connected to the nth first scanning sub-unit can form a first display area with the first display sub-area to the (m-1)th display sub-area. Similarly, the nth second scanning sub-unit to the Nth second scanning sub-unit can be cascaded together, and the (m+1)th display sub-area connected to the nth second scanning sub-unit can form a second display area with the (m+2)th to the Mth display sub-areas.

[0143] For example, where a cascading relationship can be formed between the first scan subunit and the nth scan subunit, the last stage shift register in the cascaded shift registers in the first scan subunit is cascaded with the first stage shift register in the cascaded shift registers in the second scan subunit. When the last stage shift register in the first scan subunit is the stage preceding the first stage shift register in the second scan subunit, the signal output from the last stage shift register in the first scan subunit can drive the first stage shift register in the second scan subunit to output a scan signal.

[0144] When the first-stage shift register in the first scanning subunit is cascaded with the last-stage shift register in the second scanning subunit, the first-stage shift register in the first scanning subunit is the next stage after the last-stage shift register in the second scanning subunit. In this case, the signal output by the last-stage shift register in the second scanning subunit can drive the first-stage shift register in the first scanning subunit to output a scan signal.

[0145] Figure 8 shows a timing diagram of the driving signals according to an embodiment of the present disclosure. Figure 8 illustrates the timing changes of multiple signals received in the display panel 100. An illustrative example is given with M=3 and N=2. The pixel array includes three display sub-regions 1_1, 1_2, and 1_3, and two gating circuits including gating circuits 2_1 and 2_2. The three display sub-regions 1_1, 1_2, and 1_3 and the two gating circuits 2_1 and 2_2 are arranged alternately along a first direction. Display sub-regions 1_1 and 1_2 are disposed on both sides of gating circuit 2_1, and display sub-regions 1_2 and 1_3 are disposed on both sides of gating circuit 2_2. The display panel has a first display mode mode1 and a second display mode mode2.

[0146] In this embodiment, control signal CS1 is provided to gating circuit 2_1, and control signal CS2 is provided to gating circuit 2_2. First start signal GSTV1 is provided to multiple display sub-areas within the first display area. Clock signals GCK and GCB are provided to the first scanning unit. Scan signal GOUT can be a first scan signal output by the first scanning unit, and data signal SOUT can be a first data signal output by the first data unit.

[0147] As shown in Figure 8, in the first display mode (mode1), control signal CS1 is high and control signal CS2 is low. Selection circuit 2_1 is in the second state and selection circuit 2_2 is in the first state. At this time, display sub-area 1_1 and display sub-area 1_2 can form the first display area A1, and display sub-area 1_3 can form the second display area A2.

[0148] During the transition from the first display mode (mode1) to the second display mode (mode2), control signal CS1 switches from high to low, and control signal CS2 switches from low to high. At this time, the voltage of the data signal SOUT switches to the voltage representing the black frame and enters the high-impedance Hi-Z state. This prevents abnormal display of pixel units located at the boundary between the first and second display areas when the display ratio of the first display area changes.

[0149] Figure 9 shows a schematic diagram of the structure of a display device according to an embodiment of the present disclosure.

[0150] As shown in Figure 9, the display device 200 includes a display panel 100 and a main control unit 201.

[0151] In this embodiment of the disclosure, the main control unit 201 is configured to output image data to the display panel 100. The display panel 100 displays a first data signal and a second data signal obtained based on the image data.

[0152] In this embodiment, the main control unit 201 can be a system-on-chip (SoC). The main control unit 201 can generate image data based on the user's display requirements and segment the image data to obtain first sub-data and second sub-data. The main control unit 201 sends the first and second sub-data to the display panel 100. The driving circuit in the display panel can generate a first data signal and a first scan signal for driving a display sub-area in the first display area based on the first sub-data, and generate a second data signal and a second scan signal for driving a display sub-area in the second display area based on the second sub-data.

[0153] The first display area of ​​the display panel 100 can display the display screen of the first sub-data representation, and the second display area can display the display screen of the second sub-data representation.

[0154] Figure 10 shows a schematic diagram of the structure of a display device according to another embodiment of the present disclosure.

[0155] As shown in Figure 10, the display device 200 includes a display panel 100, a main control unit 201, a serializer / deserializer (SERDES) 202, and a bridge circuit (Bridge IC) 203.

[0156] In this embodiment of the disclosure, the main control unit 201 and the driving circuit of the display panel 100 can be connected via a serializer / deserializer 202 and a bridge circuit 203. The serializer / deserializer 202 and the bridge circuit 203 can serve as relays for long-distance transmission between the main control unit 201 and the driving circuit of the display panel 100.

[0157] For example, the display device 200 can be an in-vehicle display device. During the display process of the in-vehicle display device, the vehicle signal (image data) is sent by the main control unit 201 to the serializer / deserializer 202, and then sent by the serializer / deserializer 202 to the driving circuit of the display panel 100.

[0158] The serializer / deserializer 202 can improve the signal loss problem caused by long-distance signal transmission between the main control unit 201 and the driving circuit of the display panel 100. The bridging circuit 203 can convert the signal from the serializer / deserializer 202 into two sets of signals and send the two sets of signals to the two driving units respectively. For example, if the signal from the serializer / deserializer 202 is an Embedded DisplayPort (eDP) signal, the bridging circuit 203 can convert the eDP signal into two sets of Low-Voltage Differential Signaling (LVDS) signals. The bridging circuit 203 sends the two sets of LVDS to the two driving units respectively to drive the two display areas to display in separate zones.

[0159] Figure 11 shows a schematic flowchart of a driving method according to an embodiment of the present disclosure.

[0160] As shown in Figure 11, the display method includes steps S310 to S320.

[0161] In this embodiment of the disclosure, the driving method can be applied to the display panel 100 described above.

[0162] In operation S310, in response to the received control signal, the pixel array is controlled to form two display areas by N gating circuits, which control the M display sub-regions included in the pixel array.

[0163] In operation S320, a first data signal and a second data signal are output to the two display areas respectively, so as to drive the two display areas to display a first screen and a second screen based on the first data signal and the second data signal respectively.

[0164] In this embodiment of the disclosure, the number of display sub-regions included in the two display areas is less than or equal to M, where M ≥ 3, M is an integer, and N = M - 1. The N gating circuits and the M display sub-regions are arranged alternately in sequence.

[0165] In this embodiment of the disclosure, steps S310 and S320 are similar to the operations performed by the display panel 100 described above, and will not be repeated here.

[0166] In this embodiment of the disclosure, based on the arrangement of M display sub-regions and N gating circuits, the M display sub-regions and N gating circuits are sequentially electrically connected by data lines; the data lines include M data sub-lines, and the m-th data sub-line is electrically connected to the m-th display sub-region among the M display sub-regions. The driving method further includes: in response to a received control signal, controlling the M display sub-regions included in the pixel array to form two display areas through the N gating circuits, including: under the control of the control signal, controlling the m-th data sub-line and the (m+1)-th data sub-line to be in a disconnected state, or controlling the m-th data sub-line and the (m+1)-th data sub-line to be in a connected state.

[0167] In this embodiment of the disclosure, when the m-th data sub-line and the (m+1)-th data sub-line are disconnected, the m-th display sub-area and the (m+1)-th display sub-area form different display areas; when the m-th data sub-line and the (m+1)-th data sub-line are connected, the m-th display sub-area and the (m+1)-th display sub-area form the same display area.

[0168] In this embodiment of the disclosure, the driving method further includes: outputting a first scan signal to the first to the (M-1)th display sub-regions among the M display sub-regions; and outputting a second scan signal to the second to the Mth display sub-regions among the M display sub-regions.

[0169] In this embodiment of the disclosure, outputting a first data signal and a second data signal to two display areas respectively includes: outputting the first data signal to N display sub-areas along a first direction, and outputting the second data signal to the N display sub-areas along a third direction opposite to the first direction.

[0170] In this embodiment of the disclosure, under the control of N control signals, at least one of the N gating circuits is controlled to be in an open state, wherein the gating circuit in the open state is used to block the transmission of the first data signal along the first direction and block the transmission of the second data signal along the third direction.

[0171] The block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, and combinations of blocks in the block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0172] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0173] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A display panel, comprising: A pixel array comprising M display sub-regions arranged sequentially along a first direction, where M ≥ 3 and M is an integer; N gating circuits are arranged alternately with the M display sub-regions along the first direction, where N = M - 1. The N gating circuits are configured to control the M display sub-regions to form two display areas in response to a received control signal. The number of display sub-regions included in the two display areas is less than or equal to M. as well as A driving circuit is electrically connected to the M display sub-areas, and the driving circuit is configured to output a first data signal and a second data signal to the two display areas respectively.

2. The display panel of claim 1, wherein, The driving circuit is electrically connected to the M display sub-areas and the N gating circuits via multiple data lines, and is electrically connected to the N gating circuits via N signal lines respectively; The plurality of data lines are arranged along a second direction intersecting the first direction and extend along the first direction. Each of the plurality of data lines is configured to be electrically connected to the M display sub-areas and the N gating circuits in sequence based on the arrangement of the M display sub-areas and the N gating circuits.

3. The display panel of claim 2, wherein, The driving circuit includes: A first data unit is electrically connected to the M display sub-regions via the plurality of data lines. The first data unit is configured to output the first data signal to a first display region in the two display regions via the plurality of data lines. The second data unit is electrically connected to the M display sub-areas via the plurality of data lines and is configured to output the second data signal to the second display area in the two display areas via the plurality of data lines; The first data unit and the second data unit are disposed opposite each other on both sides of the pixel array along the first direction, and the two ends of each data line are electrically connected to the first data unit and the second data unit, respectively.

4. The display panel according to claim 2, wherein, The nth gating circuit among the N gating circuits includes a plurality of first transistors arranged along the second direction, where 1 ≤ n ≤ N, and n is an integer; Each data line includes M data sub-lines, and the m-th data sub-line is electrically connected to the m-th display sub-area among the M display sub-areas, where 1 ≤ m ≤ M and m is an integer. In this circuit, the control terminals of the plurality of first transistors included in the nth selection circuit are electrically connected to the nth signal line among the N signal lines. The first terminals of the plurality of first transistors are electrically connected to the mth data sub-line of each of the plurality of data lines. The second terminals of the plurality of first transistors are electrically connected to the (m+1)th data sub-line of each of the plurality of data lines, where m = n.

5. The display panel of claim 4, wherein, The nth gating circuit among the N gating circuits is configured as follows: Under the control of the control signal from the nth signal line, the mth data sub-line and the (m+1)th data sub-line are either disconnected or connected. Specifically, when the m-th data sub-line and the (m+1)-th data sub-line are disconnected, the m-th display sub-area and the (m+1)-th display sub-area form different display areas; when the m-th data sub-line and the (m+1)-th data sub-line are connected, the m-th display sub-area and the (m+1)-th display sub-area form the same display area.

6. The display panel of claim 1, wherein, The driving circuit includes: A first scanning unit is electrically connected to the first to the (M-1)th display sub-regions among the M display sub-regions. The first scanning unit is configured to output a first scanning signal to the first to the (M-1)th display sub-regions. The second scanning unit is electrically connected to the second to the Mth display sub-areas among the M display sub-areas, and the second scanning unit is configured to output a second scanning signal to the second to the Mth display sub-areas.

7. The display panel of claim 6, wherein, The driving circuit is electrically connected to the M display sub-areas via multiple scan lines, the multiple scan lines being arranged along the first direction and extending along a second direction intersecting the first direction; Wherein, the scan line connected to the mth display sub-region is connected to the first scan unit and the second scan unit, the scan line connected to the 1st display sub-region is connected to the first scan unit, and the scan line connected to the Mth display sub-region is connected to the second scan unit, 1 < m < M.

8. The display panel according to claim 6, wherein, The first scanning unit includes N first scanning sub-units, and the N first scanning sub-units are configured to output first scanning signals to the first display sub-area to the (M-1)th display sub-area respectively; The second scanning unit includes N second scanning sub-units, which are configured to output second scanning signals to the second display sub-area to the Mth display sub-area, respectively. The nth gating circuit of the N gating circuits includes at least one of the second transistor and the third transistor; Wherein, the control electrode of the second transistor is electrically connected to the nth signal line among the N signal lines, the first electrode of the second transistor is electrically connected to the nth first scanning sub-unit, and the second electrode of the second transistor is electrically connected to the (n+1)th first scanning sub-unit, 1 < n < N; The control electrode of the third transistor is electrically connected to the nth signal line, the first electrode of the third transistor is electrically connected to the (n-1)th second scanning sub-unit, and the second electrode of the third transistor is electrically connected to the nth second scanning sub-unit.

9. The display panel according to claim 8, wherein, The driving circuit is electrically connected to N first scanning sub-units via N first starting lines, and the driving circuit is electrically connected to N second scanning sub-units via N second starting lines.

10. The display panel of claim 8, wherein, The nth gating circuit among the N gating circuits is configured as follows: Under the control of the control signal from the nth signal line, the nth first scanning subunit and the (n+1)th first scanning subunit are controlled to be in a disconnected state, or the nth first scanning subunit and the (n+1)th first scanning subunit are controlled to be in a connected state; as well as Under the control of the control signal from the nth signal line, the (n-1)th second scanning subunit is controlled to be in a disconnected state with the nth second scanning subunit, or the (n-1)th second scanning subunit is controlled to be in a connected state with the nth second scanning subunit; as well as Specifically, when the nth first scanning subunit and the (n+1)th first scanning subunit are in a connected state, the two display sub-areas connected to the nth first scanning subunit and the (n+1)th first scanning subunit form the same display area; when the (n-1)th second scanning subunit and the nth second scanning subunit are in a connected state, the two display sub-areas connected to the (n-1)th second scanning subunit and the nth second scanning subunit form the same display area.

11. The display panel according to claim 1, wherein, The driving circuit is configured to output the first data signal to the N display sub-areas along the first direction, and to output the second data signal to the M display sub-areas along a third direction opposite to the first direction; The N gating circuits are configured to, under the control of N control signals from the M signal lines, control at least one of the N gating circuits to be in an open state, wherein the gating circuit in the open state is used to block the transmission of the first data signal along the first direction and block the transmission of the second data signal along the third direction.

12. The display panel of any of claims 1-11, wherein, The driving circuit is further configured to: During the process of the gating circuit located between the two display areas switching from an open state to an open state, the first data signal and the second data signal are initialized.

13. The display panel according to any one of claims 1-11, wherein, The two display areas include a first display area and a second display area. The first data signal is used to drive the first display area to refresh the screen at a first display frequency, and the second data signal is used to drive the second display area to refresh the screen at a second display frequency.

14. A display device, comprising: The display panel according to any one of claims 1-13; as well as The main control unit is configured to output image data to the display panel; The display panel is further configured to display the first data signal and the second data signal obtained based on the image data.

15. A driving method, comprising: In response to the received control signal, the pixel array is controlled to form two display areas by N gating circuits, which include M display sub-areas. The number of display sub-areas included in the two display areas is less than or equal to M, M≥3, M is an integer, and N=M-1. as well as A first data signal and a second data signal are output to the two display areas respectively, so as to drive the two display areas to display a first screen and a second screen respectively based on the first data signal and the second data signal; The N gating circuits and the M display sub-areas are arranged alternately in sequence.

16. The driving method according to claim 15, wherein Based on the arrangement of the M display sub-areas and the N gating circuits, the M display sub-areas and the N gating circuits are sequentially electrically connected by data lines; the data lines include M data sub-lines, and the m-th data sub-line is electrically connected to the m-th display sub-area among the M display sub-areas; In response to the received control signal, the pixel array, comprising M display sub-regions, is controlled to form two display areas through N gating circuits, including: Under the control of the control signal, the m-th data sub-line and the (m+1)-th data sub-line are either disconnected or connected. Specifically, when the m-th data sub-line and the (m+1)-th data sub-line are disconnected, the m-th display sub-area and the (m+1)-th display sub-area form different display areas; when the m-th data sub-line and the (m+1)-th data sub-line are connected, the m-th display sub-area and the (m+1)-th display sub-area form the same display area.

17. The driving method according to claim 15, further comprising: Output a first scan signal to the first to the (M-1)th display sub-regions among the M display sub-regions; as well as A second scan signal is output to the second to the Mth display sub-areas among the M display sub-areas.

18. The driving method according to claim 15, wherein The step of outputting a first data signal and a second data signal to the two display areas respectively includes: The first data signal is output to the N display sub-areas along a first direction, and the second data signal is output to the N display sub-areas along a third direction opposite to the first direction; Under the control of N control signals, at least one of the N gating circuits is controlled to be in an open state. The gating circuit in the open state is used to block the transmission of the first data signal along the first direction and to block the transmission of the second data signal along the third direction.

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