Pixel driving circuit, display device, and driving method

Abstract

A pixel driving circuit, a display device, and a driving method. The pixel driving circuit comprises: a light-emitting device (LED), a driving transistor (DTFT), a first capacitor (C1), a second capacitor (C2), a connection sub-circuit (10), a first reset sub-circuit (20), and a data writing sub-circuit (30). The first capacitor (C1) is coupled between a control end of the driving transistor (DTFT) and a first node (N1). The second capacitor (C2) is coupled between the first node (N1) and a first power supply end (VDD). The connection sub-circuit (10) is coupled between the first node (N1) and a first end of the driving transistor (DTFT). The first reset sub-circuit (20) is coupled to the first end of the driving transistor (DTFT), and is configured to connect the first end of the driving transistor (DTFT) to a first reset signal end (Vinit1). The pixel driving circuit improves the current stability of the light-emitting device (LED) while eliminating the Vref direct current, thereby reducing the number of transistors and shift register units, and facilitating the layout of high-resolution pixels in the display panel.

Description

A pixel driving circuit, display device and driving method Technical Field

[0001] This disclosure relates to the field of display technology, and provides a pixel driving circuit, a display device, and a driving method. Background Technology

[0002] As display refresh rates increase, the compensation time for the threshold voltage of the driving transistors in the pixel driver circuit becomes increasingly insufficient, potentially leading to image retention and degraded low-grayscale image quality. A separate pixel circuit can separate the data voltage writing and threshold voltage compensation processes, allowing for adequate threshold voltage compensation while maintaining the refresh rate. However, this separate pixel circuit requires more traces in the shift register unit and for DC voltages such as Vint and Vref. Since the luminous current of the light-emitting device in the pixel driver circuit depends on the data voltage and the Vref voltage, the luminous current becomes unstable. Summary of the Invention

[0003] This disclosure provides a pixel driving circuit, a display device, and a driving method to improve the stability of the current of the light-emitting device in the pixel driving circuit.

[0004] The specific technical solution provided in this disclosure is as follows:

[0005] In a first aspect, embodiments of this disclosure provide a pixel driving circuit, including:

[0006] Light-emitting devices;

[0007] The driving transistor is coupled to the light-emitting device;

[0008] The first capacitor is coupled between the control terminal of the driving transistor and the first node;

[0009] The second capacitor is coupled between the first node and the first power supply terminal;

[0010] A connecting sub-circuit, coupled between the first node and the first terminal of the driving transistor, is configured to connect the first node and the first terminal of the driving transistor.

[0011] The first reset sub-circuit is coupled to the first terminal of the driving transistor and is configured to connect the first terminal of the driving transistor and the first reset signal terminal.

[0012] The data writing sub-circuit, coupled to the control terminal of the first node or the driving transistor, is configured to provide the data voltage of the data signal terminal to the control terminal of the first node or the driving transistor in response to the signal at the scan signal terminal.

[0013] In some possible implementations, the connecting sub-circuit includes: a first switching transistor;

[0014] The control terminal of the first switching transistor is coupled to the second reset control signal terminal, the first terminal of the first switching transistor is coupled to the first node, and the second terminal of the first switching transistor is coupled to the first terminal of the driving transistor.

[0015] In some possible implementations, the connecting sub-circuit includes: a connecting signal line;

[0016] The first end of the connecting signal line is coupled to the first node, and the second end of the connecting signal line is coupled to the first end of the driving transistor.

[0017] In some possible implementations, the first reset circuit includes: a second switching transistor;

[0018] The control terminal of the second switching transistor is coupled to the first reset control signal terminal, the first terminal of the second switching transistor is coupled to the first terminal of the driving transistor, and the second terminal of the second switching transistor is coupled to the first reset signal terminal.

[0019] In some possible implementations, the data writing sub-circuit includes: a third switching transistor;

[0020] The control terminal of the third switching transistor is coupled to the scan signal terminal, the first terminal of the third switching transistor is coupled to the data signal terminal, and the second terminal of the third switching transistor is coupled to the first node.

[0021] In some possible implementations, the data writing sub-circuit includes: a fourth switching transistor;

[0022] The control terminal of the fourth switching transistor is coupled to the scan signal terminal, the first terminal of the fourth switching transistor is coupled to the data signal terminal, and the second terminal of the fourth switching transistor is coupled to the control terminal of the driving transistor.

[0023] In some possible implementations, it also includes:

[0024] The first light-emitting control sub-circuit is coupled between the first terminal of the driving transistor and the first power supply terminal, and is configured to connect the first terminal of the driving transistor and the first power supply terminal.

[0025] The first light-emitting control sub-circuit includes: a fifth switching transistor;

[0026] The control terminal of the fifth switching transistor is coupled to the first light-emitting control terminal, the first terminal of the fifth switching transistor is coupled to the first power supply terminal, and the second terminal of the fifth switching transistor is coupled to the first terminal of the driving transistor.

[0027] In some possible implementations, it also includes:

[0028] The second light-emitting control sub-circuit, coupled between the second terminal of the driving transistor and the anode of the light-emitting device, is configured to connect the second terminal of the driving transistor and the anode of the light-emitting device.

[0029] The second light-emitting control sub-circuit includes: a sixth switching transistor;

[0030] The control terminal of the sixth switching transistor is coupled to the second light-emitting control terminal, the first terminal of the sixth switching transistor is coupled to the second terminal of the driving transistor, and the second terminal of the sixth switching transistor is coupled to the anode of the light-emitting device.

[0031] In some possible implementations, it also includes:

[0032] The conduction control sub-circuit is coupled between the control terminal and the second terminal of the driving transistor and is configured to connect the control terminal and the second terminal of the driving transistor.

[0033] In some possible implementations, the turn-on control sub-circuit includes: a seventh switching transistor;

[0034] The control terminal of the seventh switching transistor is coupled to the second reset control signal terminal, the first terminal of the seventh switching transistor is coupled to the control terminal of the driving transistor, and the second terminal of the seventh switching transistor is coupled to the second terminal of the driving transistor.

[0035] In some possible implementations, it also includes:

[0036] The second reset circuit, coupled to the first terminal of the first capacitor and the control terminal of the driving transistor, is configured to connect the second reset signal terminal to the first terminal of the first capacitor and the control terminal of the driving transistor.

[0037] In some possible implementations, the second reset circuit includes: an eighth switching transistor;

[0038] The control terminal of the eighth switching transistor is coupled to the second reset control signal terminal, the first terminal of the eighth switching transistor is coupled to the second reset signal terminal, and the second terminal of the eighth switching transistor is coupled to the first terminal of the first capacitor and the control terminal of the driving transistor.

[0039] In some possible implementations, it also includes:

[0040] The third reset circuit, coupled to the anode of the light-emitting device, is configured to connect the third reset signal terminal to the anode of the light-emitting device;

[0041] The third reset circuit includes: the ninth switching transistor;

[0042] The control terminal of the ninth switching transistor is coupled to the third reset control signal terminal, the first terminal of the ninth switching transistor is coupled to the anode of the light-emitting device, and the second terminal of the ninth switching transistor is coupled to the third reset signal terminal.

[0043] In some possible implementations, it also includes:

[0044] The fourth reset circuit, coupled to the second terminal of the driving transistor, is configured to connect the third reset signal terminal and the second terminal of the driving transistor.

[0045] The fourth reset circuit includes: the tenth switching transistor;

[0046] The control terminal of the tenth switching transistor is coupled to the second reset control signal terminal, the first terminal of the tenth switching transistor is coupled to the second terminal of the driving transistor, and the second terminal of the tenth switching transistor is coupled to the third reset signal terminal.

[0047] In some possible implementations, the second light emission control terminal and the first light emission control signal terminal are the same signal terminal.

[0048] In some possible implementations, the third reset control signal terminal and the first reset control signal terminal are the same signal terminal; or

[0049] The third reset control signal terminal and the second reset control signal terminal are the same signal terminal.

[0050] Secondly, embodiments of this disclosure also provide a display device including the pixel driving circuit of any of the above.

[0051] In some possible implementations, the duration of the effective level of the signal at the second reset control signal terminal in the first display mode is greater than the duration of the effective level of the signal at the second reset control signal terminal in the second display mode; and / or

[0052] In the second display mode, at least two adjacent frames include at least one refresh frame and at least one hold frame. The signal at the scan signal terminal corresponding to the refresh frame is valid when the data voltage is written, while the signal at the scan signal terminal corresponding to the hold frame is invalid. The duration of the effective level of the signal at the second reset control signal terminal corresponding to the refresh frame is equal to or less than the duration of the effective level of the signal at the second reset control signal terminal in the first display mode.

[0053] In the first display mode, the refresh rate of the displayed image is higher than that in the second display mode.

[0054] Thirdly, embodiments of this disclosure also provide a driving method for the pixel driving circuit of any of the above claims, comprising:

[0055] Initialization phase: The first reset sub-circuit responds to the signal of the first reset control signal terminal and provides the signal of the first reset signal terminal to the first terminal of the driving transistor. The connecting sub-circuit responds to the signal of the second reset control signal terminal and connects the first node and the first terminal of the driving transistor. The second reset sub-circuit responds to the signal of the second reset control signal terminal and provides the signal of the second reset signal terminal to the first terminal of the first capacitor and the control terminal of the driving transistor. The third reset sub-circuit responds to the signal of the third reset control signal terminal and provides the signal of the third reset signal terminal to the anode of the light-emitting device.

[0056] Threshold compensation stage: The conduction control subcircuit responds to the signal at the conduction control terminal, connecting the control terminal of the driving transistor to the second terminal of the driving transistor. Simultaneously, the connecting subcircuit responds to the signal at the second reset control signal terminal, connecting the first node and the first terminal of the driving transistor, thus connecting the connecting subcircuit, the driving transistor, and the conduction control subcircuit; or, the connecting subcircuit responds to the signal at the second reset control signal terminal, connecting the first node and the first terminal of the driving transistor, the second light-emitting control subcircuit responds to the signal at the second light-emitting control terminal, connecting the second terminal of the driving transistor and the anode of the light-emitting device, and the third reset subcircuit responds to the signal at the second reset control signal terminal, connecting the third reset signal terminal and the anode of the light-emitting device. The driving transistor remains conducting under the action of the second light-emitting control subcircuit and the third reset subcircuit, thus connecting the connecting subcircuit and the driving transistor; or, the conduction control subcircuit responds to the signal at the conduction control terminal, connecting the control terminal of the driving transistor to the second terminal of the driving transistor, and the connecting subcircuit responds to the signal at the second reset control signal terminal, connecting the first node and the first terminal of the driving transistor. The second light-emitting control subcircuit connects the second terminal of the driving transistor and the anode of the light-emitting device in response to the signal of the second light-emitting control terminal; the third reset subcircuit connects the third reset signal terminal and the anode of the light-emitting device in response to the signal of the second reset control signal terminal; the driving transistor remains on under the action of the second light-emitting control subcircuit and the third reset subcircuit; the connecting subcircuit connects the first node and the first terminal of the driving transistor; the driving transistor and the connecting subcircuit are connected. Alternatively, the fourth reset subcircuit connects the third reset signal terminal and the second terminal of the driving transistor in response to the signal of the second reset control signal terminal; the connecting subcircuit connects the first node and the first terminal of the driving transistor; the driving transistor remains on under the action of the fourth reset subcircuit; the driving transistor and the connecting subcircuit are connected. The second reset subcircuit, in response to the signal of the second reset control signal terminal, provides the signal of the second reset signal terminal to the first terminal of the first capacitor and the control terminal of the driving transistor; the voltage of the first node becomes the difference between the signal of the second reset signal terminal and the threshold voltage.

[0057] Data writing stage: The data writing sub-circuit responds to the signal at the scan signal terminal and provides the data voltage at the data signal terminal to the first node or the control terminal of the driving transistor;

[0058] Light emission stage: In response to the signal at the first light emission control signal terminal, the first light emission control sub-circuit turns on the first power supply terminal and the first terminal of the driving transistor, and in response to the signal at the second light emission control terminal, the second light emission control sub-circuit turns on the second terminal of the driving transistor and the anode of the light emission device.

[0059] The beneficial effects of this disclosure are as follows:

[0060] In summary, this disclosure provides a pixel driving circuit, a display device, and a driving method. The pixel driving circuit includes: a light-emitting device, a driving transistor, a first capacitor, a second capacitor, a connecting sub-circuit, a first reset sub-circuit, and a data writing sub-circuit. The driving transistor is coupled to the light-emitting device. The first capacitor is coupled between the control terminal of the driving transistor and a first node. The second capacitor is coupled between the first node and a first power supply terminal. The connecting sub-circuit is coupled between the first node and a first terminal of the driving transistor and is configured to connect the first node and the first terminal of the driving transistor. The first reset sub-circuit is coupled to the first terminal of the driving transistor and is configured to connect the first terminal of the driving transistor. The data writing sub-circuit is coupled to the control terminal of the first node or driving transistor and is configured to provide the data voltage of the data signal terminal to the control terminal of the first node or driving transistor in response to the signal of the scan signal terminal. The above-mentioned connection sub-circuit and the first reset sub-circuit enable the pixel driving circuit to achieve VRR function without the Vref DC power, effectively improving the current stability of the light-emitting device in the pixel driving circuit. At the same time, it ensures the separate execution of threshold voltage acquisition and data voltage writing, and to a certain extent saves the number of transistors and shift register units, which is beneficial to the layout of high-resolution pixels in the display panel.

[0061] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0062] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0063] Figure 1 is a schematic diagram of the connection of a separate pixel driving circuit in the related technology;

[0064] Figure 2 is a timing diagram of a discrete pixel driving circuit in the related technology;

[0065] Figure 3 is a connection diagram of the first pixel driving circuit in an embodiment of this disclosure;

[0066] Figure 4 is a connection diagram of the second pixel driving circuit in an embodiment of this disclosure;

[0067] Figure 5 is a circuit connection diagram of the first pixel driving circuit in the embodiments of this disclosure;

[0068] Figure 6 is a circuit connection diagram of the second pixel driving circuit in the embodiments of this disclosure;

[0069] Figure 7 is a connection diagram of the third pixel driving circuit in an embodiment of this disclosure;

[0070] Figure 8 is a connection diagram of the fourth pixel driving circuit in the embodiments of this disclosure;

[0071] Figure 9 is a circuit connection diagram of the third pixel driving circuit in the embodiments of this disclosure;

[0072] Figure 10 is a circuit connection diagram of the fourth pixel driving circuit in the embodiments of this disclosure;

[0073] Figure 11 is a connection diagram of the fifth pixel driving circuit in the embodiment of this disclosure;

[0074] Figure 12 is a connection diagram of the sixth pixel driving circuit in the embodiment of this disclosure;

[0075] Figure 13 is a circuit connection diagram of the fifth pixel driving circuit in the embodiments of this disclosure;

[0076] Figure 14 is a circuit connection diagram of the sixth pixel driving circuit in the embodiments of this disclosure;

[0077] Figure 15 is a connection diagram of the seventh pixel driving circuit in the embodiments of this disclosure;

[0078] Figure 16 is a connection diagram of the eighth pixel driving circuit in the embodiments of this disclosure;

[0079] Figure 17 is a circuit connection diagram of the seventh pixel driving circuit in the embodiments of this disclosure;

[0080] Figure 18 is a circuit connection diagram of the eighth pixel driving circuit in the embodiments of this disclosure;

[0081] Figure 19 is a connection diagram of the ninth pixel driving circuit in the embodiments of this disclosure;

[0082] Figure 20 is a connection diagram of the tenth pixel driving circuit in the embodiment of this disclosure;

[0083] Figure 21 is a circuit connection diagram of the ninth pixel driving circuit in the embodiments of this disclosure;

[0084] Figure 22 is a circuit connection diagram of the tenth pixel driving circuit in the embodiments of this disclosure;

[0085] Figure 23 is a connection diagram of the eleventh pixel driving circuit in the embodiment of this disclosure;

[0086] Figure 24 is a connection diagram of the twelfth pixel driving circuit in an embodiment of this disclosure;

[0087] Figure 25 is a circuit connection diagram of the eleventh pixel driving circuit in the embodiments of this disclosure;

[0088] Figure 26 is a circuit connection diagram of the twelfth pixel driving circuit in the embodiments of this disclosure;

[0089] Figure 27 is a circuit connection diagram of the thirteenth pixel driving circuit in this embodiment of the present disclosure;

[0090] Figure 28 is a circuit connection diagram of the fourteenth pixel driving circuit in this embodiment of the present disclosure;

[0091] Figure 29 is a connection diagram of the thirteenth pixel driving circuit in the present disclosure;

[0092] Figure 30 is a circuit connection diagram of the fifteenth pixel driving circuit in the embodiments of this disclosure;

[0093] Figure 31 is a timing diagram of the first pixel driving circuit in an embodiment of this disclosure;

[0094] Figure 32 is a simulation schematic diagram of a pixel driving circuit in an embodiment of this disclosure;

[0095] Figure 33 is a timing diagram of the second pixel driving circuit in an embodiment of this disclosure;

[0096] Figure 34 is a timing diagram of the third pixel driving circuit in the embodiments of this disclosure;

[0097] Figure 35 is a simulation diagram of another pixel driving circuit in an embodiment of this disclosure;

[0098] Figure 36 is a first timing diagram of the fourth pixel driving circuit in the embodiments of this disclosure;

[0099] Figure 37 is a second timing diagram of the fourth pixel driving circuit in the embodiments of this disclosure;

[0100] Figure 38 is a third timing diagram of the fourth pixel driving circuit in the embodiments of this disclosure;

[0101] Figure 39 is a first timing diagram of the fifth pixel driving circuit in the present disclosure;

[0102] Figure 40 is a second timing diagram of the fifth pixel driving circuit in the present disclosure;

[0103] Figure 41 is a third timing diagram of the fifth pixel driving circuit in the embodiments of this disclosure;

[0104] Figure 42 is a schematic flowchart of a pixel driving circuit driving method according to an embodiment of the present disclosure. Detailed Implementation

[0105] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the technical solutions of this disclosure, and not all embodiments. Based on the embodiments recorded in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the technical solutions of this disclosure.

[0106] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in sequences other than those illustrated or described herein.

[0107] In related technologies, as the refresh rate of display panels increases, the compensation time for the threshold voltage of the driving transistors in the pixel driving circuit becomes increasingly insufficient, which can lead to image retention and deterioration of low grayscale image quality in severe cases.

[0108] A separate pixel circuit can separate the data voltage writing process from the threshold voltage compensation process, thus ensuring sufficient compensation of the threshold voltage while maintaining the refresh rate. However, the aforementioned separate pixel circuit requires more traces in the shift register units and DC voltage traces such as Vint and Vref. For example, referring to Figure 1, this pixel driving circuit requires 7 transistors and 5 shift register units, where Reset2(n-1) is the output signal of the previous row shift register Reset2(n), which is detrimental to the pixel layout of high-resolution display panels.

[0109] Furthermore, the luminous current of the light-emitting device in the aforementioned pixel driving circuit depends on the data voltage and the aforementioned Vref voltage, resulting in unstable luminous current. The following describes the operation of the pixel driving circuit in Figure 1 in detail with reference to Figure 2. In timing t1, signal Reset1 is valid, transistor m1 is turned on, and voltage Vinit is supplied to node n1 through the turned-on transistor m1, changing the voltage of node n1 to Vinit. Signal Reset2 is valid, transistor m5 is turned on, and voltage Vref is supplied to node n2 through the turned-on transistor m5, changing the voltage of node n2 to Vref. In timing t2, signal Reset2 remains valid, transistor m5 remains turned on, and voltage Vref is supplied to node n2 through the turned-on transistor m5, maintaining the voltage of node n2 at Vref. Signal Gate2 is valid, transistor m2 is turned on, and transistor m2 and driving transistor m3 form a conducting loop, changing the voltage of node n1 to VDD + Vth. In timing t3, Gate1 is active, transistor m4 is turned on, and the data voltage Vdata is supplied to node n2 via the active transistor m4. The voltage at node n2 becomes Vdata. Due to the effect of capacitor c1, the voltage at node n1 becomes VDD + Vth + Vdata - Vref. In timing t4, EM is active, transistor m6 is turned on, and the first power supply terminal VDD, driving transistor m3, transistor m6, LED, and the second power supply terminal VSS form a conduction loop. The LED emits light, and the emitting current I = k(Vgs - Vth). 2 = k(Vn1-VDD-Vth) 2 =k(VDD+Vth+Vdata-Vref-VDD-Vth) 2 = k(Vdata-Vref) 2 .

[0110] In summary, the light-emitting current of the pixel driving circuit described above depends on the voltages Vdata and Vref, which can lead to the light-emitting current of the light-emitting device becoming unstable due to the Vref voltage.

[0111] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0112] Referring to Figures 3 and 4, a pixel driving circuit proposed in this application embodiment includes: a light-emitting device LED, a driving transistor DTFT, a first capacitor C1, a second capacitor C2, a connecting sub-circuit 10, a first reset sub-circuit 20, and a data writing sub-circuit 30.

[0113] Referring to Figures 5 and 6, the aforementioned driving transistor DTFT is coupled to the light-emitting device LED.

[0114] In the embodiments of this application, the light-emitting device can be any one of OLED, mini LED, micro LED, etc. Here, it is uniformly referred to as LED without any specific limitation.

[0115] Referring to Figures 5 and 6, the first capacitor C1 is coupled between the control terminal of the driving transistor DTFT and the first node N1.

[0116] In this embodiment, the first capacitor C1 is disposed between the control terminal of the driving transistor DTFT and the first node N1. That is, the first end of the first capacitor C1 is electrically connected to the control terminal of the driving transistor DTFT, and the second end of the first capacitor C1 is electrically connected to the first node N1. During implementation, the voltage across the first capacitor C1 will change with the timing, thereby completing operations such as voltage initialization, threshold voltage acquisition, and data voltage writing of the driving transistor DTFT.

[0117] Referring to Figures 5 and 6, the second capacitor C2 is coupled between the first node N1 and the first power supply terminal VDD.

[0118] In this embodiment, the second capacitor C2 is disposed between the first node N1 and the first power supply terminal VDD, that is, the first end of the second capacitor C2 is electrically connected to the first node N1, and the second end of the second capacitor C2 is electrically connected to the first power supply terminal VDD.

[0119] During implementation, referring to Figure 5, when the data writing sub-circuit 30 is electrically connected to the first node N1, the setting of the second capacitor C2 effectively ensures the stability of the voltage of the first node N1; referring to Figure 6, when the data writing sub-circuit 30 is electrically connected to the control terminal of the driving transistor DTFT, when the data voltage is written, the setting of the second capacitor C2 realizes the voltage division effect of the data voltage, thereby ensuring the stability of the driving current.

[0120] Referring to Figures 5 and 6, the aforementioned connecting sub-circuit 10 is coupled between the first node N1 and the first terminal of the driving transistor DTFT, and is configured to connect the first node N1 and the first terminal of the driving transistor DTFT.

[0121] In this embodiment of the application, referring to Figure 5, the first terminal of the connecting sub-circuit 10 is electrically connected to the first node N1, and the second terminal of the connecting sub-circuit 10 is electrically connected to the first terminal of the driving transistor DTFT, i.e., the second node N2. After removing the Vref DC voltage, the stability of the voltage at the second terminal of the first capacitor C1, i.e., the aforementioned first node N1, is guaranteed by the connecting sub-circuit 10. That is, even when the Vref DC voltage is removed in the pixel driving circuit, the setting of the connecting sub-circuit 10 ensures that the function of the pixel driving circuit is not reduced, and the pixel driving circuit still retains the functional requirements such as Variable Refresh Rate (VRR).

[0122] In one embodiment, referring to FIG5, the connecting sub-circuit 10 includes: a first switching transistor T1.

[0123] The control terminal of the first switching transistor T1 is coupled to the second reset control signal terminal Reset2, the first terminal of the first switching transistor T1 is coupled to the first node N1, and the second terminal of the first switching transistor T1 is coupled to the first terminal of the driving transistor DTFT.

[0124] For example, the first switching transistor T1 can be turned on under the control of the valid level of the second reset control signal terminal Reset2, and can be turned off under the control of the invalid level of the second reset control signal terminal Reset2. For example, if the first switching transistor T1 is set as an N-type transistor, then the valid level of the signal at the second reset control signal terminal Reset2 is a high level, and the invalid level of the signal at the second reset control signal terminal Reset2 is a low level. Alternatively, if the first switching transistor T1 is set as a P-type transistor, then the valid level of the signal at the second reset control signal terminal Reset2 is a low level, and the invalid level of the signal at the second reset control signal terminal Reset2 is a high level.

[0125] Referring to Figure 5, the first switching transistor T1 is a P-type transistor. When the signal of the second reset control signal terminal Reset2 is low, the first switching transistor T1 is turned on, and the first node N1 is connected to the first terminal of the driving transistor DTFT through the turned-on first switching transistor T1.

[0126] In another embodiment, referring to FIG6, the connecting sub-circuit 10 includes: a connecting signal line.

[0127] The first end of the connecting signal line is coupled to the first node N1, and the second end of the connecting signal line is coupled to the first end of the driving transistor DTFT.

[0128] The aforementioned connecting signal line is a conductive line connecting the first node N1 and the first end of the driving transistor DTFT, namely the second node N2. This connecting signal line can transmit a voltage signal to the second end of the first capacitor C1, namely the first node N1, thereby keeping the voltage of the first node N1 stable.

[0129] It should be noted that during implementation, the aforementioned connecting sub-circuit 10 needs to be used in conjunction with the first reset sub-circuit 20 to stabilize the voltage of the first node N1. For example, referring to Figure 5, when the connecting sub-circuit 10 includes a first switching transistor T1, the first switching transistor T1 is turned on, and the signal of the first reset signal terminal Vinit1 is provided to the first node N1 via the turned-on first reset sub-circuit 20 and the first switching transistor T1. For example, referring to Figure 6, when the connecting sub-circuit 10 includes a connecting signal line, the signal of the aforementioned first reset signal terminal Vinit1 is provided to the first node N1 via the turned-on first reset sub-circuit 20 and the connecting signal line.

[0130] Referring to Figures 3 and 4, the first reset sub-circuit 20 is coupled to the first terminal of the driving transistor DTFT and is configured to connect the first terminal of the driving transistor DTFT and the first reset signal terminal Vinit1.

[0131] During implementation, when the signal of the first reset control signal terminal Reset1 is valid, the first reset sub-circuit 20 is turned on, and the signal of the first reset signal terminal Vinit1 is provided to the first terminal of the driving transistor DTFT through the first reset sub-circuit 20.

[0132] Referring to Figures 5 and 6, the first reset circuit 20 includes a second switching transistor T2.

[0133] The control terminal of the second switching transistor T2 is coupled to the first reset control signal terminal Reset1, the first terminal of the second switching transistor T2 is coupled to the first terminal of the driving transistor DTFT, and the second terminal of the second switching transistor T2 is coupled to the first reset signal terminal Vinit1.

[0134] For example, the second switching transistor T2 can be turned on under the control of the effective level of the first reset control signal terminal Reset1, and can be turned off under the control of the ineffective level of the first reset control signal terminal Reset1. For example, if the second switching transistor T2 is set as an N-type transistor, then the effective level of the signal at the first reset control signal terminal Reset1 is a high level, and the ineffective level of the signal at the first reset control signal terminal Reset1 is a low level. Alternatively, if the second switching transistor T2 is set as a P-type transistor, then the effective level of the signal at the first reset control signal terminal Reset1 is a low level, and the ineffective level of the signal at the first reset control signal terminal Reset1 is a high level.

[0135] Referring to Figures 5 and 6, the second switching transistor T2 is a P-type transistor. When the signal of the first reset control signal terminal Reset1 is low, the second switching transistor T2 is turned on, and the signal of the first reset signal terminal Vinit1 is provided to the first terminal of the driving transistor DTFT, i.e., the second node N2, through the turned-on second switching transistor T2.

[0136] It should also be noted that the signal at the first reset signal terminal Vinit1 is typically a positive voltage. Furthermore, the signal at the first reset signal terminal Vinit1 not only eliminates the stress effect on the driving transistor DTFT, but also, in conjunction with the connecting sub-circuit, sets the second terminal (i.e., the first node) of the first capacitor before the threshold voltage is acquired. This ensures that the first node of the pixel driving circuit for each sub-pixel in the display panel has a uniform voltage value before threshold compensation, thereby guaranteeing the uniformity of threshold voltage compensation for each sub-pixel in each frame.

[0137] Referring to Figures 3 and 4, the data writing sub-circuit 30 is coupled to the control terminal of the first node N1 or the driving transistor DTFT and is configured to provide the data voltage of the data signal terminal Vdata to the control terminal of the first node N1 or the driving transistor DTFT in response to the signal of the scan signal terminal Gate.

[0138] During implementation, when the signal at the Gate terminal is valid, the data writing sub-circuit 30 is turned on, and the data voltage at the Vdata terminal is provided to the control terminal of the first node N1 or the driving transistor DTFT via the data writing sub-circuit 30.

[0139] Referring to Figure 5, the data writing sub-circuit 30 includes a third switching transistor T3.

[0140] The control terminal of the third switching transistor T3 is coupled to the scan signal terminal Gate, the first terminal of the third switching transistor T3 is coupled to the data signal terminal Vdata, and the second terminal of the third switching transistor T3 is coupled to the first node N1.

[0141] For example, the third switching transistor T3 can be turned on under the control of the effective level of the scan signal terminal Gate, and can be turned off under the control of the ineffective level of the scan signal terminal Gate. For example, if the third switching transistor T3 is set to an N-type transistor, then the effective level of the signal at the scan signal terminal Gate is a high level, and the ineffective level of the signal at the scan signal terminal Gate is a low level. Alternatively, if the third switching transistor T3 is set to a P-type transistor, then the effective level of the signal at the scan signal terminal Gate is a low level, and the ineffective level of the signal at the scan signal terminal Gate is a high level.

[0142] Referring to Figure 5, the third switching transistor T3 is a P-type transistor. When the signal at the scan signal terminal Gate is low, the third switching transistor T3 is turned on, and the data voltage at the data signal terminal Vdata is provided to the first node N1 through the turned-on third switching transistor T3.

[0143] The aforementioned setting of the third switching transistor T3 enables the data voltage at the data signal terminal Vdata to be written to the first node N1. Correspondingly, the voltage at the control terminal of the driving transistor DTFT is the sum of the data voltage and the threshold voltage of the driving transistor DTFT.

[0144] Referring to Figure 6, the data writing sub-circuit 30 includes: a fourth switching transistor T4.

[0145] The control terminal of the fourth switching transistor T4 is coupled to the scan signal terminal Gate, the first terminal of the fourth switching transistor T4 is coupled to the data signal terminal Vdata, and the second terminal of the fourth switching transistor T4 is coupled to the control terminal of the driving transistor DTFT.

[0146] For example, the fourth switching transistor T4 can be turned on under the control of the valid level of the scan signal terminal Gate, and can be turned off under the control of the invalid level of the scan signal terminal Gate. For example, if the fourth switching transistor T4 is set to an N-type transistor, then the valid level of the signal at the scan signal terminal Gate is a high level, and the invalid level of the signal at the scan signal terminal Gate is a low level. Alternatively, if the fourth switching transistor T4 is set to a P-type transistor, then the valid level of the signal at the scan signal terminal Gate is a low level, and the invalid level of the signal at the scan signal terminal Gate is a high level.

[0147] Referring to Figure 6, the fourth switching transistor T4 is a P-type transistor. When the signal at the scan signal terminal Gate is low, the fourth switching transistor T4 is turned on, and the data voltage at the data signal terminal Vdata is provided to the control terminal of the driving transistor DTFT through the turned-on fourth switching transistor T4.

[0148] The aforementioned fourth switching transistor T4 enables the data voltage at the data signal terminal Vdata to be written to the control terminal of the driving transistor DTFT, i.e., the fourth node N4. Correspondingly, the voltage change at the first node N1 is equal to the voltage change at the fourth node N4 multiplied by the ratio of the first capacitor C1 in the circuit formed by the first capacitor C1 and the second capacitor C2, i.e., VN1=Vinit2-Vth+(C1 / (C1+C2))*(Vdata-Vinit2)=(C1 / (C1+C2))*Vdata+(C2 / (C1+C2))*Vinit2-Vth.

[0149] Referring to Figures 7 and 8, the pixel driving circuit further includes a first light emission control sub-circuit 40, which is coupled between the first terminal of the driving transistor DTFT and the first power supply terminal VDD, and is configured to connect the first terminal of the driving transistor DTFT and the first power supply terminal VDD.

[0150] During implementation, when the signal of the first light-emitting control terminal EM1 is valid, the first light-emitting control sub-circuit 40 is turned on, and the first power supply terminal VDD is connected to the first terminal of the driving transistor DTFT through the first light-emitting control sub-circuit 40.

[0151] Referring to Figures 9 and 10, the first light-emitting control sub-circuit 40 includes a fifth switching transistor T5.

[0152] The control terminal of the fifth switching transistor T5 is coupled to the first light-emitting control terminal EM1, the first terminal of the fifth switching transistor T5 is coupled to the first power supply terminal VDD, and the second terminal of the fifth switching transistor T5 is coupled to the first terminal of the driving transistor DTFT.

[0153] For example, the fifth switching transistor T5 can be turned on under the control of the effective level of the first light-emitting control terminal EM1, and can be turned off under the control of the ineffective level of the first light-emitting control terminal EM1. For example, if the fifth switching transistor T5 is set as an N-type transistor, then the effective level of the signal of the first light-emitting control terminal EM1 is a high level, and the ineffective level of the signal of the first light-emitting control terminal EM1 is a low level. Alternatively, if the fifth switching transistor T5 is set as a P-type transistor, then the effective level of the signal of the first light-emitting control terminal EM1 is a low level, and the ineffective level of the signal of the first light-emitting control terminal EM1 is a high level.

[0154] Referring to Figures 9 and 10, the fifth switching transistor T5 is a P-type transistor. When the signal of the first light-emitting control terminal EM1 is low, the fifth switching transistor T5 is turned on, and the first power supply terminal VDD is connected to the first terminal of the driving transistor DTFT through the turned-on fifth switching transistor T5.

[0155] Referring to Figures 11 and 12, the pixel driving circuit described above further includes:

[0156] The second light-emitting control sub-circuit 50 is coupled between the second terminal of the driving transistor DTFT and the anode of the light-emitting device LED, and is configured to connect the second terminal of the driving transistor DTFT and the anode of the light-emitting device LED.

[0157] During implementation, when the signal of the second light-emitting control terminal EM2 is valid, the second light-emitting control sub-circuit 50 is turned on, and the second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED through the second light-emitting control sub-circuit 50.

[0158] Referring to Figures 13 and 14, the second light-emitting control sub-circuit 50 includes a sixth switching transistor T6.

[0159] The control terminal of the sixth switching transistor T6 is coupled to the second light-emitting control terminal EM2, the first terminal of the sixth switching transistor T6 is coupled to the second terminal of the driving transistor DTFT, and the second terminal of the sixth switching transistor T6 is coupled to the anode of the light-emitting device LED.

[0160] For example, the sixth switching transistor T6 can be turned on under the control of the effective level of the second light-emitting control terminal EM2, and can be turned off under the control of the ineffective level of the second light-emitting control terminal EM2. For example, if the sixth switching transistor T6 is set as an N-type transistor, then the effective level of the signal of the second light-emitting control terminal EM2 is a high level, and the ineffective level of the signal of the second light-emitting control terminal EM2 is a low level. Alternatively, if the sixth switching transistor T6 is set as a P-type transistor, then the effective level of the signal of the second light-emitting control terminal EM2 is a low level, and the ineffective level of the signal of the second light-emitting control terminal EM2 is a high level.

[0161] Referring to Figures 13 and 14, the sixth switching transistor T6 is a P-type transistor. When the signal of the second light-emitting control terminal EM2 is low, the sixth switching transistor T6 is turned on, and the second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED through the turned-on sixth switching transistor T6.

[0162] It should be noted that in some embodiments, the first light-emitting control terminal EM1 and the second light-emitting control terminal EM2 are the same signal terminal, thereby saving the use of a shift register.

[0163] Referring to Figures 15 and 16, the pixel driving circuit described above further includes:

[0164] The conduction control sub-circuit 60 is coupled between the control terminal and the second terminal of the driving transistor DTFT and is configured to connect the control terminal and the second terminal of the driving transistor DTFT.

[0165] During implementation, when the signal of the second reset control signal terminal Reset2 is valid, the conduction control sub-circuit 60 is turned on, and the control terminal of the driving transistor DTFT is connected to the second terminal of the driving transistor DTFT through the conduction control sub-circuit 60.

[0166] Referring to Figures 17 and 18, the conduction control sub-circuit 60 includes a seventh switching transistor T7.

[0167] The control terminal of the seventh switching transistor T7 is coupled to the second reset control signal terminal Reset2. The first terminal of the seventh switching transistor T7 is coupled to the control terminal of the driving transistor DTFT. The second terminal of the seventh switching transistor T7 is coupled to the second terminal of the driving transistor DTFT.

[0168] For example, the seventh switching transistor T7 can be turned on under the control of the valid level of the second reset control signal terminal Reset2, and can be turned off under the control of the invalid level of the second reset control signal terminal Reset2. For example, if the seventh switching transistor T7 is set as an N-type transistor, then the valid level of the signal at the second reset control signal terminal Reset2 is a high level, and the invalid level of the signal at the second reset control signal terminal Reset2 is a low level. Alternatively, if the seventh switching transistor T7 is set as a P-type transistor, then the valid level of the signal at the second reset control signal terminal Reset2 is a low level, and the invalid level of the signal at the second reset control signal terminal Reset2 is a high level.

[0169] Referring to Figures 17 and 18, the seventh switching transistor T7 is a P-type transistor. When the signal at the second reset control signal terminal Reset2 is low, the seventh switching transistor T7 is turned on, and the control terminal of the driving transistor DTFT is connected to the second terminal of the driving transistor DTFT through the turned-on seventh switching transistor T7.

[0170] Referring to Figures 19 and 20, the pixel driving circuit described above further includes:

[0171] The second reset circuit 70 is coupled to the first terminal of the first capacitor C1 and the control terminal of the driving transistor DTFT, and is configured to connect the second reset signal terminal Vinit2 with the first terminal of the first capacitor C1 and the control terminal of the driving transistor DTFT.

[0172] During implementation, when the signal of the second reset control signal terminal Reset2 is valid, the second reset sub-circuit 70 is turned on, and the signal of the second reset signal terminal Vinit2 is provided to the first terminal of the first capacitor C1 and the control terminal of the driving transistor DTFT through the second reset sub-circuit 70.

[0173] Referring to Figures 21 and 22, the second reset circuit 70 includes an eighth switching transistor T8.

[0174] The control terminal of the eighth switching transistor T8 is coupled to the second reset control signal terminal Reset2, the first terminal of the eighth switching transistor T8 is coupled to the second reset signal terminal Vinit2, and the second terminal of the eighth switching transistor T8 is coupled to the first terminal of the first capacitor C1 and the control terminal of the driving transistor DTFT.

[0175] For example, the eighth switching transistor T8 can be turned on under the control of the valid level of the second reset control signal terminal Reset2, and can be turned off under the control of the invalid level of the second reset control signal terminal Reset2. For example, if the eighth switching transistor T8 is set as an N-type transistor, then the valid level of the signal at the second reset control signal terminal Reset2 is a high level, and the invalid level of the signal at the second reset control signal terminal Reset2 is a low level. Alternatively, if the eighth switching transistor T8 is set as a P-type transistor, then the valid level of the signal at the second reset control signal terminal Reset2 is a low level, and the invalid level of the signal at the second reset control signal terminal Reset2 is a high level.

[0176] Referring to Figures 21 and 22, the eighth switching transistor T8 is a P-type transistor. When the signal of the second reset control signal terminal Reset2 is low, the eighth switching transistor T8 is turned on, and the signal of the second reset signal terminal Vinit2 is provided to the first terminal of the first capacitor C1 and the control terminal of the driving transistor DTFT through the eighth switching transistor T8.

[0177] It should also be noted that the signal at the second reset signal terminal Vinit2 mentioned above is usually a negative voltage.

[0178] Referring to Figures 23 and 24, the pixel driving circuit described above further includes:

[0179] The third reset circuit 80, coupled to the anode of the LED, is configured to connect the third reset signal terminal Vinit3 to the anode of the LED.

[0180] During implementation, when the signal of the third reset control signal terminal Reset3 is valid, the third reset sub-circuit 80 is turned on, and the signal of the third reset signal terminal Vinit3 is provided to the anode of the light-emitting device LED through the third reset sub-circuit 80.

[0181] Referring to Figures 25, 26, 27 and 28, the third reset circuit 80 includes a ninth switching transistor T9.

[0182] The control terminal of the ninth switching transistor T9 is coupled to the third reset control signal terminal Reset3, the first terminal of the ninth switching transistor T9 is coupled to the anode of the light-emitting device LED, and the second terminal of the ninth switching transistor T9 is coupled to the third reset signal terminal Vinit3.

[0183] For example, the ninth switching transistor T9 can be turned on under the control of the effective level of the third reset control signal terminal Reset3, and can be turned off under the control of the ineffective level of the third reset control signal terminal Reset3. For example, if the ninth switching transistor T9 is set as an N-type transistor, then the effective level of the signal at the third reset control signal terminal Reset3 is a high level, and the ineffective level of the signal at the third reset control signal terminal Reset3 is a low level. Alternatively, if the ninth switching transistor T9 is set as a P-type transistor, then the effective level of the signal at the third reset control signal terminal Reset3 is a low level, and the ineffective level of the signal at the third reset control signal terminal Reset3 is a high level.

[0184] Referring to Figures 25, 26, 27 and 28, the ninth switching transistor T9 is a P-type transistor. When the signal of the third reset control signal terminal Reset3 is low, the ninth switching transistor T9 is turned on, and the signal of the third reset signal terminal Vinit3 is provided to the anode of the light-emitting device LED through the ninth switching transistor T9.

[0185] It should also be noted that the signal at the second reset signal terminal Vinit2 mentioned above is usually a negative voltage.

[0186] Additionally, it should be noted that in some embodiments, the first reset control signal terminal Reset1 and the third reset control signal terminal Reset3 are the same signal terminal. This shared signal terminal method can save the use of a shift register.

[0187] Referring to Figure 29, the pixel driving circuit described above also includes:

[0188] The fourth reset circuit 90 is coupled to the second terminal of the driving transistor DTFT and is configured to connect the third reset signal terminal Vinit3 to the second terminal of the driving transistor DTFT.

[0189] During implementation, when the signal of the second reset control signal terminal Reset2 is valid, the fourth reset sub-circuit 90 is turned on, and the signal of the third reset signal terminal Vinit3 is provided to the second terminal of the driving transistor DTFT through the fourth reset sub-circuit 90.

[0190] Referring to Figure 30, the fourth reset circuit 90 includes: the tenth switching transistor T10.

[0191] The control terminal of the tenth switching transistor T10 is coupled to the second reset control signal terminal Reset2, the first terminal of the tenth switching transistor T10 is coupled to the second terminal of the driving transistor DTFT, and the second terminal of the tenth switching transistor T10 is coupled to the third reset signal terminal Vinit3.

[0192] For example, the tenth switching transistor T10 can be turned on under the control of the valid level of the second reset control signal terminal Reset2, and can be turned off under the control of the invalid level of the second reset control signal terminal Reset2. For example, if the tenth switching transistor T10 is set as an N-type transistor, then the valid level of the signal at the second reset control signal terminal Reset2 is a high level, and the invalid level of the signal at the second reset control signal terminal Reset2 is a low level. Alternatively, if the tenth switching transistor T10 is set as a P-type transistor, then the valid level of the signal at the second reset control signal terminal Reset2 is a low level, and the invalid level of the signal at the second reset control signal terminal Reset2 is a high level.

[0193] Referring to Figure 30, the tenth switching transistor T10 is a P-type transistor. When the signal of the second reset control signal terminal Reset2 is low, the tenth switching transistor T10 is turned on, and the signal of the third reset signal terminal Vinit3 is provided to the control terminal of the driving transistor DTFT through the tenth switching transistor T10.

[0194] The operation of the pixel driving circuit in the embodiments of this application will be described in detail below with reference to timing diagrams 31 to 37.

[0195] In this context, 0 represents a low signal level, and 1 represents a high signal level.

[0196] (1) The operation of the pixel driving circuit in Figure 25 is described below with reference to Figures 31 and 32, wherein the first reset control signal terminal Reset1 and the third reset control signal terminal Reset3 are the same signal terminal:

[0197] Phase H1 of time sequence: EM1 = 1, EM2 = 1, Reset2 = 0, Reset2(n+1) = 1, Reset1 = 0, Reset3 = 0, Gate = 1

[0198] When the first reset control signal terminal Reset1 is low, the second switching transistor T2 is turned on, and the signal of the first reset signal terminal Vinit1 is provided to the first terminal of the driving transistor DTFT via the turned-on second switching transistor T2. When the second reset control signal terminal Reset2 is low, the first switching transistor T1 is turned on, and the first terminal of the driving transistor DTFT is connected to the first node N1. The signal of the first reset signal terminal Vinit1 provided to the first terminal of the driving transistor DTFT is then provided to the second terminal of the first node N1, i.e., the first capacitor C1, via the turned-on first switching transistor T1. Thus, the voltage VN1 of the first node N1 is equal to Vinit1. When the second reset control signal terminal Reset2 is low, the eighth switching transistor T8 is turned on, and the signal of the second reset signal terminal Vinit2 is provided to the first terminal of the first capacitor C1, i.e., the fourth node N4, and the control terminal of the driving transistor DTFT via the turned-on eighth switching transistor T8. Thus, the voltage VN4 of the fourth node N4 is equal to Vinit2. When the signal at the third reset control signal terminal Reset3 is low, the ninth switching transistor T9 is turned on. The signal at the third reset signal terminal Vinit3 is provided to the anode of the light-emitting device LED through the turned-on ninth switching transistor T9, thereby realizing the reset of the anode of the light-emitting device LED.

[0199] Phase H2: EM1 = 1, EM2 = 1, Reset2 = 0, Reset2(n+1) = 0, Reset1 = 1, Reset3 = 1, Gate = 1

[0200] When the signal at the second reset control signal terminal Reset2 is still low, the eighth switching transistor T8 is turned on. The signal at the second reset signal terminal Vinit2 is provided to the first terminal of the first capacitor C1 and the control terminal of the driving transistor DTFT via the turned-on eighth switching transistor T8. Thus, the voltage at the fourth node N4 remains VN4 = Vinit2. In the next row, the signal at the second reset control signal terminal Reset2 is also low, and the seventh switching transistor T7 is turned on. The control terminal of the driving transistor DTFT is connected to the second terminal of the driving transistor DTFT. At the same time, the control terminal of the driving transistor DTFT is turned on under the action of the second reset signal terminal Vinit2. The first switching transistor T1, the driving transistor DTFT, and the seventh switching transistor T7 are connected. The voltage at the second terminal of the first capacitor C1, i.e., the first node N1, becomes VN1 = Vinit1 - Vth. That is, the threshold voltage Vth of the driving transistor DTFT is obtained in this timing sequence, and the threshold voltage Vth is stored in the first capacitor C1.

[0201] Phase H3 of the sequence: EM1 = 1, EM2 = 1, Reset2 = 0, Reset2(n+1) = 0, Reset1 = 1, Reset1 = 1, Gate = 1

[0202] The circuit conduction situation of this timing sequence is the same as that of the H2 timing sequence, so it will not be described again here.

[0203] Phase H4 of the sequence: EM1 = 1, EM2 = 1, Reset2 = 1, Reset2(n+1) = 0, Reset1 = 1, Reset1 = 1, Gate = 1

[0204] The circuit conduction situation of this timing sequence is basically the same as that of the H2 timing sequence, so it will not be described again here. In addition, it should be added that the existence of the above timing sequences H2, H3 and H4 effectively prolongs the threshold voltage compensation process.

[0205] H5 timing phase: EM1=1, EM2=1, Reset2=1, Reset2(n+1)=1, Reset1=1, Reset1=1, Gate=0

[0206] When the scan signal terminal Gate is low, the third switching transistor T3 is turned on. The data voltage at the data signal terminal Vdata is supplied to the first node N1 through the turned-on third switching transistor T3. Thus, the voltage at the first node N1 is Vdata. Under the action of the first capacitor C1, the voltage at the control terminal of the driving transistor DTFT, i.e., the fourth node N4, becomes Vdata + Vth. The corresponding driving current is I = k(Vgs - Vth). 2 = k(VN4-VN2-Vth) 2 = k(Vdata+Vth-VDD-Vth) 2 = k(Vdata-VDD) 2 .

[0207] Phase H6 of time sequence: EM1 = 0, EM2 = 0, Reset2 = 1, Reset2(n+1) = 1, Reset1 = 1, Reset1 = 1, Gate = 1

[0208] When the signal of the first light-emitting control terminal EM1 is low, the fifth switching transistor T5 is turned on, and the first power supply terminal VDD is connected to the first terminal of the driving transistor DTFT through the turned-on fifth switching transistor T5. When the signal of the second light-emitting control terminal EM2 is low, the sixth switching transistor T6 is turned on, and the second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED through the turned-on sixth switching transistor T6. Thus, the first power supply terminal VDD, the first light-emitting control sub-circuit 40, the driving transistor DTFT, the second light-emitting control sub-circuit 50, the light-emitting device LED, and the second power supply terminal VSS form a conducting loop. In this way, the light-emitting device LED emits light under the action of the driving current.

[0209] The voltage changes during each of the above timing processes are simulated in Figure 32.

[0210] (2) The operation of the pixel driving circuit in Figure 26 is described below with reference to Figure 33. The third reset control signal terminal Reset3 and the second reset control signal terminal Reset2 are the same signal terminal. The third reset control signal terminal Reset3 provides the output signal of the shift register unit of the next row of the signal provided by the second reset control signal terminal Reset2.

[0211] Phase H1 of the sequence: EM1=1, EM2=0, Reset2=0, Reset3=1, Reset1=0, Reset3=0, Gate=1

[0212] When the first reset control signal terminal Reset1 is low, the second switching transistor T2 is turned on, and the signal of the first reset signal terminal Vinit1 is provided to the first terminal of the driving transistor DTFT via the turned-on second switching transistor T2. When the second reset control signal terminal Reset2 is low, the first switching transistor T1 is turned on, and the first terminal of the driving transistor DTFT is connected to the first node N1. The signal of the first reset signal terminal Vinit1 provided to the first terminal of the driving transistor DTFT is then provided to the second terminal of the first node N1, i.e., the first capacitor C1, via the turned-on first switching transistor T1. Thus, the voltage VN1 of the first node N1 is equal to Vinit1. When the second reset control signal terminal Reset2 is low, the eighth switching transistor T8 is turned on, and the signal of the second reset signal terminal Vinit2 is provided to the first terminal of the first capacitor C1, i.e., the fourth node N4, and the control terminal of the driving transistor DTFT via the turned-on eighth switching transistor T8. Thus, the voltage VN4 of the fourth node N4 is equal to Vinit2. When the third reset control signal terminal Reset3 is low, the ninth switching transistor T9 is turned on. The signal from the third reset signal terminal Vinit3 is provided to the anode of the LED through the turned-on ninth switching transistor T9, thereby resetting the anode of the LED. When the signal from the second light-emitting control terminal EM2 is low, the sixth switching transistor T6 is turned on. The second terminal of the driving transistor DTFT is connected to the anode of the LED through the turned-on sixth switching transistor T6. The signal from the third reset signal terminal Vinit3 is provided to the second terminal of the driving transistor DTFT through the turned-on sixth switching transistor T6, thereby resetting the second terminal of the driving transistor DTFT.

[0213] Phase H2: EM1 = 1, EM2 = 0, Reset2 = 0, Reset3 = 0, Reset1 = 1, Reset3 = Reset2(n+1) = 1, Gate = 1

[0214] When the second reset control signal terminal Reset2 is still low, the eighth switching transistor T8 is turned on. The signal of the second reset signal terminal Vinit2 is provided to the first terminal of the first capacitor C1 and the control terminal of the driving transistor DTFT via the turned-on eighth switching transistor T8. Thus, the voltage of the fourth node N4 is still VN4 = Vinit2. When the third reset control signal terminal Reset3 is low, the ninth switching transistor T9 is turned on. The signal of the third reset signal terminal Vinit3 is provided to the anode of the light-emitting device LED via the turned-on ninth switching transistor T9, thereby resetting the anode of the light-emitting device LED. When the signal of the second light-emitting control terminal EM2 is low, the sixth switching transistor T6 is turned on. The second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED through the turned-on sixth switching transistor T6. At the same time, the driving transistor DTFT is turned on under the action of Vinit2 and is maintained in the conducting state under the action of the sixth switching transistor T6. The first switching transistor T1, the driving transistor DTFT and the sixth switching transistor T6 form a conducting loop. The voltage of the second terminal of the first capacitor C1, i.e. the first node N1, becomes VN1 = Vinit1 - Vth. That is, the threshold voltage Vth of the driving transistor DTFT is obtained at this time. The threshold voltage Vth is stored in the first capacitor C1.

[0215] Phase H3 of the sequence: EM1 = 1, EM2 = 0, Reset2 = 0, Reset3 = 0, Reset1 = 1, Reset3 = Reset2(n+1) = 0, Gate = 1

[0216] The circuit conduction situation of this timing sequence is basically the same as that of the H2 timing sequence, so it will not be described again here.

[0217] Phase H4 of the sequence: EM1=1, EM2=1, Reset2=1, Reset3=0, Reset1=1, Reset3=Reset2(n+1)=0, Gate=1

[0218] The circuit conduction situation of this timing sequence is basically the same as that of the H2 timing sequence, so it will not be described again here. In addition, it should be added that the existence of the above timing sequences H2, H3 and H4 effectively prolongs the threshold voltage compensation process.

[0219] H5 timing phase: EM1=1, EM2=1, Reset2=1, Reset3=1, Reset1=1, Reset3=Reset2(n+1)=1, Gate=0

[0220] When the scan signal terminal Gate is low, the third switching transistor T3 is turned on. The data voltage at the data signal terminal Vdata is supplied to the first node N1 through the turned-on third switching transistor T3. Thus, the voltage at the first node N1 is Vdata. Under the action of the first capacitor C1, the voltage at the control terminal of the driving transistor DTFT, i.e., the fourth node N4, becomes Vdata + Vth. The corresponding driving current is I = k(Vgs - Vth). 2 = k(VN4-VN2-Vth) 2 = k(Vdata+Vth-VDD-Vth) 2 = k(Vdata-VDD) 2 .

[0221] Phase H6 of time series: EM1 = 0, EM2 = 1, Reset2 = 1, Reset2(n+1) = 1, Reset1 = 1, Reset3 = Reset2(n+1) = 1, Gate = 1

[0222] When the signal of the first light-emitting control terminal EM1 is low, the fifth switching transistor T5 is turned on, and the first power supply terminal VDD is connected to the first terminal of the driving transistor DTFT through the turned-on fifth switching transistor T5.

[0223] Phase H7: EM1 = 0, EM2 = 0, Reset2 = 1, Reset2(n+1) = 1, Reset1 = 1, Reset3 = Reset2(n+1) = 1, Gate = 1

[0224] When the signal of the first light-emitting control terminal EM1 is low, the fifth switching transistor T5 is turned on, and the first power supply terminal VDD is connected to the first terminal of the driving transistor DTFT through the turned-on fifth switching transistor T5. When the signal of the second light-emitting control terminal EM2 is low, the sixth switching transistor T6 is turned on, and the second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED through the turned-on sixth switching transistor T6. Thus, the first power supply terminal VDD, the first light-emitting control sub-circuit 40, the driving transistor DTFT, the second light-emitting control sub-circuit 50, the light-emitting device LED, and the second power supply terminal VSS form a conducting loop. In this way, the light-emitting device LED emits light under the action of the driving current.

[0225] (3) The operation of the pixel driving circuit in Figure 27 is described below with reference to Figures 34 and 35. In this description, the first reset control signal terminal Reset1 and the third reset control signal terminal Reset3 are the same signal terminal:

[0226] Phase H1 of time sequence: EM1 = 1, EM2 = 1, Reset2 = 0, Reset2(n+1) = 1, Reset1 = 0, Reset3 = 0, Gate = 1

[0227] When the first reset control signal terminal Reset1 is low, the second switching transistor T2 is turned on. The signal from the first reset signal terminal Vinit1 is provided to the first terminal of the driving transistor DTFT via the turned-on second switching transistor T2. The signal from Vinit1 is also provided to the second terminal of the first node N1 (i.e., the first capacitor C1) via the connected signal line. Thus, the voltage VN1 of the first node N1 equals Vinit1. When the second reset control signal terminal Reset2 is low, the eighth switching transistor T8 is turned on. The signal from Vinit2 is provided to the first terminal of the fourth node N4 (i.e., the first capacitor C1) and the control terminal of the driving transistor DTFT via the turned-on eighth switching transistor T8. Thus, the voltage VN4 of the fourth node N4 equals Vinit2. When the third reset control signal terminal Reset3 is low, the ninth switching transistor T9 is turned on. The signal from Vinit3 is provided to the anode of the LED via the turned-on ninth switching transistor T9, thereby resetting the anode of the LED.

[0228] Phase H2: EM1 = 1, EM2 = 1, Reset2 = 0, Reset2(n+1) = 0, Reset1 = 1, Reset3 = 1, Gate = 1

[0229] When the signal at the second reset control signal terminal Reset2 is still low, the eighth switching transistor T8 is turned on. The signal at the second reset signal terminal Vinit2 is provided to the first terminal of the first capacitor C1 and the control terminal of the driving transistor DTFT via the turned-on eighth switching transistor T8. Thus, the voltage at the fourth node N4 remains VN4 = Vinit2. In the next row, the signal at the second reset control signal terminal Reset2 is also low, and the seventh switching transistor T7 is turned on. The control terminal of the driving transistor DTFT is connected to the second terminal of the driving transistor DTFT. Furthermore, since the control terminal of the driving transistor DTFT is turned on by the signal at the second reset signal terminal Vinit2, the aforementioned connected signal line, the driving transistor DTFT, and the seventh switching transistor T7 form a conducting loop. The voltage at the second terminal of the first capacitor C1, i.e., the first node N1, becomes VN1 = Vinit1 - Vth. That is, the threshold voltage Vth of the driving transistor DTFT is obtained in this timing sequence, and the threshold voltage Vth is stored in the first capacitor C1.

[0230] Phase H3 of the sequence: EM1 = 1, EM2 = 1, Reset2 = 0, Reset2(n+1) = 0, Reset1 = 1, Reset1 = 1, Gate = 1

[0231] The circuit conduction situation of this timing sequence is the same as that of the H2 timing sequence, so it will not be described again here.

[0232] Phase H4 of the sequence: EM1=1, EM2=1, Reset2=1, Reset2(n+1)=0, Reset1=1, Reset3=1, Gate=1

[0233] The circuit conduction situation of this timing sequence is basically the same as that of the H2 timing sequence, so it will not be described again here. In addition, it should be added that the existence of the above timing sequences H2, H3 and H4 effectively prolongs the threshold voltage compensation process.

[0234] H5 timing phase: EM1=1, EM2=1, Reset2=1, Reset2(n+1)=1, Reset1=1, Reset3=1, Gate=0

[0235] When the scan signal terminal Gate is low, the fourth switching transistor T4 is turned on. The data voltage at the data signal terminal Vdata is supplied to the fourth node N4 through the turned-on fourth switching transistor T4. Thus, the voltage at the fourth node N4 is Vdata. Under the action of the first capacitor C1, the voltage at the first node N1 becomes Vinit2-Vth+(C1 / (C1+C2))*(Vdata-Vinit2)=(C1 / (C1+C2))*Vdata+(C2 / (C1+C2))*Vinit2-Vth. The corresponding drive current is I=k(Vgs-Vth). 2 = k(VN4-VN2-Vth) 2 =k(VDD+(Vdata-Vinit2)*(C2 / (C1+C2))+Vth-Vth) 2 =k((Vdata-Vinit2)*(C2 / (C1+C2))) 2 .

[0236] Phase H6 of time series: EM1 = 0, EM2 = 0, Reset2 = 1, Reset2(n+1) = 1, Reset1 = 1, Reset1 = 3, Gate = 1

[0237] When the signal of the first light-emitting control terminal EM1 is low, the fifth switching transistor T5 is turned on, and the first power supply terminal VDD is connected to the first terminal of the driving transistor DTFT through the turned-on fifth switching transistor T5. When the signal of the second light-emitting control terminal EM2 is low, the sixth switching transistor T6 is turned on, and the second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED through the turned-on sixth switching transistor T6. Thus, the first power supply terminal VDD, the first light-emitting control sub-circuit 40, the driving transistor DTFT, the second light-emitting control sub-circuit 50, the light-emitting device LED, and the second power supply terminal VSS form a conducting loop. In this way, the light-emitting device LED emits light under the action of the driving current.

[0238] The voltage changes during each of the above timing processes are simulated in Figure 35.

[0239] (4) The operation of the pixel driving circuit in Figure 28 is described below with reference to Figure 36. It is assumed that the pixel driving circuit in Figure 28 operates in high-frequency mode, and the third reset control signal terminal Reset3 and the second reset control signal terminal Reset2 are the same signal terminal. The third reset control signal terminal Reset3 provides the output signal of the shift register unit of the next row of the signal provided by the second reset control signal terminal Reset2.

[0240] Phase H1 of time sequence: EM1 = 1, EM2 = 0, Reset2 = 0, Reset1 = 0, Reset3 = Reset2(n+1) = 0, Gate = 1

[0241] When the first reset control signal terminal Reset1 is low, the second switching transistor T2 is turned on. The signal from the first reset signal terminal Vinit1 is provided to the first terminal of the driving transistor DTFT via the turned-on second switching transistor T2, and then to the second terminal of the first capacitor C1, i.e., the first node N1, via the connected signal line. Thus, the voltage VN1 of the first node N1 is equal to Vinit1. When the second reset control signal terminal Reset2 is low, the eighth switching transistor T8 is turned on. The signal from the second reset signal terminal Vinit2 is provided to the first terminal of the first capacitor C1, i.e., the fourth node N4, and the control terminal of the driving transistor DTFT via the turned-on eighth switching transistor T8. Thus, the voltage VN4 of the fourth node N4 is equal to Vinit2. When the third reset control signal terminal Reset3 is low, the ninth switching transistor T9 is turned on. The signal from the third reset signal terminal Vinit3 is provided to the anode of the light-emitting device LED via the turned-on ninth switching transistor T9, thereby resetting the anode of the light-emitting device LED. When the signal at the second light-emitting control terminal EM2 is low, the sixth switching transistor T6 is turned on. The second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED through the turned-on sixth switching transistor T6. The signal at the third reset signal terminal Vinit3 is provided to the second terminal of the driving transistor DTFT through the turned-on sixth switching transistor T6, thereby resetting the second terminal of the driving transistor DTFT.

[0242] Phase H2: EM1 = 1, EM2 = 0, Reset2 = 0, Reset1 = 1, Reset3 = Reset2(n+1) = 0, Gate = 1

[0243] When the second reset control signal terminal Reset2 is still low, the eighth switching transistor T8 is turned on. The signal of the second reset signal terminal Vinit2 is provided to the first terminal of the first capacitor C1 and the control terminal of the driving transistor DTFT via the turned-on eighth switching transistor T8. Thus, the voltage of the fourth node N4 is still VN4 = Vinit2. When the third reset control signal terminal Reset3 is low, the ninth switching transistor T9 is turned on. The signal of the third reset signal terminal Vinit3 is provided to the anode of the light-emitting device LED via the turned-on ninth switching transistor T9, thereby resetting the anode of the light-emitting device LED. When the signal at the second light-emitting control terminal EM2 is low, the sixth switching transistor T6 is turned on. The second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED through the turned-on sixth switching transistor T6. At the same time, the driving transistor DTFT is still turned on under the action of the second light-emitting control sub-circuit 50 and the third reset sub-circuit 80. The connecting sub-circuit 10 connects the first node N1 and the first terminal of the driving transistor DTFT. The driving transistor DTFT and the connecting sub-circuit 10 are connected. The voltage at the second terminal of the first capacitor C1, i.e. the first node N1, becomes VN1 = Vinit2 - Vth. That is, the threshold voltage Vth of the driving transistor DTFT is obtained at this timing. The threshold voltage Vth is stored in the first capacitor C1.

[0244] Phase H3 of time sequence: EM1 = 1, EM2 = 0, Reset2 = 0, Reset1 = 1, Reset3 = Reset2(n+1) = 0, Gate = 1

[0245] The circuit conduction situation of this timing sequence is basically the same as that of the H2 timing sequence, so it will not be described again here.

[0246] Phase H4 of the sequence: EM1=1, EM2=1, Reset2=1, Reset2(n+1)=0, Reset1=1, Reset3=1, Gate=1

[0247] The circuit conduction situation of this timing sequence is basically the same as that of H2 timing sequence, so it will not be described again here. In addition, it should be added that the existence of the above timing sequences H2, H3 and H4 effectively prolongs the compensation process of the threshold voltage in high-frequency mode.

[0248] H5 timing phase: EM1=1, EM2=1, Reset2=1, Reset1=1, Reset3=Reset2(n+1)=1, Gate=0

[0249] When the scan signal terminal Gate is low, the fourth switching transistor T4 is turned on. The data voltage at the data signal terminal Vdata is supplied to the fourth node N4 through the turned-on fourth switching transistor T4. Thus, the voltage at the fourth node N4 is Vdata. Under the action of the first capacitor C1, the voltage at the first node N1 becomes VN1 = Vinit2 - Vth + (C1 / (C1+C2))*(Vdata - Vinit2) = (C1 / (C1+C2))*Vdata + (C2 / (C1+C2))*Vinit2 - Vth. The corresponding drive current is I = k(Vgs - Vth). 2 = k(VN4-VN2-Vth) 2 =k(VDD+(Vdata-Vinit2)*(C2 / (C1+C2))+Vth-Vth) 2 =k((Vdata-Vinit2)*(C2 / (C1+C2))) 2 .

[0250] Phase H6 of time sequence: EM1 = 0, EM2 = 1, Reset2 = 1, Reset1 = 1, Reset3 = Reset2(n+1) = 1, Gate = 1

[0251] When the signal of the first light-emitting control terminal EM1 is low, the fifth switching transistor T5 is turned on, and the first power supply terminal VDD is connected to the first terminal of the driving transistor DTFT through the turned-on fifth switching transistor T5.

[0252] Phase H7 of time series: EM1 = 0, EM2 = 0, Reset2 = 1, Reset1 = 1, Reset3 = Reset2(n+1) = 1, Gate = 1

[0253] When the signal of the first light-emitting control terminal EM1 is low, the fifth switching transistor T5 is turned on, and the first power supply terminal VDD is connected to the first terminal of the driving transistor DTFT through the turned-on fifth switching transistor T5. When the signal of the second light-emitting control terminal EM2 is low, the sixth switching transistor T6 is turned on, and the second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED through the turned-on sixth switching transistor T6. Thus, the first power supply terminal VDD, the first light-emitting control sub-circuit 40, the driving transistor DTFT, the second light-emitting control sub-circuit 50, the light-emitting device LED, and the second power supply terminal VSS form a conducting loop. In this way, the light-emitting device LED emits light under the action of the driving current.

[0254] (5) The operation of the pixel driving circuit in Figure 28 is described below with reference to Figure 37. It is assumed that the pixel driving circuit in Figure 28 is operating in low frequency mode. The third reset control signal terminal Reset3 and the second reset control signal terminal Reset2 are the same signal terminal. The third reset control signal terminal Reset3 provides the output signal of the shift register unit of the next row of the signal to the second reset control signal terminal Reset2.

[0255] Phase H1 of time sequence: EM1 = 1, EM2 = 0, Reset2 = 0, Reset1 = 0, Reset3 = Reset2(n+1) = 1, Gate = 1

[0256] When the first reset control signal terminal Reset1 is low, the second switching transistor T2 is turned on. The signal from the first reset signal terminal Vinit1 is provided to the first terminal of the driving transistor DTFT via the turned-on second switching transistor T2, and then to the second terminal of the first capacitor C1, i.e., the first node N1, via the connection signal line. Thus, the voltage VN1 of the first node N1 is equal to Vinit1. When the second reset control signal terminal Reset2 is low, the eighth switching transistor T8 is turned on. The signal from the second reset signal terminal Vinit2 is provided to the first terminal of the first capacitor C1, i.e., the fourth node N4, and the control terminal of the driving transistor DTFT via the turned-on eighth switching transistor T8. Thus, the voltage VN4 of the fourth node N4 is equal to Vinit2. When the signal from the second light-emitting control terminal EM2 is low, the sixth switching transistor T6 is turned on. The second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED via the turned-on sixth switching transistor T6. The signal from the third reset signal terminal Vinit3 is provided to the second terminal of the driving transistor DTFT via the turned-on sixth switching transistor T6, thereby resetting the second terminal of the driving transistor DTFT.

[0257] Phase H2: EM1 = 1, EM2 = 0, Reset2 = 0, Reset1 = 1, Reset3 = Reset2(n+1) = 0, Gate = 1

[0258] When the second reset control signal terminal Reset2 is still low, the eighth switching transistor T8 is turned on. The signal of the second reset signal terminal Vinit2 is provided to the first terminal of the first capacitor C1 and the control terminal of the driving transistor DTFT via the turned-on eighth switching transistor T8. Thus, the voltage of the fourth node N4 is still VN4 = Vinit2. When the third reset control signal terminal Reset3 is low, the ninth switching transistor T9 is turned on. The signal of the third reset signal terminal Vinit3 is provided to the anode of the light-emitting device LED via the turned-on ninth switching transistor T9, thereby resetting the anode of the light-emitting device LED. When the signal at the second light-emitting control terminal EM2 is low, the sixth switching transistor T6 is turned on. The second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED through the turned-on sixth switching transistor T6. At the same time, the driving transistor DTFT is still turned on under the action of the second light-emitting control sub-circuit 50 and the third reset sub-circuit 80. The connecting sub-circuit 10 connects the first node N1 and the first terminal of the driving transistor DTFT. The driving transistor DTFT and the connecting sub-circuit 10 are connected. The voltage at the second terminal of the first capacitor C1, i.e. the first node N1, becomes VN1 = Vinit2 - Vth. That is, the threshold voltage Vth of the driving transistor DTFT is obtained at this timing. The threshold voltage Vth is stored in the first capacitor C1.

[0259] Phase H3 of time sequence: EM1 = 1, EM2 = 0, Reset2 = 1, Reset1 = 1, Reset3 = Reset2(n+1) = 0, Gate = 1

[0260] The circuit conduction situation of this timing sequence is basically the same as that of the H2 timing sequence, so it will not be described again here.

[0261] Phase H4 of the sequence: EM1=1, EM2=1, Reset2=1, Reset2(n+1)=1, Reset1=1, Reset3=1, Gate=1

[0262] The circuit conduction situation of this timing sequence is basically the same as that of H2 timing sequence, so it will not be described again here. In addition, it should be noted that compared with Figure 36, the effective duration of the above timing sequences H2, H3 and H4 is shorter, but the above effective duration ensures the compensation process of threshold voltage in low frequency mode.

[0263] H5 timing phase: EM1=1, EM2=1, Reset2=1, Reset1=1, Reset3=Reset2(n+1)=1, Gate=0

[0264] When the scan signal terminal Gate is low, the fourth switching transistor T4 is turned on. The data voltage at the data signal terminal Vdata is supplied to the fourth node N4 through the turned-on fourth switching transistor T4. Thus, the voltage at the fourth node N4 is Vdata. Under the action of the first capacitor C1, the voltage at the first node N1 becomes VN1 = Vinit2 - Vth + (C1 / (C1+C2))*(Vdata - Vinit2) = (C1 / (C1+C2))*Vdata + (C2 / (C1+C2))*Vinit2 - Vth. The corresponding drive current is I = k(Vgs - Vth). 2 = k(VN4-VN2-Vth) 2 =k(VDD+(Vdata-Vinit2)*(C2 / (C1+C2))+Vth-Vth) 2 =k((Vdata-Vinit2)*(C2 / (C1+C2))) 2 .

[0265] Phase H6 of time sequence: EM1 = 0, EM2 = 1, Reset2 = 1, Reset1 = 1, Reset3 = Reset2(n+1) = 1, Gate = 1

[0266] When the signal of the first light-emitting control terminal EM1 is low, the fifth switching transistor T5 is turned on, and the first power supply terminal VDD is connected to the first terminal of the driving transistor DTFT through the turned-on fifth switching transistor T5.

[0267] Phase H7 of time series: EM1 = 0, EM2 = 0, Reset2 = 1, Reset1 = 1, Reset3 = Reset2(n+1) = 1, Gate = 1

[0268] When the signal of the first light-emitting control terminal EM1 is low, the fifth switching transistor T5 is turned on, and the first power supply terminal VDD is connected to the first terminal of the driving transistor DTFT through the turned-on fifth switching transistor T5. When the signal of the second light-emitting control terminal EM2 is low, the sixth switching transistor T6 is turned on, and the second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED through the turned-on sixth switching transistor T6. Thus, the first power supply terminal VDD, the first light-emitting control sub-circuit 40, the driving transistor DTFT, the second light-emitting control sub-circuit 50, the light-emitting device LED, and the second power supply terminal VSS form a conducting loop. In this way, the light-emitting device LED emits light under the action of the driving current.

[0269] (6) The operation of the pixel driving circuit in Figure 28 is described below with reference to Figure 38. It is assumed that the pixel driving circuit in Figure 28 operates in low frequency mode, and the example is that the (n-1)th frame is the refresh frame, the nth frame is the hold frame, and the (n+1)th frame is still a hold frame. The third reset control signal terminal Reset3 and the second reset control signal terminal Reset2 are the same signal terminal. The third reset control signal terminal Reset3 provides the output signal of the shift register unit of the next row of the signal provided by the second reset control signal terminal Reset2.

[0270] In frame (n-1): Timing h11 stage: EM1 = 1, EM2 = 0, Reset2 = 0, Reset1 = 0, Reset3 = Reset2(n+1) = 0, Gate = 1

[0271] When the first reset control signal terminal Reset1 is low, the second switching transistor T2 is turned on. The signal from the first reset signal terminal Vinit1 is provided to the first terminal of the driving transistor DTFT via the turned-on second switching transistor T2, and then to the second terminal of the first capacitor C1, i.e., the first node N1, via the connected signal line. Thus, the voltage VN1 of the first node N1 is equal to Vinit1. When the second reset control signal terminal Reset2 is low, the eighth switching transistor T8 is turned on. The signal from the second reset signal terminal Vinit2 is provided to the first terminal of the first capacitor C1, i.e., the fourth node N4, and the control terminal of the driving transistor DTFT via the turned-on eighth switching transistor T8. Thus, the voltage VN4 of the fourth node N4 is equal to Vinit2. When the third reset control signal terminal Reset3 is low, the ninth switching transistor T9 is turned on. The signal from the third reset signal terminal Vinit3 is provided to the anode of the light-emitting device LED via the turned-on ninth switching transistor T9, thereby resetting the anode of the light-emitting device LED. When the signal at the second light-emitting control terminal EM2 is low, the sixth switching transistor T6 is turned on. The second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED through the turned-on sixth switching transistor T6. The signal at the third reset signal terminal Vinit3 is provided to the second terminal of the driving transistor DTFT through the turned-on sixth switching transistor T6, thereby resetting the second terminal of the driving transistor DTFT.

[0272] Timing stage h12: EM1=1, EM2=0, Reset2=0, Reset1=1, Reset3=Reset2(n+1)=0, Gate=1

[0273] When the second reset control signal terminal Reset2 is still low, the eighth switching transistor T8 is turned on. The signal of the second reset signal terminal Vinit2 is provided to the first terminal of the first capacitor C1 and the control terminal of the driving transistor DTFT via the turned-on eighth switching transistor T8. Thus, the voltage of the fourth node N4 is still VN4 = Vinit2. When the third reset control signal terminal Reset3 is low, the ninth switching transistor T9 is turned on. The signal of the third reset signal terminal Vinit3 is provided to the anode of the light-emitting device LED via the turned-on ninth switching transistor T9, thereby resetting the anode of the light-emitting device LED. When the signal at the second light-emitting control terminal EM2 is low, the sixth switching transistor T6 is turned on. The second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED through the turned-on sixth switching transistor T6. At the same time, the driving transistor DTFT is still turned on under the action of the second light-emitting control sub-circuit 50 and the third reset sub-circuit 80. The connecting sub-circuit 10 connects the first node N1 and the first terminal of the driving transistor DTFT. The driving transistor DTFT and the connecting sub-circuit 10 are connected. The voltage at the second terminal of the first capacitor C1, i.e. the first node N1, becomes VN1 = Vinit2 - Vth. That is, the threshold voltage Vth of the driving transistor DTFT is obtained at this timing. The threshold voltage Vth is stored in the first capacitor C1.

[0274] Timing stage h13: EM1=1, EM2=1, Reset2=1, Reset1=1, Reset3=Reset2(n+1)=0, Gate=1

[0275] The circuit conduction situation of this timing sequence is basically the same as that of the h12 timing sequence, so it will not be described again here.

[0276] Timing stage h14: EM1=1, EM2=1, Reset2=1, Reset2(n+1)=1, Reset1=1, Reset3=1, Gate=1

[0277] The circuit conduction situation of this timing sequence is basically the same as that of the h12 timing sequence, so it will not be described again here. In addition, it should be noted that compared with Figure 36, the effective duration of the above timing sequences H2, H3 and H4 is shorter, but the above effective duration ensures the compensation process of the threshold voltage in low-frequency mode.

[0278] Timing stage h15: EM1=1, EM2=1, Reset2=1, Reset1=1, Reset3=Reset2(n+1)=1, Gate=0

[0279] When the scan signal terminal Gate is low, the fourth switching transistor T4 is turned on. The data voltage at the data signal terminal Vdata is supplied to the fourth node N4 through the turned-on fourth switching transistor T4. Thus, the voltage at the fourth node N4 is Vdata. Under the action of the first capacitor C1, the voltage at the first node N1 becomes VN1 = Vinit2 - Vth + (C1 / (C1+C2))*(Vdata - Vinit2) = (C1 / (C1+C2))*Vdata + (C2 / (C1+C2))*Vinit2 - Vth. The corresponding drive current is I = k(Vgs - Vth). 2 = k(VN4-VN2-Vth) 2 =k(VDD+(Vdata-Vinit2)*(C2 / (C1+C2))+Vth-Vth) 2 =k((Vdata-Vinit2)*(C2 / (C1+C2))) 2 .

[0280] Timing h16 stage: EM1=0, EM2=1, Reset2=1, Reset1=1, Reset3=Reset2(n+1)=1, Gate=1

[0281] When the signal of the first light-emitting control terminal EM1 is low, the fifth switching transistor T5 is turned on, and the first power supply terminal VDD is connected to the first terminal of the driving transistor DTFT through the turned-on fifth switching transistor T5.

[0282] Timing stage h17: EM1 = 0, EM2 = 0, Reset2 = 1, Reset1 = 1, Reset3 = Reset2(n+1) = 1, Gate = 1

[0283] When the signal of the first light-emitting control terminal EM1 is low, the fifth switching transistor T5 is turned on, and the first power supply terminal VDD is connected to the first terminal of the driving transistor DTFT through the turned-on fifth switching transistor T5. When the signal of the second light-emitting control terminal EM2 is low, the sixth switching transistor T6 is turned on, and the second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED through the turned-on sixth switching transistor T6. Thus, the first power supply terminal VDD, the first light-emitting control sub-circuit 40, the driving transistor DTFT, the second light-emitting control sub-circuit 50, the light-emitting device LED, and the second power supply terminal VSS form a conducting loop. In this way, the light-emitting device LED emits light under the action of the driving current.

[0284] In frame n: Timing h21 stage: EM1 = 1, EM2 = 0, Reset2 = 1, Reset1 = 0, Reset3 = Reset2(n+1) = 1, Gate = 1

[0285] When the signal at the first reset control signal terminal Reset1 is low, the second switching transistor T2 is turned on. The signal at the first reset signal terminal Vinit1 is provided to the first terminal of the driving transistor DTFT through the turned-on second switching transistor T2, and then to the second terminal of the first capacitor C1, i.e., the first node N1, through the connected signal line. Thus, the voltage at the first node N1, VN1, equals Vinit1. When the signal at the second light-emitting control terminal EM2 is low, the sixth switching transistor T6 is turned on. The second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED through the turned-on sixth switching transistor T6.

[0286] Timing stage h22: EM1 = 1, EM2 = 0, Reset2 = 1, Reset1 = 1, Reset3 = Reset2(n+1) = 1, Gate = 1

[0287] The circuit conduction situation of this timing sequence is basically the same as that of the h21 timing sequence, so it will not be described again here.

[0288] Timing stage h23: EM1=1, EM2=1, Reset2=1, Reset1=1, Reset3=Reset2(n+1)=1, Gate=1

[0289] This timing differs from the (n-1)th refresh frame. When the scan signal terminal Gate is high, it means that the scan signal terminal Gate is invalid and the data voltage of the driving transistor DTFT cannot be updated. Other details will not be elaborated further.

[0290] Timing h24 stage: EM1=0, EM2=1, Reset2=1, Reset1=1, Reset3=Reset2(n+1)=1, Gate=1

[0291] When the signal of the first light-emitting control terminal EM1 is low, the fifth switching transistor T5 is turned on, and the first power supply terminal VDD is connected to the first terminal of the driving transistor DTFT through the turned-on fifth switching transistor T5.

[0292] Timing h25 stage: EM1=0, EM2=0, Reset2=1, Reset1=1, Reset3=Reset2(n+1)=1, Gate=1

[0293] When the signal of the first light-emitting control terminal EM1 is low, the fifth switching transistor T5 is turned on, and the first power supply terminal VDD is connected to the first terminal of the driving transistor DTFT through the turned-on fifth switching transistor T5. When the signal of the second light-emitting control terminal EM2 is low, the sixth switching transistor T6 is turned on, and the second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED through the turned-on sixth switching transistor T6. Thus, the first power supply terminal VDD, the first light-emitting control sub-circuit 40, the driving transistor DTFT, the second light-emitting control sub-circuit 50, the light-emitting device LED, and the second power supply terminal VSS form a conducting loop.

[0294] In frame n+1: the circuit conduction status of timing stage h31 is basically the same as that of timing stage h21, the circuit conduction status of timing stage h32 is basically the same as that of timing stage h22, the circuit conduction status of timing stage h33 is basically the same as that of timing stage h23, the circuit conduction status of timing stage h34 is basically the same as that of timing stage h24, and the circuit conduction status of timing stage h35 is basically the same as that of timing stage h25. These will not be described in detail here.

[0295] (7) The operation of the pixel driving circuit in Figure 30 is described below with reference to Figure 39. It is assumed that the pixel driving circuit in Figure 30 operates in high-frequency mode, and the first reset control signal terminal Reset1 and the third reset control signal terminal Reset3 are the same signal terminal:

[0296] Phase H1 of time sequence: EM1 = 1, EM2 = 1, Reset2 = 0, Reset2(n+1) = 1, Reset1 = 0, Reset3 = 0, Gate = 1

[0297] When the first reset control signal terminal Reset1 is low, the second switching transistor T2 is turned on. The signal from the first reset signal terminal Vinit1 is provided to the first terminal of the driving transistor DTFT via the turned-on second switching transistor T2, and then to the second terminal of the first capacitor C1, i.e., the first node N1, via the connected signal line. Thus, the voltage VN1 of the first node N1 is equal to Vinit1. When the second reset control signal terminal Reset2 is low, the eighth switching transistor T8 is turned on. The signal from the second reset signal terminal Vinit2 is provided to the first terminal of the first capacitor C1, i.e., the fourth node N4, and the control terminal of the driving transistor DTFT via the turned-on eighth switching transistor T8. Thus, the voltage VN4 of the fourth node N4 is equal to Vinit2. When the third reset control signal terminal Reset3 is low, the ninth switching transistor T9 is turned on. The signal from the third reset signal terminal Vinit3 is provided to the anode of the light-emitting device LED via the turned-on ninth switching transistor T9, thereby resetting the anode of the light-emitting device LED.

[0298] Phase H2: EM1 = 1, EM2 = 1, Reset2 = 0, Reset2(n+1) = 0, Reset1 = 1, Reset3 = 1, Gate = 1

[0299] When the signal at the second reset control signal terminal Reset2 is still low, the eighth switching transistor T8 is turned on. The signal at the second reset signal terminal Vinit2 is provided to the first terminal of the first capacitor C1 and the control terminal of the driving transistor DTFT via the turned-on eighth switching transistor T8. Thus, the voltage at the fourth node N4 is still VN4 = Vinit2. At the same time, when the signal at the second reset control signal terminal Reset2 in the next row is low, the tenth switching transistor T10 is turned on. The signal at the third reset signal terminal Vinit3 is provided to the second terminal of the driving transistor DTFT, i.e., the third node N3, via the turned-on tenth switching transistor T10. The driving transistor DTFT remains turned on under the action of the fourth reset sub-circuit 90. The driving transistor DTFT and the connecting sub-circuit 10 are connected. The voltage at the second terminal of the first capacitor C1, i.e., the first node N1, becomes VN1 = Vinit2 - Vth. That is, the threshold voltage Vth of the driving transistor DTFT is obtained in this timing sequence, and the threshold voltage Vth is stored in the first capacitor C1.

[0300] Phase H3: EM1 = 1, EM2 = 1, Reset2 = 0, Reset2(n+1) = 0, Reset1 = 1, Reset3 = 1, Gate = 1

[0301] The circuit conduction situation of this timing sequence is basically the same as that of the H2 timing sequence, so it will not be described again here.

[0302] Phase H4 of the sequence: EM1=1, EM2=1, Reset2=1, Reset2(n+1)=0, Reset1=1, Reset3=1, Gate=1

[0303] The circuit conduction situation of this timing sequence is basically the same as that of the H2 timing sequence, so it will not be described again here. In addition, it should be added that the existence of the above timing sequences H2, H3 and H4 effectively prolongs the threshold voltage compensation process.

[0304] H5 timing phase: EM1=1, EM2=1, Reset2=1, Reset2(n+1)=1, Reset1=1, Reset3=1, Gate=0

[0305] When the scan signal terminal Gate is low, the fourth switching transistor T4 is turned on. The data voltage at the data signal terminal Vdata is supplied to the fourth node N4 through the turned-on fourth switching transistor T4. Thus, the voltage at the fourth node N4 is Vdata. Under the action of the first capacitor C1, the voltage at the first node N1 becomes VN1 = Vinit2 - Vth + (C1 / (C1+C2))*(Vdata - Vinit2) = (C1 / (C1+C2))*Vdata + (C2 / (C1+C2))*Vinit2 - Vth. The corresponding drive current is I = k(Vgs - Vth). 2 = k(VN4-VN2-Vth) 2 =k(VDD+(Vdata-Vinit2)*(C2 / (C1+C2))+Vth-Vth) 2 =k((Vdata-Vinit2)*(C2 / (C1+C2))) 2 .

[0306] Phase H6 of time series: EM1 = 0, EM2 = 0, Reset2 = 1, Reset2(n+1) = 1, Reset1 = 1, Reset3 = 1, Gate = 1

[0307] When the signal of the first light-emitting control terminal EM1 is low, the fifth switching transistor T5 is turned on, and the first power supply terminal VDD is connected to the first terminal of the driving transistor DTFT through the turned-on fifth switching transistor T5. When the signal of the second light-emitting control terminal EM2 is low, the sixth switching transistor T6 is turned on, and the second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED through the turned-on sixth switching transistor T6. Thus, the first power supply terminal VDD, the first light-emitting control sub-circuit 40, the driving transistor DTFT, the second light-emitting control sub-circuit 50, the light-emitting device LED, and the second power supply terminal VSS form a conducting loop. In this way, the light-emitting device LED emits light under the action of the driving current.

[0308] (8) The operation of the pixel driving circuit in Figure 30 is described below with reference to Figure 40. It is assumed that the pixel driving circuit in Figure 30 is operating in low frequency mode, and the first reset control signal terminal Reset1 and the third reset control signal terminal Reset3 are the same signal terminal:

[0309] Phase H1 of time sequence: EM1 = 1, EM2 = 1, Reset2 = 0, Reset2(n+1) = 1, Reset1 = 0, Reset3 = 0, Gate = 1

[0310] When the first reset control signal terminal Reset1 is low, the second switching transistor T2 is turned on. The signal from the first reset signal terminal Vinit1 is provided to the first terminal of the driving transistor DTFT via the turned-on second switching transistor T2, and then to the second terminal of the first capacitor C1, i.e., the first node N1, via the connected signal line. Thus, the voltage VN1 of the first node N1 is equal to Vinit1. When the second reset control signal terminal Reset2 is low, the eighth switching transistor T8 is turned on. The signal from the second reset signal terminal Vinit2 is provided to the first terminal of the first capacitor C1, i.e., the fourth node N4, and the control terminal of the driving transistor DTFT via the turned-on eighth switching transistor T8. Thus, the voltage VN4 of the fourth node N4 is equal to Vinit2. When the third reset control signal terminal Reset3 is low, the ninth switching transistor T9 is turned on. The signal from the third reset signal terminal Vinit3 is provided to the anode of the light-emitting device LED via the turned-on ninth switching transistor T9, thereby resetting the anode of the light-emitting device LED.

[0311] Phase H2: EM1 = 1, EM2 = 1, Reset2 = 0, Reset2(n+1) = 0, Reset1 = 1, Reset3 = 1, Gate = 1

[0312] When the signal at the second reset control signal terminal Reset2 is still low, the eighth switching transistor T8 is turned on. The signal at the second reset signal terminal Vinit2 is provided to the first terminal of the first capacitor C1 and the control terminal of the driving transistor DTFT via the turned-on eighth switching transistor T8. Thus, the voltage at the fourth node N4 is still VN4 = Vinit2. At the same time, when the signal at the second reset control signal terminal Reset2 in the next row is low, the tenth switching transistor T10 is turned on. The signal at the third reset signal terminal Vinit3 is provided to the second terminal of the driving transistor DTFT, i.e., the third node N3, via the turned-on tenth switching transistor T10. The driving transistor DTFT remains turned on under the action of the fourth reset sub-circuit 90. The driving transistor DTFT and the connecting sub-circuit 10 are connected. The voltage at the second terminal of the first capacitor C1, i.e., the first node N1, becomes VN1 = Vinit2 - Vth. That is, the threshold voltage Vth of the driving transistor DTFT is obtained in this timing sequence, and the threshold voltage Vth is stored in the first capacitor C1.

[0313] Phase H3 of time sequence: EM1=1, EM2=1, Reset2=1, Reset2(n+1)=0, Reset1=1, Reset3=1, Gate=1

[0314] The circuit conduction situation of this timing sequence is basically the same as that of the H2 timing sequence, so it will not be described again here.

[0315] Phase H4 of the sequence: EM1=1, EM2=1, Reset2=1, Reset2(n+1)=1, Reset1=1, Reset3=1, Gate=1

[0316] The circuit conduction situation of this timing sequence is basically the same as that of the H2 timing sequence, so it will not be described again here. In addition, it should be added that the existence of the above timing sequences H2, H3 and H4 effectively prolongs the threshold voltage compensation process.

[0317] H5 timing phase: EM1=1, EM2=1, Reset2=1, Reset2(n+1)=1, Reset1=1, Reset3=1, Gate=0

[0318] When the scan signal terminal Gate is low, the fourth switching transistor T4 is turned on. The data voltage at the data signal terminal Vdata is supplied to the fourth node N4 through the turned-on fourth switching transistor T4. Thus, the voltage at the fourth node N4 is Vdata. Under the action of the first capacitor C1, the voltage at the first node N1 becomes VN1 = Vinit2 - Vth + (C1 / (C1+C2))*(Vdata - Vinit2) = (C1 / (C1+C2))*Vdata + (C2 / (C1+C2))*Vinit2 - Vth. The corresponding drive current is I = k(Vgs - Vth). 2 = k(VN4-VN2-Vth) 2 =k(VDD+(Vdata-Vinit2)*(C2 / (C1+C2))+Vth-Vth) 2 =k((Vdata-Vinit2)*(C2 / (C1+C2))) 2 .

[0319] Phase H6 of time series: EM1 = 0, EM2 = 0, Reset2 = 1, Reset2(n+1) = 1, Reset1 = 1, Reset3 = 1, Gate = 1

[0320] When the signal of the first light-emitting control terminal EM1 is low, the fifth switching transistor T5 is turned on, and the first power supply terminal VDD is connected to the first terminal of the driving transistor DTFT through the turned-on fifth switching transistor T5. When the signal of the second light-emitting control terminal EM2 is low, the sixth switching transistor T6 is turned on, and the second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED through the turned-on sixth switching transistor T6. Thus, the first power supply terminal VDD, the first light-emitting control sub-circuit 40, the driving transistor DTFT, the second light-emitting control sub-circuit 50, the light-emitting device LED, and the second power supply terminal VSS form a conducting loop. In this way, the light-emitting device LED emits light under the action of the driving current.

[0321] (9) The operation of the pixel driving circuit in Figure 30 is described below with reference to Figure 41. It is assumed that the pixel driving circuit in Figure 30 operates in low frequency mode, and the example is that the (n-1)th frame is the refresh frame, the nth frame is the hold frame, and the (n+1)th frame is still the hold frame. The first reset control signal terminal Reset1 and the third reset control signal terminal Reset3 are the same signal terminal:

[0322] In frame (n-1): Timing h11 stage: EM1 = 1, EM2 = 1, Reset2 = 0, Reset2(n+1) = 1, Reset1 = 0, Reset3 = 0, Gate = 1

[0323] When the first reset control signal terminal Reset1 is low, the second switching transistor T2 is turned on. The signal from the first reset signal terminal Vinit1 is provided to the first terminal of the driving transistor DTFT via the turned-on second switching transistor T2, and then to the second terminal of the first capacitor C1, i.e., the first node N1, via the connected signal line. Thus, the voltage VN1 of the first node N1 is equal to Vinit1. When the second reset control signal terminal Reset2 is low, the eighth switching transistor T8 is turned on. The signal from the second reset signal terminal Vinit2 is provided to the first terminal of the first capacitor C1, i.e., the fourth node N4, and the control terminal of the driving transistor DTFT via the turned-on eighth switching transistor T8. Thus, the voltage VN4 of the fourth node N4 is equal to Vinit2. When the third reset control signal terminal Reset3 is low, the ninth switching transistor T9 is turned on. The signal from the third reset signal terminal Vinit3 is provided to the anode of the light-emitting device LED via the turned-on ninth switching transistor T9, thereby resetting the anode of the light-emitting device LED.

[0324] Timing stage h12: EM1=1, EM2=1, Reset2=0, Reset2(n+1)=0, Reset1=1, Reset3=1, Gate=1

[0325] When the signal at the second reset control signal terminal Reset2 is still low, the eighth switching transistor T8 is turned on. The signal at the second reset signal terminal Vinit2 is provided to the first terminal of the first capacitor C1 and the control terminal of the driving transistor DTFT via the turned-on eighth switching transistor T8. Thus, the voltage at the fourth node N4 is still VN4 = Vinit2. At the same time, when the signal at the second reset control signal terminal Reset2 in the next row is low, the tenth switching transistor T10 is turned on. The signal at the third reset signal terminal Vinit3 is provided to the second terminal of the driving transistor DTFT, i.e., the third node N3, via the turned-on tenth switching transistor T10. The driving transistor DTFT remains turned on under the action of the fourth reset sub-circuit 90. The driving transistor DTFT and the connecting sub-circuit 10 are connected. The voltage at the second terminal of the first capacitor C1, i.e., the first node N1, becomes VN1 = Vinit2 - Vth. That is, the threshold voltage Vth of the driving transistor DTFT is obtained in this timing sequence, and the threshold voltage Vth is stored in the first capacitor C1.

[0326] Timing stage h13: EM1=1, EM2=1, Reset2=1, Reset2(n+1)=0, Reset1=1, Reset3=1, Gate=1

[0327] The circuit conduction situation of this timing sequence is basically the same as that of the h12 timing sequence, so it will not be described again here.

[0328] Timing stage h14: EM1=1, EM2=1, Reset2=1, Reset2(n+1)=1, Reset1=1, Reset3=1, Gate=1

[0329] The circuit conduction situation of this timing sequence is basically the same as that of timing sequence h12, so it will not be described again here. In addition, it should be noted that compared with Figure 39, the effective duration of the above timing sequences h12, h13 and h14 is shorter, but the above effective duration ensures the compensation process of the threshold voltage in low frequency mode.

[0330] Timing stage h15: EM1=1, EM2=1, Reset2=1, Reset2(n+1)=1, Reset1=1, Reset3=1, Gate=0

[0331] When the scan signal terminal Gate is low, the fourth switching transistor T4 is turned on. The data voltage at the data signal terminal Vdata is supplied to the fourth node N4 through the turned-on fourth switching transistor T4. Thus, the voltage at the fourth node N4 is Vdata. Under the action of the first capacitor C1, the voltage at the first node N1 becomes VN1 = Vinit2 - Vth + (C1 / (C1+C2))*(Vdata - Vinit2) = (C1 / (C1+C2))*Vdata + (C2 / (C1+C2))*Vinit2 - Vth. The corresponding drive current is I = k(Vgs - Vth). 2 = k(VN4-VN2-Vth) 2 =k(VDD+(Vdata-Vinit2)*(C2 / (C1+C2))+Vth-Vth) 2 =k((Vdata-Vinit2)*(C2 / (C1+C2))) 2 .

[0332] Timing h16 stage: EM1=0, EM2=0, Reset2=1, Reset2(n+1)=1, Reset1=1, Reset3=1, Gate=1

[0333] When the signal of the first light-emitting control terminal EM1 is low, the fifth switching transistor T5 is turned on, and the first power supply terminal VDD is connected to the first terminal of the driving transistor DTFT through the turned-on fifth switching transistor T5. When the signal of the second light-emitting control terminal EM2 is low, the sixth switching transistor T6 is turned on, and the second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED through the turned-on sixth switching transistor T6. Thus, the first power supply terminal VDD, the first light-emitting control sub-circuit 40, the driving transistor DTFT, the second light-emitting control sub-circuit 50, the light-emitting device LED, and the second power supply terminal VSS form a conducting loop. In this way, the light-emitting device LED emits light under the action of the driving current.

[0334] In frame n: Timing h21 stage: EM1=1, EM2=1, Reset2=1, Reset2(n+1)=1, Reset1=0, Reset3=1, Gate=1

[0335] When the signal of the first reset control signal terminal Reset1 is low, the second switching transistor T2 is turned on. The signal of the first reset signal terminal Vinit1 is provided to the first terminal of the driving transistor DTFT through the turned-on second switching transistor T2, and then provided to the second terminal of the first capacitor C1, i.e. the first node N1, through the connected signal line. Thus, the voltage of the first node N1 VN1 = Vinit1.

[0336] Timing h22 stage: EM1=1, EM2=1, Reset2=1, Reset1=1, Reset3=1, Reset2(n+1)=1, Gate=1

[0337] This timing differs from the refresh frame. When the scan signal terminal Gate is high, it means that the scan signal terminal Gate is invalid and the data voltage of the driving transistor DTFT cannot be updated. Other details will not be elaborated further.

[0338] Timing stage h23: EM1=0, EM2=0, Reset2=1, Reset1=1, Reset3=1, Reset2(n+1)=1, Gate=1

[0339] When the signal of the first light-emitting control terminal EM1 is low, the fifth switching transistor T5 is turned on, and the first power supply terminal VDD is connected to the first terminal of the driving transistor DTFT through the turned-on fifth switching transistor T5. When the signal of the second light-emitting control terminal EM2 is low, the sixth switching transistor T6 is turned on, and the second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED through the turned-on sixth switching transistor T6. Thus, the first power supply terminal VDD, the first light-emitting control sub-circuit 40, the driving transistor DTFT, the second light-emitting control sub-circuit 50, the light-emitting device LED, and the second power supply terminal VSS form a conducting loop.

[0340] In frame n+1: the circuit conduction status of timing stage h31 is basically the same as that of timing stage h21, the circuit conduction status of timing stage h32 is basically the same as that of timing stage h22, and the circuit conduction status of timing stage h33 is basically the same as that of timing stage h23. These will not be described in detail here.

[0341] It should also be noted that the pixel driving circuits in the circuit diagrams shown in Figures 25, 26 and 27 can also operate in high-frequency mode and low-frequency mode. In this embodiment, only the specific timing operation state of the pixel driving circuits in Figures 25, 26 and 27 in high-frequency mode is described. The specific timing operation state of the pixel driving circuits in Figures 25, 26 and 27 in low-frequency mode will not be described in detail here.

[0342] Based on the same inventive concept, this disclosure provides a display device including any of the pixel driving circuits described above.

[0343] In this embodiment, the display device supports two display modes: a first display mode and a second display mode. It should be noted that the refresh rate of the display in the first display mode is higher than that in the second display mode. For example, the refresh rate in the first display mode is typically 60Hz or higher, such as 90Hz or 120Hz. The refresh rate in the second display mode is typically lower, such as 10Hz or 30Hz.

[0344] To ensure proper display of the image in both the first and second display modes, the following two methods can be used:

[0345] Method 1: The duration of the effective level of the signal at the second reset control signal terminal in the first display mode is greater than the duration of the effective level of the signal at the second reset control signal terminal in the second display mode.

[0346] During implementation, when the display screen is in the first display mode (high refresh rate display), in order to ensure the accuracy of the threshold voltage Vth of the driving transistor DTFT and the effectiveness of the data voltage writing, the duration of the effective level of the second reset control signal terminal in the first display mode is longer than that in the second display mode. For example, see Figure 36. Conversely, when the display screen is in the second display mode (low refresh rate display), the duration of the effective level of the second reset control signal terminal is shorter. For example, see Figure 37.

[0347] Method 2: In the second display mode, at least two adjacent frames include at least one refresh frame and at least one hold frame. The signal at the scan signal terminal corresponding to the refresh frame is valid during data voltage writing, while the signal at the scan signal terminal corresponding to the hold frame is invalid. The duration of the valid level of the second reset control signal terminal corresponding to the refresh frame is equal to or less than the duration of the valid level of the second reset control signal terminal in the first display mode.

[0348] During implementation, in the second display mode, where the refresh rate of the displayed image is low, a combination of refresh frames and hold frames can be used to display the image. In the aforementioned second display mode, the multiple frames displayed adjacent to each other include at least one refresh frame and at least one hold frame. It should be noted that the number of refresh frames and hold frames needs to be determined based on the specific refresh rate value.

[0349] The scan signal terminal corresponding to the refresh frame is valid during data voltage writing. This means that the scan signal terminal in the pixel driving circuit of each sub-pixel corresponding to the refresh frame is valid during data voltage writing, ensuring that the data voltage is written to the driving transistor DTFT in the current display frame and generates driving current, thereby driving the light-emitting device in the sub-pixel to emit light under the action of the driving current. Conversely, the scan signal terminal corresponding to the hold frame is invalid. This means that the scan signal terminal in the pixel driving circuit of each sub-pixel corresponding to the hold frame remains invalid. Consequently, the light-emitting device of the sub-pixel will not emit light during the time period corresponding to the hold frame. This hold frame setting effectively reduces the refresh rate of the display screen.

[0350] Furthermore, to ensure normal display of the image in the second display mode, the duration of the effective level of the second reset control signal corresponding to the aforementioned refresh frame can be equal to the duration of the effective level of the second reset control signal in the first display mode (i.e., high refresh rate mode), or the duration of the effective level of the second reset control signal can be less than the duration of the effective level of the second reset control signal in the first display mode (i.e., high refresh rate mode). During implementation, the specific value of the effective level of the second reset control signal needs to be determined by combining the specific refresh rate values ​​in both the first and second display modes.

[0351] Additionally, it should be noted that in some application scenarios, either method one or method two can be used, while in other application scenarios, method one and method two can be used in combination. The choice should be made flexibly based on the specific application scenario.

[0352] Furthermore, it should be noted that the above-mentioned display device also includes a gate driving circuit, wherein the gate driving circuit includes a reset gate driving sub-circuit and a light-emitting gate driving sub-circuit.

[0353] The output terminal of the reset gate driver sub-circuit is coupled to the first reset control signal terminal Reset1 and the third reset control signal terminal Reset3.

[0354] The output terminal of the light-emitting gate driver sub-circuit is coupled to the first light-emitting control terminal EM1 and the second light-emitting control terminal EM2.

[0355] To save on the number of shift register units, in this embodiment, the output of the reset gate drive sub-circuit is coupled to the first reset control signal terminal Reset1 and the third reset control signal terminal Reset3. The reset gate drive sub-circuit simultaneously provides signals to the first reset control signal terminal Reset1 and the third reset control signal terminal Reset3. That is, the shared signals of the first reset control signal terminal Reset1 and the third reset control signal terminal Reset3 can save one shift register unit.

[0356] Similarly, in the embodiments of this application, the output terminal of the light-emitting gate driving sub-circuit is coupled to the first light-emitting control terminal EM1 and the second light-emitting control terminal EM2. The output terminal of the light-emitting gate driving sub-circuit simultaneously provides signals to the first light-emitting control terminal EM1 and the second light-emitting control terminal EM2. That is, the shared signals of the first light-emitting control terminal EM1 and the second light-emitting control terminal EM2 can eliminate the need for a shift register unit.

[0357] The method described above, in which a single shift register unit provides signals to two signal terminals simultaneously, effectively reduces the number of shift register units required, which is beneficial for the layout of high-resolution pixels in display panels, especially small and medium-sized display panels.

[0358] In this embodiment of the invention, the display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the invention.

[0359] Based on the same inventive concept, this disclosure provides a driving method for a pixel driving circuit, as shown in Figure 42, including:

[0360] Step 201: Initialization phase: The first reset sub-circuit 20 responds to the signal of the first reset control signal terminal Reset1 by providing the signal of the first reset signal terminal Vinit1 to the first terminal of the driving transistor DTFT. The connecting sub-circuit 10 responds to the signal of the second reset control signal terminal Reset2 by connecting the first node N1 and the first terminal of the driving transistor DTFT. The second reset sub-circuit 70 responds to the signal of the second reset control signal terminal Reset2 by providing the signal of the second reset signal terminal Vinit2 to the first terminal of the first capacitor C1 and the control terminal of the driving transistor DTFT. The third reset sub-circuit 80 responds to the signal of the third reset control signal terminal Reset3 by providing the signal of the third reset signal terminal Vinit3 to the anode of the light-emitting device LED.

[0361] During implementation, the initialization phase mainly involves initializing the voltage across the first capacitor C1 and initializing the anode of the LED.

[0362] To initialize the voltage across the first capacitor C1, during implementation, the first reset sub-circuit 20, responding to the first reset control signal terminal Reset1, provides the signal Vinit1 from the first reset signal terminal Vinit1 to the first terminal of the driving transistor DTFT, meaning the voltage at the first terminal of the driving transistor DTFT is Vinit1. The connecting sub-circuit 10, responding to the second reset control signal terminal Reset2, connects the first node N1 and the first terminal of the driving transistor DTFT. Thus, the signal Vinit1 from the first reset signal terminal is provided to the first node N1 via the connecting sub-circuit 10, meaning the voltage at the second terminal of the first capacitor C1 is also Vinit1. The second reset sub-circuit 70, responding to the second reset control signal terminal Reset2, provides the signal Vinit2 from the second reset signal terminal Vinit2 to the first terminal of the first capacitor C1 and the control terminal of the driving transistor DTFT, meaning the voltage at both terminals of the first capacitor C1 and the control terminal of the driving transistor DTFT is Vinit2, thereby initializing the voltage across the first capacitor C1.

[0363] In order to initialize the anode of the LED, during the implementation process, the third reset sub-circuit 80 responds to the signal of the third reset control signal terminal Reset3 and provides the signal of the third reset signal terminal Vinit3 to the anode of the LED, that is, the voltage of the anode of the LED is initialized to Vinit3.

[0364] Step 202: Threshold Compensation Stage: In response to the signal at the conduction control terminal, the conduction control subcircuit 60 connects the control terminal of the driving transistor DTFT to the second terminal of the driving transistor DTFT. Simultaneously, in response to the signal at the second reset control signal terminal Reset2, the connection subcircuit 10 connects the first node N1 and the first terminal of the driving transistor DTFT, thus connecting the connection subcircuit 10, the driving transistor DTFT, and the conduction control subcircuit 60; or, in response to the signal at the second reset control signal terminal Reset2, the connection subcircuit 10 connects the first node N1 and the first terminal of the driving transistor DTFT, and the second light emission control subcircuit... In response to the signal from the second light-emitting control terminal EM2, circuit 50 connects the second terminal of the driving transistor DTFT to the anode of the light-emitting device LED. In response to the signal from the second reset control signal terminal Reset2, circuit 80 connects the third reset signal terminal Vinit3 to the anode of the light-emitting device LED. Under the action of the second light-emitting control circuit 50 and the third reset circuit 80, the driving transistor DTFT remains conducting, connecting sub-circuit 10 and the driving transistor DTFT. Alternatively, in response to the signal from the conduction control terminal, the conduction control sub-circuit 60 connects the control terminal of the driving transistor DTFT to the second terminal of the driving transistor DTFT. In one configuration, the connecting sub-circuit 10 responds to the signal of the second reset control signal terminal Reset2, connecting the first node N1 and the first terminal of the driving transistor DTFT, and connecting the connecting sub-circuit 10, the driving transistor DTFT, and the conduction control sub-circuit 60; or, the second light emission control sub-circuit 50 responds to the signal of the second light emission control terminal EM2, connecting the second terminal of the driving transistor DTFT and the anode of the light-emitting device LED, and the third reset sub-circuit 80 responds to the signal of the second reset control signal terminal Reset2, connecting the third reset signal terminal Vinit3 and the anode of the light-emitting device LED, and the driving transistor DTFT in the second configuration... Under the action of the second light-emitting control sub-circuit 50 and the third reset sub-circuit 80, the light-emitting control sub-circuit 50 remains conducting, and the connecting sub-circuit 10 connects the first node N1 and the first terminal of the driving transistor DTFT, and the driving transistor DTFT is connected to the connecting sub-circuit 10; or, in response to the signal of the second reset control signal terminal Reset2, the fourth reset sub-circuit 90 connects the third reset signal terminal Vinit3 and the second terminal of the driving transistor DTFT, and the connecting sub-circuit 10 connects the first node N1 and the first terminal of the driving transistor DTFT, and the driving transistor DTFT remains conducting under the action of the fourth reset sub-circuit 90, and the driving transistor DTFT is connected to the connecting sub-circuit 10;Furthermore, in response to the signal from the second reset control signal terminal Reset2, the second reset sub-circuit 70 provides the signal from the second reset signal terminal Vinit2 to the first terminal of the first capacitor C1 and the control terminal of the driving transistor DTFT, and the voltage of the first node N1 becomes the difference between the signal from the second reset signal terminal Vinit2 and the threshold voltage.

[0365] In this embodiment, during the threshold compensation stage, the second reset sub-circuit 70 responds to the signal of the second reset control signal terminal Reset2 by providing the signal of the second reset signal terminal Vinit2 to the first terminal of the first capacitor C1 and the control terminal of the driving transistor DTFT. That is, the voltage of the first terminal of the first capacitor C1 and the control terminal of the driving transistor DTFT is Vinit2. The voltage of the second terminal of the first capacitor C1, i.e., the first node N1, can be divided into five cases. That is, the specific process of obtaining the threshold voltage of the driving transistor DTFT can be divided into five cases:

[0366] In the first scenario: Referring to Figure 25, the conduction control sub-circuit 60 responds to the signal at the conduction control terminal by connecting the control terminal of the driving transistor DTFT to the second terminal of the driving transistor DTFT. Meanwhile, the connection sub-circuit 10 responds to the signal at the second reset control signal terminal Reset2 by connecting the first node N1 and the first terminal of the driving transistor DTFT. The voltage at the control terminal of the driving transistor DTFT and the first terminal of the first capacitor C1 remains Vinit2. Under the action of the second reset signal terminal Vinit2, the driving transistor DTFT is turned on, connecting the connection sub-circuit 10, the driving transistor DTFT, and the conduction control sub-circuit 60. The voltage at the first terminal of the driving transistor DTFT and the second terminal of the first capacitor C1 becomes Vinit2-Vth.

[0367] The second scenario: Referring to Figure 26, the connecting sub-circuit 10 (exemplarily, the first switching transistor T1) responds to the signal of the second reset control signal terminal Reset2, connecting the first node N1 and the first terminal of the driving transistor DTFT. The second light-emitting control sub-circuit 50 responds to the signal of the second light-emitting control terminal EM2, connecting the second terminal of the driving transistor DTFT and the anode of the light-emitting device LED. The third reset sub-circuit 80 responds to the signal of the second reset control signal terminal Reset2, connecting the third reset signal terminal Vinit3 and the anode of the light-emitting device LED. The driving transistor DTFT remains conducting under the action of the second light-emitting control sub-circuit 50 and the third reset sub-circuit 80. The connecting sub-circuit 10 and the driving transistor DTFT are connected. At the same time, the voltage of the control terminal of the driving transistor DTFT and the first terminal of the first capacitor C1 is still Vinit2, and the voltage of the first terminal of the driving transistor DTFT and the second terminal of the first capacitor C1 becomes Vinit2-Vth.

[0368] The third scenario: Referring to Figure 27, the conduction control sub-circuit 60 responds to the signal at the conduction control terminal, connecting the control terminal of the driving transistor DTFT with the second terminal of the driving transistor DTFT. The connecting sub-circuit 10 (exemplarily, the connecting signal line) connects the first node N1 and the first terminal of the driving transistor DTFT, i.e., the second node N2. The connecting sub-circuit 10, the driving transistor DTFT, and the conduction control sub-circuit 60 are connected. The driving transistor DTFT is turned on under the action of the signal at the second reset signal terminal Vinit2. The voltage at the control terminal of the driving transistor DTFT and the first terminal of the first capacitor C1 is still Vinit2, while the voltage at the first terminal of the driving transistor DTFT and the second terminal of the first capacitor C1 becomes Vinit2-Vth.

[0369] The fourth scenario: Referring to Figure 28, the second light-emitting control sub-circuit 50 responds to the signal of the second light-emitting control terminal EM2, connecting the second terminal of the driving transistor DTFT and the anode of the light-emitting device LED. The third reset sub-circuit 80 responds to the signal of the second reset control signal terminal Reset2, connecting the third reset signal terminal Vinit3 and the anode of the light-emitting device LED. The driving transistor DTFT remains conducting under the action of the second light-emitting control sub-circuit 50 and the third reset sub-circuit 80. The connecting sub-circuit 10 connects the first node N1 and the first terminal of the driving transistor DTFT. The driving transistor DTFT and the connecting sub-circuit 10 are connected. The voltage of the control terminal of the driving transistor DTFT and the first terminal of the first capacitor C1 is still Vinit2. The voltage of the first terminal of the driving transistor DTFT and the second terminal of the first capacitor C1 becomes Vinit2-Vth.

[0370] Fifth case: Referring to Figure 30, the fourth reset sub-circuit 90 responds to the signal of the second reset control signal terminal Reset2, connects the third reset signal terminal Vinit3 to the second terminal of the driving transistor DTFT, connects the first node N1 and the first terminal of the driving transistor DTFT to the connecting sub-circuit 10, and connects the driving transistor DTFT and the connecting sub-circuit 10. Under the action of the fourth reset sub-circuit 90, the driving transistor DTFT remains in the conducting state. The voltage of the control terminal of the driving transistor DTFT and the first terminal of the first capacitor C1 is still Vinit2, and the voltage of the first terminal of the driving transistor DTFT and the second terminal of the first capacitor C1 becomes Vinit2-Vth.

[0371] Step 203: Data writing stage: In response to the signal at the scan signal terminal Gate, the data writing sub-circuit 30 provides the data voltage at the data signal terminal Vdata to the control terminal of the first node N1 or the driving transistor DTFT.

[0372] In this embodiment, since the data writing sub-circuit 30 can be connected to either the first node N1 or the control terminal of the driving transistor DTFT, in one embodiment, when the signal at the scan signal terminal Gate is valid, the data writing sub-circuit 30 is turned on, providing the data voltage at the data signal terminal Vdata to the first node N1. The voltage of the first node N1 becomes Vdata, and under the action of the first capacitor C1, the voltage at the control terminal of the driving transistor DTFT, i.e., the fourth node N4, becomes Vdata+Vth. The corresponding driving current is I=k(Vgs-Vth). 2 = k(VN4-VN2-Vth) 2 = k(Vdata+Vth-VDD-Vth) 2 = k(Vdata-VDD) 2 .

[0373] In another embodiment, when the signal at the Gate terminal is valid, the data writing sub-circuit 30 is turned on, providing the data voltage at the Vdata terminal to the first terminal of the first capacitor C1 and the control terminal of the driving transistor DTFT, i.e., the voltage at the fourth node N4 is Vdata. Correspondingly, the voltage at the first node N1, VN1 = Vinit1 - Vth + (C1 / (C1+C2))*(Vdata - Vinit1) = (C1 / (C1+C2))*Vdata + (C2 / (C1+C2))*Vinit1 - Vth, and the corresponding driving current is I = k(Vgs - Vth). 2 = k(VN4-VN2-Vth) 2 =k(VDD+(Vdata-Vinit2)*(C2 / (C1+C2))+Vth-Vth) 2 =k((Vdata-Vinit2)*(C2 / (C1+C2))) 2 .

[0374] Step 204: Light emission stage: In response to the signal of the first light emission control terminal EM1, the first light emission control sub-circuit 40 turns on the first power supply terminal VDD and the first terminal of the driving transistor DTFT, and in response to the signal of the second light emission control terminal EM2, the second light emission control sub-circuit 50 turns on the second terminal of the driving transistor DTFT and the anode of the light emission device LED.

[0375] During implementation, the first light-emitting control sub-circuit 40 responds to the signal of the first light-emitting control terminal EM1 and conducts the first power supply terminal VDD and the first terminal of the driving transistor DTFT. In addition, the second light-emitting control sub-circuit 50 responds to the signal of the second light-emitting control terminal EM2 and conducts the second terminal of the driving transistor DTFT and the anode of the light-emitting device LED. This forms a conducting loop with the first power supply terminal VDD, the first light-emitting control sub-circuit 40, the driving transistor DTFT, the second light-emitting control sub-circuit 50, the light-emitting device LED, and the second power supply terminal VSS. Thus, the light-emitting device LED emits light under the action of the driving current.

[0376] In summary, the present disclosure provides a pixel driving circuit, display device, and driving method. The pixel driving circuit includes: a light-emitting device, a driving transistor, a first capacitor, a second capacitor, a connecting sub-circuit, a first reset sub-circuit, and a data writing sub-circuit. The driving transistor is coupled to the light-emitting device. The first capacitor is coupled between the control terminal of the driving transistor and a first node. The second capacitor is coupled between the first node and a first power supply terminal. The connecting sub-circuit is coupled between the first node and a first terminal of the driving transistor and configured to connect the first node and the first terminal of the driving transistor. The first reset sub-circuit is coupled to the first terminal of the driving transistor and configured to connect the first... The data writing sub-circuit is coupled to the control terminal of the first node or driving transistor and is configured to provide the data voltage of the data signal terminal to the control terminal of the first node or driving transistor in response to the signal of the scan signal terminal. The above-mentioned connection sub-circuit and the first reset sub-circuit enable the pixel driving circuit to achieve VRR function without the Vref DC power, effectively improving the current stability of the light-emitting device in the pixel driving circuit. At the same time, it ensures the separate execution of threshold voltage acquisition and data voltage writing, and to a certain extent saves the number of transistors and shift register units, which is beneficial to the layout of high-resolution pixels of the display panel.

[0377] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program product systems. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product system implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0378] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program product systems according to this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0379] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0380] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0381] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A pixel driving circuit, wherein, include: Light-emitting devices; A driving transistor is coupled to the light-emitting device; The first capacitor is coupled between the control terminal of the driving transistor and the first node; The second capacitor is coupled between the first node and the first power supply terminal; A connecting sub-circuit, coupled between the first node and the first terminal of the driving transistor, is configured to connect the first node and the first terminal of the driving transistor; A first reset sub-circuit, coupled to the first terminal of the driving transistor, is configured to connect the first terminal of the driving transistor and the first reset signal terminal; The data writing sub-circuit, coupled to the control terminal of the first node or the driving transistor, is configured to provide the data voltage of the data signal terminal to the control terminal of the first node or the driving transistor in response to a signal at the scan signal terminal.

2. The pixel driving circuit as described in claim 1, wherein, The connected sub-circuit includes: a first switching transistor; The control terminal of the first switching transistor is coupled to the second reset control signal terminal, the first terminal of the first switching transistor is coupled to the first node, and the second terminal of the first switching transistor is coupled to the first terminal of the driving transistor.

3. The pixel driving circuit as described in claim 1, wherein, The connected sub-circuit includes: a connected signal line; The first end of the connecting signal line is coupled to the first node, and the second end of the connecting signal line is coupled to the first end of the driving transistor.

4. The pixel driving circuit as described in claim 1, wherein, The first reset circuit includes: a second switching transistor; The control terminal of the second switching transistor is coupled to the first reset control signal terminal, the first terminal of the second switching transistor is coupled to the first terminal of the driving transistor, and the second terminal of the second switching transistor is coupled to the first reset signal terminal.

5. The pixel driving circuit according to any one of claims 1 to 4, wherein, The data writing sub-circuit includes: a third switching transistor; The control terminal of the third switching transistor is coupled to the scan signal terminal, the first terminal of the third switching transistor is coupled to the data signal terminal, and the second terminal of the third switching transistor is coupled to the first node.

6. The pixel driving circuit according to any one of claims 1 to 4, wherein, The data writing sub-circuit includes: a fourth switching transistor; The control terminal of the fourth switching transistor is coupled to the scan signal terminal, the first terminal of the fourth switching transistor is coupled to the data signal terminal, and the second terminal of the fourth switching transistor is coupled to the control terminal of the driving transistor.

7. The pixel driving circuit according to any one of claims 1 to 6, wherein, Also includes: A first light-emitting control sub-circuit is coupled between the first terminal of the driving transistor and the first power supply terminal, and is configured to connect the first terminal of the driving transistor and the first power supply terminal. The first light-emitting control sub-circuit includes: a fifth switching transistor; The control terminal of the fifth switching transistor is coupled to the first light-emitting control terminal, the first terminal of the fifth switching transistor is coupled to the first power supply terminal, and the second terminal of the fifth switching transistor is coupled to the first terminal of the driving transistor.

8. The pixel driving circuit according to any one of claims 1 to 7, wherein, Also includes: The second light-emitting control sub-circuit is coupled between the second terminal of the driving transistor and the anode of the light-emitting device, and is configured to connect the second terminal of the driving transistor and the anode of the light-emitting device; The second light-emitting control sub-circuit includes: a sixth switching transistor; The control terminal of the sixth switching transistor is coupled to the second light-emitting control terminal, the first terminal of the sixth switching transistor is coupled to the second terminal of the driving transistor, and the second terminal of the sixth switching transistor is coupled to the anode of the light-emitting device.

9. The pixel driving circuit according to any one of claims 1 to 8, wherein, Also includes: A conduction control sub-circuit, coupled between the control terminal and the second terminal of the driving transistor, is configured to connect the control terminal and the second terminal of the driving transistor.

10. The pixel driving circuit as described in claim 9, wherein, The conduction control sub-circuit includes: a seventh switching transistor; The control terminal of the seventh switching transistor is coupled to the second reset control signal terminal, the first terminal of the seventh switching transistor is coupled to the control terminal of the driving transistor, and the second terminal of the seventh switching transistor is coupled to the second terminal of the driving transistor.

11. The pixel driving circuit according to any one of claims 1 to 10, wherein, Also includes: The second reset sub-circuit, coupled to the first terminal of the first capacitor and the control terminal of the driving transistor, is configured to connect the second reset signal terminal to the first terminal of the first capacitor and the control terminal of the driving transistor.

12. The pixel driving circuit as described in claim 11, wherein, The second reset circuit includes: an eighth switching transistor; The control terminal of the eighth switching transistor is coupled to the second reset control signal terminal, the first terminal of the eighth switching transistor is coupled to the second reset signal terminal, and the second terminal of the eighth switching transistor is coupled to the first terminal of the first capacitor and the control terminal of the driving transistor.

13. The pixel driving circuit according to any one of claims 1 to 12, wherein, Also includes: The third reset sub-circuit, coupled to the anode of the light-emitting device, is configured to connect the third reset signal terminal to the anode of the light-emitting device; The third reset circuit includes: a ninth switching transistor; The control terminal of the ninth switching transistor is coupled to the third reset control signal terminal, the first terminal of the ninth switching transistor is coupled to the anode of the light-emitting device, and the second terminal of the ninth switching transistor is coupled to the third reset signal terminal.

14. The pixel driving circuit according to any one of claims 2 to 13, wherein, Also includes: The fourth reset sub-circuit, coupled to the second terminal of the driving transistor, is configured to connect the third reset signal terminal to the second terminal of the driving transistor; The fourth reset sub-circuit includes: a tenth switching transistor; The control terminal of the tenth switching transistor is coupled to the second reset control signal terminal, the first terminal of the tenth switching transistor is coupled to the second terminal of the driving transistor, and the second terminal of the tenth switching transistor is coupled to the third reset signal terminal.

15. The pixel driving circuit as described in claim 8, wherein, The second light-emitting control terminal and the first light-emitting control signal terminal are the same signal terminal.

16. The pixel driving circuit as described in claim 13, wherein, The third reset control signal terminal and the first reset control signal terminal are the same signal terminal; or The third reset control signal terminal and the second reset control signal terminal are the same signal terminal.

17. A display device, wherein, include: The pixel driving circuit as described in any one of claims 1 to 16.

18. The display device as claimed in claim 17, wherein, The duration of the effective level of the signal at the second reset control signal terminal in the first display mode is greater than the duration of the effective level of the signal at the second reset control signal terminal in the second display mode; and / or In the second display mode, at least two adjacent frames include at least one refresh frame and at least one hold frame. The duration of the effective level of the signal at the second reset control signal terminal corresponding to the refresh frame is equal to or less than the duration of the effective level of the signal at the second reset control signal terminal in the first display mode. The signal at the scan signal terminal corresponding to the refresh frame is valid when data voltage is written, and the signal at the scan signal terminal corresponding to the hold frame is invalid. In the first display mode, the refresh rate of the displayed image is higher than that in the second display mode.

19. A driving control method applied to a pixel driving circuit as described in any one of claims 1 to 16, wherein, include: Initialization phase: The first reset sub-circuit responds to the signal of the first reset control signal terminal and provides the signal of the first reset signal terminal to the first terminal of the driving transistor; the connecting sub-circuit responds to the signal of the second reset control signal terminal and connects the first node and the first terminal of the driving transistor; the second reset sub-circuit responds to the signal of the second reset control signal terminal and provides the signal of the second reset signal terminal to the first terminal of the first capacitor and the control terminal of the driving transistor; and the third reset sub-circuit responds to the signal of the third reset control signal terminal and provides the signal of the third reset signal terminal to the anode of the light-emitting device. Threshold compensation phase: The conduction control subcircuit responds to the signal at the conduction control terminal, connecting the control terminal of the driving transistor to the second terminal of the driving transistor. Simultaneously, the connection subcircuit responds to the signal at the second reset control signal terminal, connecting the first node and the first terminal of the driving transistor, thus connecting the connection subcircuit, the driving transistor, and the conduction control subcircuit; or, the connection subcircuit responds to the signal at the second reset control signal terminal, connecting the first node and the first terminal of the driving transistor; the second light emission control subcircuit responds to the signal at the second light emission control terminal, connecting the second terminal of the driving transistor and the anode of the light-emitting device; the third reset subcircuit responds to the signal at the second reset control signal terminal, connecting the third reset signal terminal and the anode of the light-emitting device; the driving transistor remains conducting under the action of the second light emission control subcircuit and the third reset subcircuit, thus connecting the connection subcircuit and the driving transistor; or, the conduction control subcircuit responds to the signal at the conduction control terminal, connecting the control terminal of the driving transistor to the second terminal of the driving transistor; the connection subcircuit responds to the signal at the second reset control signal terminal, connecting the first node and the driving transistor... Firstly, the connecting sub-circuit, the driving transistor, and the conduction control sub-circuit are connected; or, the second light-emitting control sub-circuit responds to the signal of the second light-emitting control terminal by connecting the second terminal of the driving transistor and the anode of the light-emitting device, and the third reset sub-circuit responds to the signal of the second reset control signal terminal by connecting the third reset signal terminal and the anode of the light-emitting device. The driving transistor remains conducting under the action of the second light-emitting control sub-circuit and the third reset sub-circuit, and the connecting sub-circuit connects the first node and the first terminal of the driving transistor, thus connecting the driving transistor and the connecting sub-circuit; or, the fourth reset sub-circuit responds to the signal of the second reset control signal terminal by connecting the third reset signal terminal and the second terminal of the driving transistor, and the connecting sub-circuit connects the first node and the first terminal of the driving transistor. The driving transistor remains conducting under the action of the fourth reset sub-circuit, thus connecting the driving transistor and the connecting sub-circuit; and the second reset sub-circuit responds to the signal of the second reset control signal terminal by providing the signal of the second reset signal terminal to the first terminal of the first capacitor and the control terminal of the driving transistor, and the voltage of the first node becomes the difference between the signal of the second reset signal terminal and the threshold voltage; Data writing stage: The data writing sub-circuit responds to the signal at the scan signal terminal by providing the data voltage at the data signal terminal to the first node or the control terminal of the driving transistor; Light emission stage: In response to the signal at the first light emission control signal terminal, the first light emission control sub-circuit turns on the first power supply terminal and the first terminal of the driving transistor, and in response to the signal at the second light emission control terminal, the second light emission control sub-circuit turns on the second terminal of the driving transistor and the anode of the light emission device.

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