Array substrate, display panel, and display apparatus

Abstract

The present application provides an array substrate, a display panel and a display apparatus. The array substrate comprises a substrate, an active layer, a first conductive layer and a second conductive layer. A first conductive portion in the second conductive layer is a laminated structure composed of a first sub-conductive portion and a second sub-conductive portion, and the active layer is connected to a source electrode or a drain electrode at least by means of the first conductive portion. The light transmittance of the first conductive layer is less than the light transmittance of the second conductive layer.

Description

Array substrate, display panel and display device

[0001] This application claims priority to Chinese patent application No. 202510487549.6, filed on April 17, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0003] Liquid crystal display (LCD) panels are widely used in various consumer electronics products such as mobile phones, televisions, personal digital assistants (PDAs), digital cameras, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body, and wide range of applications, becoming the mainstream display device. There are two types of LCD panels: amorphous silicon and low-temperature polycrystalline silicon (LTPS). LTPS LCD panels, due to their high mobility, are widely used in high-specification LCD panels. Invention Overview

[0004] Currently, the source and drain electrodes of display panels are made of metal. While metal has low contact resistance with the active layer, its low light transmittance affects the overall light transmittance of the display panel. Transparent conductive materials possess good conductivity and light transmittance, but their sheet resistance is higher than that of metals. This results in higher contact resistance between the transparent conductive material and the active layer, leading to a work function mismatch between the active layer and the transparent conductive material. If transparent conductive materials are used instead of metals to fabricate the source and drain electrodes, it can cause current-limiting problems in thin-film transistor devices.

[0005] Therefore, it is necessary to provide an array substrate, a display panel, and a display device to improve this defect.

[0006] In a first aspect, embodiments of this application provide an array substrate, comprising:

[0007] Substrate;

[0008] An active layer is disposed on one side of the substrate;

[0009] A first conductive layer is disposed on the side of the active layer away from the substrate, and the first conductive layer includes at least one of a source and a drain.

[0010] The second conductive layer is disposed on the side of the active layer away from the substrate, and the transmittance of the first conductive layer is less than that of the second conductive layer.

[0011] The second conductive layer includes a first conductive portion, which includes a first sub-conductive portion and a second sub-conductive portion. The second sub-conductive portion is disposed on the surface of the first sub-conductive portion away from the substrate. The conductivity of the first sub-conductive portion is greater than that of the second sub-conductive portion. The active layer is connected to the source or the drain through the first conductive portion.

[0012] Secondly, embodiments of this application provide a display panel including the array substrate as described above.

[0013] Thirdly, embodiments of this application provide a display device, including the display panel as described above. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments disclosed. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 is a schematic diagram of the structure of the first array substrate provided in the embodiment of this application;

[0016] Figures 2a to 2d are schematic diagrams of the fabrication process of the first array substrate provided in the embodiments of this application;

[0017] Figure 3 is a schematic diagram of the structure of the second array substrate provided in the embodiments of this application;

[0018] Figure 4 is a schematic diagram of the structure of the third array substrate provided in the embodiments of this application;

[0019] Figures 5a to 5e are schematic diagrams of the fabrication process of the third type of array substrate provided in the embodiments of this application;

[0020] Figure 6 is a schematic diagram of the structure of the display panel provided in an embodiment of this application;

[0021] Figure 7 is a schematic diagram of a display device provided in an embodiment of this application. Embodiments of the present invention

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0023] In the description of this application, it should be understood that the terms "upper," "lower," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0024] Reference numerals and / or reference letters may be repeated in different embodiments of this application. Such repetition is for the purpose of simplification and clarity and does not in itself indicate the relationship between the various implementations and / or settings discussed.

[0025] The embodiments of this application provide an array substrate, a display panel, and a display device, which can improve the light transmittance and stability of the display panel.

[0026] To achieve the above objectives, according to a first aspect of this application, an array substrate is provided, comprising:

[0027] Substrate;

[0028] An active layer is disposed on one side of the substrate;

[0029] A first conductive layer is disposed on the side of the active layer away from the substrate, and the first conductive layer includes at least one of a source and a drain.

[0030] The second conductive layer is disposed on the side of the active layer away from the substrate, and the transmittance of the first conductive layer is less than that of the second conductive layer.

[0031] The second conductive layer includes a first conductive portion, which includes a first sub-conductive portion and a second sub-conductive portion. The second sub-conductive portion is disposed on the surface of the first sub-conductive portion away from the substrate. The conductivity of the first sub-conductive portion is greater than that of the second sub-conductive portion. The active layer is connected to the source or the drain through the first conductive portion.

[0032] Optionally, the array substrate further includes a third conductive layer, which is disposed in a different layer from the second conductive layer;

[0033] The second conductive layer includes a first electrode, and the third conductive layer includes a second electrode. The first electrode is one of a common electrode and a pixel electrode, and the second electrode is the other of the common electrode and the pixel electrode.

[0034] Optionally, the first electrode includes a first sub-electrode portion and a second sub-electrode portion, the second sub-electrode portion being disposed on the surface of the first sub-electrode portion away from the substrate, the first sub-electrode portion being made of the same material as the first sub-conductive portion, and the second sub-electrode portion being made of the same material as the second sub-conductive portion.

[0035] Optionally, the second conductive layer is disposed on the side of the first conductive layer away from the substrate, and a first hole is provided between the second conductive layer and the active layer, and the first sub-conductive portion of the first conductive part is connected to the active layer through the first hole; a second hole is provided between the second conductive layer and the first conductive layer, and the second hole is spaced apart from the first hole, and the first sub-conductive portion of the first conductive part is connected to the source or the drain through the second hole.

[0036] Optionally, the array substrate further includes:

[0037] A gate insulating layer is disposed on the surface of the active layer away from the substrate;

[0038] An interlayer dielectric layer is disposed on the surface of the gate insulating layer away from the substrate; a first conductive layer is at least partially disposed on the surface of the interlayer dielectric layer away from the substrate; and a third conductive layer is at least partially disposed on the surface of the interlayer dielectric layer away from the substrate.

[0039] A passivation layer is disposed on the surface of the interlayer dielectric layer and the first conductive layer away from the substrate, and a second conductive layer is disposed on the surface of the passivation layer away from the substrate;

[0040] The first hole penetrates the passivation layer, the interlayer dielectric layer, and the gate insulating layer, while the second hole penetrates the passivation layer.

[0041] Optionally, the first conductive layer includes a second conductive portion, which is connected to the second electrode;

[0042] The second conductive portion is disposed on the surface of the second electrode away from the substrate.

[0043] Optionally, the first conductive layer includes a second conductive portion, which is connected to the second electrode;

[0044] The second electrode portion is disposed on the surface of the second conductive portion away from the substrate.

[0045] Optionally, the second conductive layer is disposed on the side of the first conductive layer close to the substrate, the third conductive layer is disposed on the side of the first conductive layer away from the substrate, and the active layer is sequentially connected to the source or the drain through the first sub-conductive portion and the second sub-conductive portion of the first conductive portion.

[0046] Optionally, the first conductive layer is disposed on the surface of the second sub-conductive portion away from the substrate.

[0047] Optionally, the orthographic projection of the first conductive layer onto the second conductive layer is located within the second conductive layer.

[0048] Optionally, the array substrate further includes:

[0049] A gate insulating layer is disposed on the surface of the active layer away from the substrate;

[0050] An interlayer dielectric layer is disposed on the surface of the gate insulating layer away from the substrate, and a second conductive layer is disposed on the surface of the interlayer dielectric layer away from the substrate; and

[0051] A passivation layer is disposed on the surfaces of the interlayer dielectric layer, the first conductive layer, and the second conductive layer away from the substrate, and a third conductive layer is disposed on the surface of the passivation layer away from the substrate.

[0052] Wherein, a first hole is provided between the second conductive layer and the active layer, the first hole penetrates the passivation layer and the interlayer dielectric layer, and the first sub-conductive part of the first conductive part is connected to the active layer through the first hole.

[0053] Optionally, the transmittance of the first sub-conductive portion is less than the transmittance of the second sub-conductive portion.

[0054] Optionally, the thickness of the first sub-conductive portion is less than the thickness of the second sub-conductive portion.

[0055] Optionally, the thickness of the first sub-conductive portion is less than or equal to 300 angstroms, and the thickness of the second sub-conductive portion is greater than or equal to 300 angstroms and less than or equal to 1000 angstroms.

[0056] Optionally, the thickness of the first sub-conductive portion is greater than or equal to 30 angstroms and less than or equal to 80 angstroms.

[0057] Optionally, the material of the first sub-conductive portion includes a metal or a mixture of a metal and a metal oxide, and the material of the second sub-conductive portion includes a transparent conductive oxide.

[0058] Optionally, the diffusion coefficient of the material of the first sub-conductive portion is less than the diffusion coefficient of the material of the second sub-conductive portion, and the diffusion coefficient of the material of the second sub-conductive portion is less than the diffusion coefficient of the material of the first conductive layer.

[0059] According to a second aspect of this application, a display panel is provided, comprising an array substrate as described above.

[0060] According to a third aspect of this application, a display device is provided, including a display panel as described above.

[0061] In the array substrate of this application embodiment, by setting the first conductive portion in the second conductive layer as a stacked structure composed of a first sub-conductive portion and a second sub-conductive portion, and connecting the active layer to the source or drain through the first conductive portion, since the transmittance of the first conductive layer is less than that of the second conductive layer, the active layer can be connected to the source or drain by using the second conductive layer with higher transmittance, thereby reducing the arrangement area of ​​the first conductive layer and improving the overall transmittance of the array substrate. Since the conductivity of the first sub-conductive portion is greater than that of the second sub-conductive portion, the contact impedance between the first conductive portion and the active layer can be reduced, avoiding the current limiting problem, thereby improving the stability of the display panel.

[0062] An embodiment of this application provides an array substrate, which includes a substrate, an active layer, a first conductive layer, and a second conductive layer. The active layer is disposed on one side of the substrate, and the first conductive layer is disposed on the side of the active layer away from the substrate. The first conductive layer includes at least one of a source and a drain. The second conductive layer is disposed on the side of the active layer away from the substrate. The transmittance of the first conductive layer is less than that of the second conductive layer. The second conductive layer includes a first conductive portion, which includes a first sub-conductive portion and a second sub-conductive portion. The second sub-conductive portion is disposed on the surface of the first sub-conductive portion away from the substrate. The conductivity of the first sub-conductive portion is greater than that of the second sub-conductive portion. The active layer is connected to the source or drain through the first conductive portion.

[0063] In the embodiments of this application, by setting the first conductive portion in the second conductive layer as a stacked structure composed of a first sub-conductive portion and a second sub-conductive portion, and by connecting the active layer to the source or drain at least through the first sub-conductive portion of the first conductive layer, since the transmittance of the first conductive layer is less than that of the second conductive layer, the active layer can be connected to the source or drain by using the second conductive layer with higher transmittance, thereby reducing the arrangement area of ​​the first conductive layer and thus improving the overall transmittance of the array substrate. Since the conductivity of the first sub-conductive portion is greater than that of the second sub-conductive portion, the contact impedance between the first conductive portion and the active layer can be reduced, avoiding the current limiting problem, thereby improving the stability of the thin-film transistor device in the array substrate.

[0064] Please refer to Figure 1, which is a schematic diagram of the structure of a first array substrate provided in an embodiment of this application. The array substrate 10 includes a substrate 1, an active layer 2, a first conductive layer 3, and a second conductive layer 4. The active layer 2 is disposed on one side of the substrate 1, and the first conductive layer 3 is disposed on the side of the active layer 2 away from the substrate 1. The first conductive layer 3 includes at least one of a source electrode 31 and a drain electrode 32. The second conductive layer 4 is disposed on the side of the active layer 2 away from the substrate 1. The transmittance of the first conductive layer 3 is less than the transmittance of the second conductive layer 4. The second conductive layer 4 includes a first conductive portion 41, which includes a first sub-conductive portion 411 and a second sub-conductive portion 412. The conductivity of the first sub-conductive portion 411 is greater than the conductivity of the second sub-conductive portion 412. The active layer 2 is connected to the source electrode 31 or the drain electrode 32 at least through the first sub-conductive portion 411 of the first conductive portion 41.

[0065] In the embodiments of this application, by setting the first conductive portion 41 in the second conductive layer 4 as a stacked structure composed of a first sub-conductive portion 411 and a second sub-conductive portion 412, and by connecting the active layer 2 to the source 31 or drain 32 at least through the first sub-conductive portion 411 of the first conductive portion 41, since the transmittance of the first conductive layer 3 is less than that of the second conductive layer 4, the active layer 2 can be connected to the source 31 or drain 32 by using the second conductive layer 4 with higher transmittance, thereby reducing the arrangement area of ​​the first conductive layer 3 and improving the overall transmittance of the array substrate. Since the conductivity of the first sub-conductive portion 411 is greater than that of the second sub-conductive portion 412, the contact impedance between the first conductive portion 41 and the active layer 2 can be reduced, avoiding the problem of current limiting, thereby improving the stability of the thin film transistor device in the array substrate.

[0066] In some embodiments, referring to FIG1, the array substrate 10 further includes a third conductive layer 5, which is disposed separately from the second conductive layer 4. The second conductive layer 4 includes a first electrode 42, and the third conductive layer 5 includes a second electrode 51. The first electrode 42 is one of a common electrode and a pixel electrode, and the second electrode is the other of a common electrode and a pixel electrode. The first electrode 42 and the second electrode 51 together form an electric field for driving the rotation of liquid crystal molecules.

[0067] Referring to Figure 1, the first conductive part 41 and the first electrode 42 are disposed in the same layer. The first conductive part 41 and the first electrode 42 are made of the same material. The first conductive part 41 can be formed simultaneously using the same process as the first electrode 42, thus avoiding the need to increase the film layer structure and related processes of the display panel. By using the first conductive part 41 with high light transmittance to connect the active layer 2 to the source electrode 31 or the drain electrode 32, not only can the arrangement area of ​​the first conductive layer 3 with low light transmittance be reduced, thereby improving the overall light transmittance of the array substrate, but also the need to avoid making openings in the insulating layer between the first conductive layer 3 and the active layer 2 can be avoided, thus saving a photomask and reducing production costs.

[0068] In some embodiments, referring to FIG1, the first electrode 42 is a pixel electrode and the second electrode 51 is a common electrode. In other embodiments, the first electrode 42 is a common electrode and the second electrode 51 is a pixel electrode.

[0069] In some embodiments, referring to FIG1, the transmittance of the first sub-conductive portion 411 is less than the transmittance of the second sub-conductive portion 412. By making the transmittance of the first sub-conductive portion 411 less than the transmittance of the second sub-conductive portion 412, the overall transmittance of the first conductive portion 41 can be improved. This can prevent current limiting problems in the thin-film transistor devices within the array substrate, improve the stability of the thin-film transistor devices, and simultaneously increase the overall transmittance of the array substrate.

[0070] In some embodiments, referring to FIG1, the thickness of the first sub-conductive portion 411 is less than the thickness of the second sub-conductive portion 412. It should be noted that if the thickness of the first sub-conductive portion 411 is too large, it will affect the overall light transmittance of the second conductive layer 4, resulting in a decrease in the overall light transmittance of the array substrate. By making the thickness of the first sub-conductive portion 411 less than the thickness of the second sub-conductive portion 412, the light transmittance of the second conductive layer 4 is ensured to be greater than the light transmittance of the first conductive layer 3, thereby increasing the overall light transmittance of the array substrate.

[0071] In some embodiments, referring to FIG1, the thickness of the first sub-conductive portion 411 is less than or equal to 300 angstroms, and the thickness of the second sub-conductive portion 412 is greater than or equal to 300 angstroms and less than or equal to 1000 angstroms. For example, the thickness of the first sub-conductive portion 411 is 10 angstroms, 20 angstroms, 30 angstroms, 60 angstroms, 100 angstroms, 150 angstroms, 200 angstroms, 250 angstroms, or 300 angstroms, etc. The thickness of the second sub-conductive portion 412 is 300 angstroms, 500 angstroms, 700 angstroms, 900 angstroms, or 1000 angstroms, etc.

[0072] It should be noted that, since the transmittance of the first sub-conductive portion 411 is lower than that of the second sub-conductive portion 412, when the thickness of the first sub-conductive portion 411 is greater than 300 angstroms, the transmittance of the first conductive portion 411 will be significantly reduced, affecting the overall transmittance of the array substrate. When the thickness of the second sub-conductive portion 412 is less than 300 angstroms, the impedance of the second sub-conductive portion 412 is too high. When the thickness of the second sub-conductive portion 412 exceeds 1000 angstroms, the transmittance of the second sub-conductive portion 412 will decrease, leading to a decrease in the overall transmittance of the array substrate. Therefore, limiting the thickness of the first sub-conductive portion 411 to within 300 angstroms and the thickness of the second sub-conductive portion 412 to between 300 and 1000 angstroms not only allows the first conductive portion 41 to have a lower impedance, thereby improving the stability of the thin-film transistor devices within the array substrate, but also improves the overall transmittance of the array substrate.

[0073] In some embodiments, the thickness of the first sub-conductive portion 411 is greater than or equal to 30 angstroms and less than or equal to 80 angstroms. It should be noted that when the thickness of the first sub-conductive portion 411 is less than 30 angstroms, the film uniformity of the first sub-conductive portion 411 is poor, and the contact impedance between the first sub-conductive portion 411 and the active layer 2 is relatively large. Therefore, by limiting the thickness of the first sub-conductive portion 411 to between 30 and 80 angstroms, not only can the contact impedance between the first sub-conductive portion 411 and the active layer 2 be reduced, but the thickness of the first sub-conductive portion 411 can also be reduced, thereby further improving the overall light transmittance of the array substrate.

[0074] In some embodiments, the material of the first sub-conductive portion 411 includes a metal or a mixture of a metal and a metal oxide.

[0075] In some embodiments, the material of the first sub-conductive part 411 includes metal. Specifically, the material of the first sub-conductive part 411 may include any pure metal material such as molybdenum, titanium, and tungsten, or may include titanium-tungsten alloy or other alloy materials.

[0076] In some embodiments, the material of the first sub-conductive portion 411 can be a mixture of metal and metal oxide. For example, the material of the first sub-conductive portion 411 can be a mixture of molybdenum and molybdenum oxide, a mixture of titanium and titanium oxide, or a mixture of tungsten and tungsten oxide. It should be noted that since metal materials such as molybdenum, titanium, and tungsten are prone to oxidation during the preparation process, a small amount of metal oxide will be formed in the final first sub-conductive portion 411.

[0077] In some embodiments, the material of the second sub-conductive portion 412 includes a transparent conductive oxide. Specifically, the material of the second sub-conductive portion 412 may include any one of transparent conductive oxides such as indium tin oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, and indium tin zinc oxide.

[0078] In some embodiments, the diffusion coefficient of the material of the first sub-conductive portion 411 is less than the diffusion coefficient of the material of the second sub-conductive portion 412, and the diffusion coefficient of the material of the second sub-conductive portion 412 is less than the diffusion coefficient of the material of the first conductive layer 3. It should be noted that since the first sub-conductive portion 411 is in direct contact with the active layer 2, the larger the diffusion coefficient of the first sub-conductive portion 411, the weaker its ion-blocking ability. Ions can more easily enter the active layer 2 from the first sub-conductive portion 411, leading to a higher risk of thin-film transistor device failure. This embodiment, by making the diffusion coefficient of the material of the first sub-conductive portion 411 less than the diffusion coefficient of the material of the second sub-conductive portion 412, can prevent ions in the first sub-conductive portion 411 and the second sub-conductive portion 412 from diffusing to the active layer 2, thereby reducing the risk of thin-film transistor device failure.

[0079] In some embodiments, referring to FIG1, the first electrode 42 includes a first sub-electrode portion 421 and a second sub-electrode portion 422, and the second sub-electrode portion 422 is disposed on the surface of the first sub-electrode portion 421 away from the substrate 1, that is, the first electrode 42 is a double-layer conductive structure formed by stacking the first sub-electrode portion 421 and the second sub-electrode portion 422.

[0080] In some embodiments, referring to FIG1, the first sub-electrode portion 421 and the first sub-conductive portion 411 are made of the same material and have the same thickness, and the second sub-electrode portion 422 and the second sub-conductive portion 412 are made of the same material and have the same thickness. The first conductive portion 41 can be formed simultaneously using the process of fabricating the first electrode 42, thus avoiding the need to increase the film layer structure and related processes of the display panel. Using the highly transparent first conductive portion 41 to connect the active layer 2 to the source electrode 31 or drain electrode 32 not only reduces the area of ​​the less transparent first conductive layer 3, thereby improving the overall transmittance of the array substrate, but also avoids the need to create openings in the insulating layer between the first conductive layer 3 and the active layer 2, thus saving a photomask and reducing production costs.

[0081] In some embodiments, the first electrode 42 can be a single-layer conductive structure formed of a transparent conductive oxide material, which can further improve the overall light transmittance of the array substrate.

[0082] In some embodiments, referring to FIG1, a second conductive layer 4 is disposed on the side of the first conductive layer 3 away from the substrate 1. A first hole V1 is provided between the second conductive layer 4 and the active layer 2. The first sub-conductive portion 411 of the first conductive portion 41 is connected to the active layer 2 through the first hole V1. A second hole V2 is provided between the second conductive layer 4 and the first conductive layer 3. The second hole V2 is spaced apart from the first hole V1. The first sub-conductive portion 411 of the first conductive portion 41 is connected to the source 31 or the drain 32 through the second hole V2.

[0083] In some embodiments, referring to FIG1, the array substrate 10 further includes a gate insulating layer 6, an interlayer dielectric layer 7, and a passivation layer 8. The gate insulating layer 6 is disposed on the surface of the active layer 2 away from the substrate 1. The interlayer dielectric layer 7 is disposed on the surface of the gate insulating layer 6 away from the substrate 1. The first conductive layer 3 is at least partially disposed on the surface of the interlayer dielectric layer 7 away from the substrate 1, and the third conductive layer 5 is at least partially disposed on the surface of the interlayer dielectric layer 7 away from the substrate 1. The passivation layer 8 is disposed on the surfaces of the interlayer dielectric layer 7 and the first conductive layer 3 away from the substrate 1, and the second conductive layer 4 is disposed on the surface of the passivation layer 8 away from the substrate 1. Along the thickness direction of the array substrate 10, a first hole V1 penetrates the passivation layer 8, the interlayer dielectric layer 7, and the gate insulating layer 6, and a second hole V2 penetrates the passivation layer 8.

[0084] In some embodiments, referring to FIG1, the active layer 2 includes a channel portion 21, a first doped portion 22, and a second doped portion 23. The first doped portion 22 is disposed between the second doped portion 23 and the channel portion 21, and the doping concentration of the first doped portion 22 is less than the doping concentration of the second doped portion 23. Along the thickness direction of the array substrate 10, a first hole V1 penetrates the passivation layer 8, the interlayer dielectric layer 7, and the gate insulating layer 6, and exposes the surface of the second doped portion 23 away from the substrate 1. A second hole V2 penetrates the passivation layer 8 and exposes the surface of the source electrode 31 or the drain electrode 32 away from the substrate 1. The first sub-conductive portion 411 of the first conductive portion 41 is connected to the second doped portion 23 of the active layer 2 through the first hole V1, and the first sub-conductive portion 411 is connected to the source electrode 31 or the drain electrode 32 through the second hole V2.

[0085] In some embodiments, please refer to FIG1, the second conductive layer 4 has a plurality of first conductive portions 41, and the source 31 and the drain 32 are respectively connected to the active layer 2 through the corresponding first conductive portions 41.

[0086] In some embodiments, referring to FIG1, the array substrate 10 further includes a buffer layer 9 and a gate layer 11. The buffer layer 9 is disposed on the surface of the substrate 1, the active layer 2 is disposed on the surface of the buffer layer 9 away from the substrate 1, the gate layer 11 is disposed on the surface of the gate insulating layer 6 away from the substrate 1, and the interlayer dielectric layer 7 covers the gate layer 11.

[0087] In some embodiments, referring to FIG1, the first conductive layer 3 includes a second conductive portion 33, which is connected to the second electrode 51. A portion of the second conductive portion 33 is disposed on the surface of the second electrode 51 away from the substrate 1, and another portion is disposed on the surface of the interlayer dielectric layer 7 away from the substrate 1. When the second electrode 51 is a common electrode, the second conductive portion 33 can be considered as a common voltage signal line. The second conductive portion 33 can transmit the common voltage signal to the second electrode 51, so that the second electrode 51 and the first electrode 42 form an electric field that controls the rotation of liquid crystal molecules.

[0088] Please refer to Figures 2a to 2d, which are schematic diagrams of the fabrication process of the first array substrate provided in the embodiments of this application. The fabrication method of the array substrate includes the following steps:

[0089] Step S1: A buffer layer 9, an active layer 2, a gate insulating layer 6, a gate layer 11, an interlayer dielectric layer 7, a third conductive layer 5, and a first conductive layer 3 are sequentially formed on the substrate 1.

[0090] Step S2: A passivation layer 8 is formed on the interlayer dielectric layer 7, the third conductive layer 5 and the first conductive layer 3. The passivation layer 8, the interlayer dielectric layer 7 and the gate insulating layer 6 are etched to form the first hole V1 and the second hole V2.

[0091] Step S3: Deposit a first sub-conductive material 401 on the surface of the passivation layer 8 away from the substrate 1, deposit a second sub-conductive material 402 on the first sub-conductive material 401, and etch the first sub-conductive material 401 and the second sub-conductive material 402 to form a plurality of first conductive parts 41 and first electrodes 42.

[0092] In some embodiments, referring to FIG2a, step S1 includes: forming a third conductive layer 5 on the interlayer dielectric layer 7, patterning the third conductive layer 5 to form a second electrode 51; forming a first conductive layer 3 on the interlayer dielectric layer 7 and the third conductive layer 5, patterning the first conductive layer 3 to form a source electrode 31, a drain electrode 32, and a second conductive portion 33.

[0093] Please refer to Figure 2a. The second conductive part 33 is connected to the second electrode 51. The second conductive part 33 is partially formed on the surface of the second electrode 51 away from the substrate 1, and the second conductive part 33 is partially formed on the surface of the interlayer dielectric layer 7 away from the substrate 1.

[0094] It should be noted that Figures 2a to 2d only illustrate the fabrication process of some film layers of the array substrate. The fabrication process of the remaining film layers in the array substrate can be replaced by the existing fabrication process of the array substrate to achieve the same or similar effect, which will not be elaborated here.

[0095] In some embodiments, please refer to FIG3, which is a schematic diagram of the structure of a second array substrate provided in the embodiments of this application. Its structure is roughly the same as that of the first array substrate shown in FIG1, except that the second electrode 51 is partially disposed on the surface of the second conductive part 33 away from the substrate 1.

[0096] The first conductive layer 3 is fabricated before the third conductive layer 5. Specifically, the first conductive layer 3 is first deposited on the interlayer dielectric layer 7, and then patterned to form a source electrode 31, a drain electrode 32, and a second conductive portion 33. Then, the third conductive layer 5 is deposited on the interlayer dielectric layer 7 and the first conductive layer 3, and patterned to form a second electrode 51. Part of the second electrode 51 is formed on the surface of the second conductive portion 33 away from the substrate 1, and the other part is formed on the surface of the interlayer dielectric layer 7 away from the substrate 1. This achieves the same technical effect as the embodiment shown in Figure 1, which will not be elaborated upon here.

[0097] In some embodiments, please refer to FIG4, which is a schematic diagram of the structure of a third array substrate provided in the embodiments of this application. Its structure is roughly the same as that of the first array substrate shown in FIG1, except that: the second conductive layer 4 is disposed on the side of the first conductive layer 3 close to the substrate 1, the third conductive layer 5 is disposed on the side of the first conductive layer 3 away from the substrate 1, and the active layer 2 is connected to the source 31 or the drain 32 in sequence through the first sub-conductive portion 411 and the second sub-conductive portion 412 of the first conductive portion 41.

[0098] Please refer to Figure 4. The second conductive layer 4 is disposed on the surface of the interlayer dielectric layer 7 away from the substrate 1, and the first conductive layer 3 is disposed on the surface of the second sub-conductive portion 412 away from the substrate 1. The first sub-conductive portion 411 of the first conductive portion 41 is connected to the second doped portion 23 of the active layer 2, and the source electrode 31 is connected to the second sub-conductive portion 412 of the first conductive portion 41. Since the conductivity of the first sub-conductive portion 411 is higher than that of the second sub-conductive portion 412, the contact impedance between the first conductive portion 41 and the active layer 2 can be reduced, thereby preventing current limiting in the thin film transistor devices in the array substrate and improving the stability of the array substrate.

[0099] In some embodiments, referring to FIG4, the orthographic projection of the first conductive layer 3 on the second conductive layer 4 is located within the second conductive layer 4. By using the second conductive layer 4 with higher light transmittance to connect the first conductive layer 3 with the active layer 2, the arrangement area of ​​the first conductive layer 3 with lower light transmittance can be reduced, thereby improving the overall light transmittance of the array substrate.

[0100] In some embodiments, referring to FIG4, a plurality of third holes V3 are provided between the second conductive layer 4 and the active layer 2. Along the thickness direction of the array substrate, the third holes V3 penetrate the interlayer dielectric layer 7 and the gate insulating layer 6, and expose the surface of the second doped portion 23 of the active layer 2 away from the substrate 1. The first sub-conductive portion 411 of the first conductive portion 41 is connected to the active layer 2 through the third holes V3, and the source 31 or drain 32 is connected to the second sub-conductive portion 412 of the first conductive portion 41.

[0101] In some embodiments, referring to FIG4, the third conductive layer 5 is disposed on the surface of the passivation layer 8 away from the substrate 1. The third conductive layer 5 includes a second electrode 51, which is a common electrode, and a first electrode 42, which is a pixel electrode. The first sub-electrode portion 421 of the first electrode 42 is directly connected to the second doped portion 23 of the active layer 2 through the third hole V3. This eliminates the need for the source electrode 31 or drain electrode 32 in the first conductive layer 3, thereby further reducing the arrangement area of ​​the first conductive layer 3 and further improving the overall light transmittance of the array substrate.

[0102] In some embodiments, please refer to Figures 5a to 5e, which are schematic diagrams of the fabrication process of a third array substrate provided in the embodiments of this application. The fabrication method of the array substrate includes the following steps:

[0103] Step S1: A buffer layer 9, an active layer 2, a gate insulating layer 6, a gate layer 11, and an interlayer dielectric layer 7 are sequentially formed on the substrate 1.

[0104] Step S2: Etch the interlayer dielectric layer 7 and the gate insulating layer 6 to form a third hole V3, which penetrates the interlayer dielectric layer 7 and the gate insulating layer 6.

[0105] Step S3: Sequentially deposit the second conductive layer 4 and the first conductive layer 3 on the interlayer dielectric layer 7, coat the photoresist on the first conductive layer 3, and use a halftone mask to expose and develop the photoresist to form multiple photoresist patterns 13.

[0106] Step S4: Simultaneously perform a first patterning process on the first conductive layer 3 and the second conductive layer 4 to form the first conductive part 41 and the first electrode 42;

[0107] Step S5: Remove the photoresist pattern 13 above the first electrode 42, remove the first conductive layer 3 not covered by the photoresist pattern 13, and form the source electrode 31 located above the first conductive part 41.

[0108] Step S5: A passivation layer 8 is formed on the first conductive layer 3 and the second conductive layer 4, and a third conductive layer 5 is formed on the passivation layer 8. The third conductive layer 5 is patterned to form the second electrode 51.

[0109] Based on the array substrate provided in the above embodiments of this application, the embodiments of this application also provide a display panel. Please refer to FIG6, which is a schematic diagram of the structure of the display panel provided in the embodiments of this application. The display panel 100 includes an array substrate 10, an opposing substrate 20 and a liquid crystal layer 30. The array substrate 10 and the opposing substrate 20 are disposed opposite to each other, and the liquid crystal layer 30 is disposed between the array substrate 10 and the opposing substrate 20. The array substrate 10 can be replaced with the array substrate provided in any of the above embodiments to achieve the same technical effect in the display panel provided in this embodiment.

[0110] Based on the display panel provided in the above embodiments of this application, embodiments of this application also provide a display device. Please refer to FIG7, which is a schematic diagram of the display device provided in an embodiment of this application. The display device 1000 includes a display panel 100 and a housing 200, with the display panel 100 disposed on the housing 200. The display panel 100 can be any of the display panels provided in the above embodiments. The display device provided in the embodiments of this application can achieve the same technical effects as the display panel provided in any of the above embodiments, and will not be elaborated upon here.

[0111] The beneficial effects of the embodiments of this application are as follows: The embodiments of this application provide an array substrate, a display panel, and a display device. The array substrate includes a substrate, an active layer, a first conductive layer, and a second conductive layer. By setting the first conductive portion in the second conductive layer as a stacked structure composed of a first sub-conductive portion and a second sub-conductive portion, and connecting the active layer to the source or drain through the first conductive portion, since the transmittance of the first conductive layer is less than that of the second conductive layer, the active layer can be connected to the source or drain by using the second conductive layer with higher transmittance, which can reduce the arrangement area of ​​the first conductive layer and thus improve the overall transmittance of the array substrate. Since the conductivity of the first sub-conductive portion is greater than that of the second sub-conductive portion, the contact impedance between the first conductive portion and the active layer can be reduced, avoiding the problem of current limiting, thereby improving the stability of the array substrate and the display panel.

[0112] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0113] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0114] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0115] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. An array substrate, comprising: Substrate; An active layer is disposed on one side of the substrate; A first conductive layer is disposed on the side of the active layer away from the substrate, and the first conductive layer includes at least one of a source and a drain. The second conductive layer is disposed on the side of the active layer away from the substrate, and the transmittance of the first conductive layer is less than that of the second conductive layer. The second conductive layer includes a first conductive portion, which includes a first sub-conductive portion and a second sub-conductive portion. The second sub-conductive portion is disposed on the surface of the first sub-conductive portion away from the substrate. The conductivity of the first sub-conductive portion is greater than that of the second sub-conductive portion. The active layer is connected to the source or the drain through the first conductive portion.

2. The array substrate as claimed in claim 1, wherein, The array substrate further includes a third conductive layer, which is disposed in a different layer from the second conductive layer. The second conductive layer includes a first electrode, and the third conductive layer includes a second electrode. The first electrode is one of a common electrode and a pixel electrode, and the second electrode is the other of the common electrode and the pixel electrode.

3. The array substrate as described in claim 2, wherein, The first electrode includes a first sub-electrode portion and a second sub-electrode portion. The second sub-electrode portion is disposed on the surface of the first sub-electrode portion away from the substrate. The first sub-electrode portion and the first sub-conductive portion are made of the same material, and the second sub-electrode portion and the second sub-conductive portion are made of the same material.

4. The array substrate as claimed in claim 2, wherein, The second conductive layer is disposed on the side of the first conductive layer away from the substrate. A first hole is provided between the second conductive layer and the active layer. The first sub-conductive portion of the first conductive part is connected to the active layer through the first hole. A second hole is provided between the second conductive layer and the first conductive layer. The second hole is spaced apart from the first hole. The first sub-conductive portion of the first conductive part is connected to the source or the drain through the second hole.

5. The array substrate as claimed in claim 4, wherein, The array substrate further includes: A gate insulating layer is disposed on the surface of the active layer away from the substrate; An interlayer dielectric layer is disposed on the surface of the gate insulating layer away from the substrate; a first conductive layer is at least partially disposed on the surface of the interlayer dielectric layer away from the substrate; and a third conductive layer is at least partially disposed on the surface of the interlayer dielectric layer away from the substrate. A passivation layer is disposed on the surface of the interlayer dielectric layer and the first conductive layer away from the substrate, and a second conductive layer is disposed on the surface of the passivation layer away from the substrate; The first hole penetrates the passivation layer, the interlayer dielectric layer, and the gate insulating layer, while the second hole penetrates the passivation layer.

6. The array substrate as claimed in claim 5, wherein, The first conductive layer includes a second conductive portion, which is connected to the second electrode; The second conductive portion is disposed on the surface of the second electrode away from the substrate.

7. The array substrate as claimed in claim 5, wherein, The first conductive layer includes a second conductive portion, which is connected to the second electrode; The second electrode portion is disposed on the surface of the second conductive portion away from the substrate.

8. The array substrate as claimed in claim 2, wherein, The second conductive layer is disposed on the side of the first conductive layer close to the substrate, and the third conductive layer is disposed on the side of the first conductive layer away from the substrate. The active layer is connected to the source or the drain in sequence through the first sub-conductive portion and the second sub-conductive portion of the first conductive portion.

9. The array substrate as claimed in claim 8, wherein, The first conductive layer is disposed on the surface of the second sub-conductive portion away from the substrate.

10. The array substrate as claimed in claim 8, wherein, The orthographic projection of the first conductive layer onto the second conductive layer lies within the second conductive layer.

11. The array substrate as claimed in claim 8, wherein, The array substrate also includes: A gate insulating layer is disposed on the surface of the active layer away from the substrate; An interlayer dielectric layer is disposed on the surface of the gate insulating layer away from the substrate, and a second conductive layer is disposed on the surface of the interlayer dielectric layer away from the substrate; and A passivation layer is disposed on the surfaces of the interlayer dielectric layer, the first conductive layer, and the second conductive layer away from the substrate, and a third conductive layer is disposed on the surface of the passivation layer away from the substrate. Wherein, a first hole is provided between the second conductive layer and the active layer, the first hole penetrates the passivation layer and the interlayer dielectric layer, and the first sub-conductive part of the first conductive part is connected to the active layer through the first hole.

12. The array substrate as claimed in claim 1, wherein, The light transmittance of the first sub-conductive part is less than that of the second sub-conductive part.

13. The array substrate as claimed in claim 12, wherein, The thickness of the first sub-conductive part is less than the thickness of the second sub-conductive part.

14. The array substrate as claimed in claim 1, wherein, The thickness of the first sub-conductive part is less than or equal to 300 angstroms, and the thickness of the second sub-conductive part is greater than or equal to 300 angstroms and less than or equal to 1000 angstroms.

15. The array substrate as claimed in claim 14, wherein, The thickness of the first sub-conductive part is greater than or equal to 30 angstroms and less than or equal to 80 angstroms.

16. The array substrate as claimed in claim 1, wherein, The material of the first sub-conductive part includes metal or a mixture of metal and metal oxide, and the material of the second sub-conductive part includes transparent conductive oxide.

17. The array substrate as claimed in claim 1, wherein, The diffusion coefficient of the material of the first sub-conductive part is less than that of the material of the second sub-conductive part, and the diffusion coefficient of the material of the second sub-conductive part is less than that of the material of the first conductive layer.

18. A display panel comprising an array substrate, an opposing substrate, and a liquid crystal layer as described in any one of claims 1 to 17, wherein the array substrate and the opposing substrate are disposed opposite to each other, and the liquid crystal layer is disposed between the array substrate and the opposing substrate.

19. A display device comprising the display panel as claimed in claim 18.

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