Display device and driving method therefor

Abstract

The present application provides a display device and a driving method therefor. In the display device, a gate driving unit comprises a pull-up control module, a pull-up module, a pull-down module, a pull-down control module, and a voltage stabilization module. An output end of the pull-up control module, a control end of the pull-up module, and an output end of the voltage stabilization module are all connected to a pull-up node. An output end of the pull-down control module, a control end of the pull-down module, and a control end of the voltage stabilization module are all connected to a pull-down node. A gate signal generated at an output end of the pull-up module and an output end of the pull-down module has a pulse amplitude corresponding to a high potential.

Description

Display device and its driving method Technical Field

[0001] This application relates to the field of display technology, and more specifically to display devices and their driving methods. Background Technology

[0002] GOA (Gate-driver On Array) technology is widely used because it facilitates the design of narrow bezels in display devices. However, existing GOA circuits struggle to generate effective gate signals with short pulse widths and high potentials using a limited number of devices, thus restricting the application scenarios of GOA circuits. Invention Overview

[0003] Embodiments of this application provide a display device and a driving method thereof to solve the problem that existing GOA circuits have difficulty generating effective pulses with small pulse widths and high potentials using fewer devices.

[0004] In a first aspect, embodiments of this application provide a display device, including a gate driving circuit, the gate driving circuit including cascaded multi-stage gate driving units, the gate driving unit including:

[0005] A pull-up control module, wherein the control terminal of the pull-up control module is electrically connected to the corresponding pull-up control signal line, and the output terminal of the pull-up control module is electrically connected to the corresponding pull-up node;

[0006] The pull-up module has its input terminal electrically connected to the corresponding pull-up signal line, its control terminal electrically connected to the corresponding pull-up node, and its output terminal electrically connected to the output terminal of the gate drive unit.

[0007] A pull-down control module, wherein the control terminal of the pull-down control module is electrically connected to the output terminal of the pull-up control module, and the output terminal of the pull-down control module is electrically connected to the corresponding pull-down node;

[0008] A pull-down module, wherein the input terminal of the pull-down module is electrically connected to the corresponding pull-down signal line, the control terminal of the pull-down module is electrically connected to the corresponding pull-down node, and the output terminal of the pull-down module is electrically connected to the output terminal of the gate driving unit;

[0009] A voltage stabilization module, wherein the control terminal of the voltage stabilization module is electrically connected to the corresponding pull-down node, and the output terminal of the voltage stabilization module is electrically connected to the corresponding pull-up node;

[0010] Wherein, the amplitude of the gate signal pulse output by the output terminal of the gate driving unit is greater than the amplitude of the gate signal in the period outside the corresponding pulse.

[0011] Secondly, embodiments of this application also provide a driving method for a display device, applied to any of the display devices described above, comprising:

[0012] In the first stage, the pull-up control module responds to the pull-up control signal transmitted by the pull-up control signal line and controls the potential of the pull-up node to the corresponding effective potential according to the frame start signal or the gate signal of the previous i stage, so that the pull-up module outputs the corresponding first gate signal according to the pull-up signal transmitted by the pull-up signal line.

[0013] In the second stage following the first stage, the pull-up control module responds to the pull-up control signal and controls the pull-down control module to turn on according to the frame start signal or the gate signal of the previous i stage, so that the potential of the pull-down node is the corresponding effective potential, so that the pull-down module outputs the corresponding second gate signal according to the pull-down signal transmitted by the pull-down signal line, wherein the amplitude of the effective potential of the first gate signal is greater than the amplitude of the invalid potential of the first gate signal and the amplitude of the second gate signal.

[0014] Beneficial effects: This application provides a display device and its driving method, wherein the gate driving unit includes a pull-up control module (whose control terminal is loaded with a pull-up control signal), a pull-up module (whose input terminal is electrically loaded with a pull-up signal), a pull-down module (whose input terminal is loaded with a pull-down signal), a pull-down control module (whose control terminal is connected to the output terminal of the pull-up control module), and a voltage stabilization module (whose control terminal is connected to the pull-down node). By connecting the output terminal of the pull-up control module, the control terminal of the pull-up module, and the output terminal of the voltage stabilization module to the pull-up node, and connecting the output terminal of the pull-down control module and the control terminal of the pull-down module to the pull-down node, and connecting the output terminal of the pull-up module and the output terminal of the pull-down module to the output terminal of the gate driving unit, and the amplitude of the pulse of the gate signal output by the output terminal of the gate driving unit is greater than its amplitude in the period outside the pulse, the number of devices in the gate driving unit is reduced while a gate signal with a high potential pulse can be formed. Attached Figure Description

[0015] The present application will be further described below with reference to the accompanying drawings. It should be noted that the accompanying drawings described below are merely for explaining some embodiments of the present application. Those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0016] Figure 1 is a structural diagram of a display device provided in an embodiment of this application.

[0017] Figures 2 and 3 are circuit diagrams of the gate driving unit provided in the embodiments of this application.

[0018] Figures 4 and 5 are timing diagrams of some signals in the gate driving unit provided in the embodiments of this application.

[0019] Figure 6 is a flowchart of a driving method for a display device provided in an embodiment of this application. Implementation methods of this application

[0020] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application. The reference to "embodiment" herein means that a specific feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0021] It should be noted that the "effective potential" in this application can be understood as the potential in the signal used to control the corresponding device to turn on, which can be its corresponding high potential or low potential.

[0022] Embodiments of this application provide a display device, which includes, but is not limited to, the following embodiments and combinations thereof.

[0023] In some embodiments, as shown in Figures 1 to 3, the display device 100 includes a gate driving circuit 10, which includes cascaded multi-stage gate driving units 101. Each gate driving unit 101 includes: a pull-up control module 201, whose control terminal is electrically connected to a corresponding pull-up control signal line (for transmitting a pull-up control signal, such as, but not limited to, a first clock signal XCK), and whose output terminal is electrically connected to a corresponding pull-up node Q; a pull-up module 202, whose input terminal is electrically connected to a corresponding pull-up signal line (for transmitting a pull-up signal, such as, but not limited to, transmitting a second clock signal CK), whose control terminal is electrically connected to the corresponding pull-up node Q, and whose output terminal is electrically connected to the output terminal of the gate driving unit 101; and a pull-down control module 203. The control terminal of the pull-up control module 203 is electrically connected to the output terminal of the pull-up control module 201 (i.e., the pre-pull-up node K), and the output terminal of the pull-down control module 203 is electrically connected to the corresponding pull-down node P; the pull-down module 204 has its input terminal electrically connected to the corresponding pull-down signal line (used to transmit the pull-down signal, which may be, for example, but is not limited to, a low-voltage signal VGL), its control terminal electrically connected to the corresponding pull-down node P, and its output terminal electrically connected to the output terminal of the gate driving unit 101; the voltage stabilization module 205 has its control terminal electrically connected to the corresponding pull-down node P, and its output terminal electrically connected to the corresponding pull-up node Q; wherein, as shown in Figures 4 and 5, the amplitude of the pulse p of the gate signal Gate output by the output terminal of the gate driving unit 101 is greater than the amplitude of the gate signal Gate in the time period outside the corresponding pulse p.

[0024] Specifically, as shown in Figure 1, the display device 100 may include a display panel 30, which may include a plurality of sub-pixels 301 and the aforementioned gate driving circuit 10 located on one side of the plurality of sub-pixels 301. The display device 100 may also include a timing controller 401 and at least one source driver 402, which may be integrated into the same chip or set independently. Each gate driving unit 101 may be electrically connected between the timing controller 401 and the corresponding plurality of sub-pixels 301, for outputting a gate signal Gate transmitted to the corresponding plurality of sub-pixels 301; each source driver 402 may be electrically connected between the timing controller 401 and the corresponding plurality of sub-pixels 301, for outputting a data signal Data transmitted to the corresponding plurality of sub-pixels 301.

[0025] For ease of description, this example uses a 301 array of multiple subpixels arranged in n rows and m columns (where n and m are both positive integers).

[0026] As shown in Figure 1, the gate driving circuit 10 may include at least n-level gate driving units 101. The gate driving circuit 10 (at least one gate driving unit 101) is controlled by the timing controller 401 so that each gate driving unit 101 generates a corresponding gate signal Gate. The n-level gate signals Gate are transmitted to the n rows of sub-pixels 301 through n gate lines (GL1 to GLn). The n pulses p in the n-level gate signals used to turn on the n rows of sub-pixels 301 can be arranged sequentially on the time axis to turn on multiple rows of sub-pixels 301 sequentially.

[0027] The source driver 402 is controlled by the timing controller 401 to generate m data signals Data that are output to m columns of sub-pixels 301 through m data lines (DL1 to DLm). Each data signal Data can include n data voltages corresponding to n sub-pixels 301 in the same column. When each row of sub-pixels 301 is turned on, the multiple data lines receive multiple data voltages corresponding to the multiple sub-pixels 301 in that row, so that the multiple data voltages act on the multiple sub-pixels 301 in that row to make the multiple sub-pixels 301 in that row light up. In this way, the sub-pixels 301 in all rows can be controlled to light up in sequence to present a complete picture.

[0028] As can be seen from the above discussion, each of the multi-stage gate driving units 101 can be loaded with pull-up control signals (e.g., but not limited to the first clock signal XCK), pull-up signals (e.g., but not limited to the second clock signal CK), and pull-down signals (e.g., but not limited to the low-voltage signal VGL). Each stage of the gate driving unit 101 can generate and output the corresponding gate signal Gate through its output terminal.

[0029] The input terminal of the pull-up control module 201 of the first-stage gate driving unit 101 (shown in Figures 2 to 4 only as an example of the first-stage gate driving unit 101) can be loaded with the frame start signal STV, and its output terminal can be electrically connected to the corresponding at least one-stage gate driving unit 101 to provide it with the first-stage gate signal Gate; the output terminal of the intermediate-stage gate driving unit 101 can be electrically connected to the corresponding at least one-stage gate driving unit 101 to transmit the gate signal Gate generated by that stage gate driving unit 101 to it, that is, the gate driving units 101 from the second stage to the last stage can be electrically connected to the output terminal of the preceding at least one-stage gate driving unit 101 to obtain the required gate signal Gate; and so on, the output terminal of the last-stage gate driving unit 101 outputs the last-stage gate signal Gate.

[0030] The waveforms of the first clock signal XCK, the second clock signal CK, the high voltage signal VGH, the low voltage signal VGL, the frame start signal STV, the signal SQ of the pull-up node Q, the signal SK of the pre-pull-up node K, and the signal SP of the pull-down node P in Figures 2 and 3 can be referred to Figures 4 and 5 respectively. The first clock signal XCK and the second clock signal CK can be clock signals, and the high voltage signal VGH and the low voltage signal VGL can be constant voltage signals.

[0031] Understandably, in this embodiment, the pull-up control module 201 is controlled by the pull-up control signal to control the potential of the pull-up node Q, the pull-up module 202 is controlled by the potential of the pull-up node Q to process the pull-up signal and output it to the output terminal of the gate driving unit 101, and the pull-down control module 203 is controlled by the potential of the output terminal of the pull-up control module 201 (i.e., the pre-pull-up node K) to control the potential of the pull-down node P. Furthermore, the pull-down module 204 is controlled by the potential of the pull-down node P to process the pull-down signal and output it to the output terminal of the gate driving unit 101. Based on this, this embodiment also includes a voltage stabilization module 205 controlled by the potential of the pull-down node P, which can adjust the voltage according to the potential of the pull-down node P. The potential of the pull-up node Q is controlled less to stabilize its potential. At the same time, this embodiment controls the potential change of the signal at the output of the gate driving unit 101 (i.e., the waveform of the corresponding gate signal Gate) through the synergistic effect of the above-mentioned multiple modules, so that the amplitude of the pulse p of the gate signal Gate is greater than the amplitude of the gate signal Gate in the period outside the corresponding pulse p. That is, the amplitude of the pulse p of the gate signal Gate is the high potential corresponding to the gate signal Gate. Furthermore, the stability of the gate signal Gate can also be improved through the action of the voltage stabilization module 205. Moreover, only the above-mentioned multiple modules are used, avoiding the need to use a large number of devices to construct the gate driving unit 101.

[0032] In some embodiments, as shown in Figures 2 to 5, the pull-up signal transmitted by the pull-up signal line (e.g., the second clock signal CK) is a clock signal, and the pull-down signal transmitted by the pull-down signal line (e.g., the low-voltage signal VGL) is a constant-voltage signal (a signal with a fixed amplitude); wherein, the pulse width of the pulse p of the gate signal Gate is equal to the duration of the effective potential of the pull-up signal. As discussed above, the pull-up module 202 is controlled by the potential of the pull-up node Q to process the pull-up signal and output it to the output terminal of the gate driving unit 101. The pull-up control signal necessarily includes alternating effective potentials (e.g., controlling the corresponding transistor in the corresponding sub-pixel 301 to turn on) and ineffective potentials (e.g., controlling the corresponding transistor in the corresponding sub-pixel 301 to turn off). In this embodiment, it can be understood that the pull-up module 202 processes the pull-up signal by at least setting the pull-up control module 201 to control the potential of the pull-up node Q and by at least setting the pull-up module 202. At the same time, the pull-down module 204 processes the pull-down signal by at least setting the pull-down control module 203 to control the potential of the pull-down node P and by at least setting the pull-down module 204. This generates a gate signal Gate with a pulse width p equal to the duration of the effective potential of the pull-up control signal, thereby avoiding a large pulse width of the gate signal Gate.

[0033] Furthermore, the amplitude of the gate signal pulse p can also be equal to the effective potential of the pull-up signal. For example, by controlling the pull-up module 202 and the pull-down module 204 to operate in a time-division multiplexing manner, the amplitude of the gate signal Gate output from the output terminal of the gate driving unit 101 can be controlled to be the amplitude of the current pull-up signal or the amplitude of the current pull-down signal. Therefore, it can be considered that the potential of the pull-up node Q and the potential of the pull-down node P can respectively control the working period of the pull-up module 202 and the working period of the pull-down module 204, thereby controlling the waveform of the gate signal Gate.

[0034] In some embodiments, as shown in Figures 2 to 5, the amplitude of the pull-up signal (e.g., the second clock signal CK) transmitted by the pull-up signal line includes an alternating first amplitude a1 (e.g., one of the above-mentioned effective potential and ineffective potential) and a second amplitude a2 (e.g., the other of the above-mentioned effective potential and ineffective potential). The voltage stabilization module 205 includes a first voltage stabilization transistor T5, one of the source and drain of the first voltage stabilization transistor T5 (e.g., the source) is electrically connected to the output terminal of the pull-up control module 201 (i.e., the pre-pull-up node K), and the other (e.g., the drain) is electrically connected to the corresponding pull-up node Q. The first voltage stabilization transistor T5 is turned off when the pull-up module 202 is turned on and when the amplitude of the pull-up signal switches from the first amplitude a1 to the second amplitude a2.

[0035] The phrase "pull-up module 202 enabled" can be understood as follows: when the pull-up control module 201 controls the potential of the pre-pull-up node K to its corresponding effective potential, the first voltage stabilizing transistor T5 is turned on, transmitting the effective potential of the pre-pull-up node K to the pull-up node Q, thereby enabling the pull-up module 202. However, if the amplitude of the pull-up signal switches from the first amplitude a1 to the second amplitude a2 at this time, at least due to the coupling effect of parasitic capacitance, the potential of the pull-up node Q changes accordingly and is transmitted to the pre-pull-up node K through the first voltage stabilizing transistor T5, thus affecting at least the working state of the pull-down control module 203, and consequently affecting the waveform of the gate signal Gate.

[0036] Therefore, in this embodiment, a first voltage stabilizing transistor T5 is set between the pre-pull-up node K and the pull-up node Q, and the first voltage stabilizing transistor T5 is turned off when the pull-up module 202 is turned on and the amplitude of the pull-up signal switches from the first amplitude a1 to the second amplitude a2. This can at least prevent the current potential of the pull-up node Q from affecting the waveform of the gate signal Gate.

[0037] For example, it can be assumed that the change in the potential of the pull-up node Q caused by the switching from the first amplitude a1 to the second amplitude a2 causes the voltage difference between the gate potential of the first voltage stabilizing transistor T5 and the potential of the pull-up node Q to be greater than or less than the threshold voltage of the first voltage stabilizing transistor T5, thereby achieving the cutoff of the first voltage stabilizing transistor T5.

[0038] Furthermore, it can be assumed that the second amplitude a2 is greater than the first amplitude a1. That is, the first voltage stabilizing transistor T5 is turned off when the pull-up module 202 is turned on and the amplitude of the pull-up signal rises from the first amplitude a1 to the second amplitude a2.

[0039] In some embodiments, as shown in Figures 2 to 5, the voltage stabilization module 205 further includes: a second voltage stabilization transistor T4, the gate of the second voltage stabilization transistor T4 being electrically connected to the corresponding pull-down node P, one of the source and drain of the second voltage stabilization transistor T4 (e.g., the source) being electrically connected to a first voltage line (for transmitting a first voltage signal, the first voltage signal being, for example, but not limited to, a high voltage signal VGH), and the other (e.g., the drain) being electrically connected to the output terminal of the pull-up control module 201 (i.e., the pre-pull-up node K); wherein, the second voltage stabilization transistor T4 is turned on when the pull-up module 202 is turned on and the pull-down module 204 is not turned on, and the first voltage signal transmitted by the first voltage line (e.g., the high voltage signal VGH) is used to stabilize the potential of the output terminal of the pull-up control module 201.

[0040] Based on the above discussion, the second voltage stabilizing transistor T4 is controlled by the potential of the pull-down node P to be either turned on or off. It can be assumed that when the pull-down module 204 is not turned on, the potential of the pull-down node P controls the second voltage stabilizing transistor T4 to turn on so as to transmit the first voltage signal to the pre-pull-up node K, thereby stabilizing the potential of the pre-pull-up node K to its effective potential. Furthermore, the first voltage stabilizing transistor T5, which is turned on, transmits this potential to the pull-up node Q, so that the potential of the pull-up node Q is also maintained at its effective potential, thereby improving the stability of the operation of the pull-up module 202.

[0041] In some embodiments, as shown in Figures 3 and 5, the voltage stabilization module 205 further includes: a third voltage stabilization transistor T8, the gate of which is electrically connected to the corresponding pull-down node P, one of the source and drain of which (e.g., the source) is electrically connected to a second voltage line (for transmitting a second voltage signal, which may be, for example, but is not limited to, a low-voltage signal VGL), and the other (e.g., the drain) is electrically connected to the corresponding pull-up node Q; wherein, the third voltage stabilization transistor T8 is turned on when the pull-down module 204 is turned on and the amplitude of the pull-up signal (e.g., the second clock signal CK) rises or falls (e.g., falls) from the first amplitude a1 to the second amplitude a2, and the second voltage signal (e.g., the low-voltage signal VGL) transmitted by the second voltage line is used to pull down or pull up the potential of the corresponding pull-up node Q.

[0042] When "Pull-down module 204 is enabled," it can be understood that when pull-up control module 201 controls the potential of pre-pull-up node K to make it the corresponding invalid potential, pull-down control module 203 controls the potential of pull-down node P to make it the corresponding valid potential, thus enabling pull-down module 204 to operate. However, if the amplitude of the pull-up signal increases or decreases at this time, at least due to the coupling effect of parasitic capacitance, the potential of pull-up node Q will also increase or decrease accordingly. This will then be transmitted to pre-pull-up node K through the first voltage stabilizing transistor T5, thus affecting at least the operating state of pull-down control module 203, and consequently affecting the waveform of the gate signal Gate.

[0043] Therefore, in this embodiment, a third voltage stabilizing transistor T8 is set between the pull-down node P and the pull-up node Q, and the third voltage stabilizing transistor T8 is turned on when the pull-down module 204 is turned on and the amplitude of the pull-up signal is switched. This can at least reduce the impact on the waveform of the gate signal Gate by transmitting the second voltage signal to the pull-up node Q as much as possible to offset the potential jump of the pull-up node Q due to the above reasons.

[0044] For example, it can be assumed that the change in the potential of the pull-up node Q caused by the switching from the first amplitude a1 to the second amplitude a2 means that the first voltage stabilizing transistor T5 is still conducting. However, since the third voltage stabilizing transistor T8 is also conducting at this time, the impact on the waveform of the gate signal Gate can be reduced by reducing the change in the potential of the pull-up node Q.

[0045] Similarly, it can be assumed that the second amplitude a2 is greater than the first amplitude a1. That is, the third voltage stabilizing transistor T8 is turned on when the pull-down module 204 is turned on and the amplitude of the pull-up signal rises from the first amplitude a1 to the second amplitude a2. The second voltage signal transmitted by the second voltage line is used to pull down the potential of the corresponding pull-up node Q.

[0046] In some embodiments, as shown in Figures 2 to 5, the pull-down control module 203 includes: a first pull-down control transistor T2, one of the source and drain of the first pull-down control transistor T2 (e.g., the source) being electrically connected to a first voltage line (which may be the same as or different from the first voltage line mentioned above; here, we take the same as an example); a second pull-down control transistor T3, one of the source and drain of the second pull-down control transistor T3 (e.g., the source) being electrically connected to a second voltage line (which may be the same as or different from the first voltage line mentioned above; here, we take the same as an example); the gates of the first pull-down control transistor T2 and the second pull-down control transistor T3 are both electrically connected to the control terminal of the pull-down control module 203; the other of the source and drain of the first pull-down control transistor T2 (e.g., the drain) and the other of the source and drain of the second pull-down control transistor T3 (e.g., the drain) are both configured as the pull-down node P.

[0047] The first pull-down control transistor T2 and the second pull-down control transistor T3 are alternately turned on; one of the first voltage signal transmitted by the first voltage line (e.g., a high voltage signal VGH) and the second voltage signal transmitted by the second voltage line (e.g., a low voltage signal VGL) is used to control the pull-down module 204 to turn on, and the other is used to control the pull-down module 204 to turn off.

[0048] Understandably, in this embodiment, both the first pull-down control transistor T2 and the second pull-down control transistor T3 are controlled by the potential of the pre-pull-up node K to be turned on or off, and the first voltage signal and the second voltage signal loaded at their source are two constant voltage signals with different amplitudes. By setting the first pull-down control transistor T2 and the second pull-down control transistor T3 to be different types of P-type transistors and N-type transistors respectively, the first pull-down control transistor T2 and the second pull-down control transistor T3 can be turned on in a time-division manner, thereby transmitting the first voltage signal and the second voltage signal to the pull-down node P in a time-division manner, and thus controlling the pull-down module 204 to be turned on and off in a time-division manner.

[0049] Furthermore, in order to avoid the simultaneous activation of pull-up module 202 and pull-down module 204 affecting the waveform of the gate signal, the above modules can be reasonably configured to control the potential of pull-up node Q and the potential of pull-down node P, thereby controlling the pull-up module 202 and pull-down module 204 to be activated in a time-sharing manner.

[0050] In some embodiments, as shown in Figures 2 to 5, the pull-up control module 201 includes: a pull-up control transistor T1, the gate of which is configured as the control terminal of the pull-up control module 201 (loading a pull-up control signal, which may be, for example, but is not limited to, a first clock signal XCK); one of the source and drain of the pull-up control transistor T1 (e.g., the source) is electrically connected to the input terminal of the pull-up control module 201; and the other of the source and drain of the pull-up control transistor T1 (e.g., the drain) is configured as the output terminal of the pull-up control module 201; wherein, the input terminal of the pull-up control module 201 is electrically connected to the frame start line or the output terminal of the gate driving unit 101 of the first i stages, where i is a positive integer.

[0051] As discussed above, the source of the pull-up control transistor T1 in the first-stage gate driving unit 101 is electrically connected to the frame start line to load the frame start signal STV, while the source of the pull-up control transistor T1 in the non-first-stage gate driving unit 101 is electrically connected to the output of the previous i-stage gate driving unit 101 to load the gate signal Gate of the previous i-stage. That is, the pull-up control transistor T1 is controlled to be turned on or off by the pull-up control signal, and when turned on, it transmits the frame start signal STV or the gate signal Gate of the previous i-stage to the pre-pull-up node K, thereby ensuring that the potential of the pre-pull-up node K is at least equal to the amplitude of the pulse in the frame start signal STV or the gate signal Gate of the previous i-stage during the corresponding time period.

[0052] In some embodiments, as shown in Figures 2 to 5, the pull-up module 202 includes: a pull-up transistor T6, the gate of which is electrically connected to the corresponding pull-up node Q, one of the source and drain of which is electrically connected to the pull-up signal line, and the other (e.g., the drain) is electrically connected to the output terminal of the gate driving unit 101; the pull-down module 204 includes: a pull-down transistor T7, the gate of which is electrically connected to the corresponding pull-down node P, one of the source and drain of which is electrically connected to the pull-down signal line, and the other (e.g., the drain) is electrically connected to the output terminal of the gate driving unit 101.

[0053] As discussed above, pull-up transistor T6 and pull-down transistor T7 are controlled by the potentials of pull-up node Q and pull-down node P, respectively, to be turned on or off. By setting the above modules and signals, the potentials of pull-up node Q and pull-down node P control the time-division multiplexing of pull-up transistor T6 and pull-down transistor T7. Consequently, the output of gate drive unit 101 outputs the current waveforms of the pull-up signal (e.g., the second clock signal CK) and the pull-down signal (e.g., the low-voltage signal VGL) in a time-division multiplexing manner, thus forming the waveform of the gate signal Gate. The pulse p of the gate signal Gate can be composed of the effective potentials in the pull-up signal.

[0054] Furthermore, the pull-up module 202 also includes a capacitor C1, electrically connected between the source and drain of the pull-up transistor T6 (e.g., the drain) and the gate of the pull-up transistor T6. It can be understood that since capacitor C1 is connected between the output of the gate driving unit 101 and the pull-up node Q, when the pull-up transistor T6 is turned on, the gate signal Gate reaches the start of its pulse p. It can be considered that the potential change of the gate signal Gate at this time, through the coupling effect of capacitor C1, can cause the pull-up node Q to jump accordingly, thereby increasing the conduction degree of the pull-up transistor T6 and enabling it to stably output the current waveform (its effective potential) of the pull-up signal so that the gate signal Gate forms the corresponding pulse p.

[0055] In some embodiments, as shown in Figures 2 to 5, the amplitude of the pull-up signal (e.g., the second clock signal CK) transmitted by the pull-up signal line includes alternating first amplitude a1 and second amplitude a2; the amplitude of the pull-up control signal (e.g., the first clock signal XCK) transmitted by the pull-up control signal line includes alternating third amplitude a3 and fourth amplitude a4; and the pull-down signal (e.g., the low-voltage signal VGL) transmitted by the pull-down signal line is a constant voltage signal. There is a phase difference between the pull-up signal and the pull-up control signal. The absolute value of the difference between the smaller of the first amplitude a1 and the second amplitude a2 (e.g., the second amplitude a2) and the amplitude of the pull-down signal is less than the absolute value of the difference between the larger of the first amplitude a1 and the second amplitude a2 (e.g., the first amplitude a1) and the amplitude of the pull-down signal.

[0056] As discussed above, when the pull-up control signal (e.g., the first clock signal XCK) is one of the third amplitude a3 and the fourth amplitude a4 (e.g., the third amplitude a3), the pull-up control transistor T1 is turned on, transmitting the frame start signal STV or the gate signal Gate of the previous i stage to the pre-pull-up node K. This, in turn, superimposes the effects of the voltage stabilization module 205 and the pull-down control module 203, respectively, controlling the potential of the pull-up node Q and the potential of the pull-down node P. Subsequently, when the pull-up control signal changes to another of the third amplitude a3 and the fourth amplitude a4 (e.g., the fourth amplitude a4), the pull-up control transistor T1 is turned off to maintain the pre-pull-up node K at its previous potential. Of course, the effect of the voltage stabilization module 205 can also affect the potential of the pre-pull-up node K.

[0057] Specifically, when the pull-up transistor T6 is turned on, it can output the current waveform of the pull-up signal (including at least its effective potential (e.g., the first amplitude a1) to form the pulse p of the gate signal Gate), and then when the pull-down transistor T7 is turned on, it can output the current waveform of the pull-down signal (e.g., the low voltage signal VGL) to form the waveform after the pulse p of the gate signal Gate.

[0058] As discussed above, since the amplitude of the pulse p of the gate signal Gate is the high potential of the gate signal Gate, the smaller second amplitude a2 and the amplitude of the pull-down signal can be basically the same to form the low potential of the gate signal Gate, while the first amplitude a1 of the pulse p of the gate signal Gate is larger.

[0059] It should be noted that this application does not limit the phase difference between the first clock signal XCK and the second clock signal CK acting on the same gate driving unit 101 (for example, the phase difference between the two in Figure 4 can be greater than the phase difference between the two in Figure 5), but their periods, duty cycles, corresponding high potentials, and corresponding low potentials can be equal. The first clock signal XCK acting on different levels of the gate driving unit 101 can be different, and the second clock signal CK can also be different, but the phase difference between the two must be the same.

[0060] This application does not limit the magnitude relationship between the constant voltage signal and the clock signal. It can be assumed that the low voltage signal VGL is closer to the low potential corresponding to the clock signal, and the high voltage signal VGH is closer to the high potential corresponding to the clock signal.

[0061] This application does not limit the types of multiple transistors, as long as the types of multiple transistors and the types of signals they carry are matched to achieve the timing shown in Figure 4 or Figure 5.

[0062] Embodiments of this application also provide a display device, which includes, but is not limited to, the following embodiments and combinations thereof.

[0063] In some embodiments, as shown in Figures 1 to 3, the display device 100 includes a gate driving circuit 10, which includes cascaded multi-stage gate driving units 101. Each gate driving unit 101 includes: a pull-up control transistor T1, the source and drain of which (e.g., the source) are electrically connected to the frame start line or the output of the previous i-stage gate driving unit 101, where i is a positive integer; and a first voltage stabilizing transistor T5, the source and drain of which (e.g., the source) are electrically connected to the frame start line or the output of the previous i-stage gate driving unit 101. The first voltage-stabilized transistor T5 is electrically connected to the other of the source and drain of the pull-up control transistor T1 (e.g., the drain), and the other of the source and drain of the first voltage-stabilized transistor T5 (e.g., the drain) is electrically connected to the corresponding pull-up node Q; the pull-up transistor T6 has its gate electrically connected to the corresponding pull-up node Q, and one of its source and drain (e.g., the source) is electrically connected to the pull-up signal line, while the other is electrically connected to the output terminal of the gate drive unit 101; the first pull-down control transistor T2 and the second... A pull-down control transistor T3, wherein the gates of the first pull-down control transistor T2 and the second pull-down control transistor T3 are both electrically connected to the other of the source and drain of the pull-up control transistor T1, and one of the source and drain of the first pull-down control transistor T2 (e.g., the drain) and one of the source and drain of the second pull-down control transistor T3 (e.g., the drain) are electrically connected to the corresponding pull-down node P; a second voltage stabilizing transistor T4, wherein the gate of the second voltage stabilizing transistor T4 is electrically connected to the corresponding pull-down node P. One of the source and drain of the second voltage-stabilized transistor T4 (e.g., the drain) is electrically connected to the other of the source and drain of the pull-up control transistor T1; the gate of the pull-down transistor T7 is electrically connected to the corresponding pull-down node P, one of the source and drain of the pull-down transistor T7 is electrically connected to the pull-down signal line, and the other is electrically connected to the output terminal of the gate drive unit 101; the capacitor C1 is electrically connected between the other of the source and drain of the pull-up transistor T6 (e.g., the drain) and the gate.

[0064] The connection relationship between the pull-up control transistor T1, the first pull-down control transistor T2, the second pull-down control transistor T3, the second voltage stabilizing transistor T4, the first voltage stabilizing transistor T5, the pull-up transistor T6, the pull-down transistor T7, and the capacitor C1, as well as the applied signal, can be found in the relevant description above.

[0065] As discussed above, the pull-up control transistor T1 is controlled by the pull-up control signal to turn on or off, so as to transmit the frame start signal or the gate signal of the previous i stage to the pre-pull-up node K, or to maintain it at the previous potential. The second voltage stabilizing transistor T4 and the first voltage stabilizing transistor T5 can control the potential of the pull-up node Q. The first pull-down control transistor T2 and the second pull-down control transistor T3 can control the potential of the pull-down node P. Furthermore, the pull-up transistor T6 is controlled by the potential of the pull-up node Q to turn on or off, so as to process the pull-up signal and output it to the output terminal of the gate driving unit 101. The pull-down transistor T7 is controlled by the potential of the pull-down node P to turn on or off, so as to process the pull-down signal and output it to the output terminal of the gate driving unit 101.

[0066] Understandably, this embodiment only uses pull-up control transistors T1 to T7 and capacitor C1, and the corresponding gate signal Gate can be generated through the above connection relationship. Furthermore, by reasonably setting the signal acting on the gate driving unit 101, the amplitude of the gate signal Gate pulse p can be made greater than the amplitude of the gate signal Gate in the time period outside the corresponding pulse p. Therefore, this embodiment can generate a gate signal Gate with strong stability and high potential pulse while saving the number of devices in the gate driving unit 101.

[0067] In some embodiments, as shown in FIG1 and FIG3, the gate driving unit 101 further includes: a third voltage stabilizing transistor T8, the gate of the third voltage stabilizing transistor T8 being electrically connected to the corresponding pull-down node P, and one of the source and drain of the third voltage stabilizing transistor T8 (e.g., the drain) being electrically connected to the pull-up node Q.

[0068] The connection relationship of the third voltage-stabilized transistor T8 and the above-mentioned devices, as well as the applied signal, can be referred to the relevant description above.

[0069] Understandably, the third voltage stabilizing transistor T8 is controlled by the potential of the pull-down node P to turn on or off, thereby controlling the potential of the pull-up node Q. This can reduce the potential change of the pull-up node Q caused by changes in the signal acting on the pull-up transistor T6, thus improving the stability of the pull-up node Q.

[0070] In some embodiments, as shown in Figures 1 to 3, the second voltage-stabilizing transistor T4 is one of an N-type transistor and a P-type transistor, and the third voltage-stabilizing transistor T8 is the other of an N-type transistor and a P-type transistor.

[0071] Understandably, since both the second voltage stabilizing transistor T4 and the third voltage stabilizing transistor T8 are controlled by the potential of the pull-down node P to turn on or off, in order to avoid both of them turning on at the same time and affecting the pull-up node Q or the pre-pull-up node K, they can be set as different types of N-type transistors and P-type transistors respectively, so that they can turn on in a time-sharing manner.

[0072] Furthermore, referring to Figures 1 to 5, the other of the source and drain of the second voltage-stabilized transistor T4 (e.g., the source) is electrically connected to a first voltage line for transmitting a first voltage signal (e.g., a high-voltage signal VGH), and the other of the source and drain of the third voltage-stabilized transistor T8 (e.g., the source) is electrically connected to a second voltage line for transmitting a second voltage signal (e.g., a low-voltage signal VGL); wherein, the first voltage signal is used to pull up or pull down the potential of the other of the source and drain of the pull-up control transistor T1 (i.e., the pre-pull-up node K), and the second voltage signal is used to pull down or pull up the potential of the pull-up node Q.

[0073] As discussed above, the second voltage stabilizing transistor T4 and the third voltage stabilizing transistor T8 can be turned on in a time-division manner to pull up or down the potential of the pre-pull-up node K and pull down or up the potential of the pull-up node Q. Even if the first voltage stabilizing transistor T5 is turned on, it can still provide a consistent pull-up or pull-down effect on the pre-pull-up node K and the pull-up node Q, thereby improving the stability of their potentials.

[0074] In some embodiments, as shown in Figures 1 to 5, the gate of the pull-up control transistor T1 is electrically connected to a pull-up control signal line for transmitting a first clock signal XCK, and the pull-up signal line is used to transmit a second clock signal CK. Therefore, both the first clock signal XCK acting on the pull-up control transistor T1 and the second clock signal CK output to the output terminal of the gate drive unit 101 are clock signals. That is, the pull-up control transistor T1 can be periodically turned on or off according to the first clock signal XCK, and the pulse p of the gate signal Gate can be generated at least according to the second clock signal CK.

[0075] In some embodiments, as shown in Figures 1 to 5, the first pull-down control transistor T2 is one of an N-type transistor and a P-type transistor, and the second pull-down control transistor T3 is the other of an N-type transistor and a P-type transistor.

[0076] Understandably, since both the first pull-down control transistor T2 and the second pull-down control transistor T3 are controlled by the potential of the pre-pull-up node K to turn on or off, in order to avoid both of them turning on at the same time and affecting the pull-down node P, they can be set as different types of N-type transistors and P-type transistors respectively, so that they can turn on in a time-division manner.

[0077] Furthermore, referring to Figures 1 to 5, the other of the source and drain of the first pull-down control transistor T2 (e.g., the source) is electrically connected to a first voltage line for transmitting a first voltage signal (e.g., a high-voltage signal VGH), and the other of the source and drain of the second pull-down control transistor T3 (e.g., the source) is electrically connected to a second voltage line for transmitting a second voltage signal (e.g., a low-voltage signal VGL); wherein, one of the first voltage signal and the second voltage signal is used to control the pull-down transistor T7 to be turned on, and the other is used to control the pull-down transistor T7 to be turned off.

[0078] As discussed above, the first pull-down control transistor T2 and the second pull-down control transistor T3 can be turned on in a time-division manner to pull up and down the potential of the aforementioned pull-down node P in a time-division manner, thereby controlling the pull-down transistor T7 to be turned on and off in a time-division manner. Specifically, to ensure that the gate drive unit 101 effectively outputs the gate signal Gate, the pull-up transistor T6 and the pull-down transistor T7 can be turned on in a time-division manner to output the current pull-up signal and the current pull-down signal as the current gate signal Gate in a time-division manner.

[0079] In some embodiments, as shown in Figures 1 to 5, the pull-up control transistor T1, the second pull-down control transistor T3, the first voltage stabilizing transistor T5, the pull-up transistor T6, and the pull-down transistor T7 are all N-type transistors; the first pull-down control transistor T2 and the second voltage stabilizing transistor T4 are both P-type transistors. Furthermore, the third voltage stabilizing transistor T8 can also be an N-type transistor. Combined with the above discussion of the multiple signals acting on the gate drive unit 101 and the transistor types, it is possible to achieve a pulse p of the gate signal Gate that has a greater amplitude than the amplitude of the gate signal Gate during periods outside of the corresponding pulse p.

[0080] To better illustrate the above-described display device, embodiments of this application also provide a driving method for the display device, applicable to display devices including but not limited to those described above. The driving method for the display device may include, but is not limited to, the following embodiments and combinations thereof.

[0081] For ease of description, this application will only refer to the first-stage gate drive unit 101, and the transistor type and signal waveform will be discussed as described above.

[0082] In some embodiments, as shown in Figures 1 to 6, the driving method for the display device includes, but is not limited to, the following steps:

[0083] S1, in the first stage, the pull-up control module responds to the pull-up control signal transmitted by the pull-up control signal line and controls the potential of the pull-up node to the corresponding effective potential according to the frame start signal or the gate signal of the previous i stage, so that the pull-up module outputs the corresponding first gate signal according to the pull-up signal transmitted by the pull-up signal line.

[0084] That is, in the first stage t1, the pull-up control signal (e.g., the first clock signal XCK) controls the pull-up control module 201 to turn on, and the effective potential of the frame start signal STV is transmitted to the pull-up node Q to make it the corresponding effective potential, so that the pull-up module 202 turns on and outputs the corresponding first gate signal (at least including the pulse p of the gate signal Gate) according to the pull-up signal (e.g., the second clock signal CK).

[0085] As shown in Figures 1 to 5, the steps in the first stage include:

[0086] S11, in the first sub-stage, the pull-up control module responds to the pull-up control signal and controls the potential of the pull-up node to the corresponding effective potential according to the frame start signal or the gate signal of the previous i stage, so that the pull-up module outputs the invalid potential of the first gate signal according to the invalid potential of the pull-up signal;

[0087] That is, in the first sub-stage t11, although the pull-up module 202 is turned on, the pull-up signal is at the corresponding invalid potential (for example, the second amplitude a2 mentioned above), so the output at this time is also the invalid potential of the first gate signal;

[0088] Meanwhile, through the inverter function of the pull-down control module 203, the pull-down node P is at the corresponding low potential, so that the pull-down module 204 is not turned on.

[0089] S12, in the second sub-stage after the first sub-stage, the pull-up control module is turned off, and the pull-up module outputs the effective potential of the corresponding first gate signal according to the effective potential of the pull-up signal.

[0090] The steps within the second sub-stage include:

[0091] In the second sub-stage t12, the pull-up signal is switched from the corresponding invalid potential to the corresponding valid potential, and the voltage stabilization module controls the output terminal of the pull-up control module to form a current disconnect between the pull-up node and the pull-down node.

[0092] That is, in the second sub-stage t12, although the pull-up control signal (e.g., the first clock signal XCK) controls the pull-up control module 201 to turn off, the pre-pull-up node K remains at the previous high potential. Even if the potential of the pull-up signal jumps upward, the potential of the pull-up node Q is further raised through the coupling effect of the parasitic capacitance. However, this causes the first voltage stabilizing transistor T5 in the voltage stabilizing module 205 to be turned off, so the pre-pull-up node K remains at the previous high potential.

[0093] Meanwhile, through the inverter function of the pull-down control module 203, the pull-down node P is at the corresponding low potential, so that the pull-down module 204 is not turned on.

[0094] Furthermore, the steps within the second sub-phase also include:

[0095] In the second sub-stage, the pull-up signal is switched from the corresponding invalid potential to the corresponding valid potential, and the voltage stabilization module responds to the signal of the pull-down node and controls the potential of the output terminal of the pull-up control module according to the first voltage signal.

[0096] That is, in the second sub-stage t12, the second voltage stabilizing transistor T4 in the voltage stabilizing module 205 is turned on by controlling the low potential of the pull-down node P, and transmits the first voltage signal (e.g., the high voltage signal VGH) to the pre-pull-up node K to maintain its high potential stability.

[0097] Following step S1 above, the following steps are also included:

[0098] S2, in the second stage after the first stage, the pull-up control module responds to the pull-up control signal and controls the pull-down control module to turn on according to the frame start signal or the gate signal of the previous i stage, so that the potential of the pull-down node is the corresponding effective potential, so that the pull-down module outputs the corresponding second gate signal according to the pull-down signal transmitted by the pull-down signal line, wherein the amplitude of the effective potential of the first gate signal is greater than the amplitude of the ineffective potential of the first gate signal and the amplitude of the second gate signal;

[0099] That is, in the second stage t2, the pull-up control signal (e.g., the first clock signal XCK) controls the pull-up control module 201 to be turned on, and the invalid potential of the frame start signal STV is transmitted to the pull-up node Q to make it the corresponding invalid potential, so that the pull-up module 202 is not turned on.

[0100] As shown in Figures 1 to 5, the steps in the second stage include:

[0101] S21, in the third sub-stage, the pull-up control module responds to the pull-up control signal and controls the pull-down control module to turn on according to the frame start signal or the gate signal of the previous i stage, so that the potential of the pull-down node is the corresponding effective potential, so that the pull-down module outputs the corresponding second gate signal according to the pull-down signal;

[0102] That is, in the third sub-stage t21, the pull-down control module 203 acts as an inverter, and the pull-down node P is at the corresponding high potential, which enables the pull-down module 204 to turn on. According to the pull-down signal (e.g., the low voltage signal VGL), the corresponding second gate signal is output, and its amplitude can be close to the amplitude of the invalid potential of the first gate signal.

[0103] S22, in the fourth sub-stage following the third sub-stage, the pull-up control module is turned off and the pull-down control module remains on, so that the potential of the pull-down node is the corresponding effective potential, so that the pull-down module outputs the corresponding second gate signal according to the pull-down signal.

[0104] That is, in the fourth sub-stage t22, although the pull-up control signal (e.g., the first clock signal XCK) controls the pull-up control module 201 to be turned off, the pre-pull-up node K is maintained at the previous low potential. Through the inverter function of the pull-down control module 203, the pull-down node P is at the corresponding high potential, the pull-down module 204 remains on, and still outputs the second gate signal according to the pull-down signal.

[0105] Furthermore, the steps within the fourth sub-phase include:

[0106] In the fourth sub-stage, the pull-up signal is switched from the corresponding invalid potential to the corresponding valid potential, and the voltage stabilization module responds to the signal of the pull-down node and controls the potential of the pull-up node according to the second voltage signal.

[0107] That is, within the fourth sub-stage t22, the pull-up signal (e.g., the second clock signal CK) switches from the corresponding invalid potential (e.g., the second amplitude a2) to the corresponding valid potential (e.g., the first amplitude a1). At this time, since the pull-up node Q is at the corresponding low potential, the first voltage stabilizing transistor T5 is turned on. However, at this time, through the effect of parasitic capacitance, if there is no interference, the potential of the pull-up node Q will rise, causing the potential of the pre-pull-up node K to also rise, which in turn affects the high potential of the pull-down node P, and thus affects the waveform of the gate signal Gate.

[0108] However, the third voltage-stabilizing transistor T8 in this application is turned on at this time under the control of the high potential of the pull-down node P, and transmits the second voltage signal (e.g., the low voltage signal VGL) to the pull-up node Q to reduce the rise of the potential of the pull-up node Q, thereby avoiding affecting the waveform of the gate signal Gate.

[0109] It should be noted that each of the timing controller 401, source driver 402, and sub-pixel 301 mentioned in this application includes at least a transistor. Furthermore, it may also include at least one of a capacitor and a resistor, as well as wires electrically connected between different components. The specific configuration is not limited, as long as the above-mentioned functions are achieved.

[0110] The structure of the display device and its driving method provided in the embodiments of this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display device, wherein, Includes a gate driving circuit, the gate driving circuit comprising cascaded multi-stage gate driving units, the gate driving unit comprising: A pull-up control module, wherein the control terminal of the pull-up control module is electrically connected to the corresponding pull-up control signal line, and the output terminal of the pull-up control module is electrically connected to the corresponding pull-up node; The pull-up module has its input terminal electrically connected to the corresponding pull-up signal line, its control terminal electrically connected to the corresponding pull-up node, and its output terminal electrically connected to the output terminal of the gate drive unit. A pull-down control module, wherein the control terminal of the pull-down control module is electrically connected to the output terminal of the pull-up control module, and the output terminal of the pull-down control module is electrically connected to the corresponding pull-down node; A pull-down module, wherein the input terminal of the pull-down module is electrically connected to the corresponding pull-down signal line, the control terminal of the pull-down module is electrically connected to the corresponding pull-down node, and the output terminal of the pull-down module is electrically connected to the output terminal of the gate driving unit; A voltage stabilization module, wherein the control terminal of the voltage stabilization module is electrically connected to the corresponding pull-down node, and the output terminal of the voltage stabilization module is electrically connected to the corresponding pull-up node; Wherein, the amplitude of the gate signal pulse output by the output terminal of the gate driving unit is greater than the amplitude of the gate signal in the period outside the corresponding pulse.

2. The display device according to claim 1, wherein The pull-up signal transmitted by the pull-up signal line is a clock signal, and the pull-down signal transmitted by the pull-down signal line is a constant voltage signal; wherein, the pulse width of the gate signal pulse is equal to the duration of the effective potential of the pull-up control signal transmitted by the pull-up control signal line.

3. The display device according to claim 1, wherein The amplitude of the pull-up signal transmitted by the pull-up signal line includes alternating first amplitude and second amplitude, and the voltage stabilization module includes: A first voltage-stabilized transistor, wherein one of its source and drain is electrically connected to the output terminal of the pull-up control module, and the other is electrically connected to the corresponding pull-up node; The first voltage stabilizing transistor is turned off when the pull-up module is turned on and when the amplitude of the pull-up signal rises from the first amplitude to the second amplitude.

4. The display device according to claim 3, wherein The voltage stabilization module also includes: The second voltage-stabilized transistor has its gate electrically connected to the corresponding pull-down node, and one of its source and drain is electrically connected to the first voltage line, while the other is electrically connected to the output terminal of the pull-up control module. The second voltage stabilizing transistor is turned on when the pull-up module is turned on and the pull-down module is turned off, and the first voltage signal transmitted by the first voltage line is used to stabilize the potential at the output terminal of the pull-up control module.

5. The display device according to claim 3 or 4, wherein The voltage stabilization module also includes: The third voltage-stabilized transistor has its gate electrically connected to the corresponding pull-down node, and one of its source and drain is electrically connected to the second voltage line, while the other is electrically connected to the corresponding pull-up node. The third voltage stabilizing transistor is turned on when the pull-down module is turned on and the amplitude of the pull-up signal rises from the first amplitude to the second amplitude. The second voltage signal transmitted by the second voltage line is used to pull down the potential of the corresponding pull-up node.

6. The display device according to claim 1, wherein The drop-down control module includes: The first pull-down control transistor, wherein one of its source and drain is electrically connected to the first voltage line; The second pull-down control transistor, wherein one of its source and drain is electrically connected to the second voltage line; The gates of the first pull-down control transistor and the second pull-down control transistor are both configured as the control terminals of the pull-down control module; The other of the source and drain of the first pull-down control transistor and the other of the source and drain of the second pull-down control transistor are electrically connected to the corresponding pull-down node.

7. The display device of claim 6, wherein, The first pull-down control transistor and the second pull-down control transistor are turned on alternately; One of the first voltage signal transmitted by the first voltage line and the second voltage signal transmitted by the second voltage line is used to control the pull-down module to turn on, and the other is used to control the pull-down module to turn off.

8. The display device according to claim 1, wherein The pull-up control module includes: A pull-up control transistor, wherein the gate of the pull-up control transistor is configured as the control terminal of the pull-up control module, one of the source and drain of the pull-up control transistor is electrically connected to the input terminal of the pull-up control module, and the other of the source and drain of the pull-up control transistor is configured as the output terminal of the pull-up control module. The input terminal of the pull-up control module is electrically connected to the frame start line or the output terminal of the gate drive unit of the first i stage, where i is a positive integer.

9. The display device according to claim 1, wherein The pull-up module includes: A pull-up transistor, wherein the gate of the pull-up transistor is electrically connected to the corresponding pull-up node, and one of the source and drain of the pull-up transistor is electrically connected to the pull-up signal line, and the other is electrically connected to the output terminal of the gate drive unit; The drop-down module includes: A pull-down transistor, wherein the gate of the pull-down transistor is electrically connected to the corresponding pull-down node, and one of the source and drain of the pull-down transistor is electrically connected to the pull-down signal line, and the other is electrically connected to the output terminal of the gate drive unit.

10. The display device of claim 9, wherein, The pull-up module also includes: A capacitor is electrically connected between the source and drain of the pull-up transistor and the gate of the pull-up transistor.

11. The display device according to claim 9 or 10, wherein The amplitude of the pull-up signal transmitted by the pull-up signal line includes an alternating first amplitude and a second amplitude; the amplitude of the pull-up control signal transmitted by the pull-up control signal line includes an alternating third amplitude and a fourth amplitude; and the pull-down signal transmitted by the pull-down signal line is a constant voltage signal. There is a phase difference between the pull-up signal and the pull-up control signal. The absolute value of the difference between the smaller of the first amplitude and the second amplitude and the amplitude of the pull-down signal is less than the absolute value of the difference between the larger of the first amplitude and the second amplitude and the amplitude of the pull-down signal.

12. The display device according to claim 1, wherein: The pull-up control module includes a pull-up control transistor, one of the source and drain of the pull-up control transistor is electrically connected to the frame start line or the output terminal of the gate driving unit of the previous i stage, where i is a positive integer; The pull-up module includes a pull-up transistor and a capacitor. The gate of the pull-up transistor is electrically connected to the corresponding pull-up node. One of the source and drain of the pull-up transistor is electrically connected to the pull-up signal line, and the other is electrically connected to the output terminal of the gate driving unit. The capacitor is electrically connected between the other of the source and drain of the pull-up transistor and the gate of the pull-up transistor. The pull-down control module includes a first pull-down control transistor and a second pull-down control transistor. The gate of the first pull-down control transistor and the gate of the second pull-down control transistor are both electrically connected to the other of the source and drain of the pull-up control transistor. The source and drain of the first pull-down control transistor and the source and drain of the second pull-down control transistor are electrically connected to the corresponding pull-down node. The pull-down module includes a pull-down transistor, the gate of which is electrically connected to the corresponding pull-down node, and one of the source and drain of which is electrically connected to the pull-down signal line, and the other is electrically connected to the output terminal of the gate driving unit. The voltage stabilization module includes: A first voltage-stabilized transistor, wherein one of the source and drain of the first voltage-stabilized transistor is electrically connected to the other of the source and drain of the pull-up control transistor, and the other of the source and drain of the first voltage-stabilized transistor is electrically connected to the corresponding pull-up node. The second voltage-stabilized transistor has its gate electrically connected to the corresponding pull-down node, and one of its source and drain is electrically connected to the other of its source and drain.

13. The display device of claim 12, wherein, The voltage stabilization module also includes: A third voltage-stabilized transistor, wherein the gate of the third voltage-stabilized transistor is electrically connected to the corresponding pull-down node, and one of the source and drain of the third voltage-stabilized transistor is electrically connected to the pull-up node; The second voltage-stabilizing transistor is either an N-type transistor or a P-type transistor, and the third voltage-stabilizing transistor is either an N-type transistor or a P-type transistor.

14. The display device of claim 13, wherein, The other of the source and drain of the second voltage-stabilized transistor is electrically connected to a first voltage line for transmitting a first voltage signal, and the other of the source and drain of the third voltage-stabilized transistor is electrically connected to a second voltage line for transmitting a second voltage signal. Wherein, the first voltage signal is used to pull up or pull up the potential of the other of the source and drain of the control transistor, and the second voltage signal is used to pull down or pull up the potential of the pull-up node.

15. A driving method of a display device, wherein, The display device includes a gate driving circuit, the gate driving circuit including cascaded multi-stage gate driving units, the gate driving unit including: A pull-up control module, wherein the output terminal of the pull-up control module is electrically connected to the corresponding pull-up node; A pull-up module, wherein the control terminal of the pull-up module is electrically connected to the corresponding pull-up node, and the output terminal of the pull-up module is electrically connected to the output terminal of the gate driving unit; A pull-down control module, wherein the control terminal of the pull-down control module is electrically connected to the output terminal of the pull-up control module, and the output terminal of the pull-down control module is electrically connected to the corresponding pull-down node; A pull-down module, wherein the control terminal of the pull-down module is electrically connected to the corresponding pull-down node, and the output terminal of the pull-down module is electrically connected to the output terminal of the gate driving unit; A voltage stabilization module, wherein the input terminal of the voltage stabilization module is electrically connected to the output terminal of the pull-up control module, the control terminal of the voltage stabilization module is electrically connected to the corresponding pull-down node, and the output terminal of the voltage stabilization module is electrically connected to the corresponding pull-up node; The driving method of the display device includes: In the first stage, the pull-up control module responds to the pull-up control signal transmitted by the pull-up control signal line and controls the potential of the pull-up node to the corresponding effective potential according to the frame start signal or the gate signal of the previous i stage, so that the pull-up module outputs the corresponding first gate signal according to the pull-up signal transmitted by the pull-up signal line. In the second stage following the first stage, the pull-up control module responds to the pull-up control signal and controls the pull-down control module to turn on according to the frame start signal or the gate signal of the previous i stage, so that the potential of the pull-down node is the corresponding effective potential, so that the pull-down module outputs the corresponding second gate signal according to the pull-down signal transmitted by the pull-down signal line, wherein the amplitude of the effective potential of the first gate signal is greater than the amplitude of the invalid potential of the first gate signal and the amplitude of the second gate signal.

16. The driving method of a display device according to claim 15, wherein The steps in the first phase include: In the first sub-stage, the pull-up control module responds to the pull-up control signal and controls the potential of the pull-up node to the corresponding effective potential according to the frame start signal or the gate signal of the previous i stage, so that the pull-up module outputs the invalid potential of the first gate signal according to the invalid potential of the pull-up signal; In the second sub-stage following the first sub-stage, the pull-up control module is turned off, and the pull-up module outputs the effective potential of the corresponding first gate signal according to the effective potential of the pull-up signal.

17. The driving method of a display device according to claim 16, wherein The steps within the second sub-phase include: In the second sub-stage, the pull-up signal is switched from the corresponding invalid potential to the corresponding valid potential, and the voltage stabilization module controls the output terminal of the pull-up control module to form a current disconnect between the pull-up node and the pull-down node.

18. The driving method of a display device according to claim 17, wherein The steps within the second sub-phase also include: In the second sub-stage, the pull-up signal is switched from the corresponding invalid potential to the corresponding valid potential, and the voltage stabilization module responds to the signal of the pull-down node and controls the potential of the output terminal of the pull-up control module according to the first voltage signal.

19. The method of driving a display device according to any one of claims 15 to 18, wherein, The steps in the second phase include: In the third sub-stage, the pull-up control module responds to the pull-up control signal and controls the pull-down control module to turn on according to the frame start signal or the gate signal of the previous i stage, so that the potential of the pull-down node is the corresponding effective potential, so that the pull-down module outputs the corresponding second gate signal according to the pull-down signal; In the fourth sub-stage following the third sub-stage, the pull-up control module is turned off and the pull-down control module remains on, so that the potential of the pull-down node is the corresponding effective potential, and so that the pull-down module outputs the corresponding second gate signal according to the pull-down signal.

20. The driving method of a display device according to claim 19, wherein The steps within the fourth sub-phase include: In the fourth sub-stage, the pull-up signal is switched from the corresponding invalid potential to the corresponding valid potential, and the voltage stabilization module responds to the signal of the pull-down node and controls the potential of the pull-up node according to the second voltage signal.

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