Phase interpolation circuit, and receiver circuit comprising phase interpolation circuit
Patent Information
- Application Number
- PCT/CN2025/098547
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-04-17
- Filing Date
- 2025-05-30
- Publication Date
- 2026-10-22
Smart Images
Figure CN2025098547_22102026_PF_FP_ABST
Abstract
Description
Phase interpolation circuit, receiver circuit including said phase interpolation circuit Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a phase interpolation circuit and a receiver circuit including the phase interpolation circuit. Background Technology
[0002] A wired communication receiver circuit consists of an analog front-end (AFE), a digital decision equalizer (DFE) or analog-to-digital converter (ADC), a clock recovery circuit (CDR), and digital circuitry. Clock recovery extracts the clock information embedded in the received digital code to provide a clock signal to the receiver circuitry and makes decisions on the received signal, facilitating data signal recovery and subsequent processing. Among different CDR structures, phase interpolation CDRs are widely used due to their strong loop stability, short acquisition time, and absence of jitter peaks. The phase interpolator is one of its core circuits. In protocols such as PCIe, the receiver circuit needs to support the reception of spread spectrum clock (SSC) signals, and the phase interpolation circuit needs to track the changing clock signal within a short time, which is very challenging. Summary of the Invention
[0003] The purpose of this application is to provide a phase interpolation circuit and a receiver circuit including the phase interpolation circuit, to avoid large jumps in the interpolation code of the phase interpolation circuit, to ensure the linearity performance of the circuit, to prevent the risk of glitch, and to improve the support for the spread spectrum clock of the data link.
[0004] This application discloses a phase interpolation circuit, including a decoding circuit and a core circuit;
[0005] The core circuit receives a multi-phase clock signal and outputs a recovered clock signal; the decoding circuit receives a phase interpolation code clock and a phase interpolation code and outputs a decoded phase interpolation code clock and a decoded phase interpolation code to the core circuit, wherein the number of data bits of the phase interpolation code is twice that of the decoded phase interpolation code, and the decoding circuit generates a phase interpolation code clock with a frequency of 2 times based on the phase interpolation code clock;
[0006] When the multi-phase clock signal adopts a spread spectrum clock, the decoded phase interpolation code clock output by the decoding circuit to the core circuit is the phase interpolation code clock at twice the frequency. The decoding circuit updates the high-order part and low-order part of the phase interpolation code to the core circuit in two consecutive clock cycles of the phase interpolation code clock at twice the frequency.
[0007] In a preferred embodiment, when the multi-phase clock signal does not use a spread spectrum clock, the decoded phase interpolation code clock output by the decoding circuit to the core circuit is the phase interpolation code clock. The decoding circuit updates the high-order or low-order part of the phase interpolation code to the core circuit in the first half of a clock cycle of the phase interpolation code clock, and does not update the phase interpolation code in the second half of a clock cycle.
[0008] In a preferred embodiment, the decoding circuit includes:
[0009] The first buffer receives the phase interpolation code clock;
[0010] The first NAND gate and the second NAND gate are connected to the output of the first buffer and the inverted signal of the phase interpolation code clock selection signal, respectively.
[0011] The first inverter has its input coupled to the output of the first NAND gate;
[0012] A second inverter and a third inverter, the inputs of which are both coupled to the output of the second NAND gate, and the third inverter outputs a sampling clock signal;
[0013] A clock multiplier and a delay unit are provided, both of which are connected to the output of the second inverter. The clock multiplier outputs a phase interpolation code clock that is 2 times the clock frequency, and the delay unit outputs a delayed phase interpolation code clock.
[0014] A fourth inverter, whose input is connected to the output of the third inverter and outputs an inverted signal of the sampling clock signal;
[0015] A first multiplexer has its input connected to the output of the first inverter and the output of the clock multiplier. The first multiplexer is controlled by the phase interpolation code clock selection signal. When the phase interpolation code clock selection signal is 0, the first multiplexer selects to use the output signal of the first inverter. When the phase interpolation code clock selection signal is 1, the first multiplexer selects to use the output signal of the clock multiplier.
[0016] A second buffer, whose input receives the phase interpolation code;
[0017] The third NAND gate and the fourth NAND gate are respectively connected to the output of the second buffer and the power supply voltage, and the two inputs of the fourth NAND gate are respectively connected to the output of the second buffer and the phase interpolation code clock selection signal. The third NAND gate receives the low-order part of the phase interpolation code, and the fourth NAND gate receives the high-order part of the phase interpolation code.
[0018] The fifth inverter has its input connected to the output of the third NAND gate;
[0019] The first flip-flop has its data terminal connected to the output of the fifth inverter and its clock terminal connected to the sampling clock signal.
[0020] The second flip-flop has its data terminal connected to the output of the first flip-flop and its clock terminal connected to the inverted signal of the sampling clock signal;
[0021] The sixth inverter has its input connected to the output of the fourth NAND gate;
[0022] The third flip-flop has its data terminal connected to the output of the sixth inverter and its clock terminal connected to the sampling clock signal.
[0023] The second multiplexer has its inputs connected to the outputs of the second and third flip-flops, respectively. The second multiplexer is controlled by the delayed phase interpolation code clock output by the delay unit. When the delayed phase interpolation code clock signal output by the delay unit is 0, the second multiplexer selects to use the output signal of the second flip-flop; when the delayed phase interpolation code clock signal output by the delay unit is 1, the second multiplexer selects to use the output signal of the third flip-flop.
[0024] The third multiplexer has its inputs connected to the outputs of the fifth inverter and the second multiplexer, respectively. The third multiplexer is controlled by the phase interpolation code clock selection signal. When the phase interpolation code clock selection signal is 0, the third multiplexer selects to use the output signal of the fifth inverter. When the phase interpolation code clock selection signal is 1, the third multiplexer selects to use the output signal of the second multiplexer.
[0025] In a preferred embodiment, when the phase interpolation code clock selection signal is low, the delayed phase interpolation code clock and the sampling clock signal are always low. The decoding circuit outputs the phase interpolation code clock to the core circuit and outputs the low-order part of the phase interpolation code to the core circuit.
[0026] In a preferred embodiment, when the phase interpolation code clock selection signal is high, the decoding circuit outputs the doubled phase interpolation code clock to the core circuit; the sampling clock signal is in phase with the phase interpolation code clock; the inverted signal of the sampling clock signal is out of phase with the phase interpolation code clock; when the delayed phase interpolation code clock is high, the decoding circuit outputs the high-order part of the phase interpolation code to the core circuit; when the delayed phase interpolation code clock is low, the decoding circuit outputs the low-order part of the phase interpolation code to the core circuit.
[0027] In a preferred embodiment, the phase interpolation code is 14 bits of data, and the decoded phase interpolation code is 7 bits of data.
[0028] In a preferred embodiment, the frequency of the phase interpolation code clock is 1 GHz, and the frequency of the doubled phase interpolation code clock is 2 GHz.
[0029] In a preferred embodiment, the frequency of the recovered clock signal is 16 times that of the phase interpolation code clock.
[0030] This application also discloses a receiver circuit including:
[0031] The circuit consists of an analog front-end circuit, an analog-to-digital conversion circuit or a digital decision equalizer, a digital circuit, and a data clock recovery circuit connected in sequence. The data clock recovery circuit includes a phase interpolation circuit, which employs a phase interpolation circuit as described above.
[0032] In a preferred embodiment, the frequency of the input data to the analog front-end circuit is 32 Gbps / s.
[0033] In a preferred embodiment, when the receiver circuit includes the digital decision equalizer, the data clock recovery circuit includes a first phase interpolation circuit and a second phase interpolation circuit; wherein the recovered clock signal output by the first phase interpolation circuit and the recovered clock signal output by the second phase interpolation circuit are quadrature clock signals.
[0034] In a preferred embodiment, the recovered clock signal output by the first phase interpolation circuit is 90° out of phase with the recovered clock signal output by the second phase interpolation circuit.
[0035] In this embodiment, large jumps in the interpolation code of the phase interpolation circuit are avoided to ensure the linearity performance of the circuit (e.g., differential linearity DNL and integral linearity INL) and prevent the risk of glitch.
[0036] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which should be considered as described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description
[0037] Figure 1 is a schematic diagram of the circuit structure of a receiver circuit according to one embodiment of the present application.
[0038] Figure 2 is a schematic diagram of the circuit structure of a traditional phase interpolation circuit.
[0039] Figure 3 is a timing diagram of traditional phase interpolation.
[0040] Figure 4 is a schematic diagram of a traditional two-way phase interpolation circuit.
[0041] Figure 5 is a schematic diagram of the circuit structure of a phase interpolation circuit according to one embodiment of the present application.
[0042] Figure 6 is a timing diagram of phase interpolation according to one embodiment of the present application.
[0043] Figure 7 is a schematic diagram of the circuit structure of a decoding circuit according to one embodiment of the present application.
[0044] Figure 8 is a schematic diagram of a two-phase interpolation circuit according to one embodiment of the present application. Detailed Implementation
[0045] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.
[0046] Explanation of some concepts:
[0047] Spread spectrum clock: This is a technique that modulates the frequency of a clock signal within a certain frequency range. Its main function is to reduce electromagnetic interference (EMI) and radiated energy peaks without affecting the normal function or performance of digital circuits.
[0048] Unit Interval (UI): A commonly used unit of time in digital communication systems, representing the time required to transmit one bit of data. It is inversely proportional to the data rate and reflects the duration of each symbol.
[0049] ppm: In clock signals or oscillator frequencies, ppm represents the magnitude of the frequency deviation, that is, the error between the actual frequency and the nominal frequency.
[0050] SerDes: Short for SERializer / DESerializer, it is a mainstream time-division multiplexing (TDM) and point-to-point (P2P) serial communication technology. At the transmitting end, multiple low-speed parallel signals are converted into high-speed serial signals, transmitted through a medium (optical fiber or copper wire), and finally converted back into low-speed parallel signals at the receiving end.
[0051] NRZ (Non-Return-to-Zero) encoding refers to a binary signal code in which 1 and 0 are represented by different salient electronic states. There are no neutral states or other states.
[0052] Half-rate architecture: The receiver samples at half the data rate clock speed, which reduces timing constraints compared to full-rate architecture and is suitable for high-speed SerDes (serial deserializer) designs.
[0053] PAM4 (4-Level Pulse Amplitude Modulation) is a multilevel modulation technique used in high-speed serial communication.
[0054] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0055] Figure 1 illustrates a receiver circuit for spread spectrum communication in one embodiment of this application. The receiver circuit comprises a continuous time linear equalization (CTLE) 101, a digital decision feedback equalizer (DFE) or analog-to-digital converter (ADC) 102, a digital circuit 103, and a data clock recovery circuit (CDR) 104. The digital circuit 103 outputs a phase interpolation code digital code (PI_CODE_INPUT) and a phase interpolation code clock PI_CODECLK_INPUT to the CDR 104. The CDR 104 extracts the clock information embedded in the data from the received digital code PI_CODE_INPUT from the digital circuit 103, provides a clock signal PI_OUTPUT_CLK to the receiver circuit, and makes a decision on the received signal to facilitate data signal recovery and subsequent processing. It can be a phase interpolator (PI) based CDR.
[0056] Figure 2 illustrates a conventional phase interpolation circuit, which includes a core circuit 201 and a decoding circuit 202. Figure 3 shows a timing diagram of the conventional phase interpolation. In protocols such as PCIe, the receiver circuit needs to support the reception of spread spectrum clock (SSC) signals. For example, in the PCIe protocol, the CDR needs to be able to track spread spectrum signals with a maximum range of -5000ppm. In the PCIe 5.0 protocol (data rate 32Gb / s), the phase interpolation circuit needs to track clock signals with a range of -3000ppm within a short period of time, which is very challenging.
[0057] As shown in Figure 3, the phase interpolation code PI_INPUT_CODE is updated once on the rising edge of the phase interpolation code clock PI_CODECLK_INPUT (e.g., PI_CODE_INPUT_N in the figure), and then the current interpolation code value remains unchanged until the rising edge of the next interpolation code clock arrives for the next update (e.g., PI_CODE_INPUT_N+1 in the figure). In one implementation, the frequency of the phase interpolation code clock PI_CODECLK_INPUT is 1 GHz.
[0058] Considering temperature, voltage, and process technology (PVT) variations, it is currently difficult for CMOS digital circuits to reliably operate at frequencies above 1 GHz. Taking PCIe 5.0 as an example, the multi-phase clocks CK0, CK90, CK180, and CK270 of the core circuit 201 in Figure 2 operate at 16 GHz. The 1 UI time shown in Figure 3 is 31.25 ps, and 32 UI is 1 ns. Using a common 7-bit phase interpolation circuit (with 7-bit phase interpolation code PI_INPUT_CODE), there are a total of 128 interpolation codes. At a data transfer rate of 32 Gbps, the corresponding clock frequency is 16 GHz, the period is 62.5 ps, and the time interval between two interpolation codes is 62.5 / 128 = 0.488 ps. Taking PCIe 5.0 non-spread spectrum as an example, one U1 time is 31.25pS. In a Half-Rate receiver, the input signal of the PI is constant at 16GHz (period is 62.5pS). The rising and falling edges of the clock signal are used to sample the received data, with an interval of 31.25pS (half of the 16GHz period). If the PI output clock correctly samples the received data for the first time, it can correctly sample data every 31.25pS without changing the phase interpolation code PI_INPUT_CODE (not considering clock jitter and other non-ideal factors). When the PCIe 5.0 spread spectrum is -3000ppm, one U1 time is 31.25pS * 1.003 = 31.3475pS. Since the input frequency of the PI signal is fixed, the sampling interval remains 31.25pS. Therefore, for each bit of data transmitted, the phase deviation between the PI output clock and the data will be 31.3475 - 31.25 = 0.9375pS. Because the phase interpolation code PI_INPUT_CODE is only updated on the rising edge of the next phase interpolation code clock PI_CODECLK_INPUT, the error between PI_CODECLK_INPUT and the falling edge of the input data will accumulate continuously, with a maximum accumulated error of 3pS (32 * 0.09375pS = 3pS). At the next rising edge of PI_CODECLK_INPUT (corresponding to the 33rd rising edge of UI in Figure 3), PI_INPUT_CODE needs to change 6 (or 7) interpolation code values to eliminate the accumulated phase difference between the PI_INPUT_CODE and the receiver input data (3 / 0.488 = 6.15). Similarly, taking a data transmission rate of 16Gbps as an example, the corresponding clock frequency is 8GHz, the period is 125pS, and the time interval between every two interpolation code encodings is 125 / 128 = 0.976pS (the phase interpolation code is still 7 bits).The RX_T1 time deviates from the PI_OUTPUT_CLK time by 5000ppm (0.3125pS per UI time deviation), with a maximum cumulative error of 10pS (32 * 0.3125pS = 10pS). The PI_INPUT_CODE needs to change 10 (or 11) interpolation code values to catch up with the edge drop of the receiver input data (RX Data input) (10 / 0.976 = 10.25). If the phase interpolation circuit continuously changes more than 6 (or 7) or 10 (or 11) interpolation code values, the circuit linearity performance (DNL / INL) will deteriorate, and there is even a risk of glitch.
[0059] To address this, this application provides an improved phase interpolation circuit. The input to the decoding circuit of this phase interpolation circuit is doubled (e.g., from 7 bits to 14 bits). With this specially designed decoding circuit, the output phase interpolation code signal sent to the PI core circuit remains 7 bits. The specific decoding circuit outputs a clock twice the frequency of the original phase interpolation code clock. After this specific design, the phase interpolation code is updated on the rising edge of this doubled clock, updating only a portion of the original code each time. This avoids continuous changes in multiple interpolation code values, prevents large jumps in the interpolation code of the phase interpolation circuit, ensures circuit linearity performance, and prevents the risk of glitch.
[0060] Figure 5 illustrates a phase interpolation circuit according to one embodiment of this application. The phase interpolation circuit includes a core circuit 301 and a decoding circuit 302. The core circuit 301 receives multi-phase clock signals and outputs recovered clock signals. In one embodiment, the core circuit 301 receives four-phase clock signals CK0, CK90, CK180, and CK270, and outputs recovered clock signals PI_OUTPUT_CLKP and PI_OUTPUT_CLKN. PI_OUTPUT_CLKP and PI_OUTPUT_CLKN are a pair of differential clock signals with the same frequency as the four-phase clock signals CK0, CK90, CK180, and CK270, for example, 16GHz and 8GHz clock signals. In this embodiment, 16GHz is used as an example.
[0061] In one embodiment, the decoding circuit 302 receives the phase interpolation code clock PI_CODECLK_INPUT and the phase interpolation code PI_CODE_INPUT, and outputs the decoded phase interpolation code clock PI_CODECLK_OUTPUT and the decoded phase interpolation code PI_CODE_OUTPUT to the core circuit 301. The number of data bits in the phase interpolation code PI_CODE_INPUT is twice that of the decoded phase interpolation code PI_CODE_OUTPUT. The decoded phase interpolation code PI_CODE_OUTPUT can be a part of the phase interpolation code PI_CODE_INPUT, for example, it can be its high-order or low-order portion.
[0062] In one embodiment, the phase interpolation code PI_CODE_INPUT can be 14 bits of data (i.e., PI_CODE_INPUT<13:0>), and the decoded phase interpolation code PI_CODE_OUTPUT can be 7 bits of data (i.e., PI_CODE_OUTPUT<6:0>). In other embodiments, the phase interpolation code PI_CODE_INPUT can be 12 bits, 16 bits of data, etc., and the decoded phase interpolation code PI_CODE_OUTPUT can also be 6 bits, 8 bits, etc. In this embodiment, a 14-bit phase interpolation code PI_CODE_INPUT is used as an example for explanation.
[0063] The decoding circuit 302 generates a phase interpolation code clock CLK_2X, which is twice the frequency of the phase interpolation code clock PI_CODECLK_INPUT (decoding circuit 302 is detailed in Figure 5 and the following description). In one embodiment, the frequencies of the recovered clock signals PI_OUTPUT_CLKP and PI_OUTPUT_CLKN are 16 times that of the phase interpolation code clock PI_CODECLK_INPUT. In one embodiment, the frequency of the phase interpolation code clock PI_CODECLK_INPUT is 1 GHz, and the frequency of the phase interpolation code clock CLK_2X, which is twice the frequency, is 2 GHz.
[0064] When the multi-phase clock signals CK0, CK90, CK180, and CK270 use spread spectrum clocks, the decoded phase interpolation code clock PI_CODECLK_OUTPUT output by the decoding circuit 302 to the core circuit 301 is a phase interpolation code clock CLK_2X with a frequency of 2 times. The decoding circuit 302 updates the high-order part PI_CODE_INPUT<13:7> and the low-order part PI_CODE_INPUT<6:0> of the phase interpolation code to the core circuit 301 in two consecutive clock cycles of the phase interpolation code clock CLK_2X with a frequency of 2 times. In other words, the high-order part PI_CODE_INPUT<13:7> of the phase interpolation code is updated in the first clock cycle, and the low-order part PI_CODE_INPUT<6:0> of the phase interpolation code is updated in the second clock cycle.
[0065] Figure 6 shows a timing diagram of phase interpolation in one embodiment. In Figure 6, PI_CODECLK_INPUT(1X) is the phase interpolation code clock, and PI_CODECLK_INPUT(2X) is the phase interpolation code clock at double frequency (CLK_2X). When the rising edge of the phase interpolation code clock at double frequency arrives, the high-order part of the phase interpolation code PI_CODE_INPUT<13:7> is updated to the core circuit 301. When the next rising edge (the next clock cycle) arrives, the low-order part of the phase interpolation code PI_CODE_INPUT<6:0> is updated to the core circuit 301. Therefore, within one time cycle of the original phase interpolation code clock at double frequency (two consecutive clock cycles of the phase interpolation code clock at double frequency), the phase interpolation code PI_CODE_INPUT is updated to the core circuit 301 twice.
[0066] It should be understood that when updating the phase interpolation code to the core circuit, the low-order part PI_CODE_INPUT<6:0> of the phase interpolation code can be updated to the core circuit 301 at the rising edge before the phase interpolation code clock of 2 times the frequency, and the high-order part PI_CODE_INPUT<13:7> of the phase interpolation code can be updated to the core circuit 301 at the next rising edge.
[0067] In this design, the clock frequency of the digital circuit (i.e., the frequency corresponding to PI_CODECLK_INPUT) remains the same as in the traditional design; only the bit width of the output interpolation code changes from 7 bits to 14 bits. This keeps the design complexity of the digital circuit consistent with the traditional approach. Directly doubling the clock frequency of the digital circuit would present significant challenges to its design. When the data link has a spread spectrum clock, the change in the interpolation code of the phase interpolation circuit is reduced to half of its previous value, greatly improving the circuit's linearity and thus enhancing support for the spread spectrum clock in the link.
[0068] When the multi-phase clock signals CK0, CK90, CK180, and CK270 do not use spread spectrum clocks, the decoded phase interpolation code clock PI_CODECLK_OUTPUT output by the decoding circuit 302 to the core circuit 301 is the phase interpolation code clock PI_CODECLK_INPUT. In the first half of a clock cycle of the phase interpolation code clock PI_CODECLK_INPUT, the decoding circuit updates the high-order part PI_CODE_INPUT<13:7> or the low-order part PI_CODE_INPUT<6:0> of the phase interpolation code to the core circuit, and does not update the phase interpolation code in the second half of the clock cycle.
[0069] For example, when the rising edge of the phase interpolation code clock PI_CODECLK_INPUT arrives, the high-order bits of the phase interpolation code PI_CODE_INPUT<13:7> are updated to the core circuit 301. When the falling edge arrives, no interpolation code needs to be updated. When the next rising edge arrives, the high-order bits of the next set of phase interpolation codes PI_CODE_INPUT<13:7> are updated to the core circuit 301. That is, the interpolation code update is completed within half a clock cycle of the phase interpolation code clock PI_CODECLK_INPUT. Therefore, the design of this application can be compatible with systems that do not need to support spread spectrum signals.
[0070] Figure 7 shows a circuit diagram of the decoding circuit in one embodiment. The decoding circuit includes a first buffer Buffer1, a second buffer Buffer2, a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, a fourth NAND gate NAND4, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a clock multiplier, a delay unit, a first flip-flop DFF1, a second flip-flop DFF2, a third flip-flop DFF3, a first multiplexer MUX1, a second multiplexer MUX2, and a third multiplexer MUX3.
[0071] The first buffer, Buffer1, receives the phase interpolation code clock PI_CODECLK_INPUT. The two inputs of the first NAND gate, NAND1, are each connected to the output of the first buffer, Buffer1, and the inverted phase interpolation code clock selection signal, PI_CODECLK_SELB. The two inputs of the second NAND gate, NAND2, are each connected to the output of the first buffer, Buffer1, and the phase interpolation code clock selection signal, PI_CODECLK_SEL. The input of the first inverter, INV1, is coupled to the output of the first NAND gate, NAND1. The inputs of the second inverter, INV2, and the third inverter, INV3, are both coupled to the output of the second NAND gate, NAND2. The third inverter, INV3, outputs the sampling clock signal CLK_1X_DFF. The clock multiplier and delay unit are both connected to the output of the second inverter, INV2. The clock multiplier outputs a phase interpolation code clock CLK_2X multiplied by 2, and the delay unit outputs a delayed phase interpolation code clock CLK_1X_MUX. The input of the fourth inverter INV4 is connected to the output of the third inverter INV3 and outputs the inverted signal CLKB_1X_DFF of the sampling clock signal. The input of the first multiplexer MUX1 is connected to the output of the first inverter INV1 and the output of the clock multiplier. The first multiplexer MUX1 receives and is controlled by the phase interpolation code clock selection signal PI_CODECLK_SEL. When the phase interpolation code clock selection signal PI_CODECLK_SEL is 0, the first multiplexer MUX1 selects to use the output signal of the first inverter INV1; when the phase interpolation code clock selection signal PI_CODECLK_SEL is 1, the first multiplexer MUX1 selects to use the output signal of the clock multiplier.
[0072] The input of the second buffer Buffer2 receives the phase interpolation code PI_CODE_INPUT<13:0>. The two inputs of the third NAND gate NAND3 are each connected to the output of the second buffer Buffer2 and the power supply voltage VDD. The two inputs of the fourth NAND gate NAND4 are each connected to the output of the second buffer Buffer2 and the phase interpolation code clock selection signal PI_CODECLK_SEL. The third NAND gate NAND3 receives the low-order portion of the phase interpolation code PI_CODE_INPUT<6:0>, and the fourth NAND gate NAND4 receives the high-order portion of the phase interpolation code PI_CODE_INPUT<13:7>. The input of the fifth inverter INV5 is connected to the output of the third NAND gate NAND3. The data terminal of the first flip-flop DFF1 is connected to the output of the fifth inverter INV5, and its clock terminal is connected to the sampling clock signal CLK_1X_DFF. The data terminal of the second flip-flop DFF2 is connected to the output of the first flip-flop DFF1, and its clock terminal is connected to the inverted signal CLKB_1X_DFF of the sampling clock signal. The input of the sixth inverter INV6 is connected to the output of the fourth NAND gate NAND4. The data input of the third flip-flop DFF3 is connected to the output of the sixth inverter INV6, and the clock input is connected to the sampling clock signal CLK_1X_DFF. The inputs of the second multiplexer MUX2 are connected to the outputs of the second flip-flop DFF2 and the third flip-flop DFF3, respectively. The second multiplexer MUX2 receives and is controlled by the delayed phase interpolation code clock CLK_1X_MUX output from the delay unit. When the delayed phase interpolation code clock signal CLK_1X_MUX output from the delay unit is 0, the second multiplexer MUX2 selects to use the output signal of the second flip-flop DFF2; when the delayed phase interpolation code clock signal CLK_1X_MUX output from the delay unit is 1, the second multiplexer MUX2 selects to use the output signal of the third flip-flop DFF3. The inputs of the third multiplexer MUX3 are connected to the outputs of the fifth inverter INV5 and the second multiplexer MUX2, respectively. The third multiplexer MUX3 receives and is controlled by the phase interpolation code clock selection signal PI_CODECLK_SEL. When the phase interpolation code clock selection signal PI_CODECLK_SEL is 0, the third multiplexer MUX3 selects to use the output signal of the fifth inverter INV5; when the phase interpolation code clock selection signal PI_CODECLK_SEL is 1, the third multiplexer MUX3 selects to use the output signal of the second multiplexer MUX2.
[0073] In one embodiment, when the phase interpolation code clock selection signal PI_CODECLK_SEL is low, the delayed phase interpolation code clock CLK_1X_MUX and the sampling clock signal CLK_1X_DFF are always low. The decoding circuit outputs the phase interpolation code clock PI_CODECLK_INPUT to the core circuit and outputs the low-order part of the phase interpolation code PI_CODE_INPUT<6:0> to the core circuit.
[0074] In one embodiment, when the phase interpolation code clock selection signal PI_CODECLK_SEL is high, the decoding circuit outputs a phase interpolation code clock CLK_2X (doubled frequency) to the core circuit. The sampling clock signal CLK_1X_DFF is in phase with the phase interpolation code clock PI_CODECLK_INPUT. The inverted signal CLKB_1X_DFF of the sampling clock signal is out of phase with the phase interpolation code clock PI_CODECLK_INPUT. When the delayed phase interpolation code clock CLK_1X_MUX is high, the decoding circuit outputs the high-order part of the phase interpolation code PI_CODE_INPUT<13:7> to the core circuit. When the delayed phase interpolation code clock CLK_1X_MUX is low, the decoding circuit outputs the low-order part of the phase interpolation code PI_CODE_INPUT<6:0> to the core circuit.
[0075] A PAM4 receiver system based on a DSP (Digital Signal Processing) architecture, meaning the receiver system includes an ADC, typically requires only one PI core circuit (i.e., just one PI circuit), as the ADC can internally generate the necessary multi-phase signals. However, for an analog half-rate NRZ serdes receiver, meaning the receiver system includes a digital decision equalizer, two PI core circuits are typically needed to generate the I-channel clock signal and the Q-channel clock signal, respectively sampling the odd-numbered bits (ODD) and even-numbered bits (EVEN) of the data signal. Figure 4 is a schematic diagram of a traditional two-channel phase interpolation circuit, with the receiver system including an I-channel phase interpolation circuit PI-I and a Q-channel phase interpolation circuit PI-Q.
[0076] Figure 6 is a schematic diagram of a two-channel phase interpolation circuit in one embodiment of this application, applied to an analog-based half-rate NRZ serdes receiver. The receiver circuit includes a digital decision equalizer, and the data clock recovery circuit includes a first phase interpolation circuit PI-I and a second phase interpolation circuit PI-Q. The recovered clock signal output by the first phase interpolation circuit and the recovered clock signal output by the second phase interpolation circuit are quadrature clock signals. For example, the recovered clock signal output by the first phase interpolation circuit is 90° out of phase with the recovered clock signal output by the second phase interpolation circuit.
[0077] Specifically, the first phase interpolation circuit PI-I includes an I-Path core circuit and an I-Path decoding circuit. The I-Path core circuit receives multi-phase clock signals (e.g., CK0, CK90, CK180, CK270) and outputs a pair of differential clock signals PI_OUTPUT_CLKP_I and PI_OUTPUT_CLKN_I. The I-Path decoding circuit receives the phase interpolation code clock PI_CODECLK_INPUT_I and the phase interpolation code PI_CODE_INPUT_I<13:0>, and outputs the decoded phase interpolation code clock PI_CODECLK_OUTPUT_I<6:0> and the decoded phase interpolation code PI_CODE_OUTPUT_I to the I-Path core circuit. The second phase interpolation circuit PI-Q includes a Q-Path core circuit and a Q-Path decoding circuit. The Q-Path core circuit receives multi-phase clock signals (e.g., CK0, CK90, CK180, CK270) and outputs a pair of differential clock signals PI_OUTPUT_CLKP_Q and PI_OUTPUT_CLKN_Q. The Q-Path decoding circuit receives the phase interpolation code clock PI_CODECLK_INPUT_Q<13:0> and the phase interpolation code PI_CODE_INPUT_Q, and outputs the decoded phase interpolation code clock PI_CODECLK_OUTPUT_Q<6:0> and the decoded phase interpolation code PI_CODE_OUTPUT_Q to the Q-Path core circuit.
[0078] The I-Path decoding circuit and the Q-Path decoding circuit receive the same phase interpolation code clock. The phase interpolation codes PI_CODE_INPUT_Q and PI_CODECLK_INPUT<13:0>_I are a pair of orthogonal interpolation codes (different by a quarter of the cycles of the multi-phase clock signals CK0, CK90, CK180, CK270), which makes the output clock signals PI_OUTPUT_CLKP_I, PI_OUTPUT_CLKN_I and PI_OUTPUT_CLKP_Q, PI_OUTPUT_CLKN_Q orthogonal clock signals. For example, PI_OUTPUT_CLKP_I and PI_OUTPUT_CLKP_Q are 90° out of phase, and PI_OUTPUT_CLKN_I and PI_OUTPUT_CLKN_Q are 90° out of phase. Therefore, the phase interpolation circuits PI-I and PI-Q generate I-channel clock signals and Q-channel clock signals, respectively, which are used for data sampling and edge sampling of odd-numbered bits (ODD) and even-numbered bits (EVEN), respectively.
[0079] One embodiment of this application also discloses a receiver circuit, including an analog front-end circuit (or a continuous-time linear equalizer), an analog-to-digital converter circuit or a digital decision equalizer, a digital circuit, and a data clock recovery circuit connected in sequence. The data clock recovery circuit includes a phase interpolation circuit as described above. In one embodiment, the frequency of the input data to the analog front-end circuit is 16 GHz. The technical details of the aforementioned phase interpolation circuit can be applied to this embodiment and will not be repeated here.
[0080] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.
[0081] The term “coupled to” and its derivatives may be used in this document. “Coupled” can mean two or more elements in direct physical or electrical contact. However, “coupled” can also mean two or more elements in indirect contact with each other, but still cooperating or interacting with each other, and can mean one or more other elements coupled or connected between elements referred to as being coupled to each other.
[0082] This specification includes combinations of various embodiments described herein. Individual references to embodiments (e.g., “one embodiment”, “some embodiments”, or “preferred embodiments”) do not necessarily refer to the same embodiment; however, these embodiments are not mutually exclusive unless indicated to be mutually exclusive or are readily apparent to those skilled in the art. It should be noted that the word “or” is used in a non-exclusive sense throughout this specification unless the context explicitly indicates or requires it.
[0083] All references to this specification are considered to be incorporated integrally into the disclosure of this application so that they can serve as the basis for modifications if necessary. Furthermore, it should be understood that the above descriptions are merely preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of one or more embodiments of this specification.
Claims
1. A phase interpolation circuit, characterized in that, Including decoding circuitry and core circuitry; The core circuit receives a multi-phase clock signal and outputs a recovered clock signal; the decoding circuit receives a phase interpolation code clock and a phase interpolation code and outputs a decoded phase interpolation code clock and a decoded phase interpolation code to the core circuit, wherein the number of data bits of the phase interpolation code is twice that of the decoded phase interpolation code, and the decoding circuit generates a phase interpolation code clock with a frequency of 2 times based on the phase interpolation code clock; When the multi-phase clock signal adopts a spread spectrum clock, the decoded phase interpolation code clock output by the decoding circuit to the core circuit is the phase interpolation code clock at twice the frequency. The decoding circuit updates the high-order part and low-order part of the phase interpolation code to the core circuit in two consecutive clock cycles of the phase interpolation code clock at twice the frequency.
2. The phase interpolation circuit as described in claim 1, characterized in that, When the multi-phase clock signal does not use a spread spectrum clock, the decoded phase interpolation code clock output by the decoding circuit to the core circuit is the phase interpolation code clock. The decoding circuit updates the high-order or low-order part of the phase interpolation code to the core circuit in the first half of a clock cycle of the phase interpolation code clock, and does not update the phase interpolation code in the second half of a clock cycle.
3. The phase interpolation circuit as described in claim 1, characterized in that, The decoding circuit includes: The first buffer receives the phase interpolation code clock; The first NAND gate and the second NAND gate are connected to the output of the first buffer and the inverted signal of the phase interpolation code clock selection signal, respectively. The first inverter has its input coupled to the output of the first NAND gate; A second inverter and a third inverter, the inputs of which are both coupled to the output of the second NAND gate, and the third inverter outputs a sampling clock signal; A clock multiplier and a delay unit are provided, both of which are connected to the output of the second inverter. The clock multiplier outputs a phase interpolation code clock that is 2 times the clock frequency, and the delay unit outputs a delayed phase interpolation code clock. A fourth inverter, whose input is connected to the output of the third inverter and outputs an inverted signal of the sampling clock signal; A first multiplexer has its input connected to the output of the first inverter and the output of the clock multiplier. The first multiplexer is controlled by the phase interpolation code clock selection signal. When the phase interpolation code clock selection signal is 0, the first multiplexer selects to use the output signal of the first inverter. When the phase interpolation code clock selection signal is 1, the first multiplexer selects to use the output signal of the clock multiplier. A second buffer, whose input receives the phase interpolation code; The third NAND gate and the fourth NAND gate are respectively connected to the output of the second buffer and the power supply voltage, and the two inputs of the fourth NAND gate are respectively connected to the output of the second buffer and the phase interpolation code clock selection signal. The third NAND gate receives the low-order part of the phase interpolation code, and the fourth NAND gate receives the high-order part of the phase interpolation code. The fifth inverter has its input connected to the output of the third NAND gate; The first flip-flop has its data terminal connected to the output of the fifth inverter and its clock terminal connected to the sampling clock signal. The second flip-flop has its data terminal connected to the output of the first flip-flop and its clock terminal connected to the inverted signal of the sampling clock signal; The sixth inverter has its input connected to the output of the fourth NAND gate; The third flip-flop has its data terminal connected to the output of the sixth inverter and its clock terminal connected to the sampling clock signal. The second multiplexer has its inputs connected to the outputs of the second and third flip-flops, respectively. The second multiplexer is controlled by the delayed phase interpolation code clock output by the delay unit. When the delayed phase interpolation code clock signal output by the delay unit is 0, the second multiplexer selects to use the output signal of the second flip-flop; when the delayed phase interpolation code clock signal output by the delay unit is 1, the second multiplexer selects to use the output signal of the third flip-flop. The third multiplexer has its inputs connected to the outputs of the fifth inverter and the second multiplexer, respectively. The third multiplexer is controlled by the phase interpolation code clock selection signal. When the phase interpolation code clock selection signal is 0, the third multiplexer selects to use the output signal of the fifth inverter. When the phase interpolation code clock selection signal is 1, the third multiplexer selects to use the output signal of the second multiplexer.
4. The phase interpolation circuit as described in claim 3, characterized in that, When the phase interpolation code clock selection signal is low, the delayed phase interpolation code clock and sampling clock signals are always low. The decoding circuit outputs the phase interpolation code clock to the core circuit and outputs the low-order part of the phase interpolation code to the core circuit.
5. The phase interpolation circuit as described in claim 3, characterized in that, When the phase interpolation code clock selection signal is high, the decoding circuit outputs the doubled phase interpolation code clock to the core circuit; when the delayed phase interpolation code clock is high, the decoding circuit outputs the high-order part of the phase interpolation code to the core circuit; when the delayed phase interpolation code clock is low, the decoding circuit outputs the low-order part of the phase interpolation code to the core circuit.
6. The phase interpolation circuit as described in claim 1, characterized in that, The phase interpolation code is 14 bits of data, and the decoded phase interpolation code is 7 bits of data.
7. The phase interpolation circuit as described in claim 1, characterized in that, The frequency of the phase interpolation code clock is 1 GHz, and the frequency of the doubled phase interpolation code clock is 2 GHz.
8. The phase interpolation circuit as described in claim 1, characterized in that, The frequency of the recovered clock signal is 16 times that of the phase interpolation code clock.
9. A receiver circuit, characterized in that, include: The circuit comprises an analog front-end circuit, an analog-to-digital converter or a digital decision equalizer, a digital circuit, and a data clock recovery circuit connected in sequence. The data clock recovery circuit includes a phase interpolation circuit, which employs the phase interpolation circuit described in any one of claims 1 to 8. The digital circuit provides a phase interpolation code clock and a phase interpolation code to the phase interpolation circuit.
10. The receiver circuit as described in claim 9, characterized in that, When the receiver circuit includes the digital decision equalizer, the data clock recovery circuit includes a first phase interpolation circuit and a second phase interpolation circuit; wherein the recovered clock signal output by the first phase interpolation circuit and the recovered clock signal output by the second phase interpolation circuit are quadrature clock signals.