Data reading method and apparatus, electronic device, and storage medium
Patent Information
- Application Number
- PCT/CN2025/101836
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-04-14
- Filing Date
- 2025-06-18
- Publication Date
- 2026-10-22
Smart Images
Figure CN2025101836_22102026_PF_FP_ABST
Abstract
Description
Data reading methods, devices, electronic equipment and storage media
[0001] Cross-references to related applications
[0002] This disclosure claims priority to Chinese Patent Application No. 2025104575754, filed on April 14, 2025, entitled “Data Reading Method, Apparatus, Electronic Device and Storage Medium”, the entire contents of which are incorporated herein by reference. Technical Field
[0003] This disclosure relates to the field of data reading, and more specifically, to a data reading method, apparatus, electronic device, and storage medium. Background Technology
[0004] Open-Ended Multiple-Block Read (OMBR) is the most basic read type in the protocol of embedded multi-media card (eMMC) devices. After the host sends a read command, the embedded storage device prepares the data according to the read command address and transmits it to the host. According to the eMMC protocol, OMBR does not define the number of blocks to be read in a multi-block operation. The device will continuously transmit data blocks until it receives a stop command (CMD12), thus completing the read command request.
[0005] Thus, based on the open multi-block read characteristic, the embedded storage device will continuously prepare data and transmit it to the host. The embedded storage device always prepares read data according to its own Random Access Memory (RAM) cache size. The data transmission latency is equal to the time to read data from Nand flash memory to RAM cache. Regardless of the size of the data block requested by the host, its read command latency is the same. When the data block requested by the host is small, it will result in a higher read command latency. Summary of the Invention
[0006] In view of this, the object of the present disclosure is to provide a data reading method, apparatus, electronic device and storage medium to at least partially improve the above-mentioned problems.
[0007] To achieve the above objectives, the technical solutions adopted in the embodiments of this disclosure are as follows:
[0008] In a first aspect, embodiments of this disclosure provide a data reading method applied to an embedded storage device, the method comprising:
[0009] Receive the current open multi-block read command sent by the host and obtain the preset read data length of the embedded storage device. If the current open multi-block read command is not the first data read, the preset read data length is set to the data transfer length accumulated by the DMA module after the previous multi-block read command has completed the data transfer.
[0010] Based on the current open multi-block read command and the preset read data length, the target data read operation is executed, the target data is cached in the RAM cache, and the target data in the RAM cache is transferred to the host through the DMA module.
[0011] Optionally, the method further includes:
[0012] After the DMA module completes the current data transfer, if no stop transfer command is received from the host, the preset read data length is set to the capacity of the embedded storage device, and the next target data read is performed until the stop transfer command is received from the host. Then, the accumulated data transfer length of the DMA module is obtained, and the accumulated data transfer length is used as the preset read data length for the next multi-block read command.
[0013] Optionally, the step of transferring the target data from the RAM cache to the host via the DMA module includes:
[0014] Configure the data transfer direction, starting address, block size, and number of blocks for the DMA module;
[0015] The DMA module transfers the target data from the RAM cache to the host, starting from the starting address and according to the block size and the number of blocks.
[0016] Optionally, after the step of performing a target data read operation based on the current open multi-block read command and the preset read data length, and caching the target data in the RAM cache, the method further includes:
[0017] Based on the current open multi-block read command and the preset read data length, perform a pre-read operation of the predicted target data to obtain the predicted target data;
[0018] After the DMA module completes the transmission of the target data and no stop transmission command is received from the host, the predicted target data is cached in the RAM cache, and the predicted target data in the RAM cache is transmitted to the host through the DMA module.
[0019] Optionally, the step of caching the predicted target data in the RAM cache and transferring the predicted target data in the RAM cache to the host via the DMA module includes:
[0020] If the size of the predicted target data is less than or equal to the size of the RAM cache, all the predicted target data is cached in the RAM cache, and the predicted target data in the RAM cache is transferred to the host through the DMA module;
[0021] If the size of the predicted target data is greater than the size of the RAM cache, the first predicted target data of the RAM cache size is cached in the RAM cache;
[0022] During the process of transferring the first predicted target data in the RAM cache to the host through the DMA module, a data request for the remaining second predicted target data is sent to the flash memory so that the flash memory prepares the second predicted target data.
[0023] After the first predicted target data in the RAM cache is transferred through the DMA module, the second predicted target data is cached in the RAM cache, and then the second predicted target data is transferred to the host through the DMA module.
[0024] Optionally, the method further includes:
[0025] If the actual accessed data is less than the size of the predicted target data, then the predicted target data that has been read and cached in the RAM cache is cleared.
[0026] Optionally, the method further includes:
[0027] If the current open multi-block read command is the first data read, then the preset read data length is set to be less than or equal to the capacity of the RAM cache.
[0028] Secondly, embodiments of this disclosure provide a data reading device applied to an embedded storage device, the device comprising:
[0029] The command acquisition unit is configured to receive the current open multi-block read command sent by the host and acquire the preset read data length of the embedded storage device. If the current open multi-block read command is not the first data read, the preset read data length is set to the data transfer length accumulated by the DMA module after the previous multi-block read command has completed the data transfer.
[0030] The data reading unit is configured to perform a target data reading operation based on the current open multi-block read command and the preset read data length, cache the target data in the RAM cache, and transfer the target data in the RAM cache to the host through the DMA module.
[0031] Thirdly, embodiments of this disclosure provide an electronic device, including a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor executes the program to implement the method described in any of the preceding descriptions.
[0032] Fourthly, embodiments of this disclosure provide a storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described in any of the preceding claims.
[0033] The present disclosure provides a data reading method, apparatus, electronic device, and storage medium that, by preset the read data length and dynamically tracking the actual transmission length of the previous open multi-block read command and using it as the preset read data length for the next multi-block read command, can reduce the read command latency when the actual requested length is less than or equal to the preset read data length, thereby significantly reducing the processing overhead of the embedded storage device.
[0034] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0035] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this disclosure and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0036] Figure 1 is a schematic structural block diagram of an electronic device provided in an embodiment of this disclosure;
[0037] Figure 2 is a schematic structural block diagram of an embedded storage device provided in an embodiment of this disclosure;
[0038] Figure 3 is a flowchart illustrating a data reading method provided in an embodiment of this disclosure;
[0039] Figure 4 is another flowchart illustrating a data reading method provided in an embodiment of this disclosure;
[0040] Figure 5 is a schematic diagram of a DMA module transmitting data according to an embodiment of this disclosure;
[0041] Figure 6 is a schematic structural block diagram of a data reading device provided in an embodiment of this disclosure.
[0042] Icons: 100 - Electronic device; 101 - Memory; 102 - Communication interface; 103 - Processor; 104 - Bus; 300 - Embedded storage device; 310 - DMA module; 320 - RAM cache; 400 - Data reading device; 410 - Command acquisition unit; 420 - Data reading unit. Detailed Implementation
[0043] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0044] Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely to illustrate selected embodiments of the disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.
[0045] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this disclosure, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0046] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0047] OMBR is the most basic read type in the embedded storage device protocol of embedded multimedia cards. After the host sends a read command, the embedded storage device prepares the data according to the read command address and transmits it to the host. According to the eMMC protocol, Open Multiple Read does not define the number of blocks to be read. The device will continuously transmit data blocks until it receives a stop transmission command, thus completing the read command request.
[0048] Thus, embedded storage devices typically prepare data for reading based on the capacity of their own Random Access Memory (RAM) cache. This means that regardless of the number of data blocks requested by the host, the device will read data from the NAND flash memory into the RAM cache before transmitting it to the host. Because this process is constrained by the size of the RAM cache and the time required to read data from the NAND flash memory, the latency of data transmission is always equal to the time required to read data from the NAND flash memory into the RAM cache. Therefore, the latency of a read command largely depends on hardware characteristics, rather than the specific size of the data block requested by the host. While this mechanism simplifies the design of read commands, it can also lead to unnecessary data latency and additional resource consumption.
[0049] Based on the above, this disclosure provides a data reading method, apparatus, electronic device, and storage medium. By preset the read data length and dynamically tracking the actual transmission length of the previous open multi-block read command, and using it as the preset read data length for the next multi-block read command, the read command latency can be reduced when the actual request length is less than or equal to the preset read data length, thereby significantly reducing the processing overhead of the embedded storage device.
[0050] To implement the process steps and functions of the various examples of this disclosure, please refer to Figure 1, which is a schematic structural block diagram of an electronic device provided in an embodiment of this disclosure. The electronic device 100 may be an embedded storage device, including a memory 101 and a processor 103. The memory 101 and the processor 103 are electrically connected directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses 104 or signal lines. The memory 101 can be used to store software programs and modules, and the processor 103 executes the software programs and modules stored in the memory 101 to perform various functional applications and data processing.
[0051] Electronic device 100 can be, but is not limited to, a personal computer (PC), a server, a distributed computer, etc. It is understood that electronic device 100 is not limited to a physical server, but can also be a virtual machine on a physical server, a virtual machine built on a cloud platform, or any other computer that can provide the same functionality as the server or virtual machine. The operating system of electronic device 100 can be, but is not limited to, Windows, Linux, etc.
[0052] The memory 101 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.
[0053] The communication connection between the electronic device 100 and external devices is achieved through at least one communication interface 102 (which can be wired or wireless).
[0054] The processor 103 may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of this embodiment can be completed by integrated logic circuits in the hardware of the processor 103 or by instructions in software form. The processor 103 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.
[0055] It is understood that the structure shown in Figure 1 is merely illustrative, and the electronic device 100 may include more or fewer components than those shown in Figure 1, or have a different configuration than that shown in Figure 1. The components shown in Figure 1 may be implemented using hardware, software, or a combination thereof.
[0056] The following is an exemplary description of the data reading method provided in the embodiments of this disclosure. Referring to Figures 2 and 3, Figure 2 is a schematic structural block diagram of an embedded storage device provided in an embodiment of this disclosure, and Figure 3 is a flowchart illustrating a data reading method provided in an embodiment of this disclosure. This method is applied to an embedded storage device 300 and includes the following steps as shown in Figure 3:
[0057] S210: Receive the current open multi-block read command sent by the host and obtain the preset read data length of the embedded storage device. If the current open multi-block read command is not the first data read, the preset read data length is set to the data transfer length accumulated by the DMA module after the previous multi-block read command has completed the data transfer.
[0058] The Open Multi-Block Read command is a read instruction in the eMMC protocol that allows the host to continuously read multiple data blocks without sending a separate command for each block. After sending this command, the host can continue reading data until a stop transmission command is sent. The preset read data length can be set when the embedded storage device is initially powered on, and can also be modified after each Open Multi-Block Read command is executed.
[0059] For the preset read data length, if the current open multi-block read command is not the first data read (i.e., the open multi-block read command has been used to read data before), then the preset read data length is the cumulative data transfer length of the DMA module 310 after the previous multi-block read command is completed.
[0060] S220: Based on the current open multi-block read command and the preset read data length, execute the target data read operation, cache the target data in the RAM cache, and transfer the target data in the RAM cache to the host through the DMA module.
[0061] The embedded storage device reads a corresponding number of data blocks as target data from the storage medium (such as a flash memory chip) according to a preset read data length, and caches the target data in the RAM cache 320. The target data in the RAM cache is then transferred to the host via the DMA module. The DMA module is configured to efficiently transfer data from the RAM cache to the host. The DMA module allows data to be transferred directly between the storage device and the host without CPU intervention, thereby improving transfer efficiency and reducing the CPU load.
[0062] This method uses a preset read data length stored in the embedded storage device. When the actual data requested by the host is less than or equal to the preset read data length, the data only needs to be prepared according to the preset read data length, without having to prepare the read data according to its own cache size. This reduces the read command latency and significantly reduces the processing overhead of the embedded storage device.
[0063] In a single data read, the preset read data length may be less than the actual data to be read. After the DMA module completes the current data transfer, it needs to continue reading the target data. The method may also include: after the DMA module completes the current data transfer, if no stop transmission command is received from the host, the preset read data length is set to the capacity of the embedded storage device, and the next target data read is performed until a stop transmission command is received from the host.
[0064] If no stop transmission command is received from the host after the DMA module completes the current data transfer, it means that the data of the current open multi-block read command has not been read. When reading the target data for the next time, the preset read data length is first set to the capacity of the embedded storage device. When the open multi-block read command reads data in the future, the preset read data length will be the capacity of the embedded storage device.
[0065] Optionally, the method may further include: after receiving a stop transmission command from the host, obtaining the accumulated data transmission length of the DMA module, and using the accumulated data transmission length as the preset read data length for the next multi-block read command.
[0066] Specifically, after the data reading of the current open multi-block read command is completed, i.e. the host sends a stop transmission command, the DMA module will record the total data length transmitted in this open multi-block read command and use this total data length as the preset read data length for the next multi-block read command.
[0067] For example, referring to Figure 4, the data reading process of an open multi-block read command provided in this embodiment of the disclosure includes:
[0068] S1: Sets the read data length of the multi-block read command to the preset read data length.
[0069] If this read command is not the first open multi-block read command after the embedded storage device is powered on, the preset read data length is the actual transmission length of the previous open multi-block read command. If it is the first open multi-block read command, the preset read data length is the storage capacity of the embedded storage device.
[0070] In one possible implementation, if the current open multi-block read command is the first data read, the preset read data length is set to be less than or equal to the RAM cache size. For example, if the RAM cache size is 2GB and the preset read data length is set to 1GB, when the open multi-block read command is the first data read, if the actual data to be read is less than 1GB, then this data read does not need to read 2GB of data into the RAM cache, which can improve data read efficiency.
[0071] S2: Read data from flash memory into RAM cache according to the adjusted read data length.
[0072] S3: CPU configures DMA module to start data transfer.
[0073] The steps for transferring data using the DMA module may include:
[0074] Configure the data transfer direction, starting address, block size, and number of blocks for the DMA module.
[0075] The target data is transferred from the RAM cache to the host via the DMA module, starting from the starting address and according to the block size and the number of blocks.
[0076] Referring to Figure 5, after the data is read into the RAM cache, the CPU completes the data transfer from the RAM cache to the eMMC hardware interface by configuring the DMA module, and then transmits the data to the host-side eMMC interface via the eMMC BUS. The core parameters for configuring the DMA module include: DMA direction: RAM cache to eMMC hardware interface; DMA start address: the physical address of the RAM cache; DMA block size: typically the sector size, such as 512 bytes; DMA block quantity: the number of data blocks to be transferred in this operation.
[0077] S4: Wait for the DMA module to complete or abort the transfer.
[0078] A DMA module transfer completion indicates that the data in the RAM cache has been transferred to the host, but no stop transfer command has been received from the host. A DMA module transfer abort indicates that a stop transfer command has been received from the host.
[0079] S5: If the DMA module transfer is completed and the host does not send a stop transfer command, then update the cumulative data transfer length of the DMA module in this transfer, and update the starting address of the next data read. The data read length is restored to the default data length of the open read command, which is the capacity of the embedded storage device. Continue to repeat steps S2 to S4 until the DMA module transfer is stopped.
[0080] S6: If the DMA module transfer is interrupted, the host sends a stop transfer command, accumulates the length of the data transferred in this DMA transfer, and sets the accumulated value to the actual data length read in this open multi-block read command. The preset read data length is then set to this actual read data length, and the next open multi-block read command will use this preset read data length for data reading. The processing of this open multi-block read command ends.
[0081] After caching the target data in the RAM cache, the DMA module transfers the data to the host. During this period, the embedded storage device does nothing else. To further accelerate data reading, the data needed by the host can be prepared during this time. Based on this, in one possible implementation, after performing the target data read operation according to the current open multi-block read command and the preset read data length, and caching the target data in the RAM cache, the method may further include:
[0082] Based on the current open multi-block read command and the preset read data length, perform a pre-read operation on the predicted target data to obtain the predicted target data.
[0083] After the DMA module has completed transmitting the target data and has not received a stop transmission command from the host, the predicted target data is cached in the RAM cache, and the predicted target data in the RAM cache is transmitted to the host through the DMA module.
[0084] Embedded storage devices perform predictive read operations based on current multi-block read commands and preset read data lengths. By analyzing current read patterns and historical data access patterns, they pre-read potentially needed data to optimize subsequent read efficiency. After the DMA module completes a transfer of target data, it checks whether a stop transfer command has been received from the host. If no stop transfer command is received, the previously predicted target data is directly cached in RAM. The predicted target data in RAM cache is then transferred to the host again via the DMA module, ensuring that the host can seamlessly obtain the required data.
[0085] There are several scenarios for caching the predicted target data in RAM and then transferring the predicted target data from RAM to the host via a DMA module. The size of the predicted target data may be smaller or larger than the RAM cache size. Based on this scenario, the steps for caching the predicted target data in RAM and transferring the predicted target data from RAM to the host via a DMA module may include:
[0086] In one embodiment, when the size of the predicted target data is less than or equal to that of the RAM cache, all the predicted target data is cached in the RAM cache, and the predicted target data in the RAM cache is transferred to the host through the DMA module.
[0087] In another embodiment, if the size of the predicted target data is larger than the RAM cache, the first predicted target data of the RAM cache size is cached in the RAM cache, and the first predicted target data in the RAM cache is transferred to the host through the DMA module.
[0088] Optionally, during the process of transferring the first predicted target data from the RAM cache to the host via the DMA module, a data request for the remaining second predicted target data is sent to the flash memory to prepare the second predicted target data.
[0089] After the first prediction target data in the RAM cache is transferred through the DMA module, the second prediction target data is cached in the RAM cache and then transferred to the host through the DMA module.
[0090] Specifically, if the size of the predicted target data is less than or equal to the size of the RAM cache, all the predicted target data is directly read into the RAM cache, and the DMA module is used to transfer the predicted target data in the RAM cache to the host.
[0091] If the size of the predicted target data exceeds the RAM cache size, segmented transmission is required. First, the first set of predicted target data, equal in size to the RAM cache, is loaded into the RAM cache. Then, two operations are performed simultaneously: the DMA module is initiated to transfer the first predicted target data from the RAM cache to the host, while a read request for the second predicted target data is sent to the flash memory, utilizing the time difference in the DMA module's transmission to prepare the data in advance. Once the first predicted target data transmission is complete, the second predicted target data is immediately loaded into the RAM cache, and the DMA module is used again to transfer the second predicted target data to the host.
[0092] To free up RAM cache resources, the method may further include: if the actual accessed data is less than the size of the predicted target data, then clearing the predicted target data that has been read and cached in the RAM cache.
[0093] When the DMA module is transferring data, if a stop transfer command is received from the host before the data transfer in the RAM cache is completed, the RAM cache still contains the read target data, which needs to be cleared.
[0094] Optionally, referring to FIG6, this disclosure also provides a data reading device for use in an embedded storage device, the data reading device 400 including:
[0095] Command acquisition unit 410 is configured to receive the current open multi-block read command sent by the host and acquire the preset read data length of the embedded storage device. If the current open multi-block read command is not the first data read, the preset read data length is set to the data transfer length accumulated by the DMA module after the previous multi-block read command has completed the data transfer.
[0096] The data reading unit 420 is configured to perform a target data reading operation based on the current open multi-block read command and the preset read data length, cache the target data in the RAM cache, and transfer the target data in the RAM cache to the host through the DMA module.
[0097] In summary, the data reading method, apparatus, electronic device, and storage medium provided in this disclosure reduce read command latency and significantly decrease the processing overhead of embedded storage devices when the actual requested length is less than or equal to the preset read data length. By presetting the read data length and dynamically tracking the actual transmission length of the previous open multi-block read command, and using it as the preset read data length for the next multi-block read command, the read command latency can be reduced. Furthermore, by predicting and preparing the target data after reading data from flash memory into the RAM cache, the speed of the next data read from flash memory can be accelerated.
[0098] In the embodiments provided in this disclosure, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions configured to perform a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.
[0099] In addition, the functional modules in the various embodiments of this disclosure can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.
[0100] If a function is implemented as a software module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a computer-readable storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.
[0101] The above are merely preferred embodiments of this disclosure and are not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.
[0102] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims. Industrial applicability
[0103] By adopting the above scheme, by preset the read data length and dynamically tracking the actual transmission length of the previous open multi-block read command, and using it as the preset read data length for the next multi-block read command, the read command latency can be reduced when the actual request length is less than or equal to the preset read data length, thus significantly reducing the processing overhead of the embedded storage device.
Claims
1. A data reading method, characterized in that, Applied to embedded storage devices, the method includes: Receive the current open multi-block read command sent by the host and obtain the preset read data length of the embedded storage device. If the current open multi-block read command is not the first data read, the preset read data length is set to the data transfer length accumulated by the DMA module after the previous multi-block read command has completed the data transfer. Based on the current open multi-block read command and the preset read data length, the target data read operation is executed, the target data is cached in the RAM cache, and the target data in the RAM cache is transferred to the host through the DMA module.
2. The method according to claim 1, characterized in that, The method further includes: After the DMA module completes the current data transfer, if it does not receive a stop transmission command from the host, it sets the preset read data length to the capacity of the embedded storage device and performs the next target data read until it receives a stop transmission command from the host.
3. The method according to claim 2, characterized in that, The method further includes: After receiving the stop transmission command sent by the host, the accumulated data transmission length of the DMA module is obtained, and the accumulated data transmission length is used as the preset read data length for the next multi-block read command.
4. The method according to claim 1, characterized in that, The step of transferring the target data from the RAM cache to the host via the DMA module includes: Configure the data transfer direction, starting address, block size, and number of blocks for the DMA module; The DMA module transfers the target data from the RAM cache to the host, starting from the starting address and according to the block size and the number of blocks.
5. The method according to claim 4, characterized in that, The data transmission direction is from the RAM cache to the eMMC hardware interface, the starting address is the physical address of the RAM cache, the block size is the sector size, and the number of blocks is the number of data blocks to be transmitted this time.
6. The method according to claim 1, characterized in that, After the step of performing a target data read operation based on the current open multi-block read command and the preset read data length, and caching the target data in the RAM cache, the method further includes: Based on the current open multi-block read command and the preset read data length, perform a pre-read operation of the predicted target data to obtain the predicted target data; After the DMA module completes the transmission of the target data and no stop transmission command is received from the host, the predicted target data is cached in the RAM cache, and the predicted target data in the RAM cache is transmitted to the host through the DMA module.
7. The method according to claim 6, characterized in that, The step of caching the predicted target data in the RAM cache and transferring the predicted target data in the RAM cache to the host via the DMA module includes: If the size of the predicted target data is less than or equal to that of the RAM cache, all the predicted target data is cached in the RAM cache, and the predicted target data in the RAM cache is transferred to the host through the DMA module.
8. The method according to claim 7, characterized in that, The method further includes: If the size of the predicted target data is greater than the size of the RAM cache, the first predicted target data of the RAM cache size is cached in the RAM cache; The first predicted target data in the RAM cache is transferred to the host via the DMA module.
9. The method according to claim 8, characterized in that, The method further includes: During the process of transferring the first predicted target data in the RAM cache to the host through the DMA module, a data request for the remaining second predicted target data is sent to the flash memory so that the flash memory prepares the second predicted target data. After the first predicted target data in the RAM cache is transferred through the DMA module, the second predicted target data is cached in the RAM cache, and then the second predicted target data is transferred to the host through the DMA module.
10. The method according to claim 7, characterized in that, The method further includes: If the actual accessed data is less than the size of the predicted target data, then the predicted target data that has been read and cached in the RAM cache is cleared.
11. The method according to any one of claims 1-10, characterized in that, The method further includes: If the current open multi-block read command is the first data read, then the preset read data length is set to be less than or equal to the capacity of the RAM cache.
12. A data reading device, characterized in that, Applied to an embedded storage device, the device includes: The command acquisition unit is configured to receive the current open multi-block read command sent by the host and acquire the preset read data length of the embedded storage device. If the current open multi-block read command is not the first data read, the preset read data length is set to the data transfer length accumulated by the DMA module after the previous multi-block read command has completed the data transfer. The data reading unit is configured to perform a target data reading operation based on the current open multi-block read command and the preset read data length, cache the target data in the RAM cache, and transfer the target data in the RAM cache to the host through the DMA module.
13. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the program, it implements the method according to any one of claims 1 to 11.
14. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, it implements the method according to any one of claims 1 to 11.