Memory system, disaster recovery control method for memory system, and electronic device

Abstract

Provided in the present application are a memory system, a disaster recovery control method for a memory system, and an electronic device, which may be applied to the technical field of memory disaster recovery. The memory system comprises: a power supply monitoring module, which is used for monitoring mainboard power supply parameters of a mainboard power source interface; and a memory controller, which is electrically connected to the power supply monitoring module, wherein the memory controller is used for determining an operating mode of the memory system on the basis of the mainboard power supply parameters from the power supply monitoring module and heartbeat information of the memory system, determining a plurality of pieces of target data migration protocol information on the basis of a control instruction and a plurality of pieces of dynamic data stored in a dynamic random access memory when the operating mode is an emergency operating mode and the control instruction from a central processing unit has been received; and respectively calling a plurality of data migration protocol interfaces of the memory controller on the basis of the plurality of pieces of target data migration protocol information, so as to migrate the plurality of pieces of dynamic data from the dynamic random access memory to a target solid state disk among a plurality of solid state disks.

Description

Memory systems, memory system disaster recovery control methods and electronic devices

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510481769.8, filed on April 17, 2025, entitled “Memory System, Memory System Disaster Recovery Control Method and Electronic Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of memory disaster recovery, specifically to a memory system, a memory system disaster recovery control method, and an electronic device. Background Technology

[0004] A memory controller is a hardware component that supports high-performance memory interconnect protocols. It optimizes traditional memory architectures and improves the efficiency of data interaction between memory and the central processing unit (CPU), enabling memory systems to meet the demands of today's high-intensity data scenarios. However, in the event of a failure, memory controller-based memory systems often lack robust disaster recovery capabilities. Summary of the Invention

[0005] In view of the above problems, this application provides a memory system, a memory system disaster recovery control method, and an electronic device.

[0006] According to a first aspect of this application, a memory system is provided, comprising: a power supply monitoring module for monitoring motherboard power supply parameters of the motherboard power interface; and a memory controller electrically connected to the power supply monitoring module, wherein the memory controller is configured to: determine the operating mode of the memory system based on the motherboard power supply parameters from the power supply monitoring module and the heartbeat information of the memory system; and, when the operating mode is emergency operating mode and a control instruction is received from the central processing unit, determine multiple target data migration protocol information based on the control instruction and multiple dynamic data stored in dynamic random access memory; and, based on the multiple target data migration protocol information, call multiple data migration protocol interfaces of the memory controller respectively to migrate the multiple dynamic data from dynamic random access memory to target solid-state drives in multiple solid-state drives.

[0007] The second aspect of this application provides a memory system disaster recovery control method, comprising: obtaining motherboard power supply parameters of the motherboard power interface; determining the operating mode of the memory system based on the motherboard power supply parameters and the heartbeat information of the memory system; when the operating mode is emergency operating mode and a control instruction is received from the central processing unit, determining multiple target data migration protocol information based on the control instruction and multiple dynamic data stored in dynamic random access memory; and, based on the multiple target data migration protocol information, calling multiple data migration protocol interfaces respectively to migrate multiple dynamic data from dynamic random access memory to a target solid-state drive.

[0008] A third aspect of this application provides an electronic device comprising: one or more processors; and a memory for storing one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement the steps of the method described above.

[0009] A fourth aspect of this application also provides a computer non-volatile readable storage medium having a computer program or instructions stored thereon, wherein the computer program or instructions, when executed by a processor, implement the steps of the above method.

[0010] The fifth aspect of this application also provides a computer program product, including a computer program or instructions that, when executed by a processor, implement the steps of the above-described method.

[0011] According to embodiments of this application, the memory system may include a power supply monitoring module, a memory controller, and memory modules. The power supply monitoring module is electrically connected to the motherboard power interface, the central processing unit is electrically connected to the memory controller, the memory controller is electrically connected to the power supply monitoring module, and the memory modules are electrically connected to the memory controller. The power supply monitoring module monitors the motherboard power supply parameters of the motherboard power interface in real time and sends these parameters to the memory controller via an integrated circuit bus protocol or a system management bus protocol, enabling the memory controller to quickly determine the operating mode and configure the current power supply mode.

[0012] According to embodiments of this application, the memory controller determines the current operating mode of the memory system based on motherboard power supply parameters and the memory system's heartbeat information. When the operating mode is emergency operating mode and a control command is received from the central processing unit, multiple target data migration protocol information is determined based on the information in the control command and multiple dynamic data stored in the dynamic random access memory. Then, based on the multiple target data migration protocol information, multiple data migration protocol interfaces are called respectively, thereby quickly and orderly migrating and storing the multiple dynamic data in the dynamic random access memory to the target solid-state drive. Thus, in the event of a memory system failure, nanosecond-level power switching can be achieved through multi-protocol collaborative control and dynamic power management. Furthermore, by backing up volatile dynamic data to the solid-state drive for storage, the risk of data loss in disaster recovery scenarios can be reduced, and the integrity of dynamic data and system configuration parameters can be improved. Further, depending on different disaster recovery scenarios, different protocols or different protocol retrieval orders can be used to adaptively back up volatile dynamic data and system configuration parameters to the solid-state drive for storage, improving the flexibility and adaptability of the memory system, thus enabling its widespread application in various high-standard data-intensive scenarios. Attached Figure Description

[0013] The above-mentioned contents, other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0014] Figure 1 shows a schematic diagram of a memory system according to an embodiment of this application;

[0015] Figure 2 shows a schematic diagram of a data migration engine and a data migration protocol module according to an embodiment of this application;

[0016] Figure 3 shows a schematic diagram of a data migration engine according to an embodiment of this application;

[0017] Figure 4 shows a schematic diagram of a solid-state drive according to an embodiment of this application;

[0018] Figure 5 shows a schematic diagram of an enable controller according to an embodiment of this application;

[0019] Figure 6 shows a schematic diagram of a power supply monitoring module according to an embodiment of this application;

[0020] Figure 7 shows a schematic diagram of a charge / discharge electronic module according to an embodiment of this application;

[0021] Figure 8 shows a flowchart of a memory system disaster recovery control method according to an embodiment of this application;

[0022] Figure 9 shows a block diagram of an electronic device suitable for implementing a memory system disaster recovery control method according to an embodiment of this application. Detailed Implementation

[0023] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of this application for ease of explanation. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0025] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0026] When using expressions such as "at least one of A, B, and C", they should generally be interpreted in accordance with the meaning that is commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B, and C, etc.).

[0027] A memory controller is a hardware component that supports high-performance memory interconnect protocols. It optimizes traditional memory architectures and improves the efficiency of data interaction between memory and the central processing unit (CPU), enabling memory systems to meet the demands of today's high-intensity data scenarios. However, in the event of a failure, memory controller-based memory systems often lack robust disaster recovery capabilities.

[0028] An embodiment of this application provides a memory system, including: a power supply monitoring module for monitoring motherboard power supply parameters of the motherboard power interface; and a memory controller electrically connected to the power supply monitoring module. The memory controller is used to: determine the operating mode of the memory system based on the motherboard power supply parameters from the power supply monitoring module and the heartbeat information of the memory system; when the operating mode is emergency operating mode and a control instruction is received from the central processing unit, determine multiple target data migration protocol information based on the control instruction and multiple dynamic data stored in dynamic random access memory; and, based on the multiple target data migration protocol information, call multiple data migration protocol interfaces of the memory controller to migrate multiple dynamic data from dynamic random access memory to target solid-state drives in multiple solid-state drives.

[0029] Figure 1 shows a schematic diagram of a memory system according to an embodiment of this application.

[0030] As shown in Figure 1, the memory system includes a power supply monitoring module 101, a memory controller 102, and a memory module 103. The power supply monitoring module 101 monitors the motherboard voltage at the motherboard power interface 104. The central processing unit 105 interacts with the memory controller 102. The memory module 103 includes multiple dynamic random access memory 1031 and multiple solid-state drives 1032.

[0031] According to an embodiment of this application, the power supply monitoring module is used to monitor the motherboard power supply parameters of the motherboard power interface.

[0032] The power supply monitoring module can be electrically connected to hardware components such as the memory controller and memory modules. It can monitor the motherboard power supply parameters of the motherboard power interface while supplying power to the memory controller and memory modules to keep the memory system working. The power supply parameters of the power supply monitoring module are transmitted to the memory controller through the integrated circuit bus protocol or system management bus protocol so that the memory controller can perform control and storage operations. The motherboard power supply parameters include motherboard voltage and motherboard current. The power supply monitoring module usually monitors the motherboard voltage of the motherboard power interface so that the memory controller can determine the operating mode of the memory system based on the motherboard voltage.

[0033] According to an embodiment of this application, the memory controller is electrically connected to the power supply monitoring module. The memory controller is used to: determine the operating mode of the memory system based on the motherboard power supply parameters and the heartbeat information of the memory system from the power supply monitoring module; when the operating mode is emergency operating mode and a control instruction is received from the central processing unit, determine multiple target data migration protocol information based on the control instruction and multiple dynamic data stored in the dynamic random access memory; and, based on the multiple target data migration protocol information, call multiple data migration protocol interfaces of the memory controller to migrate multiple dynamic data from the dynamic random access memory to the target solid-state drives in the multiple solid-state drives.

[0034] The heartbeat information of the memory system can represent the operating status of the memory system within a certain period of time. Based on the heartbeat information, it can be determined whether the memory system has crashed.

[0035] The operating modes of a memory system can include multiple modes, such as normal operation mode, emergency operation mode, and paused operation mode, but are not limited to these modes. Based on motherboard power supply parameters and heartbeat information, the current operating mode of the memory system is determined. This allows for different operations to be performed by the memory controller and power supply monitoring module, including storing and migrating cached data sent by the central processing unit or data in the memory modules.

[0036] The target data migration protocol information may include the target solid-state drive used to store backup dynamic data.

[0037] According to an embodiment of this application, the memory system further includes a memory module electrically connected to the memory controller. The memory module may include multiple dynamic random access memories (DRAMs) and multiple solid-state drives (SSDs). The DRAMs may store multiple dynamic data sets, and the SSDs may store multiple non-volatile data sets. When the current operating mode of the memory system is determined to be emergency operating mode, the dynamic data in the DRAMs and the power supply parameters of the power supply monitoring module can be migrated and stored on the SSDs to back up the dynamic data. When the memory system returns to normal operating mode, the dynamic data and the power supply parameters of the power supply monitoring module can be restored.

[0038] According to embodiments of this application, the memory system may include a power supply monitoring module, a memory controller, and memory modules. The power supply monitoring module is electrically connected to the motherboard power interface, the central processing unit is electrically connected to the memory controller, the memory controller is electrically connected to the power supply monitoring module, and the memory modules are electrically connected to the memory controller. The power supply monitoring module monitors the motherboard power supply parameters of the motherboard power interface in real time and sends these parameters to the memory controller via an integrated circuit bus protocol or a system management bus protocol, enabling the memory controller to quickly determine the operating mode and configure the current power supply mode.

[0039] The memory controller determines the current operating mode of the memory system based on the motherboard power supply parameters and the memory system's heartbeat information. When the operating mode is emergency mode and a control command is received from the central processing unit, multiple target data migration protocol information is determined based on the information in the control command and multiple dynamic data stored in the dynamic random access memory. Then, based on the multiple target data migration protocol information, multiple data migration protocol interfaces are called respectively, thereby quickly and orderly migrating and storing the multiple dynamic data in the dynamic random access memory to the target solid-state drive. Thus, in the event of a memory system failure, nanosecond-level power switching can be achieved through multi-protocol coordinated control and dynamic power management. In addition, by backing up volatile dynamic data to the solid-state drive, the risk of data loss in disaster recovery scenarios can be reduced, and the integrity of dynamic data and system configuration parameters can be improved. Furthermore, depending on different disaster recovery scenarios, different protocols or different protocol retrieval orders can be used to adaptively back up volatile dynamic data and system configuration parameters to the solid-state drive, improving the flexibility and adaptability of the memory system, thus enabling its widespread application in various high-standard data-intensive scenarios.

[0040] When the memory system is in emergency operation mode, unused data channels can be shut down, leaving only the x4 link (4 data transmission channels) or x2 link (2 data transmission channels) open. This reduces the serializer drive current to 30% of its normal value, lowers the clock frequency and system power consumption, and retains only the functions required for data migration.

[0041] According to an embodiment of this application, the target data migration protocol information includes the target data migration protocol and the target data migration protocol priority.

[0042] Figure 2 shows a schematic diagram of a data migration engine and a data migration protocol module according to an embodiment of this application.

[0043] As shown in Figure 2, the memory controller 102 includes a data migration engine 201 and a data migration protocol module 202. The data migration engine 201 is electrically connected to the central processing unit 105 and the power supply monitoring module 101. The data migration protocol module 202 is electrically connected to the data migration engine 201. The data migration protocol module 202 can obtain hard disk attribute information and dynamic data from the target solid-state drive 203 and dynamic random access memory 1031 by calling the data migration access protocol interface, and determine multiple target data migration protocols and their priorities.

[0044] According to an embodiment of this application, the data migration engine is electrically connected to the central processing unit (CPU). The data migration engine is used to send an emergency power supply mode configuration command to the power supply monitoring module according to the emergency operation mode; in response to the power supply monitoring module being configured to emergency power supply mode, it generates emergency operation information based on multiple dynamic data and the hard disk attribute information of the solid-state drive (SSD), and calls the data migration access protocol interface to send the emergency operation information to the CPU; and calls the data migration control protocol interface to receive control commands generated by the CPU in response to the emergency operation information, the control commands including multiple target migration information and target SSD information.

[0045] When the memory system is determined to be in emergency operation mode, the memory controller generates an emergency power supply mode configuration instruction and sends it to the power supply monitoring module via the integrated circuit bus protocol or system management bus protocol. After receiving the emergency power supply mode configuration instruction, the power supply monitoring module can adjust the power supply voltage to hardware components such as the memory controller and memory modules, so that the hardware components such as the memory controller and memory modules can migrate and store dynamic data to the target solid-state drive in emergency operation mode, maintaining the temporary working state of the memory system.

[0046] When the power supply monitoring module is configured in emergency power supply mode, it can call the data migration access protocol interface to obtain multiple dynamic data and hard disk attribute information from multiple dynamic random access memory and multiple solid-state drives. Then, it generates emergency operation information based on the multiple dynamic data and hard disk attribute information, and then calls the data migration access protocol interface to send the emergency operation information to the central processing unit. The hard disk attribute information may include the storage capacity and storage capacity of the solid-state drive.

[0047] After receiving the emergency operation information, the central processing unit generates control instructions containing the target solid-state drive and target migration information based on the hard drive attribute information of each solid-state drive. The target migration information may include migration instructions such as dynamic data switching, backup, update, and address allocation.

[0048] According to an embodiment of this application, the data migration protocol module is electrically connected to the data migration engine and is used to determine multiple target data migration protocols and multiple target data migration protocol priorities for multiple dynamic data based on multiple target migration information.

[0049] According to an embodiment of this application, the data migration protocol module is further configured to: determine multiple first data migration protocols for multiple dynamic data based on multiple target migration information; call a data migration access protocol interface to perform consistency verification on multiple dynamic data stored in dynamic random access memory and non-volatile data stored in a target solid-state drive to obtain first storage consistency information; determine multiple target data migration protocols based on the first storage consistency information and the first data migration protocols; and determine the target data migration protocol priority of the multiple target data migration protocols based on the multiple target migration information and the multiple dynamic data.

[0050] Based on multiple target migration information, multiple first data migration protocols can be determined for migrating multiple dynamic data. For example, when the target migration information is switchover, backup, update, or address allocation, multiple first data migration protocols can all be data migration storage protocols, but they are not limited to the above migration information. The target migration information can have custom opcodes, thereby extending the migration information instructions. When the target migration information is address allocation and backup, multiple first data migration protocols can also be data migration control protocols and data migration storage protocols; when the target migration information is update, backup, or address allocation, multiple first data migration protocols can also be data migration access protocols, data migration storage protocols, and data migration control protocols.

[0051] The first storage consistency information can characterize the identical data between multiple dynamic data stored in dynamic random access memory and the non-volatile data stored in the target solid-state drive. Based on the first storage consistency information, a portion of the dynamic data already stored in the target solid-state drive can be marked, thus eliminating the need to migrate and store that portion of dynamic data again.

[0052] The priority of target migration information can be preset, thereby determining the priority of multiple target data migration protocols to be used based on the preset priority of target migration information. For example, backup migration information can be preset as the first priority, address migration information as the second priority, and update migration information as the third priority, so that the priority of data migration storage protocol is greater than that of data migration control protocol, which is greater than that of data migration access protocol.

[0053] Furthermore, based on the number of dynamic data items corresponding to each target migration information, the target data migration protocol with the largest number of dynamic data items corresponding to that migration information can be assigned the highest priority, while the target data migration protocol with the smallest number of dynamic data items corresponding to that migration information can be assigned the lowest priority. For example, if there are 500 dynamic data items corresponding to backup migration information, 30 dynamic data items corresponding to address migration information, and 172 dynamic data items corresponding to update migration information, then the data migration storage protocol can be assigned the first priority, the data migration access protocol the second priority, and the data migration control protocol the third priority.

[0054] Multiple priority weights and empirical parameters for calling target migration information can be pre-defined. Then, multiple data size weights are set based on the storage size occupied by multiple dynamic data corresponding to each target migration information. Finally, the emergency duration weight is determined based on the duration of the emergency operation mode. By multiplying the call priority weight, empirical parameters, data size weight, and emergency duration weight, the target weight corresponding to the target data migration protocol is calculated. Based on the magnitude of the target weight, the priority of multiple target data migration protocols is determined.

[0055] For example, the priority weight for calling backup migration information is pre-set to 0.7, the priority weight for calling address migration information is pre-set to 0.6, and the priority weight for calling update migration information is pre-set to 0.4. The empirical parameters for backup migration information are set to 0.5, for address migration information to 0.3, and for update migration information to 0.4. The storage size occupied by multiple dynamic data corresponding to backup migration information is 500MB, the storage size occupied by multiple dynamic data corresponding to address migration information is 1000MB, and the storage size occupied by multiple dynamic data corresponding to update migration information is 800MB. Therefore, the data size weight of the multiple dynamic data corresponding to backup migration information is 0.25, the data size weight of the multiple dynamic data corresponding to address migration information is 0.7, and the data size weight of the multiple dynamic data corresponding to backup migration information is 0.5. The current duration of the memory system in emergency operation mode is 2 minutes, and the emergency duration weight is determined to be 0.6. Multiplying the above weights together, we get a target weight of 0.0525 for the data migration storage protocol, a target weight of 0.0756 for the data migration control protocol, and a target weight of 0.048 for the data migration orientation protocol. Thus, we determine that the data migration control protocol is the first priority, the data migration storage protocol is the second priority, and the data migration access protocol is the third priority.

[0056] According to embodiments of this application, by determining the priority of multiple target data migration protocols, the disaster recovery requirements of the memory system under different disaster recovery scenarios can be flexibly addressed, improving the flexibility and adaptability of the memory system, and thus enabling its widespread application in various high-standard data-intensive scenarios.

[0057] According to an embodiment of this application, the memory controller includes a data migration engine and a data migration protocol module. The data migration engine and the data migration protocol module are electrically connected. In emergency operation mode, the power supply mode of the power supply monitoring module is configured using the data migration engine. Then, emergency operation information is generated based on multiple dynamic data and hard disk attribute information and sent to the central processing unit by calling the data migration access protocol interface. This allows the central processing unit to react quickly according to the current system status, generate and issue control commands, and prepare for the migration and storage of multiple dynamic data.

[0058] According to an embodiment of this application, after the data migration engine receives a control command, it sends it to the data migration protocol module. The data migration protocol module first determines the multiple first data migration protocols needed based on the multiple target migration information in the control command. Then, by calling the data migration access protocol interface, it confirms the data consistency information between the two storage areas. Based on the first storage consistency information, it filters the multiple first data migration protocols, removing those for dynamic data that does not require repeated backups, thus obtaining the target data migration protocol. Next, based on the target migration information and dynamic data, it determines the priority of the multiple target data migration protocols. This allows for the invocation of the corresponding protocol interface according to priority, enabling multi-protocol collaborative control. Under multi-protocol collaborative control, multiple dynamic data are migrated and stored, thereby reducing the risk of data loss in the memory system during disaster recovery scenarios and improving the integrity of dynamic data and system configuration parameters.

[0059] According to an embodiment of this application, the data migration engine is further configured to process multiple dynamic data and multiple target migration information according to multiple target data migration protocols and multiple target data migration protocol priorities, obtain multiple target dynamic data, and call the data migration storage protocol interface to store the multiple target dynamic data to the target solid-state drive.

[0060] Figure 3 shows a schematic diagram of a data migration engine according to an embodiment of this application.

[0061] As shown in Figure 3, the data migration engine 201 includes a monitoring trigger submodule 301, a direct memory access submodule 302, a data compression hybrid verification submodule 303, and a storage queue management submodule 304. The data compression hybrid verification submodule 303 includes a streaming compression engine 3031 and a hybrid verification unit 3032. The direct memory access submodule 302 migrates multiple dynamic data from the dynamic random access memory 1031 to the data compression hybrid verification submodule 303. The storage queue management submodule 304 stores multiple dynamically compressed data to the target solid-state drive 203 respectively.

[0062] According to an embodiment of this application, the monitoring triggering submodule is used to send multiple target migration information to the direct memory access submodule in response to receiving multiple target migration information.

[0063] The monitoring trigger submodule can also be used to receive cached data sent by the central processing unit (CPU). In emergency operation mode, if the memory system does not crash, cached data storage is suspended; if the memory system crashes, the CPU will not send any cached data to the data migration engine during the period of memory system failure.

[0064] According to an embodiment of this application, the direct memory access submodule is electrically connected to the monitoring trigger submodule and is used to sequentially call multiple data migration protocol interfaces based on the priority of multiple target data migration protocols to migrate multiple dynamic data and multiple target migration information from dynamic random access memory to the data compression hybrid verification submodule.

[0065] The direct memory access submodule can be a dual-channel direct memory access submodule. One channel can migrate multiple target migration information to the data compression and hybrid verification submodule in a lossless and zero-copy transmission manner. The other channel can call multiple data migration protocol interfaces in sequence according to the priority of multiple target data migration protocols to migrate multiple dynamic data to the data compression and hybrid verification submodule in a lossless and zero-copy transmission manner.

[0066] For example, the first priority is the data migration storage protocol, and the second priority is the data migration access protocol. Currently, there are five dynamic data items. The target migration information for the first, second, and fifth dynamic data items is backup, while the target migration information for the third and fourth dynamic data items is update. Based on the priorities of the multiple target data migration protocols, one channel migrates the backup target migration information to the data compression and hybrid verification submodule with lossless and zero-copy transmission. Another channel calls the data migration storage protocol interface to migrate the first, second, and fifth dynamic data items to the data compression and hybrid verification submodule with lossless and zero-copy transmission. Then, one channel migrates the update target migration information to the data compression and hybrid verification submodule with lossless and zero-copy transmission, and another channel calls the data migration access protocol interface to migrate the third and fourth dynamic data items to the data compression and hybrid verification submodule with lossless and zero-copy transmission.

[0067] According to an embodiment of this application, the direct memory access submodule is further used to call the data migration access protocol interface to transmit multiple verification information for multiple dynamic data to the data compression hybrid verification submodule, wherein the verification information includes a first redundancy check code and a first linear block code.

[0068] In addition to storing multiple dynamic data, dynamic random access memory can also store verification information corresponding to the dynamic data. This allows the verification information to be used to check the data migrated to the target SSD when the dynamic data is migrated and stored thereto, ensuring that the data stored on the target SSD is consistent with the data in the dynamic random access memory.

[0069] According to an embodiment of this application, the data compression and verification submodule is used to compress and verify multiple dynamic data and multiple target migration information to obtain multiple target dynamic data.

[0070] According to an embodiment of this application, the data compression hybrid verification submodule includes a streaming compression engine and a hybrid verification unit.

[0071] According to an embodiment of this application, the streaming compression engine is electrically connected to the direct memory access submodule for compressing multiple dynamic data to obtain multiple dynamically compressed data.

[0072] Compression methods can include LZ4 compression, but are not limited to the above compression methods.

[0073] According to an embodiment of this application, the hybrid verification unit is electrically connected to the streaming compression engine and is used to verify multiple dynamic compressed data using multiple verification information to obtain verification results; if the verification results indicate that the verification is passed, the multiple dynamic compressed data and multiple target migration information are packaged and processed separately to obtain multiple target dynamic data.

[0074] According to an embodiment of this application, the hybrid verification unit is further configured to obtain a first intermediate verification result based on a plurality of first redundancy check codes and a plurality of second redundancy check codes obtained by performing cyclic redundancy checks on a plurality of dynamically compressed data respectively; and if the first intermediate verification result indicates that the verification is passed, the first intermediate verification result is used as the verification result.

[0075] If the first redundancy check code and the second redundancy check code match, the first intermediate check result is confirmed as successful. If the first redundancy check code and the second redundancy check code do not match, the first intermediate check result is confirmed as unsuccessful.

[0076] According to an embodiment of this application, the hybrid verification unit is further configured to: perform error correction processing on the multiple dynamic compressed data based on the multiple first linear block codes and the multiple second linear block codes obtained by performing finite field verification on the multiple dynamic compressed data respectively, to obtain multiple dynamic corrected data; and obtain a second intermediate verification result based on the third redundancy check code and the first redundancy check code obtained by performing cyclic redundancy check on the multiple dynamic corrected data respectively, and use the second intermediate verification result as the verification result.

[0077] If the first intermediate verification result indicates that the verification fails, the first linear block code and the second linear block code are usually inconsistent. Therefore, based on the first linear block code, error correction operations in finite field verification are used to correct the dynamically compressed data, thereby obtaining dynamically corrected data.

[0078] If the third redundancy check code and the first redundancy check code match, both the second intermediate check result and the check result are considered to have passed. If the third redundancy check code and the first redundancy check code do not match, both the second intermediate check result and the check result are considered to have failed. The abnormal dynamic correction data is then removed from the pool of dynamic data to be migrated, ensuring that the correct dynamic compressed data can continue to be migrated and stored. Simultaneously, the abnormal dynamic correction data and the corresponding original dynamic compressed data can be temporarily stored in the hybrid check generation unit. After all dynamic compressed data has been successfully migrated to the storage queue management submodule, the abnormal dynamic correction data and the corresponding original dynamic compressed data are subjected to further error correction processing according to the predetermined error correction rounds.

[0079] Furthermore, during the verification process of each dynamically compressed data item, multiple first intermediate verification results and multiple second intermediate verification results can be obtained. Based on each first intermediate verification result and each second intermediate verification result, the dynamically compressed data items are sequentially released to the storage queue management submodule. This eliminates the need to wait for multiple dynamically compressed data items to pass verification before transmitting them to the storage queue management submodule, thus improving processing efficiency.

[0080] According to embodiments of this application, by combining multiple verification methods, the correctness of dynamically compressed data transmitted to the hybrid verification generation unit is verified using a first redundancy check code and a first linear block code. If verification using the first redundancy check code fails, error correction is performed using the first linear block code based on finite field verification, so that erroneous dynamic data can be corrected back to dynamic data consistent with the dynamic data stored in dynamic random access memory. This facilitates the storage of correct dynamically compressed data in the target solid-state drive, reducing the risk of data loss in disaster recovery scenarios for the memory system and improving the integrity and correctness of dynamic data and system configuration parameters.

[0081] According to embodiments of this application, the data migration engine further includes a storage queue management submodule.

[0082] According to an embodiment of this application, the storage queue management submodule is used to respond to receiving multiple target dynamic data from the data compression hybrid verification submodule, and store the multiple dynamically compressed data into multiple predetermined storage spaces of the target solid-state drive according to the multiple target migration information.

[0083] Figure 4 shows a schematic diagram of a solid-state drive according to an embodiment of this application.

[0084] As shown in Figure 4, each solid-state drive 1032 may include multiple predetermined storage spaces, including a configuration storage space 401, an address storage space 402, and a data storage space 403. The configuration storage space 401 can be used to store configuration information such as address allocation, mode configuration, and application type of the memory controller. The address storage space 402 can be used to store information such as the source address, destination address, and transmission ID routing of cached data. The data storage space 403 is used to store cached data and dynamic data.

[0085] Multiple pre-defined storage spaces may include configuration storage space, address storage space, and data storage space, but are not limited to these storage spaces.

[0086] The storage queue management submodule can be used to store multiple dynamically compressed data corresponding to configuration migration information in the configuration storage space; store multiple dynamically compressed data corresponding to address migration information in the address storage space; and store multiple dynamically compressed data corresponding to backup migration information in the data storage space.

[0087] According to embodiments of this application, by pre-dividing the storage space within the solid-state drive (SSD) based on its functions, and optimizing SSD write scheduling and channel allocation, better storage management of the SSD can be achieved. Furthermore, combined with the queue characteristics of the storage queue management submodule, multiple dynamic data can be stored in an orderly and efficient manner into their corresponding predetermined storage spaces, improving the efficiency of storage migration.

[0088] According to the embodiments of this application, through pipeline-style collaborative cooperation among multiple sub-modules and units within the data migration engine, combined with collaborative control among multiple protocols, lossless migration of 128GB of dynamic data can be achieved within 300ms, extending the backup time window of dynamic data and improving the effective throughput of the memory system.

[0089] According to embodiments of this application, the memory controller may further include a data migration confirmation module.

[0090] According to an embodiment of this application, the data migration confirmation module is used to call the data migration access protocol interface to confirm the consistency of multiple dynamic data stored in the dynamic random access memory and multiple non-volatile data stored in the target solid-state drive, and obtain second storage consistency information; when the second storage consistency information indicates that the storage is consistent, the emergency operation mode is switched to the pause operation mode, wherein the pause operation mode indicates that the migration of multiple dynamic data is frozen and the physical layer training state between the memory system and the central processing unit is maintained.

[0091] After all dynamic data in emergency operation mode has been migrated and stored to the target SSD, the memory system needs to switch to pause operation mode, freezing multiple dynamic data migrations and maintaining only the physical layer training state between the memory system and the CPU. Basic parameters such as balancing parameters and bit error rate are preserved, and the memory system's power consumption is reduced while awaiting host restart and wake-up. Therefore, the data migration confirmation module needs to re-confirm the consistency of the data stored on the target SSD and in dynamic random access memory. If the second storage consistency information indicates that the storage is consistent, it means that all dynamic data in dynamic random access memory has been backed up and stored on the target SSD. If the second storage consistency information indicates that the storage is inconsistent, the memory system needs to maintain emergency operation mode until the second storage consistency information indicates that the storage is consistent, at which point it enters pause operation mode.

[0092] According to an embodiment of this application, the memory controller is further configured to call multiple data migration protocol interfaces to store cached data from the central processing unit to multiple dynamic random access memory and / or multiple solid-state drives when the operating mode is normal operating mode.

[0093] When the memory system is in normal operating mode, multiple data migration protocol interfaces can be called simultaneously to perform various data processing functions while preserving all data channels.

[0094] Figure 5 shows a schematic diagram of an enable controller according to an embodiment of this application.

[0095] As shown in Figure 5, the memory system also includes an enable controller 501, which is electrically connected to the memory controller 102 and the power supply monitoring module 101. The central processing unit 105 is electrically connected to the memory controller 102.

[0096] According to an embodiment of this application, the enable controller is electrically connected to the memory controller and the power supply monitoring module, and is used to send an enable signal or an interrupt signal to the power supply monitoring module in response to the operating mode, so as to control the power supply monitoring module to switch to normal power supply mode or emergency power supply mode.

[0097] In normal operating mode, the memory controller controls the enable controller to send an enable signal to the power supply monitoring module, so that the memory system is powered by the motherboard voltage from the motherboard power interface. In emergency operating mode, the memory controller controls the enable controller to send an enable signal or an interrupt signal to the power supply monitoring module, so that the memory system is powered by the motherboard voltage from the motherboard power interface or by the backup power submodule within the power supply monitoring module.

[0098] According to embodiments of this application, the motherboard power supply parameters include the motherboard voltage, and the emergency power supply mode may include a first emergency power supply mode and a second emergency power supply mode.

[0099] According to an embodiment of this application, the memory controller is further configured to control the enable controller to send an enable signal to the power supply monitoring module when the motherboard voltage is greater than a first preset voltage threshold and the heartbeat information is greater than the first heartbeat threshold, so that the power supply monitoring module switches to a first emergency power supply mode.

[0100] According to an embodiment of this application, the memory controller is further configured to control the enable controller to send an interrupt signal to the power supply monitoring module when the motherboard voltage is less than a second preset voltage threshold, so that the power supply monitoring module switches to a second emergency power supply mode, wherein the first preset voltage threshold is greater than the second preset voltage threshold.

[0101] According to an embodiment of this application, the memory controller is further configured to: when the motherboard voltage is greater than a first preset voltage threshold and the heartbeat information is less than the first heartbeat threshold, control the enable controller to send an interrupt signal to the power supply monitoring module so that the power supply monitoring module switches to normal power supply mode.

[0102] The first preset voltage threshold can be 11.5V, the second preset voltage threshold can be 10.8V, and the first heartbeat threshold can be 30ms.

[0103] When the motherboard voltage is greater than a first preset voltage threshold and the heartbeat information is greater than a first heartbeat threshold, the first emergency power supply mode is powered by the motherboard voltage from the motherboard power interface. When the motherboard voltage is less than a second preset voltage threshold, the second emergency power supply mode is powered by the backup power submodule within the power supply monitoring module.

[0104] When the motherboard voltage is lower than the first preset voltage threshold but higher than the second preset voltage threshold, the memory system still operates in normal mode, and can send motherboard power supply parameters to the memory controller. The memory controller can closely monitor the motherboard voltage at this time, so as to quickly retrieve multiple dynamic data and solid-state drive attribute information when switching to emergency operation mode.

[0105] The system can be determined to enter emergency operation mode if either the heartbeat information is greater than the first heartbeat threshold or the motherboard voltage is less than the second preset voltage threshold. Then, the current emergency power supply mode is further determined based on the motherboard voltage at the motherboard power interface.

[0106] The operating modes, including normal operation mode, emergency operation mode, and pause operation mode, are shown in Table 1.

[0107] Table 1

[0108] Figure 6 shows a schematic diagram of a power supply monitoring module according to an embodiment of this application.

[0109] As shown in Figure 6, the power supply monitoring module 101 includes a monitoring submodule 601, a charge / discharge electronics module 602, a backup power supply submodule 603, and a power conversion submodule 604. The monitoring submodule 601 is electrically connected to the motherboard power interface 104. The charge / discharge electronics module 602 is electrically connected to the monitoring submodule 601, the backup power supply submodule 603, the enable controller 501, and the memory controller 102. The backup power supply submodule 603 is electrically connected to the charge / discharge electronics module 602. The power conversion submodule 604 is electrically connected to the charge / discharge electronics module 602, the monitoring submodule 601, the memory controller 102, and the memory module 103.

[0110] According to an embodiment of this application, the monitoring submodule is electrically connected to the motherboard power interface and is used to monitor the motherboard voltage. When the motherboard voltage is greater than a first preset voltage threshold, the monitoring submodule connects the motherboard power interface to the charging and discharging electronic module. When the motherboard voltage is less than a second preset voltage threshold, the monitoring submodule disconnects the motherboard power interface from the charging and discharging electronic module.

[0111] The monitoring submodule can monitor the motherboard voltage and current, and can be equipped with a switch. When the motherboard voltage is greater than a first preset voltage threshold, the switch is turned on, connecting the motherboard power interface to the charging / discharging electronic module. When the motherboard voltage is less than a second preset voltage threshold, the switch is turned off, disconnecting the motherboard power interface from the charging / discharging electronic module.

[0112] According to an embodiment of this application, the charge / discharge electronic module is electrically connected to the monitoring submodule and the backup power submodule, and is used to be in a charging state or a discharging state in response to the electrical connection state between the motherboard power interface and the charge / discharge electronic module.

[0113] Figure 7 shows a schematic diagram of a charge / discharge electronic module according to an embodiment of this application.

[0114] As shown in Figure 7, the charge / discharge electronic module 602 includes a power switching unit 701, an interaction unit 702, and a power dynamic adjustment unit 703. The power switching unit 701 is electrically connected to the monitoring submodule 601, the backup power submodule 603, and the power conversion submodule 604. The interaction unit 702 is electrically connected to the enable controller 501 and the memory controller 102. The power dynamic adjustment unit 703 is electrically connected to the power switching unit 701.

[0115] According to an embodiment of this application, the power switching unit is electrically connected to the monitoring submodule and the backup power submodule, and is used to control the power supply from the motherboard voltage to the memory controller when the motherboard power interface is connected to the charging and discharging electronic module, in normal power supply mode or first emergency power supply mode; and to control the backup power submodule to supply power to the memory controller when the motherboard power interface is disconnected from the charging and discharging electronic module, in second emergency power supply mode.

[0116] When the motherboard power interface is connected to the charging / discharging electronic module, the first terminal VIN0 of the power switching unit receives the motherboard voltage, VIN0 is pulled high to 1, and the second terminal VIN1 is pulled low to 0. Thus, in normal power supply mode or first emergency power supply mode, the power switching unit outputs the motherboard voltage. Simultaneously, in response to the charging status configuration command transmitted from the interaction unit, the power switching unit is configured to charge, using the output motherboard voltage to charge the backup power submodule. The motherboard power interface directly sends the motherboard voltage to the power conversion submodule, allowing the power conversion submodule to convert the motherboard voltage.

[0117] When the motherboard power interface is disconnected from the charging / discharging electronic module, the first terminal VIN0 of the power switching unit is pulled low to 0. The memory controller configures the backup power submodule to discharge mode, and the backup power submodule supplies power to the power switching unit. The second terminal VIN1 is pulled high to 1, so that the power switching unit outputs power voltage in the second emergency power supply mode. Simultaneously, in response to the discharge state configuration command transmitted from the interaction unit, the power switching unit is configured to discharge mode. The backup power submodule and the power switching unit jointly send power voltage to the power conversion submodule, enabling the power conversion submodule to convert the power voltage.

[0118] According to an embodiment of this application, the interaction unit is electrically connected to the enable controller and the memory controller, and is used to provide the power switching unit with the enable signal or interrupt signal from the enable controller and the charge / discharge state configuration instruction from the memory controller, and to provide the input voltage and output voltage of the power switching unit to the memory controller.

[0119] Based on the configuration parameters of the monitoring submodule and the backup power submodule transmitted via the integrated circuit bus protocol or system management bus protocol, the memory controller sends charging / discharging status configuration commands and voltage / current limiting configuration commands for the power switching unit to the interaction unit, and controls the enable controller to send an enable signal or interrupt signal to the interaction unit. Upon receiving the charging / discharging status configuration commands and the enable or interrupt signal, the interaction unit sends them to the power switching unit to switch the charging / discharging status, the on / off state of the first terminal VIN0, and the on / off state of the second terminal VIN1. After the power switching unit is configured, the configuration parameters can be sent back to the memory controller via the interaction unit. Specifically, reducing the serializer drive current to 30% of its normal value in emergency operation mode can be achieved by the memory controller sending the corresponding voltage / current limiting configuration command to the interaction unit.

[0120] According to an embodiment of this application, the power dynamic adjustment unit is electrically connected to the power switching unit and is used to dynamically adjust the input voltage and output voltage to stabilize the input voltage and output voltage.

[0121] When the motherboard power interface is connected to the charging / discharging electronic module, the power dynamic adjustment unit can dynamically adjust both the input and output motherboard voltages. When the motherboard power interface is disconnected from the charging / discharging electronic module, the power dynamic adjustment unit can dynamically adjust both the input and output power voltages.

[0122] According to an embodiment of this application, the backup power submodule is electrically connected to the charge / discharge electronic module and is used to supply power to the memory controller in response to the charge / discharge electronic module being in a discharge state.

[0123] The backup power submodule can be a battery module.

[0124] When the motherboard voltage is lower than the second preset voltage threshold, the backup power submodule in the discharge state and the charge / discharge electronic module in the discharge state jointly supply power to the memory system to maintain the memory system retaining only the power required for data migration.

[0125] The power conversion submodule is electrically connected to the monitoring submodule, charge / discharge electronics module, memory controller, and memory module. It converts the motherboard voltage or power supply voltage to obtain output voltages of various specifications to power different hardware components. For example, it can output 12V DC, 1.2V DC, 1.1V DC, and 0.6V DC. The 12V DC voltage powers the memory controller, and the 1.2V DC voltage powers the memory module.

[0126] Figure 8 shows a flowchart of a memory system disaster recovery control method according to an embodiment of this application.

[0127] As shown in Figure 8, the memory system disaster recovery control method of this embodiment includes operations S810 to S840.

[0128] Using the S810, obtain the motherboard power supply parameters from the motherboard power interface.

[0129] When operating the S820, the operating mode of the memory system is determined based on the motherboard power supply parameters and the memory system's heartbeat information.

[0130] When operating the S830 in emergency operation mode and receiving control instructions from the central processing unit, multiple target data migration protocol information is determined based on the control instructions and multiple dynamic data stored in dynamic random access memory.

[0131] When operating the S840, based on multiple target data migration protocol information, multiple data migration protocol interfaces are called to migrate multiple dynamic data from dynamic random access memory to the target solid-state drive.

[0132] After migrating multiple dynamic data sets from dynamic random access memory (DRAM) to the target SSD, the consistency of the data in DRAM and the target SSD is verified. Once the consistency is confirmed, the memory system's operating mode is switched to paused operation mode.

[0133] According to embodiments of this application, the motherboard power supply parameters of the motherboard power interface are first obtained, and then the operating mode of the memory system is determined based on the motherboard power supply parameters and the heartbeat information of the memory system. When a memory system failure occurs, the operating mode switches to emergency operating mode and receives control instructions from the central processing unit. Based on the control instructions and multiple dynamic data stored in dynamic random access memory, multiple target data migration protocol information is determined. Based on the multiple target data migration protocol information, multiple data migration protocol interfaces are called respectively to migrate multiple dynamic data from dynamic random access memory to the target solid-state drive. This achieves rapid switching of the memory system's operating mode through real-time monitoring of motherboard power supply parameters and heartbeat information, while configuring the switching of power supply units to achieve nanosecond-level power switching. The memory control protocol is dynamically adjusted under different operating states, ensuring data integrity while reducing power consumption. Compared with the prior art, the data loss risk of this application can be reduced by 90%.

[0134] Figure 9 shows a block diagram of an electronic device suitable for implementing a memory system disaster recovery control method according to an embodiment of this application.

[0135] As shown in FIG9, the electronic device according to an embodiment of the present application includes a processor 901, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 902 or a program loaded from a storage portion 908 into a random access memory (RAM) 903. The processor 901 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor, and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 901 may also include onboard memory for caching purposes. The processor 901 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present application.

[0136] RAM 903 stores various programs and data required for the operation of the electronic device. Processor 901, ROM 902, and RAM 903 are interconnected via bus 904. Processor 901 executes various operations of the method flow according to embodiments of this application by executing programs in ROM 902 and / or RAM 903. It should be noted that programs may also be stored in one or more memories other than ROM 902 and RAM 903. Processor 901 may also execute various operations of the method flow according to embodiments of this application by executing programs stored in one or more memories.

[0137] According to embodiments of this application, the electronic device may further include an input / output (I / O) interface 905, which is also connected to a bus 904. The electronic device 900 may also include one or more of the following components connected to the input / output (I / O) interface 905: an input section 906 including a keyboard, mouse, etc.; an output section 907 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 908 including a hard disk, etc.; and a communication section 909 including a network interface card such as a LAN card, modem, etc. The communication section 909 performs communication processing via a network such as the Internet. A drive 910 is also connected to the input / output (I / O) interface 905 as needed. A removable medium 911, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 910 as needed so that computer programs read from it can be installed into the storage section 908 as needed.

[0138] This application also provides a computer non-volatile readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The aforementioned computer non-volatile readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of this application.

[0139] According to embodiments of this application, a computer non-volatile readable storage medium may include, but is not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this application, a computer non-volatile readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of this application, a computer non-volatile readable storage medium may include ROM 902 and / or RAM 903 and / or one or more memories other than ROM 902 and RAM 903 described above.

[0140] Embodiments of this application also include a computer program product comprising a computer program containing program code for performing the methods shown in the flowchart. When the computer program product is run on a computer system, the program code enables the computer system to implement the memory system disaster recovery control method provided in the embodiments of this application.

[0141] When the computer program is executed by the processor 901, it performs the functions defined in the system / apparatus of this application embodiment. According to the embodiments of this application, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0142] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and downloaded and installed via the communication section 909, and / or installed from a removable medium 911. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0143] In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 909, and / or installed from the removable medium 911. When the computer program is executed by the processor 901, it performs the functions defined in the system of this application embodiment. According to the embodiments of this application, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0144] According to embodiments of this application, program code for executing the computer programs provided in the embodiments of this application can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0145] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0146] Those skilled in the art will understand that the features described in the various embodiments of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application.

[0147] The embodiments of this application have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of this application. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Without departing from the scope of this application, those skilled in the art can make various substitutions and modifications, all of which should fall within the scope of this application.

Claims

1. A memory system, characterized in that, The memory system includes: The power supply monitoring module is configured to monitor the motherboard power supply parameters of the motherboard power interface; The memory controller is electrically connected to the power supply monitoring module, and the memory controller is configured as follows: The operating mode of the memory system is determined based on the motherboard power supply parameters from the power supply monitoring module and the heartbeat information of the memory system. When the operating mode is emergency operating mode and a control instruction is received from the central processing unit, multiple target data migration protocol information is determined based on the control instruction and multiple dynamic data stored in dynamic random access memory. Based on multiple target data migration protocol information, multiple data migration protocol interfaces of the memory controller are invoked respectively to migrate multiple dynamic data from the dynamic random access memory to the target solid-state drives in multiple solid-state drives.

2. The system according to claim 1, characterized in that, The target data migration protocol information includes the target data migration protocol and the target data migration protocol priority; The memory controller includes: A data migration engine, electrically connected to the central processing unit (CPU), is configured to send an emergency power supply mode configuration command to the power supply monitoring module according to the emergency operation mode; in response to the power supply monitoring module being configured to emergency power supply mode, it generates emergency operation information based on multiple dynamic data and the hard drive attribute information of the solid-state drive (SSD), and calls a data migration access protocol interface to send the emergency operation information to the CPU; and calls a data migration control protocol interface to receive a control command generated by the CPU in response to the emergency operation information, the control command including multiple target migration information and target SSD information; and The data migration protocol module, electrically connected to the data migration engine, is configured to determine, based on the multiple target migration information, multiple target data migration protocols configured as multiple dynamic data and multiple target data migration protocol priorities.

3. The system according to claim 2, characterized in that, The data migration protocol module is also configured to: Based on the multiple target migration information, multiple first data migration protocols configured as multiple dynamic data are determined; the data migration access protocol interface is called to perform consistency verification on the multiple dynamic data stored in the dynamic random access memory and the non-volatile data stored in the target solid-state drive, and first storage consistency information is obtained; Based on the first storage consistency information and the first data migration protocol, a plurality of the target data migration protocols are determined; Based on multiple target migration information and multiple dynamic data, the target data migration protocol priority of multiple target data migration protocols is determined.

4. The system according to claim 2, characterized in that, The data migration engine is also configured to: Based on multiple target data migration protocols and their priorities, multiple dynamic data and multiple target migration information are configured and processed to obtain multiple target dynamic data. Then, the data migration storage protocol interface is called to store the multiple target dynamic data into the target solid-state drive.

5. The system according to claim 4, characterized in that, The data migration engine includes: The monitoring triggering submodule is configured to send multiple target migration messages to the direct memory access submodule in response to receiving multiple target migration messages; The direct memory access submodule is electrically connected to the monitoring triggering submodule and is configured to sequentially call multiple data migration protocol interfaces based on the priority of multiple target data migration protocols to migrate multiple dynamic data and multiple target migration information from the dynamic random access memory to the data compression hybrid verification submodule. The data compression and verification submodule is configured to compress and verify multiple sets of dynamic data and multiple sets of target migration information to obtain multiple sets of target dynamic data.

6. The system according to claim 5, characterized in that, The direct memory access submodule is also configured to: The data migration access protocol interface is invoked to transmit multiple verification information of the dynamic data that are configured as multiple data to the data compression hybrid verification submodule, wherein the verification information includes a first redundancy check code and a first linear block code.

7. The system according to claim 5, characterized in that, The data compression and hybrid verification submodule includes: A streaming compression engine, electrically connected to the direct memory access submodule, is configured to compress multiple dynamic data to obtain multiple dynamically compressed data. The hybrid verification unit, electrically connected to the streaming compression engine, is configured to verify multiple dynamically compressed data using multiple verification information to obtain verification results; if the verification results indicate that the verification is successful, the multiple dynamically compressed data and multiple target migration information are packaged separately to obtain multiple target dynamic data.

8. The system according to claim 7, characterized in that, The hybrid verification unit is further configured to: A first intermediate verification result is obtained based on multiple first redundancy check codes and multiple second redundancy check codes obtained by performing cyclic redundancy checks on multiple dynamically compressed data respectively. If the first intermediate verification result indicates that the verification is successful, the first intermediate verification result shall be used as the verification result.

9. The system according to claim 8, characterized in that, The hybrid verification unit is further configured to, in the event that the first intermediate verification result indicates that the verification has failed: Based on multiple first linear block codes and multiple second linear block codes obtained by performing finite field verification on multiple dynamically compressed data respectively, error correction processing is performed on multiple dynamically corrected data to obtain multiple dynamically corrected data. Based on the third redundancy check code and the first redundancy check code obtained by performing cyclic redundancy check on multiple dynamic correction data respectively, a second intermediate check result is obtained, and the second intermediate check result is used as the check result.

10. The system according to claim 5, characterized in that, The data migration engine also includes: The storage queue management submodule is configured to, in response to receiving multiple target dynamic data from the data compression hybrid verification submodule, store the multiple dynamically compressed data into multiple predetermined storage spaces of the target solid-state drive according to the multiple target migration information.

11. The system according to claim 1, characterized in that, The memory controller also includes: The data migration confirmation module is configured to call the data migration access protocol interface to confirm the consistency of multiple dynamic data stored in the dynamic random access memory and multiple non-volatile data stored in the target solid-state drive, and obtain second storage consistency information; if the second storage consistency information indicates storage consistency, the emergency operation mode is switched to the pause operation mode, wherein the pause operation mode indicates freezing the migration of multiple dynamic data and maintaining the physical layer training state between the memory system and the central processing unit.

12. The system according to claim 1, characterized in that, The memory controller is also configured to, when the operating mode is normal operating mode, call multiple data migration protocol interfaces to store cached data from the central processing unit to the dynamic random access memory or solid-state drive.

13. The system according to claim 1, characterized in that, The memory system also includes: An enable controller, electrically connected to the memory controller and the power supply monitoring module, is configured to send an enable signal or an interrupt signal to the power supply monitoring module in response to the operating mode, so as to control the power supply monitoring module to switch to normal power supply mode or emergency power supply mode.

14. The system according to claim 13, characterized in that, The motherboard power supply parameters include the motherboard voltage, and the emergency power supply modes include a first emergency power supply mode and a second emergency power supply mode. The memory controller is further configured to: when the motherboard voltage is greater than a first preset voltage threshold and the heartbeat information is greater than the first heartbeat threshold, control the enable controller to send the enable signal to the power supply monitoring module so that the power supply monitoring module switches to the first emergency power supply mode; and when the motherboard voltage is less than a second preset voltage threshold, control the enable controller to send the interrupt signal to the power supply monitoring module so that the power supply monitoring module switches to the second emergency power supply mode, wherein the first preset voltage threshold is greater than the second preset voltage threshold.

15. The system according to claim 14, characterized in that, The memory controller is also configured to: When the motherboard voltage is greater than the first preset voltage threshold and the heartbeat information is less than the first heartbeat threshold, the enable controller is controlled to send the interrupt signal to the power supply monitoring module so that the power supply monitoring module switches to the normal power supply mode.

16. The system according to claim 1, characterized in that, The power supply monitoring module includes: A monitoring submodule, electrically connected to the motherboard power interface, is configured to monitor the motherboard voltage. When the motherboard voltage is greater than a first preset voltage threshold, the monitoring submodule connects the motherboard power interface to the charging / discharging electronic module. When the motherboard voltage is less than a second preset voltage threshold, the monitoring submodule disconnects the motherboard power interface from the charging / discharging electronic module. The charge / discharge electronic module is electrically connected to the monitoring submodule and the backup power submodule, and is configured to be in a charging state or a discharging state in response to the electrical connection state between the motherboard power interface and the charge / discharge electronic module. A backup power submodule, electrically connected to the charge / discharge electronic module, is configured to supply power to the memory controller in response to the charge / discharge electronic module being in the discharge state.

17. The system according to claim 16, characterized in that, The charge / discharge electronic module includes: The power switching unit, electrically connected to the monitoring submodule and the backup power submodule, is configured to operate in either normal power supply mode or first emergency power supply mode when the motherboard power interface is connected to the charging / discharging electronic module. The system controls the supply of power to the memory controller from the motherboard voltage; when the motherboard power interface is disconnected from the charging and discharging electronic module, it enters a second emergency power supply mode and controls the backup power submodule to supply power to the memory controller. An interaction unit, electrically connected to an enable controller and the memory controller, is configured to provide an enable signal or interrupt signal from the enable controller and a charge / discharge state configuration command from the memory controller to the power switching unit, and to provide the input voltage and output voltage of the power switching unit to the memory controller.

18. The system according to claim 17, characterized in that, The charge / discharge electronic module also includes a power dynamic adjustment unit; A power dynamic adjustment unit, electrically connected to the power switching unit, is configured to dynamically adjust the input voltage and the output voltage to stabilize the input voltage and the output voltage.

19. The system according to claim 1, characterized in that, The step of determining the operating mode of the memory system based on the motherboard power supply parameters from the power supply monitoring module and the heartbeat information of the memory system includes: If the heartbeat information is greater than the first heartbeat threshold or the motherboard power supply parameter is less than the second preset voltage threshold, the operating mode is determined to be the emergency operating mode.

20. A memory system disaster recovery control method applied to the memory system according to any one of claims 1-19, characterized in that, include: Obtain the motherboard power supply parameters from the motherboard power connector; The operating mode of the memory system is determined based on the motherboard power supply parameters and the memory system's heartbeat information; When the operating mode is emergency operating mode and a control instruction is received from the central processing unit, multiple target data migration protocol information is determined based on the control instruction and multiple dynamic data stored in dynamic random access memory. Based on multiple target data migration protocol information, multiple data migration protocol interfaces are invoked to migrate multiple dynamic data from the dynamic random access memory to the target solid-state drive.

21. An electronic device, comprising: One or more processors; Memory, configured to store one or more computer programs, The characteristic feature is that the one or more processors execute the one or more computer programs to implement the method according to claim 20.

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