Flash memory data storage method, flash memory data reading method, and flash memory

Abstract

The present application provides a flash memory data storage method, a flash memory data reading method, and a flash memory. The storage method comprises: inverting original data, forming codewords from the original data, inverted data, redundant data, and check data, inverting the codewords, and writing the codewords and inverted codewords into a flash memory. The reading method comprises: reading a codeword and an inverted codeword from a flash memory, inverting the inverted codeword for recovery, performing bitwise comparison and adjustment on original codeword data and recovered codeword data, extracting a codeword comprising original data and inverted data, inverting the inverted data for recovery, performing bitwise comparison and adjustment on the original data and recovered data to obtain original data, and after supplementary redundant data is adjusted, performing error correction decoding on adjusted data to obtain target read data. By using the characteristic of asymmetric flipping probabilities of flash memory data storage states, multiple pieces of original data and inverted data are backed up, counted, and adjusted, thereby improving the probability of correctly reading data.

Description

Flash memory data storage methods, flash memory data reading methods, and flash memory Technical Field

[0001] This application relates to the field of memory, and more particularly to flash memory data storage methods, flash memory data reading methods, and flash memory itself. Background Technology

[0002] NAND flash memory is a non-volatile data storage solution that retains data even when power is off. However, due to its inherent characteristics, the data stored in flash memory can develop errors to varying degrees depending on factors such as ambient temperature, storage time, and wear and tear. Once the number of errors reaches a certain level and exceeds the error correction capability of the main control chip, the data may be lost. Adding multiple backups can improve the probability of correctly retrieving critical data. Current backup methods typically involve storing multiple identical backups in the flash memory, with the difference primarily depending on the required storage space and read time. Increasing the number of backups aims to improve the probability of reading correct data. Since these backups are identical, the probability of errors is theoretically the same, thus the improvement in the probability of correct data retrieval is limited. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] The purpose of this application is to at least partially solve one of the technical problems existing in the related technologies. The embodiments of this application provide a flash memory data storage method, a flash memory data reading method, and a flash memory, which can improve the probability of correctly reading data.

[0005] An embodiment of the first aspect of this application provides a flash memory data storage method, comprising:

[0006] Obtain the original data to be backed up;

[0007] Invert the original data to obtain inverted data;

[0008] The original data, the inverted data, the redundant data, and the check data are used to form a codeword;

[0009] Invert the codeword to obtain the inverted codeword;

[0010] The number of codewords p and the number of inverted codewords q are determined based on the storage space and reliability requirements of the flash memory.

[0011] Write p copies of the codeword and q copies of the inverted codeword into the flash memory.

[0012] According to certain embodiments of the first aspect of this application, the step of forming a codeword from the original data, the inverted data, the redundant data, and the check data includes:

[0013] Obtain the size of the original data and the size of the user data area for the codewords;

[0014] The maximum number of original data and inverted data is determined based on the size of the original data and the size of the user data area of ​​the codeword;

[0015] The quantity n of the original data and the quantity m of the inverted data are determined based on the maximum quantity.

[0016] The user data area of ​​the codeword is formed by n copies of the original data, m copies of the inverted data, and redundant data; the check data is formed by the check data to form the check data area of ​​the codeword.

[0017] The user data area and the verification data area are combined to form a codeword.

[0018] According to certain embodiments of the first aspect of this application, the locations where p copies of the codeword and q copies of the inverted codeword are written in the flash memory are the same or have the same storage characteristics.

[0019] According to certain embodiments of the first aspect of this application, writing p copies of the codeword and q copies of the inverted codeword into the flash memory includes:

[0020] Write p copies of the codeword and q copies of the inverted codeword into the same block, the same page, or an offset within the same page of the flash memory.

[0021] According to certain embodiments of the first aspect of this application, the redundant data consists of data 0.

[0022] According to a second aspect of this application, a flash memory data reading method is provided, wherein data in the flash memory is backed up according to the flash memory data storage method described in the first aspect of this application; the flash memory data reading method includes:

[0023] Get the first data storage address of the data to be read;

[0024] At least one codeword and at least one inverted codeword are read from the flash memory according to the first data storage address;

[0025] Invert the inverted codeword to obtain the restored codeword;

[0026] The codeword and the restored codeword are compared and adjusted in terms of bit positions to obtain a valid codeword;

[0027] The original data and the inverted data are extracted from the user data area of ​​the valid codewords;

[0028] The inverted data is inverted to obtain the restored data;

[0029] The original data and the restored data are compared and adjusted in terms of bits to obtain the first valid data;

[0030] The user data area of ​​the first valid codeword is replaced with the first valid data and redundant data to obtain the second valid data;

[0031] The second valid data is then corrected and decoded based on the verification data in the verification data area of ​​the second valid data to obtain the target read data.

[0032] According to certain embodiments of the second aspect of this application, the step of comparing and adjusting the codeword and the restored codeword at the bit positions to obtain a valid codeword includes:

[0033] Count the first number of data 0s and the second number of data 1s in the same bit position in the user data area of ​​the codeword and the user data area of ​​the restored codeword;

[0034] When the first quantity is greater than the second quantity, the first candidate data for the bit is determined to be data 0;

[0035] When the first quantity is less than the second quantity, the first candidate data for the bit is determined to be data 1;

[0036] The effective codeword is obtained by combining the first candidate data of each bit.

[0037] According to certain embodiments of the second aspect of this application, the step of comparing and adjusting the original data and the restored data at the bit level to obtain first valid data includes:

[0038] Align the original data and the restored data;

[0039] Count the third number of data 0s and the fourth number of data 1s in the same bit position in the original data and the restored data;

[0040] When the third quantity is greater than the fourth quantity, the second candidate data for the bit is determined to be data 0;

[0041] When the third quantity is less than the fourth quantity, the second candidate data for the bit is determined to be data 1;

[0042] The first valid data is obtained by combining the second candidate data of each bit.

[0043] A third aspect of this application provides a flash memory that applies the flash memory data storage method described in the first aspect of this application and the flash memory data reading method described in the second aspect of this application. The flash memory includes a storage controller and flash memory chips, with the storage controller connected to the flash memory chips. The storage controller includes a codeword adjustment control module and an error correction control module. The codeword adjustment module is used to perform codeword-related operations, and the error correction control module is used to perform error correction decoding operations.

[0044] According to certain embodiments of the third aspect of this application, the storage controller further includes a protocol interface control module, a system processor, and a system cache. The codeword adjustment control module and the error correction control module are disposed in the flash memory read / write control module. The protocol interface control module, the system processor, and the system cache are connected to the flash memory read / write control module via an internal bus.

[0045] The above scheme has at least the following beneficial effects: The storage method includes inverting the original data, constructing a codeword from the original data, inverted data, redundant data, and check data, inverting the codeword, and writing the codeword and the inverted codeword into flash memory; The reading method includes reading the codeword and the inverted codeword from flash memory, inverting and restoring the inverted codeword, adjusting the original data and restored data by comparing and adjusting the bits, extracting the original data and the inverted data, inverting and restoring the inverted data, adjusting the original data and restored data by comparing and adjusting the bits, and performing error correction decoding on the adjusted data to obtain the target read data; Utilizing the unequal probability of flash memory data storage state flipping, multiple copies of the original data and the inverted data are backed up and statistically adjusted to improve the probability of correctly reading the data. Attached Figure Description

[0046] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0047] Figure 1 is a flowchart illustrating the steps of a flash memory data storage method provided in an embodiment of this application;

[0048] Figure 2 is a diagram of the sub-steps of step S130;

[0049] Figure 3 is a flowchart illustrating the steps of a flash memory data reading method provided in an embodiment of this application;

[0050] Figure 4 is a diagram of the sub-steps of step S240;

[0051] Figure 5 is a diagram of the sub-steps of step S270;

[0052] Figure 6 is a structural diagram of the codeword;

[0053] Figure 7 is a structural diagram of p-part codewords and q-part inverted codewords;

[0054] Figure 8 is a schematic diagram of step S240;

[0055] Figure 9 is a schematic diagram of step S280;

[0056] Figure 10 is a structural diagram of the flash memory provided in an embodiment of this application. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0058] It should be noted that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, or the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0059] Due to the inherent characteristics of flash memory, the data stored within it may experience varying degrees of errors depending on factors such as ambient temperature, storage time, and wear and tear. Once the number of errors reaches a certain level and exceeds the error correction capability of the main controller chip, the data may be lost. Adding multiple backups helps increase the probability of correctly retrieving critical data.

[0060] Flash memory data is stored in binary 0 and 1 states. During storage, data flips may occur due to changes in the environment and time, flipping 0 to 1 or 1 to 0. Since the two states 0 and 1 correspond to two different voltage ranges in flash memory, changes in the external environment or the length of storage time affect the voltage distribution inside the flash memory. Therefore, the probability of 0 flipping to 1 is usually not exactly equal to the probability of 1 flipping to 0.

[0061] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0062] To address the above problems, embodiments of this application provide a flash memory data storage method.

[0063] Referring to Figure 1, the flash memory data storage method includes the following steps:

[0064] Step S110: Obtain the original data to be backed up;

[0065] Step S120: Invert the original data to obtain the inverted data;

[0066] Step S130: The original data, the inverted data, the redundant data, and the check data are combined to form a codeword;

[0067] Step S140: Invert the codeword to obtain the inverted codeword;

[0068] Step S150: Determine the number of codewords p and the number of inverted codewords q based on the storage space and reliability requirements of the flash memory;

[0069] Step S160: Write p copies of codewords and q copies of inverted codewords into the flash memory.

[0070] For step S110, obtain the original data to be backed up, and denote the original data as X. The original data includes user data.

[0071] In step S120, the original data X is inverted to obtain inverted data Xb. For example, inverting data 0 yields data 1, and inverting data 1 yields data 0. Inverting consecutive data 0011 yields data 1100. The inverted data can be used as a reference along with the original data, increasing data security and reliability.

[0072] Referring to Figure 2, for step S130, the original data, inverted data, redundant data, and check data are used to form a codeword, which includes the following steps:

[0073] Step S131: Obtain the size of the original data and the size of the user data area of ​​the codeword;

[0074] Step S132: Determine the maximum number of original data and inverted data based on the size of the original data and the size of the user data area of ​​the codeword;

[0075] Step S133: Determine the number of original data n and the number of inverted data m based on the maximum number;

[0076] Step S134: The user data area of ​​the codeword is formed by combining n original data, m inverted data and redundant data; the check data is formed by combining the check data into the check data area of ​​the codeword.

[0077] Step S135: Combine the user data area and the check data area to form a codeword.

[0078] The size of the raw data refers to the amount of storage space occupied by the data to be stored. The file size can be obtained using file operation functions in a programming language, or determined by reading the length of the data buffer.

[0079] A codeword consists of a user data area and a parity data area. The size of the user data area refers to the storage space used to store the original data, the inverted data, and redundant data within the codeword. This size is typically determined by the design of the storage system. For example, the user data area size of a codeword might be fixed at 4KB, or it could be flexibly configured according to actual application requirements and the characteristics of the storage device.

[0080] If the size of the original data is S_original and the size of the user data area is S_user, then the maximum number of original data and inverted data is K = S_user / S_original, rounded down to the nearest integer.

[0081] It is understandable that we assume the size of the original data is Soriginal, and the size of the user data area for the codeword is Suser. Since the user data area needs to store the original data, the inverted data, and redundant data, we can derive the following relationship: n*Soriginal + m*Sinverted + Sredundant ≤ Suser, where n is the number of original data, m is the number of inverted data, Sinverted is the size of the inverted data (usually the same as the original data size, i.e., Sinverted = Soriginal), and Sredundant is the size of the redundant data. Without considering redundant data (i.e., Sredundant = 0), the maximum number of original data and inverted data satisfies n*Soriginal + m*Soriginal ≤ Suser, i.e., (n+m)*Soriginal ≤ Suser. Therefore, the maximum number is K = n+m ≤ Suser / Soriginal.

[0082] For example, if the original data size is 128 bytes and the user data area size of the codeword is 1024 bytes, and redundant data is not considered, then the maximum number is n+m≤1024 / 128=8. This means that a maximum of 8 combinations of original data and inverted data can be stored, such as 5 original data and 3 inverted data, or 4 original data and 4 inverted data, etc., as long as the total number does not exceed 8.

[0083] When determining the amount of original data (n) and the amount of inverted data (m), factors such as storage space utilization and data reliability requirements need to be considered. Generally, increasing the amount of original data (n) can improve data redundancy and thus enhance data reliability, but it will reduce storage space utilization. Conversely, increasing the amount of inverted data (m) can improve error correction capabilities to some extent, but it will also affect storage space utilization. Therefore, it is necessary to determine the appropriate values ​​of n and m based on the specific application scenario and requirements.

[0084] Assuming the maximum number is 8, if the reliability of the data is required to be high, n can be set to 5 and m to 3, that is, store 5 copies of the original data and 3 copies of the inverted data; if the utilization of storage space is required to be high, n can be set to 6 and m to 2, that is, store 6 copies of the original data and 2 copies of the inverted data.

[0085] The user data area of ​​the codeword is formed by combining n original data, m inverted data, and redundant data in a certain order or according to certain rules. For example, the n original data can be arranged sequentially, the m inverted data can be arranged sequentially after the original data, and finally the redundant data can be added after the inverted data to form a complete user data area. The redundant data can be used to improve the error correction capability of the data. For example, it can be redundant bits for parity checking, or redundant data generated by other error correction coding algorithms. In this embodiment, the redundant data consists of data 0.

[0086] Checksum data is additional data used for verifying and correcting user data, typically generated by error correction coding algorithms. It is stored separately as a checksum area within a codeword, distinct from the user data. For example, during error correction coding, algorithms such as EEC codes can be used to encode user data, generating corresponding checksum data, which is then stored in the checksum area.

[0087] ECC error correction is a key mechanism to ensure the correctness of flash memory data. It sacrifices some data storage space in exchange for data reliability. When writing data, the ECC algorithm is used to encode and generate verification information, which is then written to the flash memory along with the user data area.

[0088] The user data area and check data area of ​​the codeword are combined together according to a certain format or structure to form a complete codeword.

[0089] Referring to Figure 6, codeword H is generated. H includes an error correction codeword user data area consisting of n original data, m inverted data, and redundant data, and an error correction codeword verification data area consisting of backup verification data C. The n original data are backup data X1, backup data X2, ..., backup data Xn, and the m inverted data are backup data Xb1, backup data Xb2, ..., backup data Xbn.

[0090] For step S140, the codeword is inverted to obtain the inverted codeword.

[0091] For step S150, the number of codewords p and the number of inverted codewords q are determined based on the storage space and reliability requirements of the flash memory.

[0092] Determine the total available storage space of the current flash memory device. For example, suppose the flash memory has a total storage space of 10GB, and a portion of that space, say 5GB, is available for storing the original and inverted codewords. Calculate the number of copies that can be stored based on the individual sizes of the codewords and the inverted codewords. For instance, if each codeword is 1qB and the inverted data is also 1qB (the inversion operation itself does not change the data storage size), then a maximum of 5 × 1024 = 5120 copies of this data can be stored in the 5GB storage area. If we set p copies of the codewords and q copies of the inverted codewords, then p + q ≤ 5120 must be satisfied.

[0093] The ratio of p to q should be weighed based on the expected data reliability. Generally, higher reliability requires more redundant data. For example, in the process of data storage and retrieval, in order to recover the original information from other data even if some data is corrupted, a certain redundancy ratio is often required.

[0094] For example, to achieve higher reliability, three copies of the codeword and one inverted copy of the codeword can be set (i.e., p=3, q=1). This provides multiple sources of redundancy for verification and repair when data recovery is needed. However, the utilization rate of storage space is relatively low in this case because a large portion of the total storage units are used for redundant data. On average, assuming each codeword requires S storage space, the total storage requirement is 3S + 1S = 4S. For even higher storage space utilization, the redundancy ratio can be reduced, such as p=2 and q=1. In this case, the storage requirement is 3S, resulting in higher space utilization, but the data reliability is relatively lower.

[0095] A balance needs to be found between storage space and reliability. For example, after comprehensive consideration, it may be set to p=3, q=1 or a similar combination, so as to meet basic reliability requirements while minimizing excessive use of storage space.

[0096] Referring to Figure 7, the p codewords are denoted as H1, H2, ... Hp; the q codewords are denoted as Hb1, Hb2, ... Hbq.

[0097] For step S160, p copies of codewords and q copies of inverted codewords are written into the flash memory.

[0098] Determine the storage locations. Flash memory has multiple storage cells, each with a specific address. It's necessary to pre-plan which address ranges the stored codewords and their inverted counterparts will be written to. For example, the first copy of a codeword might be written to addresses 0x00000000 to 0x00000FFF, the second to 0x00001000 to 0x00001FFF, and so on. The inverted codewords are then allocated sequentially to subsequent address ranges.

[0099] Clear the storage cell. Before writing, the target storage area typically needs to be erased. This is because flash memory writing relies on erasing; after erasing, all bits are 1 before 0 can be written. Writing data directly to an unerased area may result in write failure or incomplete data.

[0100] The microcontroller performs the write operation through the flash memory controller. The controller writes the codewords and their inverted counterparts to the corresponding memory locations in the flash memory according to a pre-planned address and data order. For example, the controller first issues a write command to the flash memory, specifying the first address and transmitting the first copy of the codeword data. Upon receiving the command, the flash memory writes the data to the memory location corresponding to that address. This process continues until all n codewords and m inverted codewords have been written.

[0101] It is important to note that the n copies of codewords to be backed up and the m copies of inverted codewords written to the flash memory should be in the same location area or have the same storage characteristics. This ensures that the factors and degree of data flipping affecting the two types of backup data are as similar as possible. For example, they should be stored in the same flash memory block, page, or offset within the page. These identical storage areas can be determined by analyzing the data based on the flash memory characteristics. In other words, the n copies of codewords to be backed up and the m copies of inverted codewords should be written to the same block, page, or offset within the same page in the flash memory.

[0102] After the write operation is complete, data verification is performed. This includes reading back the stored data and comparing it with the expected data to ensure the written data is correct. For example, after the write is complete, the controller reads some or all of the data from the flash memory and compares it with the codewords before transmission and the inverted codewords to check for any differences. If differences are found, rewriting or other error correction measures may be necessary to ensure data accuracy.

[0103] Understandably, flash memory write operations have specific limitations and characteristics, such as the limited erase / write lifespan of each storage cell, and frequent erase / write operations can lead to performance degradation or even damage to the flash memory. Therefore, during multiple write operations, the flash memory controller automatically and rationally allocates storage locations and erase / write cycles to avoid excessive wear on the same storage cell.

[0104] Another embodiment of this application provides a flash memory data reading method. Data in the flash memory is backed up according to the flash memory data storage method described above.

[0105] Referring to Figure 3, the flash memory data reading method includes the following steps:

[0106] Step S210: Obtain the first data storage address of the data to be read;

[0107] Step S220: Read at least one codeword and at least one inverted codeword from the flash memory according to the first data storage address;

[0108] Step S230: Invert the inverted codeword to obtain the restored codeword;

[0109] Step S240: Compare and adjust the codeword and the restored codeword in terms of bit positions to obtain the valid codeword;

[0110] Step S250: Extract the original data and the inverted data from the user data area of ​​the valid codewords;

[0111] Step S260: Invert the inverted data to obtain the restored data;

[0112] Step S270: The original data and the restored data are compared and adjusted in terms of bits to obtain the first valid data;

[0113] Step S280: Replace the user data area of ​​the first valid codeword with the first valid data and redundant data to obtain the second valid data;

[0114] Step S290: Perform error correction decoding on the second valid data according to the verification data in the verification data area of ​​the second valid data to obtain the target read data.

[0115] For step S210, the first data storage address of the data to be read is obtained. For example, the data storage address of the data to be read is obtained by querying the address mapping table maintained by the flash memory as the first data storage address. The address mapping table stores the mapping from logical addresses to physical addresses. When data needs to be read, the corresponding physical address is first looked up in the mapping table according to the logical address (such as the file offset address in the file system). For example, assuming the logical address is 0x00123456, and the mapping table records the corresponding physical address as 0x87654321, then the data is read starting from the physical address 0x87654321.

[0116] For step S220, at least one codeword and at least one inverted codeword are read from the flash memory according to the first data storage address. Specifically, using the first data storage address as the starting point, data is read from the flash memory in a preset order or rule. For example, assuming the first data storage address corresponds to the first cell storing the original data, the controller will read several subsequent cells sequentially starting from that address, which may contain multiple codewords and inverted codewords.

[0117] In step S230, the inverted codeword is inverted to obtain the restored codeword. Specifically, during the storage stage, the inverted codeword is obtained by flipping each bit of the codeword; now, the inverted codeword is inverted again, that is, each bit of it is flipped again. For example, if the inverted codeword is 10010101, after inverting it, it becomes 01101010, and at this time the restored codeword should be the same as the corresponding codeword.

[0118] Referring to Figure 4, for step S240, the codeword and the restored codeword are compared and adjusted in terms of bits to obtain the valid codeword, which includes the following steps:

[0119] Step S241: Count the first number of data 0s and the second number of data 1s in the same bit position in the user data area of ​​the codeword and the user data area of ​​the restored codeword;

[0120] Step S242: When the first quantity is greater than the second quantity, determine the first candidate data of the bit as data 0;

[0121] Step S243: When the first quantity is less than the second quantity, determine the first candidate data of the bit as data 1;

[0122] Step S244: Combine the first candidate data of each bit to obtain the valid codeword.

[0123] The user data areas of the codeword and the restored codeword are compared bit by bit to check for differences at each bit. For example, if the user data area of ​​the codeword is 0 at a certain bit, while the user data area of ​​the restored codeword is 1 at the corresponding bit, it indicates that there may be an error in that bit.

[0124] Referring to Figure 8, read the codewords and restore the codewords, denoted as rH1, rH2, ..., rHp; rHb1, rHb2, ..., rHbq, respectively. Invert the bitwise backups of the inverted data to obtain rHbb1, rHbb2, ..., rHbbq. Expand rH1, rH2, ..., rHp with rHbb1, rHbb2, ..., rHbbq by bitwise statistical analysis to obtain the first candidate data R. Further, count the number of 0s and 1s at the same bit positions in rH1, rH2, ..., rHp and rHbb1, rHbb2, ..., rHbbq. If there are more 1s than 0s, the first candidate data is determined to be R, where the bit at the same position is 1; otherwise, it is 0. Combine the first candidate data at each bit position to obtain the valid codeword.

[0125] For step S250, the original data and inverted data are extracted from the user data area of ​​the valid codeword. The user data area of ​​the valid codeword contains the original data, inverted data, and redundant data. Based on the structure and size of the user data area, and the size and quantity of the original data, the original data is extracted from the user data area. Based on the structure and size of the user data area, and the size and quantity of the inverted data, the inverted data is extracted from the user data area.

[0126] Extract the original data and restored data from the user data area, and denote them as: rX1, rX2, ..., rXn; rXb0, rXb1, ..., rXbm, respectively.

[0127] For step S260, the inverted data is inverted to obtain the restored data. The m copies rXb1, rXb2, ..., rXbm are adjusted by inverting each bit to obtain rXbb1, rXbb2, ..., rXbbm.

[0128] Referring to Figure 5, for step S270, the original data and the restored data are compared and adjusted in terms of bits to obtain the first valid data, including the following steps:

[0129] Step S271: Align the original data and the restored data;

[0130] Step S272: Count the third number of data 0s and the fourth number of data 1s that are in the same bit position in the original data and the restored data;

[0131] Step S273: When the third quantity is greater than the fourth quantity, determine the second candidate data of the bit as data 0;

[0132] Step S274: When the third quantity is less than the fourth quantity, determine the second candidate data of the bit as data 1;

[0133] Step S275: Combine the second candidate data of each bit to obtain the first valid data.

[0134] Align all the original and restored data on the first bit; then the original and restored data will correspond one-to-one on the subsequent bits.

[0135] Count the number of 0s and 1s at the same bit positions as rX1, rX2, ..., rXn and rXbb1, rXbb2, ..., rXbbm. If there are more 1s than 0s, the second candidate data is determined to be 1; otherwise, it is 0. Combine the second candidate data for each bit position to obtain the first valid data.

[0136] In step S280, the user data area of ​​the first valid codeword is replaced with first valid data and redundant data to obtain the second valid data. Specifically, the user data area includes one copy of the first valid data, and the remaining positions are filled with redundant data, which consists of data 0. The second valid data is composed of the user data area and the check data area. Referring to Figure 9, the user data area of ​​codeword R is replaced with the first valid data and redundant data to obtain codeword T.

[0137] In step S290, error correction decoding is performed on the second valid data based on the verification data in the verification data area of ​​the second valid data to obtain the target read data. Specifically, the verification data is ECC verification information.

[0138] When reading data, both valid information and ECC verification information are read from the flash memory. Through ECC decoding and error correction operations, it can be ensured that the correct data can be read within the error-correctable range.

[0139] Error correction decoding is performed on the second valid data. If decoding is correct, the target data to be read is obtained; if decoding is incorrect, the second data storage address of the data to be read is obtained. The second original data and the second inverted data corresponding to the data to be read are read from the second data storage address. The second inverted data is inverted to obtain the second restored data. The second original data and the second restored data are compared and adjusted in terms of bits to obtain the second adjusted data. Error correction decoding is performed on the second adjusted data to obtain the target data to be read. The second data storage address is different from the first data storage address. If decoding is incorrect, other backups are searched until all backups have been tried.

[0140] In addition to storing the original data, we also store the inverted data. By reading the combination of the original data and the inverted data, we can increase the probability of obtaining the correct data.

[0141] Examples are given below:

[0142] Assume the original data has only 1 bit, stored in two backups, denoted as X1 and X2; the inverted data is denoted as Xb1 and Xb2; a total of four copies of the original data and the inverted data are written to flash memory. When reading data, the original data and the inverted data read from flash memory are denoted as Y1, Y2, Yb1, and Yb2 respectively. Then, Yb1 and Yb2 are inverted to obtain Ybb1 and Ybb2. After sorting, the data read from flash memory is: Y1, Y2, Ybb1, and Ybb2. The number of 0s and 1s in Y1, Y2, Ybb1, and Ybb2 is counted. If there are more 1s than 0s, the final data is determined to be 1; otherwise, it is 0.

[0143] First, assume the original data is 1, then X1 = X2 = 1, Xb1 = Xb2 = 0.

[0144] The probability of 0 turning into 1 (P0->1) is greater than the probability of 1 turning into 0 (P1->0) (i.e., P0->1>P1->0). Reading data Y1 and Y2 and writing corresponding data X1 and X2, both are 1. Since the probability of 1 turning into 0 is low, we assume neither is turned, so (Y1,Y2) = (1,1). Reading data Yb1 and Yb2 and writing corresponding data Xb1 and Xb2, both are 0. Since the probability of 0 turning into 1 is high, we assume a 50% turning rate, so (Yb1,Yb2) can be (1,0) or (0,1). Here, we take (1,0), and after inverting, we get Ybb1 and Ybb2 as (0,1). Finally, (Y1,Y2,Ybb1,Ybb2) = (1,1,0,1), with 3 1s and 1 0, so the final data is determined to be 1.

[0145] The probability of 0 turning into 1, P0->1, is less than the probability of 1 turning into 0, P1->0 (i.e., P0->1).<p1->In the case of (0), the data read from Y1 and Y2 are written to X1 and X2 respectively, both being 1. Since the probability of 1 being flipped to 0 is high, assuming a flip rate of 50%, (Y1, Y2) can be (1, 0) or (0, 1). Here, we take (1, 0). The data read from Yb1 and Yb2 are written to Xb1 and Xb2 respectively, both being 0. Since the probability of 0 being flipped to 1 is low, we assume no flipping, then (Yb1, Yb2) = (0, 0). After inverting, we get Ybb1 and Ybb2 as (1, 1). Finally, (Y1, Y2, Ybb1, Ybb2) = (1, 0, 1, 1), with 3 1s and 1 0, so the final data is also 1.

[0146] When P0->1 = P1->0, the probability of error is equal, and the probability of determining the final data as 1 is 50%.

[0147] The above writing, reading, and judgment process is similar when the original data is 0. It is evident that adding a backup of the inverted data can increase the probability of reading the correct data.

[0148] Another embodiment of this application provides a flash memory, applying the flash memory data storage method and flash memory data reading method described above.

[0149] Referring to Figure 10, the flash memory includes a storage controller and flash memory chips, with the storage controller connected to the flash memory chips.

[0150] The storage controller is responsible for coordinating and managing data interaction between the flash memory chips and the external host. It receives data from the external host and writes it to the flash memory chips for storage; at the same time, it also reads data from the flash memory chips and then transmits it back to the external host, ensuring the correct storage and retrieval of data.

[0151] Data is stored in flash memory chips. The storage controller reads data from the external host and writes the data to the flash memory chips; the storage controller reads data from the flash memory chips and transmits the data to the external host.

[0152] The storage controller includes a codeword adjustment control module and an error correction control module; the codeword adjustment module is used to perform codeword-related operations; the error correction control module is used to perform error correction and decoding operations.

[0153] The codeword adjustment module performs the following codeword-related operations: filling the codeword with redundant data, filling the codeword with multiple identical data, and inverting the codeword.

[0154] The error correction control module is responsible for performing error correction decoding operations to detect and correct errors that may occur during data storage and retrieval. During data retrieval, if an error is detected, the error correction control module calculates the location and value of the error based on the error correction coding algorithm and corrects it to ensure the accuracy and integrity of the data.

[0155] The storage controller also includes a protocol interface control module, a system processor, and a system cache. The codeword adjustment control module and the error correction control module are located in the flash memory read / write control module. The protocol interface control module, the system processor, and the system cache are connected to the flash memory read / write control module via an internal bus.

[0156] The protocol interface control module is responsible for converting and controlling the communication protocol with the external host, ensuring that the flash memory system can communicate and be compatible with different types of external hosts. It typically supports multiple storage protocols, such as SATA, SAS, and NVMe. Based on the protocol requirements of the external host, it converts and processes the commands and data sent by the host, and then passes them to the flash memory read / write control module for corresponding operations. Simultaneously, it also encapsulates and sends the data and status information returned by the flash memory system according to the host's protocol format to achieve normal communication with the external host.

[0157] The system processor is the central processing unit of the storage controller, responsible for the management and control of the entire flash memory system. It coordinates the work between various modules and executes various system-level tasks and operations, such as initialization, configuration, and monitoring. For example, during system startup, the system processor initializes the various modules and sets the operating modes and parameters of the storage controller; during data read / write operations, it monitors the data transmission status and coordinates the work of the codeword adjustment control module, error correction control module, and protocol interface control module to ensure correct data processing and transmission.

[0158] System cache is used for temporary storage of data and information to improve the speed and efficiency of data read and write operations. During data writing, the system cache can temporarily store data received from the external host, awaiting the storage controller to write the data to the flash memory chips. During data reading, it can cache data read from the flash memory chips to quickly transfer data to the external host. Furthermore, the system cache can also be used to store system configuration information, status information, etc., so that the system processor can quickly access and process this information.

[0159] The flash memory read / write control module also includes a bus and register module, a flash memory bus timing module, a data transfer control module, and a cache.

[0160] The bus and register module manages the bus communication and register operations within the flash memory read / write control module. It provides a bus interface for data transfer and communication between submodules, ensuring fast and accurate data transmission between them. It also includes registers to store various control, status, and data information, allowing other submodules to access and use this information.

[0161] The flash bus timing module is responsible for controlling the bus timing of the flash memory chips, ensuring that data is written or read at the correct time. It generates corresponding timing signals based on the characteristics and requirements of the flash memory chips to control data transmission and access. For example, during data writing, it controls the write timing to ensure that data is correctly written within the write window of the flash memory chip; during data reading, it controls the read timing to ensure that data is read at the correct time.

[0162] The data transfer control module is responsible for controlling the data transfer process between the flash memory read / write control module and the flash memory chips. Based on commands and data from the memory controller, it divides the data into appropriately sized blocks and then writes these blocks one by one to the flash memory chips via the flash bus timing module. During data reading, it reads data blocks one by one from the flash memory chips, combines the blocks into complete data, and transmits the data to the memory controller via the bus and register module.

[0163] Caching is used for temporary data storage to improve the speed and efficiency of data read and write operations. During data writing, the cache can temporarily store data received from the storage controller, waiting for free storage space to become available in the flash memory chips before writing the data. During data reading, it can cache data read from the flash memory chips to quickly transfer data to the storage controller. Furthermore, the cache can also be used to store intermediate data and information, enabling the data transfer control module to perform data transfer and processing more efficiently.

[0164] The above is a detailed description of the preferred embodiments of this application, but this application is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application, and these equivalent modifications or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A flash memory data storage method, characterized in that, include: Obtain the original data to be backed up; Invert the original data to obtain inverted data; The original data, the inverted data, the redundant data, and the check data are used to form a codeword; Invert the codeword to obtain the inverted codeword; The number of codewords p and the number of inverted codewords q are determined based on the storage space and reliability requirements of the flash memory. Write p copies of the codeword and q copies of the inverted codeword into the flash memory.

2. The flash memory data storage method according to claim 1, characterized in that, The step of constructing a codeword from the original data, the inverted data, the redundant data, and the check data includes: Obtain the size of the original data and the size of the user data area for the codewords; The maximum number of original data and inverted data is determined based on the size of the original data and the size of the user data area of ​​the codeword; The quantity n of the original data and the quantity m of the inverted data are determined based on the maximum quantity. The user data area of ​​the codeword is formed by n copies of the original data, m copies of the inverted data, and redundant data; the check data is formed by the check data to form the check data area of ​​the codeword. The user data area and the verification data area are combined to form a codeword.

3. The flash memory data storage method according to claim 1, characterized in that, The p copies of the codeword and the q copies of the inverted codeword are written in the same location area or have the same storage characteristics in the flash memory.

4. The flash memory data storage method according to claim 1, characterized in that, The step of writing p copies of the codeword and q copies of the inverted codeword into the flash memory includes: Write p copies of the codeword and q copies of the inverted codeword into the same block, the same page, or an offset within the same page of the flash memory.

5. The flash memory data storage method according to claim 1, characterized in that, The redundant data consists of data 0.

6. A flash memory data reading method, characterized in that, The data in the flash memory is backed up according to the flash memory data storage method as described in any one of claims 1 to 5; The flash memory data reading method includes: Get the first data storage address of the data to be read; At least one codeword and at least one inverted codeword are read from the flash memory according to the first data storage address; Invert the inverted codeword to obtain the restored codeword; The codeword and the restored codeword are compared and adjusted in terms of bit positions to obtain a valid codeword; The original data and the inverted data are extracted from the user data area of ​​the valid codewords; The inverted data is inverted to obtain the restored data; The original data and the restored data are compared and adjusted in terms of bits to obtain the first valid data; The user data area of ​​the first valid codeword is replaced with the first valid data and redundant data to obtain the second valid data; The second valid data is then corrected and decoded based on the verification data in the verification data area of ​​the second valid data to obtain the target read data.

7. The flash memory data reading method according to claim 6, characterized in that, The step of comparing and adjusting the codeword and the restored codeword at the bit positions to obtain a valid codeword includes: Count the first number of data 0s and the second number of data 1s in the same bit position in the user data area of ​​the codeword and the user data area of ​​the restored codeword; When the first quantity is greater than the second quantity, the first candidate data for the bit is determined to be data 0; When the first quantity is less than the second quantity, the first candidate data for the bit is determined to be data 1; The effective codeword is obtained by combining the first candidate data of each bit.

8. The flash memory data reading method according to claim 6, characterized in that, The step of comparing and adjusting the original data and the restored data at the bit level to obtain the first valid data includes: Align the original data and the restored data; Count the third number of data 0s and the fourth number of data 1s in the same bit position in the original data and the restored data; When the third quantity is greater than the fourth quantity, the second candidate data for the bit is determined to be data 0; When the third quantity is less than the fourth quantity, the second candidate data for the bit is determined to be data 1; The first valid data is obtained by combining the second candidate data of each bit.

9. A flash memory, characterized in that, The flash memory application uses the flash memory data storage method as described in any one of claims 1 to 5 and the flash memory data reading method as described in any one of claims 6 to 8; the flash memory includes a storage controller and flash memory chips, the storage controller being connected to the flash memory chips; the storage controller includes a codeword adjustment control module and an error correction control module; the codeword adjustment module is used to perform codeword-related operations; the error correction control module is used to perform error correction decoding operations.

10. The flash memory according to claim 9, characterized in that, The storage controller further includes a protocol interface control module, a system processor, and a system cache. The codeword adjustment control module and the error correction control module are located in the flash memory read / write control module. The protocol interface control module, the system processor, and the system cache are connected to the flash memory read / write control module via an internal bus.

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