Semiconductor device and preparation method therefor, and electronic device
Patent Information
- Application Number
- PCT/CN2025/126557
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-04-17
- Filing Date
- 2025-10-09
- Publication Date
- 2026-10-22
Smart Images
Figure CN2025126557_22102026_PF_FP_ABST
Abstract
Description
Semiconductor devices and their fabrication methods, electronic devices
[0001] This application claims priority to Chinese Patent Application No. 202510488359.6, filed on April 17, 2025, entitled "Semiconductor Device and Preparation Method Thereof, Electronic Device", the contents of which shall be construed as incorporated herein by reference. Technical Field
[0002] This article relates to, but is not limited to, the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, and electronic equipment. Background Technology
[0003] With the development of integrated circuit technology, the critical dimensions of devices are shrinking daily, while the types and number of devices contained in a single chip are increasing. This means that even minor differences in the manufacturing process can affect device performance. To minimize product costs, the goal is to fabricate as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention
[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.
[0005] This disclosure provides a semiconductor device, a method for fabricating the same, and an electronic device.
[0006] On one hand, embodiments of this disclosure provide a semiconductor device including a substrate and a plurality of memory cell layers stacked on the substrate. The memory cell layers include at least one memory cell, and the memory cell includes at least one transistor. The transistor includes a channel layer and a gate electrode. The channel layer and the gate electrode both extend in a direction parallel to the plane of the substrate, and the channel layer surrounds the sidewall of the gate electrode and is insulated from the gate electrode. The semiconductor device further includes at least one bit line, which extends in a direction perpendicular to the plane of the substrate, and the channel layer contacts the bit line.
[0007] In some exemplary embodiments, the semiconductor device includes at least one memory cell string, the memory cell string including a plurality of stacked memory cells, and the channel layer of the transistors located in the same memory cell string is in contact with the same bit line.
[0008] In some exemplary embodiments, the channel layer of the transistors in at least one set of two adjacent memory cell strings is in contact with the same bit line.
[0009] In some exemplary embodiments, the channel layer of the transistors of at least one set of two adjacent memory cell strings is in contact with different bit lines, and the two adjacent memory cell strings are arranged side by side along a first direction, along which two bit lines are respectively located on both sides of the two memory cell strings, and the first direction is parallel to the plane of the substrate.
[0010] In some exemplary embodiments, multiple bit lines are arranged in pairs with multiple memory cell strings, the channel layer of the transistor located in the same memory cell string is in contact with the paired bit lines, and there is a gap between the two bit lines connected to any two adjacent memory cell strings along a first direction, and at least one set of two adjacent sets of two memory cell strings are connected to each other adjacently, the first direction being parallel to the plane of the substrate.
[0011] In some exemplary embodiments, the channel layer extends along a first direction, and the gate electrode extends along a second direction; the first direction intersects the second direction, and the plane formed thereby is parallel to the plane of the substrate.
[0012] In some exemplary embodiments, the memory cell layer further includes at least one memory cell column, the memory cell column including a plurality of the memory cells, and the gate electrodes of the transistors located in the same memory cell column are interconnected as a single structure and form a word line.
[0013] In some exemplary embodiments, the storage cell includes at least one capacitor, the capacitor including a first plate, a second plate, and a dielectric layer located between the first plate and the second plate; the second plates of the capacitors of at least one set of adjacent storage cells are an integral structure interconnected.
[0014] On the other hand, this disclosure provides a method for fabricating a semiconductor device, the semiconductor device including a substrate, a plurality of memory cell layers stacked on the substrate, and at least one bit line, the memory cell layers including at least one memory cell, the memory cell including at least one transistor; the fabrication method includes:
[0015] A stacked structure comprising multiple first dielectric layers and multiple second dielectric layers arranged alternately in sequence is formed on the substrate;
[0016] At least one bit line via is formed, and the bit line via extends in a direction perpendicular to the plane of the substrate. The stacked structure located within the bit line via is etched away, and the bit line is formed based on the bit line via.
[0017] A trench is formed, and the stacked structure located within the trench is etched away; the trench extends along a first direction in the orthographic projection of the plane on which the substrate is located, and the trench is located on both sides of the bit line via along a second direction, and the plane formed by the first direction and the second direction is parallel to the plane on which the substrate is located;
[0018] Based on the trench, the second dielectric layer is etched away to form a plurality of accommodating spaces, and a semiconductor thin film, a gate insulating thin film and a conductive thin film are sequentially formed in the accommodating spaces;
[0019] Based on the trench, the semiconductor thin film, the gate insulating film, and the conductive thin film are etched such that the semiconductor thin film forms the channel layer of the transistor, the gate insulating film forms the gate insulating layer of the transistor, and the conductive thin film forms the gate electrode of the transistor, and the channel layer is in contact with the bit line.
[0020] In some exemplary embodiments, forming the trench includes:
[0021] The trench includes a first trench and a second trench, and there is a gap between the first trench and the second trench along the first direction; along the first direction, there is a first gap between the first trench and the second trench; along the second direction, there is a second gap between two adjacent trenches, and the first gap is smaller than the second gap.
[0022] In some exemplary embodiments, the storage unit further includes a capacitor, the capacitor including a first plate, a second plate, and a dielectric layer located between the first plate and the second plate;
[0023] The preparation method further includes: forming a capacitor via before forming the bit line, or forming a capacitor via after forming the bit line and before forming the trench;
[0024] A first thin film, a dielectric thin film, and a second thin film are sequentially formed within the capacitor via. The first thin film is used to form the first electrode plate, the dielectric thin film includes the dielectric layer, and the second thin film includes the second electrode plate.
[0025] In some exemplary embodiments, forming a capacitor via before forming the bit line, and sequentially forming a first thin film, a dielectric thin film, and a second thin film within the capacitor via includes:
[0026] The capacitor via extends in a direction perpendicular to the plane of the substrate, and the stacked structure located within the capacitor via is etched away.
[0027] The first dielectric layer is laterally etched based on the capacitor via to form a first lateral trench;
[0028] Based on the capacitor via and the first transverse groove, the first thin film, the dielectric thin film and the second thin film are formed sequentially.
[0029] The preparation method further includes: forming the bit line via after forming the second thin film;
[0030] The first dielectric layer is etched away based on the bit line via to form a receiving cavity, and the receiving cavity exposes a portion of the first thin film;
[0031] The first thin film exposed by the receiving cavity is etched away so that the first thin film forms a plurality of pre-fabricated electrodes spaced apart along a direction perpendicular to the plane of the substrate, the pre-fabricated electrodes being used to form two first electrode plates spaced apart along the first direction.
[0032] In some exemplary embodiments, the trench includes a first trench and a second trench, and the first trench and the second trench have a spacing along the first direction, and the first trench exposes a portion of the first film;
[0033] After forming the transistor, the fabrication method further includes: etching away the first thin film exposed by the first trench based on the first trench, so that the pre-fabricated electrode forms two first electrode plates spaced apart along the first direction.
[0034] In some exemplary embodiments, the method further includes: after forming the transistor, etching the bit lines exposed by the trench based on the trench to form two bit lines spaced apart along the first direction.
[0035] On the other hand, embodiments of this disclosure provide an electronic device, including the semiconductor device described in any of the foregoing embodiments, or including a semiconductor device prepared by the method described in any of the foregoing embodiments.
[0036] The semiconductor device provided in this disclosure, by arranging the bit lines along a direction perpendicular to the plane of the substrate and arranging the channel layer and gate electrode of the transistor along a direction parallel to the plane of the substrate, can increase the spacing between two adjacent bit lines, reduce the coupling capacitance between two adjacent bit lines, reduce the circuit load, and reduce the occupied area of the semiconductor device. In the fabrication process, it can simplify the fabrication process and reduce the fabrication cost.
[0037] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.
[0038] Overview of the attached figures
[0039] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.
[0040] Figure 1A is a plan view of a semiconductor device according to an embodiment of the present disclosure;
[0041] Figure 1B is a plan view of a semiconductor device according to another embodiment of the present disclosure;
[0042] Figure 2A is a perspective view of a semiconductor device according to an embodiment of the present disclosure;
[0043] Figure 2B is a cross-sectional view of section AA in Figure 2A;
[0044] Figure 2C is a cross-sectional view of the section marked BB in Figure 2A;
[0045] Figure 2D is a cross-sectional view of the area marked CC in Figure 2A;
[0046] Figure 2E is a cross-sectional view of the section marked DD in Figure 2A.
[0047] Figure 2F is a cross-sectional view of the section marked EE in Figure 2A;
[0048] Figure 3A is a three-dimensional schematic diagram of the semiconductor devices after forming a stacked structure according to an embodiment of the present disclosure;
[0049] Figure 3B is a top view of the semiconductor devices after they have been stacked according to an embodiment of the present disclosure.
[0050] Figure 3C is a cross-sectional view of section AA in Figure 3A;
[0051] Figure 4A is a three-dimensional schematic diagram of a semiconductor device after the first via has been formed according to an embodiment of the present disclosure;
[0052] Figure 4B is a top view of the semiconductor device after the first via has been formed according to an embodiment of the present disclosure;
[0053] Figure 4C is a cross-sectional view of section AA in Figure 4A;
[0054] Figure 5A is a three-dimensional schematic diagram of the semiconductor device after the support body is formed according to an embodiment of the present disclosure;
[0055] Figure 5B is a top view of the semiconductor device after the support body is formed according to an embodiment of the present disclosure;
[0056] Figure 5C is a cross-sectional view of section AA in Figure 5A;
[0057] Figure 6A is a three-dimensional schematic diagram of the semiconductor device after the second via is formed according to an embodiment of the present disclosure;
[0058] Figure 6B is a top view of the semiconductor device after the second via has been formed according to an embodiment of the present disclosure;
[0059] Figure 6C is a cross-sectional view of section AA in Figure 6A;
[0060] Figure 6D is a cross-sectional view of the section marked BB in Figure 6A;
[0061] Figure 7A is a three-dimensional schematic diagram of the semiconductor device after the cavity is formed according to an embodiment of the present disclosure;
[0062] Figure 7B is a top view of the semiconductor device after the cavity is formed according to an embodiment of the present disclosure;
[0063] Figure 7C is a cross-sectional view of section AA in Figure 7A;
[0064] Figure 7D is a cross-sectional view of the section marked BB in Figure 7A;
[0065] Figure 7E is a cross-sectional view of the section marked CC in Figure 7A;
[0066] Figure 8A is a three-dimensional schematic diagram of a semiconductor device after bit lines have been formed according to an embodiment of the present disclosure;
[0067] Figure 8B is a top view of a semiconductor device after bit lines have been formed according to an embodiment of the present disclosure;
[0068] Figure 8C is a cross-sectional view of section AA in Figure 8A;
[0069] Figure 8D is a cross-sectional view of the section marked BB in Figure 8A;
[0070] Figure 9A is a three-dimensional schematic diagram of a semiconductor device after trenching according to an embodiment of the present disclosure;
[0071] Figure 9B is a top view of a semiconductor device after trenching according to an embodiment of the present disclosure;
[0072] Figure 9C is a cross-sectional view of section AA in Figure 9A;
[0073] Figure 9D is a cross-sectional view of the section marked BB in Figure 9A;
[0074] Figure 9E is a cross-sectional view of the area marked CC in Figure 9A;
[0075] Figure 9F is a cross-sectional view of the section marked DD in Figure 9A;
[0076] Figure 10A is a three-dimensional schematic diagram of a semiconductor device after a conductive thin film has been formed according to an embodiment of the present disclosure;
[0077] Figure 10B is a cross-sectional view of section AA in Figure 10A;
[0078] Figure 10C is a cross-sectional view of the section marked BB in Figure 10A;
[0079] Figure 10D is a cross-sectional view of the area marked CC in Figure 10A;
[0080] Figure 10E is a cross-sectional view of the section marked DD in Figure 10A;
[0081] Figure 10F is a cross-sectional view of the section marked FF in Figure 10A;
[0082] Figure 11A is a three-dimensional schematic diagram of a semiconductor device after the gate electrode is formed according to an embodiment of the present disclosure;
[0083] Figure 11B is a cross-sectional view of section AA in Figure 11A;
[0084] Figure 11C is a cross-sectional view of the section marked BB in Figure 11A;
[0085] Figure 11D is a cross-sectional view of the area marked CC in Figure 11A;
[0086] Figure 11E is a cross-sectional view of the section marked DD in Figure 11A;
[0087] Figure 12A is a three-dimensional schematic diagram of the semiconductor device after the first electrode plate is formed according to an embodiment of the present disclosure;
[0088] Figure 12B is a cross-sectional view of section AA in Figure 12A;
[0089] Figure 13A is a three-dimensional schematic diagram of a semiconductor device after a filler layer has been formed according to an embodiment of the present disclosure;
[0090] Figure 13B is a cross-sectional view of section AA in Figure 13A;
[0091] Figure 13C is a cross-sectional view of the section marked BB in Figure 13A;
[0092] Figure 13D is a cross-sectional view of the area marked CC in Figure 13A;
[0093] Figure 13E is a cross-sectional view of the section marked DD in Figure 13A.
[0094] Detailed Explanation
[0095] The embodiments of this disclosure will be described below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be changed to one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.
[0096] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values shown in the drawings.
[0097] The ordinal numbers such as "first," "second," and "third" in this disclosure are used to avoid confusion among the constituent elements, not to limit the quantity. "Multiple" in this disclosure includes two or more quantities.
[0098] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.
[0099] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.
[0100] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.
[0101] In this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.
[0102] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components having one or more functions.
[0103] In this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore can include a state in which the angle is greater than or equal to -5° and less than 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore can include a state in which the angle is greater than or equal to 85° and less than 95°.
[0104] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".
[0105] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.
[0106] This disclosure provides a semiconductor device including a substrate and a plurality of memory cell layers stacked on the substrate. Each memory cell layer includes at least one memory cell, and each memory cell includes at least one transistor. The transistor includes a channel layer and a gate electrode. Both the channel layer and the gate electrode extend in a direction parallel to the plane of the substrate, and the channel layer surrounds the sidewall of the gate electrode and is insulated from the gate electrode. The semiconductor device further includes at least one bit line extending in a direction perpendicular to the plane of the substrate, and the channel layer contacts the bit line.
[0107] The semiconductor device provided in this disclosure can increase the spacing between two adjacent bit lines, reduce the coupling capacitance between two adjacent bit lines, reduce the circuit load, and reduce the occupied area of the semiconductor device by setting the bit lines along a direction perpendicular to the plane of the substrate and setting the channel layer and the gate electrode along a direction parallel to the plane of the substrate. In the fabrication process, it can simplify the fabrication process and reduce the fabrication cost.
[0108] Figure 1A is a plan view of a semiconductor device according to one embodiment of the present disclosure, and Figure 1B is a plan view of a semiconductor device according to another embodiment of the present disclosure. As shown in Figures 1A and 1B, the semiconductor device may include a substrate 10 and at least one memory cell layer located on the substrate 10. For example, the semiconductor device may include one memory cell layer, two memory cell layers, three memory cell layers, or five memory cell layers, etc. Multiple memory cell layers may be stacked sequentially along a direction perpendicular to the plane of the substrate 10. The plane of the substrate 10 is parallel to the plane formed by the first direction X and the second direction Y. A memory cell layer may include at least one memory cell MC. For example, a memory cell layer may include one memory cell MC, two memory cells MC, or three memory cells MC, etc. Figures 1A and 1B illustrate a memory cell layer, and the memory cell layer may include eight memory cells MC. For example, the eight memory cells MC may be arranged in an array of 2 rows (e.g., the row direction is parallel to the first direction X) and 4 columns (e.g., the column direction is parallel to the second direction Y). In Figures 1A and 1B, a single memory cell MC is indicated by a dashed box, and two adjacent memory cells MC along the first direction X are indicated by different dashed boxes for easy identification. However, the embodiments of this disclosure do not limit the number of memory cells included in the memory cell layer. As shown in Figures 1A and 1B, a memory cell MC may include a transistor 20 and a capacitor 30, and the transistor 20 and the capacitor 30 may be arranged side by side and connected along the first direction X.
[0109] As shown in Figures 1A and 1B, a semiconductor device may include at least one bit line BL. For example, a semiconductor device may include one bit line BL, two bit lines BL, four bit lines BL, or eight bit lines BL. As shown in Figure 1A, a semiconductor device may include four bit lines BL, namely bit line BL1, bit line BL2, bit line BL3, and bit line BL4. As shown in Figure 1B, a semiconductor device may include eight bit lines BL. The bit lines BL may extend along a direction perpendicular to the plane of the substrate 10. Multiple bit lines BL may be arranged at intervals along a first direction X, and multiple bit lines BL may be arranged at intervals along a second direction Y. There is a gap along the first direction X between any two adjacent bit lines BL. In the embodiments of this disclosure, setting the bit lines along a direction perpendicular to the plane of the substrate can increase the spacing between adjacent bit lines, reduce the coupling capacitance between adjacent bit lines, reduce the circuit load, and improve the performance of the semiconductor device.
[0110] The memory cell layer may also include at least one word line WL. For example, the memory cell layer may include one word line WL, two word lines WL, or four word lines WL, etc. Figures 1A and 1B illustrate a memory cell layer, which may include four word lines WL, namely word line WL1, word line WL2, word line WL3, and word line WL4. Multiple word lines WL may extend along a second direction Y and be spaced apart along a first direction X. The extension direction of the word lines WL is parallel to the plane of the substrate 10. For example, the word lines WL may extend along the second direction Y.
[0111] In some exemplary embodiments, the memory cell layer may further include at least one memory cell column, which may include multiple memory cells MC, and the multiple memory cells MC are arranged sequentially along the second direction Y. The multiple memory cells MC located in the same memory cell column are connected to the same word line WL. Alternatively, the gate electrodes of the transistors 20 of the multiple memory cells MC located in the same memory cell column are interconnected as a single structure and form a word line WL.
[0112] In some exemplary embodiments, the storage cell layer may further include at least one storage cell row, and the storage cell row may include multiple storage cells MC, and the multiple storage cells MC are arranged sequentially along the first direction X.
[0113] In some exemplary embodiments, the semiconductor device may further include at least one memory cell string, which may include a plurality of memory cells MC, and the plurality of memory cells MC are arranged sequentially along a direction perpendicular to the plane of the substrate 10. The plurality of memory cells MC located in the same memory cell string are connected to the same bit line BL.
[0114] In some exemplary embodiments, as shown in FIG1A, along the first direction X, the channel layers of transistors of at least one set of two adjacent memory cell strings are connected to the same bit line BL, which can reduce the number of bit lines, which is beneficial to reduce the occupied area of semiconductor devices and can improve the integration density of semiconductor devices.
[0115] In some exemplary embodiments, as shown in FIG1A, along the first direction X, the channel layers of transistors of at least one set of two adjacent memory cell strings are connected to different bit lines BL.
[0116] In some exemplary embodiments, as shown in FIG1B, multiple bit lines BL are arranged in pairs with multiple memory cell strings, and the channel layer of transistors located in the same memory cell string is connected to the paired bit lines BL.
[0117] In some exemplary embodiments, the channel layers of transistors 20 of at least one set of two adjacent memory cell strings are in contact with different bit lines BL, and the two adjacent memory cell strings are arranged side by side along a first direction X. Along the first direction X, the two bit lines BL are located on both sides of the two memory cell strings, and the first direction X is parallel to the plane where the substrate 10 is located.
[0118] In some exemplary embodiments, multiple bit lines BL are arranged in pairs with multiple memory cell strings. The channel layer of the transistor 20 located in the same memory cell string is in contact with the paired bit lines BL, and there is a gap between the two bit lines BL connected to any two adjacent memory cell strings along the first direction X. At least one set of two adjacent memory cell strings are connected to two bit lines BL arranged adjacently.
[0119] As shown in Figures 1A and 1B, multiple memory cells MC may include a first memory cell MC1 and a second memory cell MC2. For example, the first memory cell MC1 and the second memory cell MC2 are arranged side-by-side along a first direction X. As shown in Figure 1A, when performing a write operation on the first memory cell MC1, word line WL2 is turned off; that is, no write operation is performed on the second memory cell MC2. As shown in Figure 1A, when performing a write operation on the memory cell column containing the first memory cell MC1, all other word lines WL not connected to the first memory cell MC1 are turned off by applying a shutdown potential, word line WL1 is turned on, and a potential is applied to the bit line BL connected to the memory cells in the memory cell column containing the first memory cell MC1 to achieve the write operation. When performing a read operation on the memory cell column containing the first memory cell MC1, word line WL1 is turned on, and other word lines WL are turned off, allowing reading from the memory cell column containing the first memory cell MC1. As shown in Figure 1B, memory cells MC can be written to and read from simultaneously.
[0120] Figure 2A is a perspective view of a semiconductor device according to an embodiment of the present disclosure. Figure 2B is a cross-sectional view at point AA in Figure 2A. Figure 2C is a cross-sectional view at point BB in Figure 2A. Figure 2D is a cross-sectional view at point CC in Figure 2A. Figure 2E is a cross-sectional view at point DD in Figure 2A. Figure 2F is a cross-sectional view at point EE in Figure 2A. As shown in Figure 2A, it is a partial cross-sectional perspective view of a semiconductor device according to an embodiment of the present disclosure. In this embodiment of the present disclosure, the direction perpendicular to the plane where the substrate 10 is located is defined as the third direction Z. As shown in Figures 2A, 2B, 2C, 2D, 2E, and 2F, the semiconductor device may include a substrate 10 and a plurality of memory cell layers stacked on the substrate 10. Only five memory cell layers are shown in the illustration. A memory cell layer may include at least one memory cell MC. A memory cell MC may include at least one transistor 20. A transistor 20 may include a channel layer 21, a gate electrode 22, and a gate insulating layer 23 located between the channel layer 21 and the gate electrode 22. The memory cell MC may also include at least one capacitor 30. For example, the memory cell MC may include a transistor 20 and a capacitor 30, with the transistor 20 and capacitor 30 arranged side by side and connected. The capacitor 30 may include a first electrode 31, a second electrode 32, and a dielectric layer 33 located between the first electrode 31 and the second electrode 32. The first electrode 31 may be in contact with the channel layer 21 of the transistor 20.
[0121] As shown in Figure 2F, the channel layer 21 may include a first sidewall 21a, a second sidewall 21b, a top wall 21c, and a bottom wall 21d. The first sidewall 21a and the second sidewall 21b may be arranged relatively apart along a first direction X, and both extend along a third direction Z. The first sidewall 21a may contact the bit line BL, and the second sidewall 21b may contact the first electrode plate 31. The top wall 21c and the bottom wall 21d may be arranged relatively apart along a third direction Z, and both extend along a second direction Y, with the top wall 21c being farther away from the substrate 10 than the bottom wall 21d. The first sidewall 21a, the second sidewall 21b, the top wall 21c, and the bottom wall 21d can be connected to form a rectangular ring. The channel layer 21 and the gate electrode 22 can both extend in a direction parallel to the plane of the substrate 10, and the channel layer 21 can surround the sidewalls of the gate electrode 22. A first sidewall 21a, a second sidewall 21b, a top wall 21c, and a bottom wall 21d can surround the sidewalls of the gate electrode 22. For example, the channel layer 21 can extend along a first direction X, and the gate electrode 22 can extend along a second direction Y. The gate electrodes 22 of a plurality of transistors 20 arranged along the second direction Y can be interconnected to form a word line WL.
[0122] In some exemplary embodiments, as shown in FIG2F, the second plates 32 of two adjacent capacitors 30 along the first direction X are interconnected as an integral structure, which can simplify the structure of semiconductor devices, reduce the occupied area of semiconductor devices, and increase the integration density of semiconductor devices.
[0123] The following example illustrates the structure of a semiconductor device through its fabrication process. The fabrication process is illustrated using only one memory cell as an example, and the perspective view is a partial cross-sectional view to identify the internal structure of the semiconductor device. The fabrication process of a semiconductor device may include the following steps:
[0124] (01) A stacked structure 40 comprising a plurality of first dielectric layers 11 and a plurality of second dielectric layers 12 arranged alternately in sequence is formed on one side of the substrate 10, as shown in Figures 3A, 3B, and 3C. For example, the stacked structure 40 may include six first dielectric layers 11 and five second dielectric layers 12; however, this disclosure does not limit the number of first dielectric layers 11 and second dielectric layers 12 included in the stacked structure 40. For example, the first dielectric layers 11 and second dielectric layers 12 may be formed on one side of the substrate 10 by deposition. Deposition methods include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.
[0125] In some exemplary embodiments, the material of substrate 10 may include a semiconductor material, such as silicon or germanium. For example, substrate 10 may be a single-crystal silicon substrate. For example, substrate 10 may be a wafer. For example, substrate 10 may also be a substrate containing other circuits, electronic devices, or conductive structures.
[0126] In some exemplary embodiments, the orthographic projection of the stacked structure 40 onto the plane containing the substrate 10 can be a rectangle.
[0127] In some exemplary embodiments, the materials of the first dielectric layer 11 and the second dielectric layer 12 may be different. For example, the material of the first dielectric layer 11 may include silicon oxide, such as silicon dioxide (SiO2). The material of the second dielectric layer 12 may include silicon nitride (SiO2). x N y For example, the silicon nitride can be silicon nitride (SiN) or silicon tetranitride (Si3N4), etc. This disclosure does not limit the materials of the first dielectric layer and the second dielectric layer, provided that selective etching requirements are met.
[0128] (02) A first sacrificial layer 13 is formed on the side of the stacked structure 40 away from the substrate 10, and the first sacrificial layer 13 and the stacked structure 40 are etched to form a plurality of first vias K1, as shown in Figures 4A, 4B, and 4C. The first sacrificial layer 13 and the stacked structure 40 located within the first vias K1 are etched away, and the first vias K1 expose a portion of the substrate 10. The plurality of first vias K1 can be arranged at intervals along the second direction Y and extend along the third direction Z. Etching can include at least one of photolithography, chemical etching, and physical etching, and chemical etching can include at least one of dry etching and wet etching. In the embodiments of this disclosure, the first vias can also be referred to as capacitor vias.
[0129] In some exemplary embodiments, the orthographic projection of the first via K1 onto the plane of the substrate 10 can be a circle, an ellipse, or a rectangle, etc.
[0130] In some exemplary embodiments, the material of the first sacrificial layer 13 may be the same as the material of the second dielectric layer 12.
[0131] (03) Based on the first via K1, a plurality of first dielectric layers 11 are laterally etched to form a plurality of first lateral trenches K11, which are connected to the first via K1, as shown in Figures 5A, 5B, and 5C. For example, wet lateral etching can be used to etch the plurality of first dielectric layers 11 to form a plurality of first lateral trenches K11. The first lateral trench K11 refers to a groove extending parallel to the plane of the substrate 10.
[0132] Subsequently, based on the first via K1 and the first transverse groove K11, a first thin film 30a, a dielectric thin film, and a second thin film are formed sequentially. The first thin film 30a is used to form multiple first plates of multiple capacitors in subsequent processes. The dielectric thin film includes multiple dielectric layers 33 of multiple capacitors, and the second thin film includes multiple second plates 32 of multiple capacitors. The multiple dielectric layers 33 of the multiple capacitors arranged along the third direction Z can be an interconnected integral structure, and the multiple second plates 32 of the multiple capacitors arranged along the third direction Z can be an interconnected integral structure. For example, the first thin film 30a, the dielectric thin film, and the second thin film can be formed using an atomic layer deposition process.
[0133] Subsequently, a support 14 is formed based on the first via K1 and the first transverse groove K11, and then the first sacrificial layer 13 is removed. The first thin film 30a, the dielectric thin film, the second thin film, and the support 14 can together fill the first via K1 and the first transverse groove K11. For example, the support 14 can be formed using an atomic layer deposition process.
[0134] In some exemplary embodiments, the materials of the first thin film 30a and the second thin film may be the same or different. The structures of the first thin film 30a and the second thin film may be the same or different. The material of the first thin film 30a may include a metallic material or other conductive material. For example, the metallic material may include at least one of tungsten (W), molybdenum (Mo), cobalt (Co), titanium (Ti), copper (Cu), aluminum (Al), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), silver (Ag), or gold (Au), or an alloy of the above metals. The first thin film 30a may be a single-layer or multi-layer structure. For example, the first thin film 30a may be a multi-layer structure formed of titanium nitride (TiN) and tungsten (W). Alternatively, the first thin film 30a may be a single-layer structure formed of titanium nitride (TiN). For example, both the first thin film 30a and the second thin film are monolayer structures formed of titanium nitride (TiN).
[0135] In some exemplary embodiments, the material of the support 14 may include polycrystalline silicon or silicon germanium, etc.
[0136] In some exemplary embodiments, the material of the dielectric thin film may include hafnium oxide, etc.
[0137] (04) A second sacrificial layer 15 is formed on the side of the stacked structure 40 away from the substrate 10, and the second sacrificial layer 15 and the stacked structure 40 are etched to form a plurality of second vias K2, as shown in Figures 6A, 6B, 6C, and 6D. The second sacrificial layer 15 and the stacked structure 40 located within the second vias K2 are etched away, and the second vias K2 expose a portion of the substrate 10. The plurality of second vias K2 can be arranged at intervals along the second direction Y and extend along the third direction Z. Etching can include at least one of photolithography, chemical etching, and physical etching, and chemical etching can include at least one of dry etching and wet etching. In the embodiments of this disclosure, the second vias can also be referred to as bit line vias.
[0138] In some exemplary embodiments, the orthographic projection of the second via K2 onto the plane of the substrate 10 can be circular, elliptical, or rectangular, etc.
[0139] In some exemplary embodiments, there is a gap between the first via K1 and the second via K2 along a first direction X. For example, the first via K1 and the second via K2 may be aligned in the first direction X.
[0140] In some exemplary embodiments, the material of the second sacrificial layer 15 may be the same as the material of the second dielectric layer 12.
[0141] (05) Based on the second via K2, the stacked structure 40 is etched laterally to remove multiple first dielectric layers 11 to form multiple receiving cavities 41, and the receiving cavities 41 expose portions of the first thin film 30a, as shown in Figures 7A, 7B, 7C, 7D and 7E. For example, wet lateral etching can be used to etch the stacked structure 40 to form multiple receiving cavities 41.
[0142] (06) The first thin film 30a exposed by the cavity 41 is etched away, so that the first thin film 30a forms a plurality of pre-fabricated electrodes 31a spaced apart along a third direction Z. The pre-fabricated electrodes 31a are used to form two first electrode plates spaced apart along a first direction X in subsequent processes, as shown in Figures 8A, 8B, 8C, and 8D. For example, wet etching can be used to etch away the first thin film 30a exposed by the cavity 41.
[0143] Subsequently, multiple isolation layers 16 are formed based on the second via K2 and the receiving cavity 41. For example, the isolation layers 16 can be formed using an atomic layer deposition process.
[0144] Subsequently, the isolation layer 16 located within the second via K2 is etched away, and the isolation layer 16 is laterally etched based on the second via K2 to form a plurality of second lateral trenches K22. For example, wet lateral etching can be used to form a plurality of second lateral trenches K22. The second lateral trenches K22 refer to grooves extending parallel to the plane of the substrate 10.
[0145] Subsequently, bit line BL is formed based on the second via K2, and the second sacrificial layer 15 is removed. Bit line BL extends along the third direction Z.
[0146] In some exemplary embodiments, the material of the isolation layer 16 may be the same as the material of the first dielectric layer 11.
[0147] In some exemplary embodiments, the material of the bit line BL may include a metallic material or other conductive material. For example, the metallic material may include at least one of tungsten (W), molybdenum (Mo), cobalt (Co), titanium (Ti), copper (Cu), aluminum (Al), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), silver (Ag), or gold (Au), or an alloy of the above metals. The bit line BL may be a single-layer or multi-layer structure. For example, the bit line BL may be a multi-layer structure formed of titanium nitride (TiN) and tungsten (W). Alternatively, the bit line BL may be a single-layer structure formed of titanium nitride (TiN).
[0148] (07) The substrate 10 obtained by the aforementioned operation is etched to form a plurality of trenches 42, as shown in Figures 9A, 9B, 9C, 9D, 9E, and 9F. The second dielectric layer 12 and the isolation layer 16 located within the trenches 42 are etched away, exposing a portion of the substrate 10. The plurality of trenches 42 may extend along a first direction X and a third direction Z, and be spaced apart along a second direction Y. For example, a photolithography process may be used to etch the substrate 10 obtained by the aforementioned operation to form the plurality of trenches 42.
[0149] The plurality of trenches 42 may include at least a first trench 42a and a second trench 42b. For example, the first trench 42a and the second trench 42b may be aligned in a first direction X. The first trench 42a may be located between two adjacent prefabricated electrodes 31a along a second direction Y, and exposes a portion of the prefabricated electrodes 31a. The second trench 42b may be located between two adjacent bit lines BL along the second direction Y, and exposes a portion of the bit lines BL. There is a gap between the first trench 42a and the second trench 42b along the first direction X.
[0150] In some exemplary embodiments, as shown in FIG9B, a first interval L1 is provided between the first trench 42a and the second trench 42b along the first direction X. The first interval L1 refers to the maximum interval between the first trench 42a and the second trench 42b along the first direction X. Along the second direction Y, a second interval L2 is provided between two adjacent trenches 42. The second interval L2 refers to the minimum interval between two adjacent trenches 42 along the second direction Y. The first interval L1 is smaller than the second interval L2, which ensures that after etching the semiconductor thin film in subsequent processes, the semiconductor thin film can form multiple channel layers spaced apart along the second direction, thus avoiding the generation of parasitic capacitance between the channel layers of two adjacent transistors.
[0151] (08) Based on multiple trenches 42, the substrate 10 formed by the aforementioned operation is etched away to remove multiple second dielectric layers 12 and form multiple accommodating spaces. Subsequently, a semiconductor thin film 17, a gate insulating film 18, and a conductive thin film 19 are formed sequentially, as shown in Figures 10A, 10B, 10C, 10D, 10E, and 10F. The semiconductor thin film 17, the gate insulating film 18, and the conductive thin film 19 together fill the accommodating spaces, but do not fill the trenches 42. For example, lateral wet etching can be used to remove the multiple second dielectric layers 12. For example, atomic layer deposition can be used to form the semiconductor thin film 17, the gate insulating film 18, and the conductive thin film 19 sequentially.
[0152] In some exemplary embodiments, the material of the semiconductor thin film 17 may include a metal oxide material, such as indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the transistor leakage current is relatively small (leakage current less than or equal to 10). -15 A) This helps improve the refresh rate of the memory. It should be noted that the metal oxide material can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc oxide), IZOx, etc., as long as the leakage current of the transistor meets the requirements. Specific adjustments can be made according to the actual situation. For example, the material of semiconductor thin film 17 can be indium gallium zinc oxide.
[0153] In some exemplary embodiments, the material of the gate insulating film 18 may include a high dielectric constant material, which can improve the insulation between the channel layer and the gate electrode, thereby improving the performance of the semiconductor device. In embodiments of this disclosure, the high dielectric constant material may be a material with a dielectric constant equal to or greater than 3.9. The high dielectric constant material may include hafnium oxide (HfO). X The gate insulating film 18 can be any one or more of aluminum oxide (Al2O3), zirconium oxide (ZrO), and strontium titanate (SrTiO3). The gate insulating film 18 can be a multilayer or composite layer structure. For example, the material of the gate insulating film 18 can be hafnium dioxide.
[0154] In some exemplary embodiments, the material of the conductive thin film 19 may include a metallic material. For example, the metallic material may include at least one of the following: tungsten (W), molybdenum (Mo), cobalt (Co), titanium (Ti), copper (Cu), aluminum (Al), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), silver (Ag), or gold (Au), or an alloy of the above metals. The conductive thin film 19 may be a single-layer or multi-layer structure. For example, the material of the conductive thin film 19 may be ITO.
[0155] (09) Based on multiple trenches 42, the aforementioned semiconductor thin film 17, gate insulating film 18, and conductive thin film 19 are etched to form multiple channel layers 21 on the semiconductor thin film 17, multiple gate insulating layers 23 on the gate insulating film 18, and multiple gate electrodes 22 on the conductive thin film 19, as shown in Figures 11A, 11B, 11C, 11D, and 11E. The channel layers 21 may surround the sidewalls of the gate electrodes 22, and the gate insulating layers 23 are located between the channel layers 21 and the gate electrodes 22. The orthographic projection of the channel layers 21 onto the plane of the substrate 10 may be an elongated strip extending along the first direction X. Along the second direction Y, the multiple gate electrodes 22 are interconnected to form a word line WL.
[0156] (10) Based on the plurality of first trenches 42a, the first thin film 30a exposed by the first trenches 42a is etched away, so that the prefabricated electrode 31a forms two first electrode plates 31 spaced apart along the first direction X, as shown in FIG12A and 12B. For example, a wet etching process can be used to etch the first thin film 30a exposed by the first trenches 42a.
[0157] In some possible embodiments, based on a plurality of second trenches 42b, the bit lines BL exposed by the second trenches 42b are etched away so that the bit lines BL form two bit lines spaced apart along the first direction X.
[0158] (11) A filling layer 24 is formed based on multiple trenches 42, as shown in Figures 13A, 13B, 13C, 13D, and 13E. For example, the filling layer 24 can be formed using atomic layer deposition. Along the second direction Y, the filling layer 24 can isolate two adjacent capacitors 30, two adjacent transistors 20, and two adjacent bit lines BL, thereby avoiding electrical crosstalk between adjacent capacitors, transistors, and bit lines and improving the storage performance of the semiconductor device.
[0159] In some exemplary embodiments, the material of the filling layer 24 may include an inorganic material. Inorganic materials include, for example, silicon oxynitride (SiO₂). x N y ) or silicon nitride (SiN) x ) or silicon oxide (SiO) x ) or silicon dioxide (SiO) x C y The filling layer 24 can be any one or more of the following: (e.g., hafnium oxide, 2fO2). Alternatively, the filling layer 24 can be made of a high-dielectric-constant material, which may include hafnium oxide (HfO2). X It can be any one or more of aluminum oxide (Al2O3), zirconium oxide (ZrO), and strontium titanate (SrTiO3).
[0160] This disclosure provides a method for fabricating a semiconductor device, the semiconductor device comprising a substrate, a plurality of memory cell layers stacked on the substrate, and at least one bit line, wherein each memory cell layer comprises at least one memory cell, and each memory cell comprises at least one transistor; the fabrication method includes:
[0161] A stacked structure comprising multiple first dielectric layers and multiple second dielectric layers arranged alternately in sequence is formed on the substrate;
[0162] At least one bit line via is formed, and the bit line via extends in a direction perpendicular to the plane of the substrate. The stacked structure located within the bit line via is etched away, and the bit line is formed based on the bit line via.
[0163] A trench is formed, and the stacked structure located within the trench is etched away; the trench extends along a first direction in the orthographic projection of the plane on which the substrate is located, and the trench is located on both sides of the bit line via along a second direction, and the plane formed by the first direction and the second direction is parallel to the plane on which the substrate is located;
[0164] Based on the trench, the second dielectric layer is etched away to form a plurality of accommodating spaces, and a semiconductor thin film, a gate insulating thin film and a conductive thin film are sequentially formed in the accommodating spaces;
[0165] Based on the trench, the semiconductor thin film, the gate insulating film, and the conductive thin film are etched such that the semiconductor thin film forms the channel layer of the transistor, the gate insulating film forms the gate insulating layer of the transistor, and the conductive thin film forms the gate electrode of the transistor, and the channel layer is in contact with the bit line.
[0166] In some exemplary embodiments, forming the trench includes:
[0167] The trench includes a first trench and a second trench, and there is a gap between the first trench and the second trench along the first direction; along the first direction, there is a first gap between the first trench and the second trench; along the second direction, there is a second gap between two adjacent trenches, and the first gap is smaller than the second gap.
[0168] In some exemplary embodiments, the storage unit further includes a capacitor, the capacitor including a first plate, a second plate, and a dielectric layer located between the first plate and the second plate;
[0169] The preparation method further includes: forming a capacitor via before forming the bit line, or forming a capacitor via after forming the bit line and before forming the trench;
[0170] A first thin film, a dielectric thin film, and a second thin film are sequentially formed within the capacitor via. The first thin film is used to form the first electrode plate, the dielectric thin film includes the dielectric layer, and the second thin film includes the second electrode plate.
[0171] In some exemplary embodiments, forming a capacitor via before forming the bit line, and sequentially forming a first thin film, a dielectric thin film, and a second thin film within the capacitor via includes:
[0172] The capacitor via extends in a direction perpendicular to the plane of the substrate, and the stacked structure located within the capacitor via is etched away.
[0173] The first dielectric layer is laterally etched based on the capacitor via to form a first lateral trench;
[0174] Based on the capacitor via and the first transverse groove, the first thin film, the dielectric thin film and the second thin film are formed sequentially.
[0175] The preparation method further includes: forming the bit line via after forming the second thin film;
[0176] The first dielectric layer is etched away based on the bit line via to form a receiving cavity, and the receiving cavity exposes a portion of the first thin film;
[0177] The first thin film exposed by the receiving cavity is etched away so that the first thin film forms a plurality of pre-fabricated electrodes spaced apart along a direction perpendicular to the plane of the substrate, the pre-fabricated electrodes being used to form two first electrode plates spaced apart along the first direction.
[0178] In some exemplary embodiments, the trench includes a first trench and a second trench, and the first trench and the second trench have a spacing along the first direction, and the first trench exposes a portion of the first film;
[0179] After forming the transistor, the fabrication method further includes: etching away the first thin film exposed by the first trench based on the first trench, so that the pre-fabricated electrode forms two first electrode plates spaced apart along the first direction.
[0180] In some exemplary embodiments, the method further includes: after forming the transistor, etching the bit lines exposed by the trench based on the trench to form two bit lines spaced apart along the first direction.
[0181] This disclosure also provides an electronic device, which includes the semiconductor device provided in any of the above embodiments, or includes a semiconductor device fabricated using the fabrication method provided in any of the above embodiments. This electronic device can be any electronic product with storage function, such as a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank.
[0182] While the embodiments disclosed in this invention have been described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. It should be noted that the above embodiments or implementation methods are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the content specifically shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.
Claims
1. A semiconductor device comprising a substrate and a plurality of memory cell layers stacked on the substrate, the memory cell layers comprising at least one memory cell, the memory cell comprising at least one transistor, the transistor comprising a channel layer and a gate electrode, the channel layer and the gate electrode both extending in a direction parallel to a plane of the substrate, and the channel layer surrounding a sidewall of the gate electrode and being insulated from the gate electrode; the semiconductor device further comprising at least one bit line extending in a direction perpendicular to the plane of the substrate, and the channel layer contacting the bit line.
2. The semiconductor device of claim 1, comprising at least one memory cell string, the memory cell string comprising a plurality of stacked memory cells, and the channel layer of the transistors located in the same memory cell string being in contact with the same bit line.
3. The semiconductor device as claimed in claim 2, wherein, The channel layer of the transistors in at least one set of two adjacent memory cell strings is in contact with the same bit line.
4. The semiconductor device as claimed in claim 3, wherein, The channel layer of the transistors in at least one set of two adjacent memory cell strings is in contact with different bit lines, and the two adjacent memory cell strings are arranged side by side along a first direction, along which two bit lines are respectively located on both sides of the two memory cell strings, and the first direction is parallel to the plane of the substrate.
5. The semiconductor device as claimed in claim 2, wherein, Multiple bit lines are arranged in pairs with multiple memory cell strings. The channel layer of the transistor located in the same memory cell string is in contact with the paired bit lines, and there is a gap between the two bit lines connected to any two adjacent memory cell strings along a first direction. At least one set of two adjacent memory cell strings are connected to two bit lines that are arranged adjacent to each other. The first direction is parallel to the plane where the substrate is located.
6. The semiconductor device according to any one of claims 1 to 5, wherein, The channel layer extends along a first direction, and the gate electrode extends along a second direction; the first direction and the second direction intersect and form a plane parallel to the plane of the substrate.
7. The semiconductor device according to any one of claims 1 to 5, wherein, The memory cell layer further includes at least one memory cell column, which includes a plurality of memory cells. The gate electrodes of the transistors located in the same memory cell column are interconnected as a single structure and form a word line.
8. The semiconductor device according to any one of claims 1 to 5, wherein, The storage unit includes at least one capacitor, the capacitor including a first plate, a second plate, and a dielectric layer located between the first plate and the second plate; The second plates of the capacitors of at least one pair of adjacent storage cells are interconnected as a single unit.
9. A method for fabricating a semiconductor device, the semiconductor device comprising a substrate, a plurality of memory cell layers stacked on the substrate, and at least one bit line, wherein each memory cell layer comprises at least one memory cell, and each memory cell comprises at least one transistor; the fabrication method comprising: A stacked structure comprising multiple first dielectric layers and multiple second dielectric layers arranged alternately in sequence is formed on the substrate; At least one bit line via is formed, and the bit line via extends in a direction perpendicular to the plane of the substrate. The stacked structure located within the bit line via is etched away, and the bit line is formed based on the bit line via. Trenches are formed, and the stacked structure located within the trenches is etched away; The trench extends along a first direction in the orthographic projection of the plane on which the substrate is located, and the trench is located on both sides of the bit line via along a second direction. The plane formed by the first direction and the second direction is parallel to the plane on which the substrate is located. Based on the trench, the second dielectric layer is etched away to form a plurality of accommodating spaces, and a semiconductor thin film, a gate insulating thin film and a conductive thin film are sequentially formed in the accommodating spaces; Based on the trench, the semiconductor thin film, the gate insulating film, and the conductive thin film are etched such that the semiconductor thin film forms the channel layer of the transistor, the gate insulating film forms the gate insulating layer of the transistor, and the conductive thin film forms the gate electrode of the transistor, and the channel layer is in contact with the bit line.
10. The method for fabricating a semiconductor device as described in claim 9, wherein, The formation of the trench includes: the trench includes a first trench and a second trench, and there is a gap between the first trench and the second trench along the first direction; along the first direction, there is a first gap between the first trench and the second trench; along the second direction, there is a second gap between two adjacent trenches, and the first gap is smaller than the second gap.
11. The method for fabricating a semiconductor device as described in claim 9 or 10, wherein, The storage unit further includes a capacitor, which includes a first plate, a second plate, and a dielectric layer located between the first plate and the second plate. The preparation method further includes: forming a capacitor via before forming the bit line, or forming a capacitor via after forming the bit line and before forming the trench; A first thin film, a dielectric thin film, and a second thin film are sequentially formed within the capacitor via. The first thin film is used to form the first electrode plate, the dielectric thin film includes the dielectric layer, and the second thin film includes the second electrode plate.
12. The method for fabricating a semiconductor device as described in claim 11, wherein, The step of forming a capacitor via before forming the bit line, and sequentially forming a first thin film, a dielectric thin film, and a second thin film within the capacitor via, includes: The capacitor via extends in a direction perpendicular to the plane of the substrate, and the stacked structure located within the capacitor via is etched away. The first dielectric layer is laterally etched based on the capacitor via to form a first lateral trench; Based on the capacitor via and the first transverse groove, the first thin film, the dielectric thin film and the second thin film are formed sequentially. The preparation method further includes: forming the bit line via after forming the second thin film; The first dielectric layer is etched away based on the bit line via to form a receiving cavity, and the receiving cavity exposes a portion of the first thin film; The first thin film exposed by the receiving cavity is etched away so that the first thin film forms a plurality of pre-fabricated electrodes spaced apart along a direction perpendicular to the plane of the substrate, the pre-fabricated electrodes being used to form two first electrode plates spaced apart along the first direction.
13. The method for fabricating a semiconductor device as described in claim 12, wherein, The trench includes a first trench and a second trench, and the first trench and the second trench are spaced apart along the first direction, and the first trench exposes a portion of the first film. After forming the transistor, the fabrication method further includes: etching away the first thin film exposed by the first trench based on the first trench, so that the pre-fabricated electrode forms two first electrode plates spaced apart along the first direction.
14. The method for fabricating a semiconductor device as described in claim 9 or 10, further comprising: After the transistor is formed, the bit lines exposed by the trench are etched to form two bit lines spaced apart along the first direction.
15. An electronic device comprising a semiconductor device as described in any one of claims 1 to 8, or comprising a semiconductor device manufactured using a method for manufacturing a semiconductor device as described in any one of claims 9 to 14.