Polarization-effect-based p-channel gallium nitride-based insulated gate bipolar transistor, and preparation method

Abstract

A polarization-effect-based P-channel gallium nitride-based insulated gate bipolar transistor, and a preparation method. A hole current of a P-type MOSFET is introduced into a base region of an NPN-type BJT, and is amplified by means a two-dimensional electron gas, which has ultra-high mobility, thereby realizing a current density that is significantly greater than that of a conventional P-type MOSFET. The preparation method for a device comprises: sequentially growing a nucleation layer, a buffer layer, a channel layer, a barrier layer and a spacer layer on a substrate, forming a P-type gallium nitride base region by means of ion implantation, then growing a lightly doped P-type gallium nitride region and a heavily doped P-type gallium nitride region, and finally etching a gate trench, growing a gate oxide layer and depositing a gate metal electrode.

Description

P-channel gallium nitride-based insulated-gate bipolar transistor based on polarization effect and its fabrication method Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a P-channel gallium nitride-based insulated-gate bipolar transistor based on polarization effect, and also to a method for fabricating a P-channel gallium nitride-based insulated-gate bipolar transistor based on polarization effect. Background Technology

[0002] With the continuous development of microelectronics technology, the performance of traditional silicon-based devices and integrated circuits has approached the theoretical limits achievable by the materials themselves. In contrast, gallium nitride (GaN) materials, due to their advantages such as large bandgap, thermal conductivity, and high dielectric constant, are widely considered strong contenders for next-generation mass-produced electronic devices. Furthermore, N-channel GaN-based transistors (N-type transistors) can form two-dimensional electron gases with extremely high mobility (exceeding 1500 cm⁻¹). 2 V -1 s -1 Gallium nitride (GaN) can achieve high current density and high-frequency switching. However, its hole mobility (below 15 cm⁻¹) is limited. 2 V -1 s -1 The current density of a P-channel gallium nitride-based transistor (P-type transistor) is significantly lower than that of an N-type transistor because the electron mobility is much lower, and the formation conditions for a two-dimensional hole gas are more stringent than those for a two-dimensional electron gas. Currently, the most widely used complementary logic circuit architecture (Figure 1(a)) requires that the output currents of the P-type and N-type transistors be relatively close to ensure normal operation. If a traditional P-type transistor structure is used to implement a complementary logic circuit, the area of ​​the P-type transistor needs to be more than 10 times that of the N-type transistor, which is unacceptable for practical circuit design.

[0003] Currently, there are two mainstream solutions to address the lack of P-type transistors. The first solution is to use normally-on N-type transistors to replace the pull-up function of traditional P-type transistors (Figure 1(b)). The disadvantage of this solution is that the normally-on N-type transistor is always in the on state, with current continuously flowing out of the power supply, resulting in a significant increase in the overall power consumption of the system. In addition, normally-on N-type transistors are rarely used in traditional silicon-based integrated circuits, and their use requires new circuit design methods and architectures, increasing the design complexity. The second solution is to use silicon-based complementary logic circuits to control gallium nitride power devices (Figure 1(c)). The disadvantage of this solution is that the electrical connections between gallium nitride devices and silicon-based circuits increase parasitic capacitance and inductance, leading to a decrease in the overall system switching speed. Since the most important application of gallium nitride devices is in high-frequency switching, they are very sensitive to parasitic components and switching speed. In addition, researchers have proposed structures such as P-type gallium nitride FinFETs and P-type gallium nitride superlattice transistors. While these structures improve current density to some extent, they still differ significantly from N-type transistors. Furthermore, they require extremely high-precision manufacturing equipment and complex fabrication processes, making them incompatible with commercially available N-type transistors and unsuitable for large-scale gallium nitride integrated circuits. Given gallium nitride's extremely low hole mobility, traditional P-type transistors, which rely solely on hole conduction, theoretically cannot achieve current densities close to those of N-type transistors, which are based on electron conduction, thus limiting the development of gallium nitride-based integrated circuits. Summary of the Invention

[0004] To address the aforementioned problems, this invention proposes a P-channel gallium nitride-based IGBT device based on polarization effect and its fabrication method.

[0005] This invention introduces the hole current of a traditional P-type gallium nitride (GaN)-based transistor into the base region of an NPN-type GaN-based BJT. By amplifying the hole current through a two-dimensional electron gas with ultra-high mobility, it achieves a current density comparable to that of an N-type transistor while maintaining the advantages of the original P-type transistor, such as negative threshold voltage and low leakage current. The fabrication process of the device proposed in this invention is fully compatible with commercially available N-type transistors, allowing for the simultaneous fabrication of N-type transistors and P-type IGBTs on the same chip without requiring high-precision manufacturing equipment or complex fabrication processes. The specific technical solution is as follows:

[0006] The present invention discloses a P-type channel gallium nitride-based insulated gate bipolar transistor based on polarization effect, comprising an NPN type BJT1. The NPN type BJT includes a channel layer, a barrier layer, a spacer layer, a P-type gallium nitride base region, and an emitter metal, which are stacked sequentially. The P-type gallium nitride base region extends into the channel layer. The spacer layer, the barrier layer, and the two-dimensional electron gas formed at the interface between the channel layer and the barrier layer are respectively divided by the P-type gallium nitride base region into a collector spacer region and an emitter spacer region, a collector barrier region and an emitter barrier region, and a collector two-dimensional electron gas and an emitter two-dimensional electron gas. The emitter metal extends into the channel layer and is connected to the emitter two-dimensional electron gas. The NPN type BJT is characterized by having a P-type MOSFET2, the source metal of the P-type MOSFET is connected to the emitter metal, and the lightly doped P-type gallium nitride region of the drain region of the P-type MOSFET is connected to the P-type gallium nitride base region.

[0007] Furthermore, the P-type MOSFET includes a lightly doped P-type gallium nitride region disposed on the P-type gallium nitride base region and emitter spacer region of the NPN type BJT, a heavily doped P-type gallium nitride region disposed on the lightly doped P-type gallium nitride region, a gate metal disposed in the heavily doped P-type gallium nitride region and extending into the lightly doped P-type gallium nitride region, a gate oxide layer disposed between the gate metal and the lightly and heavily doped P-type gallium nitride regions, and the source metal being connected to the heavily doped P-type gallium nitride region.

[0008] Furthermore, the heavily doped p-type gallium nitride region is an epitaxially grown heavily doped p-type gallium nitride with a thickness of 20–50 nm, which can be heavily doped using magnesium, and the hole concentration therein is 5e17–5e18 cm⁻¹. -3 .

[0009] Furthermore, the lightly doped p-type gallium nitride region is an epitaxially grown lightly doped p-type gallium nitride with a thickness of 20–50 nm, which can be lightly doped with magnesium, and the hole concentration therein is 1e17–1e18 cm⁻¹. -3 .

[0010] The method for fabricating a P-type channel gallium nitride-based insulated-gate bipolar transistor based on polarization effect, as described in this invention, involves epitaxially growing a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a spacer layer sequentially on a substrate; forming a P-type gallium nitride base region through ion implantation; epitaxially growing P-type gallium nitride to sequentially form a lightly doped P-type gallium nitride region and a heavily doped P-type gallium nitride region; using the barrier layer and spacer layer located on one side of the P-type gallium nitride base region as the collector barrier region and the collector spacer region, respectively; dry etching the lightly and heavily doped P-type gallium nitride regions above the collector spacer region; and etching one side of the spacer layer, barrier layer, and channel layer. On the other side and above, the lightly and heavily doped P-type gallium nitride regions form electrode vias for the emitter and collector, leading out the collector metal and emitter metal. The source electrode region on the heavily doped P-type gallium nitride region is etched and metal is deposited to form the source metal and electrically connect it to the emitter metal. The heavily doped P-type gallium nitride region is completely etched in the gate region, and the lightly doped P-type gallium nitride region is partially etched to form a gate trench, removing excess photoresist and surface contaminants. A gate oxide layer is thermally grown on the surface of the gate trench and the heavily doped P-type gallium nitride region, and then metal is deposited in the gate trench to form the gate metal.

[0011] Furthermore, during the formation of the p-type gallium nitride base region, magnesium ions are implanted twice within the base region. The dose of the first implantation is 5e12–5e13 cm⁻¹. -2 The energy is 20–40 keV; the dose of the second injection is 1e13–1e14 cm⁻¹. -2 The energy is 60-100 keV; after ion implantation, high-temperature annealing is carried out, with an annealing temperature above 1000℃; the depth of the p-type gallium nitride base region after magnesium ion activation is greater than the thickness of the barrier layer, but does not exceed the sum of the thicknesses of the barrier layer and the channel layer.

[0012] Compared with the prior art, the present invention has the following advantages:

[0013] This invention amplifies hole current by using electron current, based on P-type gallium nitride-based MOSFETs and NPN-type gallium nitride-based BJT devices. The collector, emitter, source, and gate of the device are all located on the device surface, allowing for integration with other devices such as N-type transistors on the same chip, facilitating the fabrication of all-gallium nitride-based integrated circuits.

[0014] Since the emitter and collector of the NPN type BJT in this device are formed by two-dimensional electron gas, the mobility of two-dimensional electron gas is much higher than that of hole mobility, thus it has a very high current gain and can significantly amplify the hole current.

[0015] Compared to traditional P-type gallium nitride-based MOSFETs, the present invention offers significantly improved current density, comparable to that of N-type transistors. Compared to P-type gallium nitride-based FinFET devices and P-type gallium nitride-based superlattice transistors, the present invention does not require high-precision photolithography and etching equipment, is fully compatible with commercial gallium nitride process platforms, and can further enhance current density. Attached Figure Description

[0016] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0017] Figure 1 shows three application methods of gallium nitride devices in circuits: (a) a complementary logic circuit using N-type transistors and P-type transistors, (b) a circuit using ordinary N-type transistors and normally open N-type transistors, and (c) a circuit using silicon-based complementary logic circuits to control gallium nitride-based transistors.

[0018] Figure 2 is a schematic diagram of the structure of the P-type channel gallium nitride-based IGBT device based on polarization effect proposed in this application. In the figure, 1 is an NPN type BJT (1) and 2 is a P-type MOSFET.

[0019] Figure 3 is a schematic diagram of the fabrication steps of the P-channel gallium nitride-based IGBT device of this application.

[0020] Figure 4 shows the P-channel gallium nitride-based IGBT device of this invention in various V... GE The I below C -V CE Output characteristic curve. Detailed Implementation

[0021] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0023] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, different regions of the same material layer are distinguished by the terms "emitter" and "collector"; and semiconductor regions are distinguished by the fact that the majority carriers are holes or electrons, and are referred to as P-type or N-type regions.

[0024] Example 1

[0025] Example 1 relates to a device: a P-channel gallium nitride-based insulated gate bipolar transistor based on polarization effect, including an NPN type BJT1. The NPN type BJT includes a channel layer 104, a barrier layer, a spacer layer, a P-type gallium nitride base region 106, and an emitter metal 1082 stacked sequentially. The P-type gallium nitride base region 106 extends into the channel layer 104. The spacer layer, the barrier layer, and the two-dimensional electron gas formed at the interface between the channel layer 104 and the barrier layer are respectively divided by the P-type gallium nitride base region 106 into a collector spacer region 1091 and an emitter spacer region. 1092, collector barrier region 1071 and emitter barrier region 1072, collector two-dimensional electron gas 1051 and emitter two-dimensional electron gas 1052, emitter metal 1082 extending into the channel layer 104 and connected to the emitter two-dimensional electron gas 1052, characterized in that a P-type MOSFET 2 is provided on the NPN type BJT, the source metal 205 of the P-type MOSFET is connected to the emitter metal 1082, and the lightly doped P-type gallium nitride region 201 of the drain region of the P-type MOSFET is connected to the P-type gallium nitride base region 106. The potential of the emitter metal 1082 and the source metal 205 is denoted as V. E The potential of the gate metal 204 is denoted as V. G The potential difference between the gate metal 204 and the emitter metal 1082 is denoted as V. GE The potential of the collector metal 1081 is denoted as V. C The potential difference between the collector metal 1081 and the emitter metal 1082 is denoted as V. CE ;

[0026] In the NPN-type gallium nitride-based BJT1, the on-state voltage of the PN junction formed by the collector two-dimensional electron gas 1051 and the P-type gallium nitride base region 106 is denoted as V. on The value is positive; the threshold voltage of the P-type gallium nitride-based MOSFET2 is denoted as V. Tp , which is a negative value;

[0027] When V GE ≥V Tp When the lightly doped P-type gallium nitride region 201 and the gate oxide 203 interface are depleted by the MOS system, the channel of the P-type MOSFET is turned off, and it cannot provide hole current to the base region of the NPN type BJT, so the device is in the off state.

[0028] Specifically, because the work function of the gate metal 204 is very low, the lightly doped P-type gallium nitride region 201 at the bottom of the gate trench will undergo an inversion effect. Although the region is P-type doped, the actual hole concentration is lower than the electron concentration. The channel at the bottom of the trench cannot conduct hole current, and no hole current is injected into the P-type gallium nitride base region 106. The NPN type BJT is also in the off state.

[0029] When V GE <V Tp and -V on ≤V CE When -V is ≤0, the inversion effect at the interface between the lightly doped p-type gallium nitride region 201 and the gate oxide 203 is eliminated, resulting in a high concentration of holes. However, due to -V on ≤V CE ≤0, the PN junction formed by the collector two-dimensional electron gas 1051 and the P-type gallium nitride base region 106 is not conducting, and holes cannot be injected into the collector two-dimensional electron gas 1051, so the output current of the device is still very weak.

[0030] When V GE <V Tp And V CE <-V on When the P-type MOSFET channel is turned on, the PN junction formed by the collector two-dimensional electron gas 1051 and the P-type gallium nitride base region 106 is turned on. Holes are injected into the collector two-dimensional electron gas 1051 to form a base region current. Electrons start from the collector two-dimensional electron gas 1051, pass through the P-type gallium nitride base region 106 and enter the emitter two-dimensional electron gas 1052. At this time, the NPN type BJT is in the amplification state, which can effectively amplify the base region hole current into an electron current.

[0031] Specifically, negative V GE This will eliminate the inversion effect at the interface between the lightly doped p-type gallium nitride region 201 and the gate oxide 203, restore the hole concentration to a higher level, and allow the channel at the bottom of the trench to conduct hole current; and, V CE <-V on At this time, the PN junction formed by the P-type gallium nitride base region 106 and the collector two-dimensional electron gas 1051 is forward biased, and the NPN type BJT is in the amplification state. The hole current injected from the lightly doped P-type gallium nitride region 201 into the P-type gallium nitride base region 106 is amplified into a highly concentrated electron current. The electron current starts from the collector two-dimensional electron gas 1051, passes through the P-type gallium nitride base region 106 and enters the emitter two-dimensional electron gas 1052.

[0032] The following technical measures can be further adopted in this embodiment:

[0033] When forming the p-type gallium nitride base region 106, magnesium ions are implanted twice within the base region. The dose of the first implantation is 5e12~5e13cm. -2 The energy is 20–40 keV; the dose of the second injection is 1e13–1e14 cm⁻¹. -2 The energy is 60–100 keV; after ion implantation, high-temperature annealing is required in a high-pressure nitrogen atmosphere, with an annealing temperature above 1000℃, and the hole concentration of the 106 p-type gallium nitride base region is 1e16–1e17 cm⁻¹. -3 The thickness of the lightly doped p-type gallium nitride region 201 is 20–50 nm, and the hole concentration is 1e18–5e18 cm⁻¹. -3 The thickness of the heavily doped p-type gallium nitride region 202 is 20–50 nm, and the hole concentration therein is 5e18–5e19 cm⁻¹. -3 The depth of the gate trench should be greater than the thickness of the heavily doped P-type gallium nitride region 202, and the remaining lightly doped P-type gallium nitride region 201 below the trench should be 5-10 nm; the gate oxide layer 203 should be Al2O3 with a thickness of 10-30 nm.

[0034] Example 2

[0035] Example 2 relates to a device fabrication method, namely: a method for fabricating a P-type channel gallium nitride-based IGBT device based on polarization effect, the steps of which include:

[0036] A nucleation layer 102, a buffer layer 103, a channel layer 104, a barrier layer, and a spacer layer are epitaxially grown on substrate 101 in sequence. A p-type gallium nitride base region 106 is formed by ion implantation. P-type gallium nitride is epitaxially grown to form a lightly doped p-type gallium nitride region 201 and a heavily doped p-type gallium nitride region 202 in sequence. The barrier layer and spacer layer located on one side of the p-type gallium nitride base region 106 are used as the collector barrier region 1071 and the collector spacer region 1091, respectively. The lightly and heavily doped p-type gallium nitride regions above the collector spacer region 1091 are dry etched. The lightly and heavily doped p-type gallium nitride regions on one side, the other side, and above the spacer layer, barrier layer, and channel layer 104 are etched. A heavy-doped p-type gallium nitride region is formed, with electrode vias for the emitter and collector, leading out collector metal 1081 and emitter metal 1082. The source electrode region on the heavily doped p-type gallium nitride region 202 is etched and metal is deposited to form source metal 205, which is electrically connected to emitter metal 1082. The heavily doped p-type gallium nitride region 202 is completely etched in the gate region, and the lightly doped p-type gallium nitride region 201 is partially etched to form a gate trench, removing excess photoresist and surface contaminants. A gate oxide layer 203 is thermally grown on the surface of the gate trench and the heavily doped p-type gallium nitride region 202, and then metal is deposited in the gate trench to form gate metal 204.

[0037] The following technical measures can be further adopted in this embodiment:

[0038] The dry etching of the P-type gallium nitride uses BF3 plasma, and after etching, the groove area is treated with NH3:H2O mixed solution to remove excess photoresist and surface contamination.

[0039] During the formation of the p-type gallium nitride base region (106), magnesium ions were implanted twice within the base region. The dose of the first implantation was 5e12 to 5e13 cm⁻¹. -2 The energy is 20–40 keV; the dose of the second injection is 1e13–1e14 cm⁻¹. -2 The energy is 60-100 keV; after ion implantation, it is required to anneal at high temperature in a high-pressure nitrogen atmosphere, with an annealing temperature above 1000℃; the depth of the p-type gallium nitride base region 106 after magnesium ion activation is greater than the thickness of the barrier layer, but does not exceed the sum of the thicknesses of the barrier layer and the channel layer 104.

[0040] The invention will now be further described with reference to the accompanying drawings:

[0041] This application addresses the problem of insufficient current capability in traditional P-type gallium nitride-based MOSFETs by proposing a P-type channel gallium nitride-based IGBT based on the polarization effect. Figure 2 is a schematic diagram of the structure of the proposed P-type channel gallium nitride-based IGBT based on the polarization effect. The P-type gallium nitride base region 106 and the lightly doped P-type gallium nitride region 201 on the drain side of the P-type MOSFET are connected, and the emitter metal 1082 and the source metal 205 are connected to form a P-type IGBT structure that amplifies hole current using the polarization effect.

[0042] When the P-channel gallium nitride-based IGBT device based on polarization effect proposed in this invention is in the off state, the source metal 205, emitter metal 1082 and gate metal 204 are all connected to zero potential, so that the holes in the lightly doped P-type gallium nitride region 201 at the bottom of the gate groove are exhausted by the MOS structure, the channel of the P-type MOSFET is turned off, and no holes are injected into the P-type gallium nitride base region 106.

[0043] When the p-channel gallium nitride-based IGBT device based on polarization effect proposed in this invention is in the on state, the source metal 205 and emitter metal 1082 are both connected to zero potential, and the gate metal 204 is connected to a potential lower than V. Tp The negative voltage increases the hole concentration in the P-type channel region 201 at the bottom of channel 205, turning on the P-type MOSFET; simultaneously, the collector metal 1081 is connected below -V. onThe negative voltage causes the collector junction, composed of the P-type gallium nitride base region 106 and the collector two-dimensional electron gas 1051, to be forward biased, and the emitter junction, composed of the P-type gallium nitride base region 106 and the emitter two-dimensional electron gas 1052, to be reverse biased. The source of the P-type MOSFET injects hole current into the base region. The NPN type BJT is in the reverse amplification state, which can amplify the hole current injected into the base region into electron current, and these electrons are collected by the emitter metal 1082.

[0044] Referring to Figures 3 and 5, these are schematic diagrams illustrating the fabrication steps of the P-type channel gallium nitride-based IGBT device based on the polarization effect according to this invention, including the following steps:

[0045] S01, Obtain the substrate and grow an epitaxial layer on the substrate.

[0046] Use any one of sapphire, silicon carbide, silicon, gallium nitride, aluminum nitride, or zinc oxide as a substrate, and grow epitaxial layers such as core layer, buffer layer, channel layer, barrier layer, and spacer layer in sequence.

[0047] SO2 forms the base region in the epitaxial layer through ion implantation.

[0048] Two magnesium ion implantations were performed in the base region, followed by high-temperature annealing to form a P-type base region.

[0049] S03, epitaxial growth and etching of P-type gallium nitride.

[0050] Two layers of P-type gallium nitride with different doping concentrations are formed by epitaxial growth. Then, the excess P-type gallium nitride is etched away, leaving only the designated area of ​​P-type gallium nitride.

[0051] S04, etch the barrier layer and channel layer, and deposit the collector and emitter electrodes.

[0052] The barrier layer is completely etched in the collector and emitter electrode regions, the channel layer is partially etched, and a metal alloy with a low work function is deposited to form an ohmic contact with the two-dimensional electron gas.

[0053] S05, deposited source metal electrode.

[0054] A metal alloy with a high work function is deposited in the source electrode region to form an ohmic contact with p-type gallium nitride.

[0055] S06, etch the groove for P-type gallium nitride and grow the gate oxide layer.

[0056] A trench is etched in the gate region of the P-type gallium nitride, the P+ channel layer is completely etched, the P-type channel layer is partially etched, and a portion of the P-type channel layer is retained at the bottom of the trench. Then, the gate oxide layer is thermally grown.

[0057] S07, deposit gate metal electrode.

[0058] A metal alloy with a low work function is deposited in the gate electrode region to form a MOS structure with the gate oxide layer and the P-type channel layer.

[0059] S08, deposited interlayer dielectric, leads out electrode.

[0060] An oxide layer is deposited as an interlayer dielectric to bring out the collector, emitter, source, and gate electrodes.

[0061] Referring to Figure 4, when VGE = 0V or -2V, the P-type MOSFET does not invert, and the device as a whole has no output current. When VGE ≤ -3.5V, the P-type MOSFET inverts, and a hole channel is formed. When VCE ≤ -3V, the PN junction formed between the P-type gallium nitride base region and the collector two-dimensional electron gas is in a forward bias state, and the PN junction formed between the P-type gallium nitride base region and the emitter two-dimensional electron gas is in a reverse bias state. The NPN type BJT is in an amplification state, amplifying the hole current injected into the P-type gallium nitride base region from lightly doped P-type gallium nitride into the electron current. Since the mobility of the two-dimensional electron gas is much higher than that of the hole, the current density of this device is significantly greater than that of a conventional P-type MOSFET. For example, the typical output current of a conventional P-type gallium nitride MOSFET is -15mA / mm when VGS = -8V and VDE = -15V, while the current density of this device exceeds -700mA / mm under the same voltage conditions.

Claims

1. A P-type channel gallium nitride-based insulated gate bipolar transistor based on polarization effect, comprising an NPN type BJT (1), wherein the NPN type BJT comprises a channel layer (104), a barrier layer, a spacer layer, a P-type gallium nitride base region (106), and an emitter metal (1082) stacked sequentially, wherein the P-type gallium nitride base region (106) extends into the channel layer (104), and the spacer layer, the barrier layer, and the spacer layer are formed at the interface between the channel layer (104) and the barrier layer. The two-dimensional electron gas is divided by a p-type gallium nitride base region (106) into a collector spacer region (1091) and an emitter spacer region (1092), a collector barrier region (1071) and an emitter barrier region (1072), and a collector two-dimensional electron gas (1051) and an emitter two-dimensional electron gas (1052). The emitter metal (1082) extends into the channel layer (104) and is connected to the emitter two-dimensional electron gas (1052). Its characteristic is that... The NPN type BJT is provided with a P-type MOSFET (2), the source metal (205) of the P-type MOSFET is connected to the emitter metal (1082), and the lightly doped P-type gallium nitride region (201) of the drain region of the P-type MOSFET is connected to the P-type gallium nitride base region (106).

2. The polarization effect-based P-channel gallium nitride-based insulated gate bipolar transistor of claim 1, wherein P The NPN type MOSFET includes a lightly doped gallium nitride region (201) disposed on a p-type gallium nitride base region (106) and an emitter spacer region (1092) of an NPN type BJT. A heavily doped gallium nitride region (202) is disposed on the lightly doped gallium nitride region (201). A gate metal (204) is disposed on the heavily doped gallium nitride region (202) and extends into the lightly doped gallium nitride region (201). A gate oxide layer (203) is disposed between the gate metal (204) and the lightly and heavily doped gallium nitride regions. The source metal (205) is connected to the heavily doped gallium nitride region (202).

3. The polarization effect-based P-channel gallium nitride-based insulated gate bipolar transistor of claim 2, wherein the heavily doped The P-type gallium nitride region (202) is a heavily doped P-type gallium nitride grown epitaxially, with a thickness of 20-50 nm, and can be heavily doped with magnesium, with a hole concentration of 5e17-5e18 cm -3 . ​ 4. The polarization effect-based P-channel gallium nitride-based insulated gate bipolar transistor of claim 2, wherein The lightly doped P-type gallium nitride region (201) is a lightly doped P-type gallium nitride grown by epitaxy, with a thickness of 20-50 nm, and can be lightly doped with magnesium, with a hole concentration of 1e17-1e18 cm -3 .

5. The P-type channel polarization effect based gallium nitride based insulated gate bipolar transistor according to claim 1 or 2, characterized in that The NPN type BJT (1) also includes a substrate (101) and a collector metal (1081). A nucleation layer (102), a buffer layer (103) and a channel layer (104) are sequentially disposed on the substrate (101). The channel layer (104) is disposed on the channel layer (104). The collector metal (1081) extends into the channel layer (104) and is connected to the collector two-dimensional electron gas (1051).

6. A method for fabricating the transistor according to claim 1, characterized in that, In A nucleation layer (102), a buffer layer (103), a channel layer (104), a barrier layer, and a spacer layer are epitaxially grown on a substrate (101) in sequence. A p-type gallium nitride base region (106) is formed by ion implantation. P-type gallium nitride is epitaxially grown to form a lightly doped p-type gallium nitride region (201) and a heavily doped p-type gallium nitride region (202) in sequence. The barrier layer and spacer layer located on one side of the p-type gallium nitride base region (106) are used as the collector barrier region (1071) and the collector spacer region (1091), respectively. The lightly and heavily doped p-type gallium nitride regions above the collector spacer region (1091) are dry etched. The lightly and heavily doped regions on one side, the other side, and above the spacer layer, barrier layer, and channel layer (104) are etched. The heavily doped P-type gallium nitride region forms electrode vias for the emitter and collector, leading out the collector metal (1081) and emitter metal (1082); the source electrode region on the heavily doped P-type gallium nitride region (202) is etched and metal is deposited to form the source metal (205) and electrically connected to the emitter metal (1082); the heavily doped P-type gallium nitride region (202) is completely etched in the gate region, and the lightly doped P-type gallium nitride region (201) is partially etched to form a gate trench, removing excess photoresist and surface contaminants; a gate oxide layer (203) is thermally grown on the surface of the gate trench and the heavily doped P-type gallium nitride region (202), and then metal is deposited in the gate trench to form the gate metal (204).

7. The method of claim 6, wherein When forming the p-type gallium nitride base region (106), magnesium ions are implanted twice within the base region. The dose of the first implantation is 5e12~5e13cm. -2 The energy is 20–40 keV; the dose of the second injection is 1e13–1e14 cm⁻¹. -2 The energy is 60-100keV; after ion implantation, high-temperature annealing is performed, with an annealing temperature above 1000℃; the depth of the P-type gallium nitride base region (106) after magnesium ion activation is greater than the thickness of the barrier layer, and does not exceed the sum of the thicknesses of the barrier layer and the channel layer.

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