Chip structure and chip stacking structure

Abstract

A chip structure and a chip stacking structure. The chip structure comprises: a substrate comprising a front surface and a rear surface that are arranged opposite each other, a circuit layer being provided on the front surface; a trench located on the rear surface; and a stress adjustment layer filling the trench, wherein a stress applied by the stress adjustment layer to the rear surface is less than a stress applied by the circuit layer to the front surface. The stress adjustment layer can effectively reduce warpage of the chip structure.

Description

Chip structure, chip stacking structure

[0001] This application claims priority to Chinese Patent Application No. 202510486776.7, filed on April 17, 2025, entitled “Chip Structure, Chip Stacking Structure”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of semiconductor technology, and more particularly to a chip structure and a chip stacking structure. Background Technology

[0003] During the semiconductor manufacturing process, as various material layers and semiconductor device structures are formed on the wafer surface, various stresses are generated on the wafer surface. At the same time, as the chip thickness becomes thinner, the chip will warp. Summary of the Invention

[0004] According to a first aspect of the present disclosure, a chip structure is provided, comprising:

[0005] A substrate, comprising a front side and a back side disposed opposite to each other, wherein a circuit layer is present on the front side;

[0006] Grooves are located on the back side;

[0007] A stress-adjusting layer fills the trench, wherein the stress applied by the stress-adjusting layer to the back side is less than the stress applied by the circuit layer to the front side.

[0008] In some embodiments, the stress adjustment layer includes a first stress adjustment layer and a second stress adjustment layer. The first stress adjustment layer is located on the inner wall of the trench, and the second stress adjustment layer is located on the first stress adjustment layer. The coefficient of thermal expansion of the first stress adjustment layer is greater than the coefficient of thermal expansion of the substrate and less than the coefficient of thermal expansion of the second stress adjustment layer.

[0009] In some embodiments, the elastic modulus of the first stress adjustment layer is greater than the elastic modulus of the substrate and less than the elastic modulus of the second stress adjustment layer.

[0010] In some embodiments, the first stress adjustment layer and the substrate have the same first chemical element, the first stress adjustment layer and the second stress adjustment layer have the same second chemical element, and the first chemical element is different from the second chemical element.

[0011] In some embodiments, the difference between the thermal expansion coefficient of the first stress adjustment layer and the thermal expansion coefficient of the substrate is less than the difference between the thermal expansion coefficient of the second stress adjustment layer and the thermal expansion coefficient of the first stress adjustment layer.

[0012] In some embodiments, the difference between the elastic modulus of the first stress adjustment layer and the elastic modulus of the substrate is less than the difference between the elastic modulus of the second stress adjustment layer and the elastic modulus of the first stress adjustment layer.

[0013] In some embodiments, the stress adjustment layer further includes a third stress adjustment layer located on the second stress adjustment layer, wherein the coefficient of thermal expansion of the third stress adjustment layer is greater than that of the second stress adjustment layer, and the elastic modulus of the third stress adjustment layer is greater than that of the second stress adjustment layer.

[0014] In some embodiments, the second stress-adjusting layer and the third stress-adjusting layer have the same third chemical element, which is different from the first chemical element and the second chemical element.

[0015] In some embodiments, the difference between the thermal expansion coefficient of the third stress adjustment layer and the thermal expansion coefficient of the second stress adjustment layer is greater than the thermal expansion coefficient of the second stress adjustment layer, which is less than the thermal expansion coefficient of the first stress adjustment layer.

[0016] In some embodiments, the difference between the elastic modulus of the third stress adjustment layer and the elastic modulus of the second stress adjustment layer is less than the difference between the elastic modulus of the second stress adjustment layer and the elastic modulus of the first stress adjustment layer.

[0017] In some embodiments, the trenches are crisscrossing strip structures, and the contact area between the stress adjustment layer and the substrate is smaller than the contact area between the circuit layer and the substrate.

[0018] In some embodiments, the trench includes a lower trench and an upper trench, wherein the depth of the lower trench is greater than the depth of the upper trench, and the width of the lower trench is less than the width of the upper trench.

[0019] In some embodiments, the chip structure further includes:

[0020] Multiple through-silicon via structures extend from the front side to the back side;

[0021] In a first direction, a portion of the stress adjustment layer passes through the region between adjacent through-silicon via structures, and there is a first spacing between the through-silicon via structures and the stress adjustment layer;

[0022] In the second direction, a portion of the stress adjustment layer passes through the region between adjacent through-silicon via structures, and there is a second spacing between the through-silicon via structures and the stress adjustment layer, wherein the first spacing is greater than the second spacing.

[0023] In some embodiments, the chip structure further includes:

[0024] Multiple pads are located on the back side, and each pad is connected to each through-silicon via structure;

[0025] In the first direction, there is a third spacing between adjacent pads, and a portion of the stress adjustment layer passes through the area between adjacent pads;

[0026] In the second direction, there is a fourth spacing between adjacent pads, the third spacing is greater than the fourth spacing, and a portion of the stress adjustment layer passes through the area between adjacent pads;

[0027] The width of the stress adjustment layer in the first direction is greater than the width of the stress adjustment layer in the second direction.

[0028] In some embodiments, in the second direction, the spacing between the through-silicon via structure and the stress adjustment layer is greater than the width of the pad.

[0029] In some embodiments, in the second direction, the spacing between the pad and the stress adjustment layer is smaller than the diameter of the through-silicon via structure.

[0030] According to a second aspect of the present disclosure, a chip stacking structure is provided, comprising:

[0031] Multiple chip structures are stacked together, and the chip structures include the structures described above.

[0032] In summary, this disclosure provides a chip structure and a chip stacking structure. The chip structure includes a substrate with a circuit layer on its front side and trenches on its back side, where a stress-adjusting layer is filled. Since the circuit layer applies stress to the front side of the substrate, causing warping, this embodiment applies stress to the back side of the substrate using the stress-adjusting layer. Simultaneously, the stress applied by the stress-adjusting layer to the back side of the substrate is less than the stress applied by the circuit layer to the front side, thereby improving the chip's warping condition. Furthermore, in this embodiment, because the stress-adjusting layer is filled on the back side of the chip, i.e., flush with the back side of the chip, it does not increase the chip's thickness. Attached Figure Description

[0033] Figure 1 is a schematic diagram illustrating a chip structure according to an exemplary embodiment;

[0034] Figure 2 is a schematic diagram illustrating the warping of Figure 1 according to an exemplary embodiment;

[0035] Figure 3 is another schematic diagram of a chip structure according to an exemplary embodiment;

[0036] Figure 4 is a cross-sectional view of Figure 3 in the AA direction according to an exemplary embodiment;

[0037] Figure 5 is a schematic diagram of a trench according to an exemplary embodiment;

[0038] Figure 6 is a schematic diagram of a stress adjustment layer according to an exemplary embodiment;

[0039] Figure 7 is another schematic diagram of a stress adjustment layer according to an exemplary embodiment;

[0040] Figure 8 is another schematic diagram of a stress adjustment layer according to an exemplary embodiment;

[0041] Figure 9 is another schematic diagram of a chip structure according to an exemplary embodiment;

[0042] Figure 10 is a cross-sectional view of Figure 9 in the BB direction according to an exemplary embodiment;

[0043] Figure 11 is a schematic diagram of a chip stacking structure according to an exemplary embodiment. Detailed Implementation

[0044] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0045] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0046] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0047] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0048] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0049] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0050] As shown in Figures 1 and 2, this disclosure provides a chip structure 100, which may include a substrate 101, a circuit layer 102, and a stress layer 103. The circuit layer 102 is on the front side of the substrate 101, and the stress layer 103 is on the back side of the substrate 101. The circuit layer 102 may include a metal layer and an insulating layer, thereby applying stress to the substrate 101. Simultaneously, as the thickness of the chip structure 100 decreases, significant warping occurs. To mitigate the warping of the chip structure 100, a stress layer 103 is typically formed on the back side of the substrate 101. The stress layer 103 is typically silicon nitride or silicon oxide. This stress layer 103 applies stress to the back side of the substrate 101, thereby resisting the stress applied by the circuit layer 102 to the front side of the substrate 101, and thus improving the warping state of the chip structure 100. However, to significantly improve the warpage of the chip structure 100, a stress layer 103 of considerable thickness needs to be formed. However, when the thickness of the stress layer 103 is uneven, it cannot effectively improve the warpage. Therefore, although forming a stress layer 103 on the back side of the substrate 101 can improve the warpage, the chip structure 100 will still be in a warped state.

[0051] As shown in Figures 3 and 4, Figure 3 shows a schematic diagram of the back side 1012 of the chip structure 100, and Figure 4 shows a cross-sectional view of Figure 3 along the AA direction. This disclosure proposes another chip structure 100, which may include a substrate 101, a circuit layer 102, and a stress adjustment layer 104. The substrate 101 may be a silicon substrate, such as a single-crystal silicon wafer. Semiconductor devices, such as word line structures and TSVs, may be present in the substrate 101. The substrate 101 includes a front side 1011 and a back side 1012, which are disposed opposite to each other. The circuit layer 102 may be located on the front side 1011 and may include an insulating layer and a metal trace layer. The circuit layer 102 can provide signal transmission for the semiconductor devices in the substrate 101. Because the coefficient of thermal expansion (CTE) of the circuit layer 102 does not match that of the substrate 101, the circuit layer 102 will apply stress to the front side 1011 of the substrate 101, which will cause the substrate 101 to warp. In this embodiment, a stress adjustment layer 104 is formed on the back side 1012 of the substrate 101. The stress adjustment layer 104 extends from the back side 1012 of the substrate 101 into the interior of the substrate 101, so that the stress adjustment layer 104 can be flush with the back side 1012, that is, the stress adjustment layer 104 will not increase the thickness of the chip structure 100.

[0052] As shown in Figures 3 and 4, the stress adjustment layer 104 can be a strip structure, such as a straight strip structure. In this embodiment, the stress adjustment layer 104 is a crisscrossing strip structure. Of course, in some embodiments, the stress adjustment layer 104 can also be a curved structure, such as an S-shape. Since the stress adjustment layer 104 is inside the substrate 101, rather than covering the back side 1012 of the substrate 101, and adjacent stress adjustment layers 104 are spaced apart in the same direction, the circuit layer 102 completely covers the front side 1011 of the substrate 101. Therefore, the contact area between the circuit layer 102 and the substrate 101 is larger than the contact area between the stress adjustment layer 104 and the substrate 101. Consequently, the stress applied by the circuit layer 102 to the front side 1011 (i.e., the substrate) is greater than the stress applied by the stress adjustment layer 104 to the back side 1012 (i.e., the substrate), thereby improving the warpage state of the substrate 101. Simultaneously, while the circuit layer 102 applies stress to the front side 1011, a portion of the substrate 101 between adjacent stress adjustment layers 104 resists the stress applied by the circuit layer 102 to the front side 1011. This resistance, combined with the stress applied by the stress adjustment layer 104 to the back side 1012, collectively resists the stress applied by the circuit layer 102 to the front side 1011, thereby adjusting the warping state of the substrate 101. Conversely, if the stress applied by the stress adjustment layer 104 to the back side 1012 is greater than the stress applied by the circuit layer 102 to the front side 1011, the substrate 101 will warp in the opposite direction, which is detrimental to adjusting the warping of the substrate 101.

[0053] As shown in Figures 3 and 4, in this embodiment, to adjust the stress applied by the stress adjustment layer 104 to the back surface 1012, the contact area between the stress adjustment layer 104 and the substrate 101 can be appropriately increased or decreased. For example, the density of the stress adjustment layer 104 can be increased or decreased to adjust the contact area between the stress adjustment layer 104 and the substrate 101. Since the contact area between the stress adjustment layer 104 and the substrate 101 changes, the stress applied by the stress adjustment layer 104 to the back surface 101 will also change. In this embodiment, the contact area between the stress adjustment layer 104 and the substrate 101 is equal to 10%-36% of the contact area between the circuit layer 102 and the substrate 101. If the contact area between the stress adjustment layer 104 and the substrate 101 is greater than 36% of the contact area between the circuit layer 102 and the substrate 101, the stress applied by the stress adjustment layer 104 to the substrate 101 will become greater, which will cause the substrate to warp in the opposite direction. If the contact area between the stress adjustment layer 104 and the substrate 101 is less than 10% of the contact area between the circuit layer 102 and the substrate 101, the stress applied by the stress adjustment layer 104 to the substrate 101 will be smaller, and its effect on improving warping will be minimal.

[0054] As shown in Figures 4 and 5, since the stress adjustment layer 104 extends from the back surface 1012 of the substrate 101 into the substrate 101, a trench 105 can be formed on the back surface 1012 of the substrate 101, and the stress adjustment layer 104 can be formed in the trench 105. The trench 105 may include an upper trench 1051 and a lower trench 1052. The upper trench 1051 may be located above the lower trench 1052. In the vertical direction, the upper trench 1051 has a first depth H1, and the lower trench 1052 has a second trench H2, and the first depth H1 is less than the second depth H2. In the horizontal direction, the upper trench 1051 has a first width D1, and the lower trench 1052 has a second width D2. When fabricating the trench 105, the upper trench 1051 can be formed first by an etching process, and then the upper trench 1051 can be etched to form the lower trench 1052. In this embodiment, the first depth H1 can be less than the second depth H2, and the first width D1 can be greater than the second width D2. That is, in this embodiment, the contact area between the stress adjustment layer 104 and the substrate 101 is adjusted by adjusting the depth and width of the upper trench 1051 and the lower trench 1052, thereby adjusting the stress applied by the stress adjustment layer 104 to the substrate 101.

[0055] As shown in Figure 6, in this embodiment, the stress adjustment layer 104 fills the trench 105. That is, the stress adjustment layer 104 can be made of a material such as silicon nitride or silicon oxide. The coefficient of thermal expansion of the stress adjustment layer 104 can be greater than that of the substrate 101 (silicon substrate). Since the stress adjustment layer 104 occupies a portion of the volume of the substrate 101, it can reduce and improve the expansion volume of the substrate 101. Simultaneously, the stress adjustment layer 104 can apply stress to the substrate 101, effectively improving the warpage of the substrate 101.

[0056] As shown in Figure 7, in this embodiment, the stress adjustment layer 104 may include a two-layer structure, such as a first stress adjustment layer 1041 and a second stress adjustment layer 1042. The first stress adjustment layer 1041 covers the sidewall of the trench 105, and the second stress adjustment layer 1042 covers the first stress adjustment layer 1041, thereby filling the trench 105. In this embodiment, the first stress adjustment layer 1041 and the substrate 101 share the same first chemical element, and the second stress adjustment layer 1042 and the first stress adjustment layer 1041 share the same second chemical element, but the first chemical element is different from the second chemical element. Because the first stress adjustment layer 1041 and the substrate 101 share the same chemical element, lattice mismatch problems can be reduced during the deposition of the first stress adjustment layer 1041, thus resulting in better adhesion between the first stress adjustment layer 1041 and the substrate 101. Meanwhile, the second stress adjustment layer 1042 has the same chemical elements as the first stress adjustment layer 1041, which reduces lattice mismatch during the deposition of the second stress adjustment layer 1042, thereby ensuring good adhesion between the first stress adjustment layer 1041 and the second stress adjustment layer 1042. Furthermore, since the first and second chemical elements are different, the first and second stress adjustment layers 1041 and 1042 have different coefficients of thermal expansion, thus forming a composite film with different coefficients of thermal expansion. This allows for the adjustment of the stress applied to the substrate 101 by the stress adjustment layer 104. In this embodiment, since the substrate 101 is made of silicon, the first stress adjustment layer 1041 can be silicon nitride, meaning it has the same silicon atoms as the substrate 101, and the second stress adjustment layer 1042 can be aluminum nitride, meaning it has the same nitrogen atoms as both layers.

[0057] As shown in Figure 7, the first stress adjustment layer 1041 and the second stress adjustment layer 1042 are made of different materials, that is, the first stress adjustment layer 1041 and the second stress adjustment layer 1042 have different coefficients of thermal expansion, and at the same time, the first stress adjustment layer 1041 and the second stress adjustment layer 1042 have different elastic moduli. In this embodiment, the coefficient of thermal expansion of the first stress adjustment layer 1041 can be greater than the coefficient of thermal expansion of the substrate 101, and the coefficient of thermal expansion of the second stress adjustment layer 1042 can be greater than the coefficient of thermal expansion of the first stress adjustment layer 1041, thereby forming a composite film layer with successively increasing coefficients of thermal expansion. Because the second stress adjustment layer 1042 has a larger coefficient of thermal expansion, the second stress adjustment layer 1042 can apply a larger stress to the substrate 101, thereby increasing the stress applied to the substrate 101 by the stress adjustment layer 104, and thus resisting the stress applied to the substrate 101 by the circuit layer 103. In this embodiment, the difference between the thermal expansion coefficient of the first stress adjustment layer 1041 and the thermal expansion coefficient of the substrate 101 is smaller than the difference between the thermal expansion coefficient of the second stress adjustment layer 1042 and the thermal expansion coefficient of the first stress adjustment layer 1041. Since the first stress adjustment layer 1041 is in direct contact with the substrate 101, when the chip structure 100 is at a high temperature, the circuit layer 102 applies stress to the substrate 101, causing the substrate 101 to deform. The thermal expansion coefficients of the first stress adjustment layer 1041 and the substrate 101 are close, thus the first stress adjustment layer 1041 and the substrate 101 have similar deformations, preventing the first stress adjustment layer 1041 from detaching from the substrate 101. Simultaneously, since the second stress adjustment layer 1042 has a larger thermal expansion coefficient, it can provide greater resistance to warping, thereby improving the warping of the substrate 101.

[0058] As shown in Figure 7, the stress adjustment layer 104 includes a first stress adjustment layer 1041 and a second stress adjustment layer 1042. The elastic modulus of the first stress adjustment layer 1041 can be less than that of the second stress adjustment layer 1042. The elastic modulus of the first stress adjustment layer 1041 can be greater than that of the substrate 101. When the chip structure 100 enters a low-temperature environment, the circuit layer 102 shrinks, thereby applying stress to the substrate 101, causing the substrate 101 to warp. In this embodiment, the first stress adjustment layer 1041 and the second stress adjustment layer 1042 are provided with sequentially increasing elastic moduli, so that the stress adjustment layer 104 maintains a certain rigidity in a low-temperature environment, thereby applying stress to the substrate 101 to resist the stress generated by the circuit layer 102, and thus improving the warping state of the substrate 101. Meanwhile, since the difference between the elastic modulus of the first stress adjustment layer 1041 and the elastic modulus of the substrate 101 is smaller than the difference between the elastic modulus of the second stress adjustment layer 1042 and the elastic modulus of the first stress adjustment layer 1041, the elastic modulus of the first stress adjustment layer 1041 is closer to that of the substrate 101. Therefore, the first stress adjustment layer 1041 can undergo similar shrinkage as the substrate 101, thereby preventing the first stress adjustment layer 1041 from detaching from the substrate 101. Simultaneously, since the elastic modulus of the second stress adjustment layer 1042 is larger, it can generate greater resistance. Therefore, the second stress adjustment layer 1042 can apply greater stress to the substrate 101, thereby improving the warping of the substrate 101.

[0059] As shown in Figure 8, to further improve the ability of the stress adjustment layer 104 to improve the warping of the substrate 101, another stress adjustment layer 104 is disclosed in this embodiment. This stress adjustment layer 104 may include a first stress adjustment layer 1041, a second stress adjustment layer 1042, and a third stress adjustment layer 1043. The first stress adjustment layer 1041, the second stress adjustment layer 1042, and the third stress adjustment layer 1043 are sequentially deposited in a trench 105. The first stress adjustment layer 1041 is located on the inner wall of the trench 105, the second stress adjustment layer 1042 is located on the first stress adjustment layer 1041, and the third stress adjustment layer 1043 is located on the second stress adjustment layer 1043, filling the trench 105.

[0060] As shown in Figure 8, the first stress adjustment layer 1041 is in diametrical contact with the substrate 101. The first stress adjustment layer 1041 can have the same first chemical element as the substrate 101, which is more conducive to utilizing the synergistic effect of chemical bonds, reducing lattice mismatch problems, and resulting in better adhesion between the first stress adjustment layer 1041 and the substrate 101, making delamination less likely. The second stress adjustment layer 1042 is in direct contact with the first stress adjustment layer 1041, and both the first and second stress adjustment layers 1041 can have the same second chemical element. However, the first chemical element is different from the second chemical element. Because the first and second stress adjustment layers 1041 and 1042 have the same chemical element, the second stress adjustment layer 1042 can be deposited more effectively on the first stress adjustment layer 1041. Since the first chemical element is different from the second chemical element, the coefficient of thermal expansion of the first stress adjustment layer 1041 can be different from that of the second stress adjustment layer 1042. The third stress-adjusting layer 1042 is in direct contact with the second stress-adjusting layer 1041. Both the second and third stress-adjusting layers 1042 and 1043 share the same third chemical element, while the first, second, and third chemical elements are different. Because the second and third stress-adjusting layers 1042 and 1043 share the same chemical element, the third stress-adjusting layer 1043 can be deposited more effectively on the second stress-adjusting layer 1042. Since the second and third chemical elements are different, the coefficient of thermal expansion of the third stress-adjusting layer 1043 is different from that of the second stress-adjusting layer 1042.

[0061] As shown in Figure 8, the substrate 101 is made of silicon. The first stress adjustment layer 1041 can be made of silicon nitride, the second stress adjustment layer 1042 can be made of aluminum nitride, and the third stress adjustment layer 1043 can be made of titanium aluminum nitride. Thus, the first stress adjustment layer 1041 and the substrate 101 share the same silicon element, the second stress adjustment layer 1042 and the first stress adjustment layer 1041 share the same nitrogen element, and the third stress adjustment layer 1043 and the second stress adjustment layer 1042 share the same aluminum element. Alternatively, the first stress adjustment layer 1041 can be made of silicon oxide, the second stress adjustment layer 1042 can be made of aluminum oxide, and the third stress adjustment layer 1043 can be made of titanium aluminum nitride, resulting in the first stress adjustment layer 1041 and the substrate 101 sharing the same silicon element, the second stress adjustment layer 1042 and the first stress adjustment layer 1041 sharing the same oxygen element, and the third stress adjustment layer 1043 and the second stress adjustment layer 1041 sharing the same aluminum element.

[0062] As shown in Figure 8, the coefficient of thermal expansion of the first stress adjustment layer 1041 can be greater than that of the substrate 101, the coefficient of thermal expansion of the second stress adjustment layer 1042 can be greater than that of the first stress adjustment layer 1041, and the coefficient of thermal expansion of the third stress adjustment layer 1043 can be greater than that of the second stress adjustment layer 1042, thus forming a composite film layer with progressively increasing coefficients of thermal expansion. The elastic modulus of the first stress adjustment layer 1041 can be greater than that of the substrate 101, the second stress adjustment layer 1042 can be greater than that of the first stress adjustment layer 1041, and the third stress adjustment layer 1043 can be greater than that of the second stress adjustment layer 1042, thus forming a composite film layer with progressively increasing elastic modulus.

[0063] As shown in Figure 8, the coefficient of thermal expansion of the first stress adjustment layer 1041 is greater than that of the substrate 101, but less than that of the second stress adjustment layer 1042. Furthermore, the difference between the coefficients of thermal expansion of the first stress adjustment layer 1041 and the substrate 101 is less than the difference between the coefficients of thermal expansion of the second stress adjustment layer 1042 and the first stress adjustment layer 1041. In other words, the coefficients of thermal expansion of the first stress adjustment layer 1041 and the substrate 101 are closer. Therefore, when the chip structure 100 is at a high temperature, the circuit layer 102 deforms, thereby applying stress to the substrate 101. Consequently, the substrate 101 and the first stress adjustment layer 1041 undergo deformations of similar magnitude, ensuring that the first stress adjustment layer 1042 does not detach from the substrate 101. Meanwhile, the difference between the thermal expansion coefficient of the third stress adjustment layer 1043 and the thermal expansion coefficient of the second stress adjustment layer 1042 is greater than the difference between the thermal expansion coefficient of the second stress adjustment layer 1042 and the thermal expansion coefficient of the first stress adjustment layer 1041. That is, the thermal expansion coefficients of the third stress adjustment layer 1043 and the second stress adjustment layer 1042 are larger than those of the first stress adjustment layer 1041. Therefore, the third stress adjustment layer 1043 and the second stress adjustment layer 1042 will generate greater resistance, thereby enabling the stress adjustment layer 104 to improve the warping state of the substrate 101. In this embodiment, by designing the stress adjustment layer 104 with sequentially increasing thermal expansion coefficients, the stress adjustment layer 104 can possess high bending strength while maintaining good adhesion to the substrate 101.

[0064] As shown in Figure 8, the elastic modulus of the first stress adjustment layer 1041 is greater than that of the substrate 101 and less than that of the second stress adjustment layer 1042. The difference between the elastic modulus of the first stress adjustment layer 1041 and the elastic modulus of the substrate 101 is less than the difference between the elastic modulus of the second stress adjustment layer 1042 and the elastic modulus of the first stress adjustment layer 1041. That is, the elastic modulus of the first stress adjustment layer 1041 and the elastic modulus of the substrate 101 are relatively close. Therefore, when the chip structure 100 is in a low-temperature environment, the circuit layer 102 will shrink, thereby applying stress to the substrate 101 and causing the substrate 101 to deform. Since the first stress adjustment layer 1041 has a certain rigidity, the first stress adjustment layer 1041 and the substrate 101 will undergo deformations of similar degree, thereby ensuring that the first stress adjustment layer 1041 will not detach from the substrate 101. Meanwhile, the difference between the elastic modulus of the third stress adjustment layer 1043 and the elastic modulus of the second stress adjustment layer 1042 is smaller than the difference between the elastic modulus of the second stress adjustment layer 1042 and the elastic modulus of the first stress adjustment layer 1041. That is, although the elastic moduli of the first stress adjustment layer 1041, the second stress adjustment layer 1042, and the third stress adjustment layer 1043 increase sequentially, the increase in the elastic modulus of the third stress adjustment layer 1043 relative to the elastic modulus of the second stress adjustment layer 1042 is relatively small. This results in the third stress adjustment layer 1043 having good rigidity and high bending strength, which can improve the warping of the substrate 101. Conversely, if the third stress adjustment layer 1043 has a larger elastic modulus, its rigidity will be greater, which will cause the third stress adjustment layer 1043 to exert a larger stress on the substrate 101. This may lead to the stress exerted on the substrate 101 by the stress adjustment layer 104 being greater than the stress exerted on the substrate 101 by the circuit layer 102, thus failing to improve the warping of the substrate 101.

[0065] As shown in Figure 8, in this embodiment, by setting a first stress adjustment layer 1041, a second stress adjustment layer 1042, and a third stress adjustment layer 1043 with sequentially increasing coefficients of thermal expansion and elastic modulus, the stress adjustment layer 104 possesses high bending strength while maintaining good compatibility with the substrate 101. In this embodiment, since the contact area between the stress adjustment layer 104 and the substrate 101 is smaller than the contact area between the circuit layer 102 and the substrate 101, the stress applied by the stress adjustment layer 104 to the substrate 101 is less than the stress applied by the circuit layer 102 to the substrate 101. Combined with the substrate 101's own resistance, the stress applied by the stress adjustment layer 104 to the substrate 101 is more closely matched with the substrate 101's own resistance, thereby improving the warpage of the substrate 101. Meanwhile, since the stress adjustment layer 104 is located in the substrate 101, it can increase the contact area between the stress adjustment layer 104 and the substrate 101, and also increase the stress release area in the substrate 101. The stress in the substrate 101 can be released along the direction of the stress adjustment layer 104.

[0066] As shown in Figure 9, this embodiment of the present disclosure also proposes another chip structure 100, which may include a substrate 101. The substrate 101 has multiple through-silicon via (TSV) structures 106 extending from the front side to the back side of the substrate 101. Multiple pads 107 are located on the back side of the substrate 101, and the pads 107 contact the TSV structures 106, thus achieving a one-to-one correspondence. A stress adjustment layer 104 is also disposed on the back side of the substrate 101, and the structure of the stress adjustment layer 104 can be referred to the above description. The stress adjustment layer 104 can apply stress to the substrate 101, thereby adjusting the warpage of the substrate 101.

[0067] As shown in Figure 9, two rows of through-silicon via (TSV) structures 106 are disposed on the back side of the substrate 101, each row including multiple TSV structures 106. In the first direction (X direction), the spacing between two adjacent TSV structures 106 is greater than the spacing between two adjacent TSV structures 106 in the second direction (Y direction). The stress adjustment layer 104 is staggered in the first and second directions, allowing the stress adjustment layer 104 to pass through the area between adjacent TSV structures 106. Along the first direction, a portion of the stress adjustment layer 104 can pass through the area between adjacent TSV structures 106, and along the second direction, a portion of the stress adjustment layer 104 can pass through the area between adjacent TSV structures 106. Since the spacing between two adjacent through-silicon via (TSV) structures 106 is relatively large in the first direction, to increase the contact area between the stress adjustment layer 104 and the substrate 101 and to increase the stress applied by the stress adjustment layer 104 to the substrate 101, the width of the stress adjustment layer 104 in this region can be increased. That is, the width of the stress adjustment layer 104 in the first direction is greater than the width of the stress adjustment layer 104 in the second direction. Simultaneously, in the first direction, the distance from the TSV structure 106 to the stress adjustment layer 104 is a first spacing L1. In the second direction, the distance from the TSV structure 106 to the stress adjustment layer 104 is a second spacing L2. In this embodiment, the first spacing L1 can be greater than the second spacing L2. Because the first spacing L1 is relatively large, it prevents the stress adjustment layer 104 from being too close to the TSV structure 106 in the first direction, preventing the formation of grooves on the stress adjustment layer 104 during subsequent polishing, and thus preventing uneven stress adjustment.

[0068] As shown in Figure 9, each through-silicon via (TSV) structure 106 has a pad 107. In the first direction, the distance between two adjacent pads 107 is a third spacing L3. In the second direction, the distance between two adjacent pads 107 is a fourth spacing L4, and the fourth spacing L4 is smaller than the third spacing L3. Since the arrangement of the pads 107 is the same as the arrangement of the TSV structures 106, the fourth spacing L4 can be greater than the third spacing L3, thus allowing the width of the stress adjustment layer 104 in the first direction to be greater than the width of the stress adjustment layer 104 in the second direction. It should be noted that the width of the stress adjustment layer 104 in the first direction is the width of the portion of the stress adjustment layer 104 extending along the second direction. The width of the stress adjustment layer 104 in the second direction is the width of the portion of the stress adjustment layer 104 extending along the first direction.

[0069] As shown in Figure 9, in the second direction, the width of the pad 107 is greater than the diameter of the through-silicon via (TSV) structure 106, and the distance from the TSV structure 106 to the stress adjustment layer 104 is greater than the width of the pad 107. This results in a larger spacing between the TSV structure 106 and the stress adjustment layer 104. Consequently, when the TSV structure 106 is exposed on the back side of the substrate 101 after grinding, it effectively prevents the stress adjustment layer 104 from being too close to the TSV structure 106, thus preventing the formation of grooves on the stress adjustment layer 104. This ensures that the stress adjustment layer 104 applies stress evenly to the substrate 101. Simultaneously, to increase the contact area between the stress adjustment layer 104 and the substrate 101 and to increase the stress applied by the stress adjustment layer 104 to the substrate 101, in the second direction, the distance from the pad 107 to the stress adjustment layer 104 is smaller than the diameter of the TSV structure 106. This results in a smaller spacing between the stress adjustment layer 104 and the pad 107, effectively increasing the contact area between the stress adjustment layer 104 and the substrate 101. In this embodiment, the diameter of the through-silicon via structure 106 can be 5-6 micrometers, the width of the pad 107 can be 40-42 micrometers, the distance from the through-silicon via structure 106 to the stress adjustment layer 104 can be 50-55 micrometers, and the distance from the pad 107 to the stress adjustment layer 104 can be 2-4 micrometers.

[0070] As shown in Figure 10, which is a cross-sectional view of Figure 9 along the AA direction, the chip structure 100 may include a substrate 101. The front side of the substrate 101 has a circuit layer 102, and the back side of the substrate 101 has a stress adjustment layer 104. The stress adjustment layer 104 extends from the back side of the substrate 101 into the interior of the substrate 101. The structure of the stress adjustment layer 104 can be referred to the description above. A through-silicon via (TSV) structure 106 is present in the substrate 101. The TSV structure 106 extends from the front side of the substrate 101 to the back side, thereby electrically connecting to pads 107. Simultaneously, a metal pad 108 is also present on the front side of the substrate 101, located on the circuit layer 102, thereby electrically connecting to the TSV structure 106. Solder balls 109 are present on the metal pad 108, and the solder balls 109 are used for electrical connection to external pads.

[0071] As shown in Figure 10, in this embodiment, when the chip structure 100 is at a high or low temperature, when the circuit layer 102 applies stress to the substrate 101, the substrate 101 will deform. At this time, the stress adjustment layer 104 will also deform, thereby applying stress to the substrate 101. The stress applied by the stress adjustment layer 104 to the substrate 101 is less than the stress applied by the circuit layer 102 to the substrate 101. Combined with the inherent resistance of the substrate 101, this can improve the warping of the substrate 101. Conversely, if the stress applied by the stress adjustment layer 104 to the substrate 101 is greater than the stress applied by the circuit layer 102 to the substrate 101, then combined with the inherent resistance of the substrate 101, the substrate 101 will warp in the opposite direction. In this embodiment, the contact area between the stress adjustment layer 104 and the substrate 101 is smaller than the contact area between the circuit layer 109 and the substrate 101. Therefore, the stress applied by the stress adjustment layer 104 to the substrate 101 (the back side of the substrate 101) is less than the stress applied by the circuit layer 109 to the substrate 101 (the front side of the substrate 101). In some embodiments, by providing composite film layers with different coefficients of thermal expansion and different elastic moduli, the stress applied by the stress adjustment layer 104 to the substrate 101 can be reasonably adjusted, ensuring that the stress applied by the stress adjustment layer 104 to the substrate 101 (the back side of the substrate 101) is less than the stress applied by the circuit layer 109 to the substrate 101 (the front side of the substrate 101).

[0072] As shown in FIG11, this disclosure also discloses a chip stacking structure 10, which may include a packaging substrate 11 and a plurality of chip structures 100. These chip structures 100 may be stacked on the packaging substrate 11. The structure of the chip structure 100 can be referred to the above description. When the chip structure 100 is soldered, the chip structure 100 is in a high-temperature state. The stress adjustment layer 104 can improve the warpage of the chip structure 100, thereby ensuring the stability of the soldering. The chip structure 100 may be a memory chip. Each of the memory semiconductor chips may be, for example, a volatile memory semiconductor chip (such as dynamic random access memory (DRAM) or static random access memory (SRAM)) or a non-volatile memory semiconductor chip (such as phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (RRAM)). According to some exemplary embodiments, the plurality of chip structures 100 may be flash memory, for example, NAND flash memory. This chip stacking structure 10 can be used in a variety of electronic devices. The electronic device may include one or more of the following: for example, smartphones, tablet PCs, mobile phones, video phones, e-book readers, desktop PCs, laptop PCs, netbooks, workstations, servers, personal digital assistants (PDAs), portable multimedia players (PMPs), MPEG-1 audio layer 3 (MP3) players, mobile medical devices, cameras, home appliances, medical devices, Internet of Things (IoT) devices, and wearable devices. Wearable devices may be accessory-type, fabric or clothing-type, body-attached type, or implantable circuit type. Accessory-type wearable devices may be, for example, watches, rings, bracelets, anklets, necklaces, glasses, contact lenses, or head-mounted devices (HMDs). The electronic device can also be used in large servers, such as data centers, AI computers, etc. The electronic device can also be used in personal navigation devices or portable navigation devices (PNDs), handheld game consoles, mobile internet devices (MIDs), wearable computers, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, and / or drones.

[0073] In summary, this disclosure provides a chip structure and a chip stacking structure. The chip structure includes a substrate with a circuit layer on its front side and trenches on its back side, where a stress-adjusting layer is filled. Since the circuit layer applies stress to the front side of the substrate, causing warping, this embodiment applies stress to the back side of the substrate using the stress-adjusting layer. Simultaneously, the stress applied by the stress-adjusting layer to the back side of the substrate is less than the stress applied by the circuit layer to the front side, thereby improving the chip's warping condition. Furthermore, in this embodiment, because the stress-adjusting layer is filled on the back side of the chip, i.e., flush with the back side of the chip, it does not increase the chip's thickness.

[0074] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A chip structure (100), characterized in that, include: The substrate (101) includes a front side (1011) and a back side (1012) disposed opposite to each other, wherein a circuit layer (102) is provided on the front side; A groove (105) is located on the back side (1012); A stress adjustment layer (104) fills the trench (105), and the stress applied by the stress adjustment layer (104) to the back side (1012) is less than the stress applied by the circuit layer (102) to the front side (1011).

2. The chip structure according to claim 1, characterized in that, The stress adjustment layer includes a first stress adjustment layer and a second stress adjustment layer. The first stress adjustment layer is located on the inner wall of the trench, and the second stress adjustment layer is located on the first stress adjustment layer. The thermal expansion coefficient of the first stress adjustment layer is greater than that of the substrate and less than that of the second stress adjustment layer.

3. The chip structure according to claim 2, characterized in that, The elastic modulus of the first stress adjustment layer is greater than that of the substrate and less than that of the second stress adjustment layer.

4. The chip structure according to claim 2 or 3, characterized in that, The first stress adjustment layer and the substrate have the same first chemical element, the first stress adjustment layer and the second stress adjustment layer have the same second chemical element, and the first chemical element is different from the second chemical element.

5. The chip structure according to claim 2 or 3, characterized in that, The difference between the thermal expansion coefficient of the first stress adjustment layer and the thermal expansion coefficient of the substrate is less than the difference between the thermal expansion coefficient of the second stress adjustment layer and the thermal expansion coefficient of the first stress adjustment layer.

6. The chip structure according to claim 3, characterized in that, The difference between the elastic modulus of the first stress adjustment layer and the elastic modulus of the substrate is less than the difference between the elastic modulus of the second stress adjustment layer and the elastic modulus of the first stress adjustment layer.

7. The chip structure according to claim 5, characterized in that, The stress adjustment layer further includes a third stress adjustment layer, which is located on the second stress adjustment layer. The coefficient of thermal expansion of the third stress adjustment layer is greater than that of the second stress adjustment layer, and the elastic modulus of the third stress adjustment layer is greater than that of the second stress adjustment layer.

8. The chip structure according to claim 7, characterized in that, The second stress-adjusting layer and the third stress-adjusting layer have the same third chemical element, which is different from the first chemical element and the second chemical element.

9. The chip structure according to claim 7, characterized in that, The difference between the thermal expansion coefficient of the third stress adjustment layer and the thermal expansion coefficient of the second stress adjustment layer is greater than the difference between the thermal expansion coefficient of the second stress adjustment layer and the thermal expansion coefficient of the first stress adjustment layer.

10. The chip structure according to claim 7, characterized in that, The difference between the elastic modulus of the third stress adjustment layer and the elastic modulus of the second stress adjustment layer is less than the difference between the elastic modulus of the second stress adjustment layer and the elastic modulus of the first stress adjustment layer.

11. The chip structure according to any one of claims 1-10, characterized in that, The trenches are crisscrossing strip structures, and the contact area between the stress adjustment layer and the substrate is smaller than the contact area between the circuit layer and the substrate.

12. The chip structure according to claim 11, characterized in that, The trench includes a lower trench and an upper trench, wherein the depth of the lower trench is greater than the depth of the upper trench, and the width of the lower trench is less than the width of the upper trench.

13. The chip structure according to any one of claims 1-10, characterized in that, The chip structure also includes: Multiple through-silicon via structures extend from the front side to the back side; In a first direction, a portion of the stress adjustment layer passes through the region between adjacent through-silicon via structures, and there is a first spacing between the through-silicon via structures and the stress adjustment layer; In the second direction, a portion of the stress adjustment layer passes through the region between adjacent through-silicon via structures, and there is a second spacing between the through-silicon via structures and the stress adjustment layer, wherein the first spacing is greater than the second spacing.

14. The chip structure according to claim 13, characterized in that, The chip structure also includes: Multiple pads are located on the back side, and each pad is connected to each through-silicon via structure; In the first direction, there is a third spacing between adjacent pads, and a portion of the stress adjustment layer passes through the area between adjacent pads; In the second direction, there is a fourth spacing between adjacent pads, the third spacing is greater than the fourth spacing, and a portion of the stress adjustment layer passes through the area between adjacent pads; The width of the stress adjustment layer in the first direction is greater than the width of the stress adjustment layer in the second direction.

15. The chip structure according to claim 14, characterized in that, In the second direction, the spacing between the through-silicon via structure and the stress adjustment layer is greater than the width of the pad.

16. The chip structure according to claim 14, characterized in that, In the second direction, the distance between the pad and the stress adjustment layer is smaller than the diameter of the through-silicon via structure.

17. A chip stacking structure (10), characterized in that, include: Multiple chip structures (100), said chip structures including the chip structure (100) according to any one of claims 1-16.

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