Ferroelectric high-voltage ITO thin film transistor and preparation method therefor

Abstract

A ferroelectric high-voltage ITO thin film transistor and a preparation method therefor. The structure of the transistor comprises: a substrate, a bottom gate electrode, a ferroelectric thin film layer, a gate electrode layer, a gate dielectric layer, an ITO active layer, a source electrode layer, and a drain electrode layer. A non-overlap area is introduced between the drain electrode layer of the device and the gate electrode layer in the horizontal direction, and a drift area is formed in the ITO active layer; the bottom gate electrode is located below the drift area, and different lengths are designed for the bottom gate electrode; and by applying a pulse voltage, the polarization characteristics of the upper ferroelectric thin film layer are regulated, thereby further affecting the carrier distribution in the active layer of the device and adjusting the output current and on-resistance of the device. The present invention provides a high-voltage thin film transistor having favorable breakdown characteristics and adjustable on-resistance. While achieving good voltage-withstanding capability of a device, regulation of the current output capability and on-resistance of the device is achieved by means of the design of a bottom gate electrode and an HfZrO ferroelectric thin film layer.

Description

A ferroelectric high-voltage ITO thin-film transistor and its fabrication method Technical Field

[0001] This invention relates to the field of high-voltage metal oxide thin-film transistors and their fabrication processes, specifically to a ferroelectric high-voltage ITO thin-film transistor and its fabrication method, and more particularly to a ferroelectric high-voltage ITO thin-film transistor with good withstand voltage and adjustable output resistance and its fabrication method. Background Technology

[0002] Indium tin oxide (ITO), a metal-oxide-semiconductor, is used as the channel layer material in next-generation thin-film transistor (TFT) technology. Compared to traditional amorphous silicon, it exhibits higher carrier mobility, good conductivity, and lower on-resistance. ITO has a wide bandgap of 3.5–4.2 eV, demonstrating good stability under high voltage and high power conditions, and is less prone to electrical breakdown or material degradation. It also possesses good thermal stability and oxidation resistance, supporting long-term device operation. Therefore, high-voltage ITO thin-film transistors have been proposed and extensively studied.

[0003] The polarization characteristics of the ferroelectric thin film material HfZrO originate from the non-centrosymmetric orthorhombic crystalline phase formed in the film, exhibiting low coercive electric field and high remanent polarization, as well as good fatigue resistance, which is beneficial for reducing power consumption and improving device reliability. HfZrO also has a low leakage current density and exhibits excellent dielectric strength even with very small film thickness. Furthermore, annealing HfZrO during the manufacturing process can increase the proportion of the ferroelectric phase in the HfZrO film, reduce stress and defects in the film, and improve dielectric strength and ferroelectric properties.

[0004] Research reports indicate that there are two main methods to improve the breakdown voltage characteristics of thin-film transistor (TFT) devices. The first is to increase the thickness of the gate dielectric layer. Increasing the thickness of the gate dielectric layer reduces the device capacitance per unit area, thereby reducing the vertical electric field distribution in the dielectric layer at the same voltage. This helps alleviate the insulation layer breakdown phenomenon caused by electric field concentration in the electrode overlap region under high voltage. The second method involves offsetting the drain electrode horizontally from the gate electrode by a certain distance to form a carrier drift region, eliminating the overlap between the drain metal and the gate metal, thus improving the device's breakdown performance. However, the increased equivalent gate thickness in the first method simultaneously reduces the device's output current capability, while the drift region in the second method, being uncontrolled by the gate voltage, exhibits a high-resistivity state, reducing the overall conductivity of the semiconductor channel. Therefore, it is necessary to propose a new type of high-voltage thin-film transistor device that can improve the device's voltage withstand capability, optimize the carrier distribution in the channel layer, and achieve adjustable resistance in the drift region (for example, in high-voltage switching circuits and high-voltage drive circuits, there are requirements for the device's voltage withstand capability and on-resistance, and the key is to make trade-offs based on load characteristics, switching frequency, power consumption, and other indicators), improve the device's conductivity, and achieve a good balance between the device's voltage withstand capability and output current capability. Summary of the Invention

[0005] Technical problem solved: In addressing the technical issues existing in the improvement of high-voltage thin-film transistor device performance, such as the sacrifice of output current capability by stacked gate dielectric layer or pull-off drift region structure while ensuring the device's withstand voltage characteristics, this invention proposes a ferroelectric high-voltage ITO thin-film transistor and its fabrication method, which can adjust the device's output current and control the device's on-resistance while achieving the withstand voltage characteristics of the thin-film transistor device.

[0006] Technical solution: The first objective of this invention is to provide a ferroelectric high-voltage ITO thin-film transistor, which includes a substrate, a bottom gate electrode, a ferroelectric thin film layer, a gate electrode layer, a gate dielectric layer, an ITO active layer, a source electrode layer, and a drain electrode layer.

[0007] The bottom gate electrode is located in the middle of the upper surface of the substrate. The length of the bottom gate electrode is based on the design range. The longer the bottom gate length, the stronger the current output capability of the corresponding device and the smaller the on-resistance.

[0008] The ferroelectric thin film layer covers the bottom gate electrode and the substrate, and is located above the bottom gate electrode and is controlled by the bottom gate electrode.

[0009] The gate electrode layer is disposed on the upper surface of the ferroelectric thin film layer, and there is an overlap area between the gate electrode layer and the bottom gate electrode in the horizontal direction;

[0010] The gate dielectric layer covers the gate electrode layer and the ferroelectric thin film layer;

[0011] The ITO active layer is disposed on the upper surface of the gate dielectric layer;

[0012] The source electrode layer is located on the left side of the upper surface of the ITO active layer, and the drain electrode layer is located on the right side of the upper surface of the ITO active layer. In the horizontal direction, there is an overlapping region between the source electrode layer and the gate electrode layer, and a non-overlapping region between the drain electrode layer and the gate electrode layer. A carrier drift region is formed in the ITO active layer, and there is also a non-overlapping region between the drain electrode layer and the bottom gate electrode in the horizontal direction.

[0013] During application, due to the memory retention characteristic of ferroelectric polarization, applying a pulse to the bottom gate electrode will cause the ferroelectric layer to correspond to different polarization states. For example, writing a positive pulse voltage will cause the ferroelectric layer to correspond to a positive polarization state, promoting channel layer conduction and resulting in a state with high current and low on-resistance. Similarly, a negative pulse will correspond to the opposite state with low current and high resistance.

[0014] Preferably, the length range of the bottom gate electrode is as follows: the left end extends to be flush with the gate electrode layer, and the right end extends to maintain a non-overlapping region with a length of at least 2 μm with the drain electrode layer.

[0015] Preferably, in the horizontal direction, the distance between the source electrode layer and the drain electrode layer is 18-60 μm, and the length of the non-overlapping region between the gate electrode layer and the drain electrode layer is 8-50 μm.

[0016] Preferably, in the horizontal direction, the length of the overlap region between the bottom gate electrode and the gate electrode layer is 5-15 μm; the length of the non-overlap region between the bottom gate electrode and the drain electrode layer is 4-20 μm. The length of the non-overlap region will affect the breakdown voltage of the device. When it is reduced to 1 μm, the device will have no breakdown voltage. When the length is too long, it will significantly increase the on-resistance and size of the device.

[0017] Preferably, the ferroelectric thin film layer is made of HfZrO material with a thickness of 10-20 nm; the ITO active layer is made of ITO material with a thickness of 4-10 nm.

[0018] Furthermore, the ferroelectric thin film layer has a thickness of 12 nm. The HfZrO material has a high dielectric constant and good polarization characteristics at a nanometer-thickness. Subsequent annealing processes are used to improve the proportion and stability of the ferroelectric phase in the HfZrO thin film. The ITO active layer has a thickness of 6 nm. ITO has high carrier mobility and a wide bandgap, enabling the realization of high-voltage thin-film transistors with low on-resistance.

[0019] Preferably, the bottom gate electrode is made of molybdenum metal with a thickness of 50-120 nm; the gate electrode layer is made of molybdenum metal with a thickness of 50-120 nm; the gate dielectric layer is made of aluminum oxide with a thickness of 10-30 nm; and the source electrode layer and drain electrode layer are made of molybdenum with a thickness of 50-120 nm.

[0020] Furthermore, the thickness of the bottom gate electrode is 100 nm; the thickness of the gate electrode layer is 100 nm; the thickness of the gate dielectric layer is 20 nm; and the thickness of the source electrode layer and the drain electrode layer is 100 nm. The thickness of the Mo metal electrode should not be too high, as this is not conducive to reducing device size, subsequent coating, and 3D integration; the thickness of the alumina electrode is typically 10-30 nm to ensure sufficient gate control capability and sufficiently low leakage current.

[0021] The second objective of this invention is to provide a method for fabricating a ferroelectric high-voltage ITO thin-film transistor based on the above, the steps of which are as follows:

[0022] Step 1: Obtain the substrate;

[0023] Step 2: Form a bottom gate electrode on the substrate;

[0024] Step 3: Form a ferroelectric thin film layer on the bottom gate electrode and the substrate;

[0025] Step 4: Form a gate electrode layer on the ferroelectric thin film layer;

[0026] Step 5: Perform thermal annealing on the ferroelectric thin film layer to form good ferroelectric properties;

[0027] Step 6: Form a gate dielectric layer on the gate electrode layer and the ferroelectric thin film layer;

[0028] Step 7: Form an ITO active layer on the gate dielectric layer;

[0029] Step 8: Form a source electrode layer on the left side above the ITO active layer, and form a drain electrode layer on the right side above the ITO active layer.

[0030] Preferably, magnetron sputtering is used to form the bottom gate electrode, gate electrode layer, ITO active layer, source electrode layer and drain electrode layer.

[0031] Preferably, the ferroelectric thin film layer and the gate dielectric layer are formed using the ALD process.

[0032] Preferably, the temperature for hot annealing in step five is 400-600℃.

[0033] Furthermore, during device operation, a pulse voltage is pre-written to the bottom gate electrode, causing the HfZrO ferroelectric thin film layer to generate a polarization effect under the action of the electric field. The polarization charge of the HfZrO ferroelectric thin film layer further affects the carrier concentration in the drift region. Bottom gate electrodes of different lengths have different controllability, thereby enabling the device's on-resistance to be adjustable.

[0034] This invention provides a ferroelectric high-voltage ITO thin-film transistor and its fabrication method. Based on a high-voltage thin-film transistor structure with a drift region structure, a bottom gate electrode and a ferroelectric thin-film layer are introduced below the device. The bottom gate electrode is designed with different lengths. By applying pulses to the bottom gate electrode, the polarization of the ferroelectric thin-film layer is controlled, which further affects the charge carriers in the channel layer, thereby realizing a high-voltage thin-film transistor with adjustable offset region resistance.

[0035] Beneficial effects: This invention proposes a ferroelectric high-voltage ITO thin-film transistor device. Based on the traditional high-voltage thin-film transistor with a drift region structure, a bottom gate electrode and a ferroelectric thin-film layer HfZrO are introduced. Bottom gate electrodes of different lengths are designed below the drift region, making the control range of the bottom gate electrode adjustable. By applying a pulse voltage to the bottom gate electrode, the HfZrO thin film is polarized. The polarization charge and the charge of the semiconductor channel layer influence each other through Coulomb coupling, thereby adjusting the output current and on-resistance of the device. Attached Figure Description

[0036] Figure 1 is a schematic diagram of the structure of a ferroelectric high-voltage ITO thin-film transistor device according to the present invention, where L... channel The length of the channel between the source electrode layer 170 and the drain electrode layer 180; L drift The length of the non-overlapping region between the drain electrode layer 180 and the gate electrode layer 140;

[0037] Figure 2 is a process flow diagram of the fabrication method of a ferroelectric high voltage ITO thin film transistor device according to the present invention;

[0038] Figure 3 is a schematic diagram of the structure of a conventional high-voltage TFT device described in the embodiment of the present invention. It only has a drift region structure. The difference between it and the device of the present invention is that it does not have a bottom gate electrode and a ferroelectric thin film layer, but the other thin film structure parameters are the same as those of the present invention.

[0039] Figure 4 is a comparison of the output characteristic curves of ferroelectric high-voltage ITO thin film transistors with different bottom gate electrode lengths designed in the embodiments of the present invention and the above-mentioned conventional high-voltage TFT devices. In the embodiments of the present invention, the output current of the devices is higher than that of conventional high-voltage TFT devices. Moreover, compared with devices with different bottom gate electrode lengths, the device with a longer bottom gate electrode has a larger corresponding output current value and a smaller on-resistance.

[0040] Figure 5 shows the comparison results of the breakdown characteristics of the device of the present invention and the conventional high voltage TFT device. Both the device of the present invention and the conventional high voltage TFT device have a withstand voltage of about 140V. Therefore, the design of the bottom gate electrode and the ferroelectric thin film layer in the present invention does not significantly reduce the withstand voltage capability of the device.

[0041] The numbers in the diagram represent the following: 110. Substrate; 120. Bottom gate electrode; 130. Ferroelectric thin film layer; 140. Gate electrode layer; 150. Gate dielectric layer; 160. ITO active layer; 170. Source electrode layer; 180. Drain electrode layer; 210. Conventional high-voltage TFT substrate; 220. Conventional high-voltage TFT gate electrode layer; 230. Conventional high-voltage TFT gate dielectric layer; 240. Conventional high-voltage TFT ITO active layer; 250. Conventional high-voltage TFT source electrode layer; 260. Conventional high-voltage TFT drain electrode layer. Detailed Implementation

[0042] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0043] This invention provides a ferroelectric high-voltage ITO thin-film transistor, which includes a substrate 110, a bottom gate electrode 120, a ferroelectric thin film layer 130, a gate electrode layer 140, a gate dielectric layer 150, an ITO active layer 160, a source electrode layer 170, and a drain electrode layer 180.

[0044] The bottom gate electrode 120 is located in the middle of the upper surface of the substrate 110. The length of the bottom gate electrode is based on the design range. The longer the bottom gate length, the stronger the current output capability of the corresponding device and the smaller the on-resistance.

[0045] The ferroelectric thin film layer 130 covers the bottom gate electrode 120 and the substrate 110;

[0046] The gate electrode layer 140 is disposed on the upper surface of the ferroelectric thin film layer 130, and there is an overlapping area between the gate electrode layer 140 and the bottom gate electrode 120 in the horizontal direction.

[0047] The gate dielectric layer 150 covers the gate electrode layer 140 and the ferroelectric thin film layer 130;

[0048] The ITO active layer 160 is disposed on the upper surface of the gate dielectric layer 150;

[0049] The source electrode layer 170 is disposed on the left side of the upper surface of the ITO active layer 160, and the drain electrode layer 180 is disposed on the right side of the upper surface of the ITO active layer 160. In the horizontal direction, the source electrode layer 170 and the gate electrode layer 140 have an overlapping region, and the drain electrode layer 180 and the gate electrode layer 140 have a non-overlapping region. A carrier drift region is formed in the ITO active layer 160, and in the horizontal direction, there is also a non-overlapping region between the drain electrode layer 180 and the bottom gate electrode 120.

[0050] As a further preferred embodiment, the length range of the bottom gate electrode 120 is as follows: the left end extends to be flush with the gate electrode layer 140, and the right end extends to maintain a non-overlapping region with a length of at least 2 μm with the drain electrode layer 180.

[0051] As a further preferred embodiment, in the horizontal direction, the distance between the source electrode layer 170 and the drain electrode layer 180 is 18-60 μm, and the length of the non-overlapping region between the drain electrode layer 180 and the gate electrode layer 140 is 8-50 μm.

[0052] As a further preferred embodiment, in the horizontal direction, the length of the overlapping region between the bottom gate electrode 120 and the gate electrode layer 140 is 5-15 μm, and the length of the non-overlapping region between the bottom gate electrode 120 and the drain electrode layer 180 is 4-20 μm.

[0053] As a further preferred embodiment, the ferroelectric thin film layer 130 is made of HfZrO material with a thickness of 10-20 nm; the ITO active layer 160 is made of ITO material with a thickness of 4-10 nm.

[0054] As a further preferred embodiment, the bottom gate electrode 120 is made of molybdenum metal with a thickness of 50-120 nm; the gate electrode layer 140 is made of molybdenum metal with a thickness of 50-120 nm; the gate dielectric layer 150 is made of aluminum oxide with a thickness of 10-30 nm; and the source electrode layer 170 and the drain electrode layer 180 are made of molybdenum with a thickness of 50-120 nm.

[0055] As a further preferred embodiment, the bottom gate electrode 120 is made of molybdenum metal with a thickness of 100 nm; the gate electrode layer 140 is made of molybdenum metal with a thickness of 100 nm; the gate dielectric layer 150 is made of aluminum oxide with a thickness of 20 nm; and the source electrode layer 170 and the drain electrode layer 180 are made of molybdenum with a thickness of 100 nm.

[0056] A method for fabricating a ferroelectric high-voltage ITO thin-film transistor based on the above, comprising the following steps:

[0057] Step 1: Obtain substrate 110;

[0058] Step 2: Form a bottom gate electrode 120 on the substrate 110;

[0059] Step 3: Form a ferroelectric thin film layer 130 on the bottom gate electrode 120 and the substrate 110;

[0060] Step 4: Form a gate electrode layer 140 on the ferroelectric thin film layer 130;

[0061] Step 5: Perform thermal annealing on the ferroelectric thin film layer 130;

[0062] Step 6: Form a gate dielectric layer 150 on the gate electrode layer 140 and the ferroelectric thin film layer 130;

[0063] Step 7: Form an ITO active layer 160 on the gate dielectric layer 150;

[0064] Step 8: A source electrode layer 170 is formed on the left side above the ITO active layer 160, and a drain electrode layer 180 is formed on the right side above the ITO active layer 160.

[0065] As a further preferred embodiment, magnetron sputtering is used to form the bottom gate electrode 120, the gate electrode layer 140, the ITO active layer 160, the source electrode layer 170, and the drain electrode layer 180.

[0066] As a further preferred embodiment, the ferroelectric thin film layer 130 and the gate dielectric layer 150 are formed using the ALD process.

[0067] As a further preferred embodiment, the temperature of the hot annealing in step five is 400-600℃.

[0068] The specific implementation method is as follows:

[0069] Example 1

[0070] The structure of the ferroelectric high-voltage ITO thin-film transistor in this embodiment is shown in Figure 1, including a substrate 110, a bottom gate electrode 120, a ferroelectric thin film layer 130, a gate electrode layer 140, a gate dielectric layer 150, an ITO active layer 160, a source electrode layer 170, and a drain electrode layer 180 arranged sequentially.

[0071] The bottom gate electrode 120 is disposed in the middle of the upper surface of the substrate 110. In this embodiment, the length of the bottom gate electrode 120 is 24 μm, denoted as L. BG =24μm;

[0072] The ferroelectric thin film layer 130 covers the bottom gate electrode 120 and the substrate 110;

[0073] The gate electrode layer 140 is disposed on the upper surface of the ferroelectric thin film layer 130, and in the horizontal direction, there is an overlap region between the gate electrode layer 140 and the bottom gate electrode 120, the length of which is 5 μm.

[0074] The gate dielectric layer 150 covers the gate electrode layer 140 and the ferroelectric thin film layer 130;

[0075] The ITO active layer 160 is disposed on the upper surface of the gate dielectric layer 150;

[0076] The source electrode layer 170 is disposed on the left side of the upper surface of the ITO active layer 160, and the drain electrode layer 180 is disposed on the right side of the upper surface of the ITO active layer 160. In the horizontal direction, there is a 5 μm overlap between the source electrode layer 170 and the gate electrode layer 140, and there is a non-overlapping region between the drain electrode layer 180 and the gate electrode layer 140. The length of the non-overlapping region is 28 μm. A carrier drift region is formed in the ITO active layer 160. In the horizontal direction, there is a 4 μm non-overlapping region between the drain electrode layer 180 and the bottom gate electrode 120.

[0077] Based on the above-mentioned method for fabricating a ferroelectric high-voltage ITO thin-film transistor, as shown in Figure 2, the steps are as follows:

[0078] S10. Obtain substrate 110. Substrate 110 can be a rigid substrate or a flexible substrate known in the art. In this embodiment, the substrate is a silicon oxide semiconductor substrate (or a silicon semiconductor substrate). The substrate is ultrasonically cleaned for five minutes at a power of 100W in the order of deionized water, acetone, anhydrous ethanol, and deionized water to obtain a substrate for subsequent operations.

[0079] S20. A bottom gate electrode 120 is formed on the substrate 110, specifically as follows: A patterned photoresist is obtained by performing spin coating, photolithography, drying, exposure, and development on the substrate surface described in S10. Any residual photoresist in the patterned area is removed using a photoresist stripper. A molybdenum metal layer is formed on the substrate (where the patterned photoresist is present) using magnetron sputtering. A lift-off process is then used to obtain the patterned gate electrode layer. Other materials / structures known in the art can also be used as the gate electrode layer. In this embodiment, the thickness of the prepared bottom gate electrode 120 is 100 nm.

[0080] S30. A ferroelectric thin film layer 130 is formed on the bottom gate electrode 120. A 12nm thick HfZrO is deposited on the bottom gate electrode 120 and the substrate 110 in S20 by an ALD process as the ferroelectric thin film layer 130.

[0081] S40. A gate electrode layer 140 is formed on the ferroelectric thin film layer 130. A 100nm thick molybdenum metal layer is formed above the ferroelectric thin film layer 130 described in S30 using a magnetron sputtering process. The gate electrode is obtained using a lift-off process, and the horizontal dimension of the gate electrode is 15μm.

[0082] S50. The ferroelectric thin film layer 130 is thermally annealed as follows: the structure formed by S40 is annealed for 3 hours in a N2 environment at 400℃ with an oxygen content of 0.003271% (volume fraction), a heating rate of 10℃ / s, and a holding time of 30s-60s to improve the ferroelectricity of HfZrO and increase the efficiency of the tetragonal to orthorhombic phase transformation of the ferroelectric lattice.

[0083] S60, A gate dielectric layer 150 is formed on the gate electrode layer 140 and the ferroelectric thin film layer 130. The gate dielectric layer 150 is formed on the gate electrode layer 140 and the ferroelectric thin film layer 130 in S50 by ALD process. In this embodiment, the gate dielectric layer 150 is made of aluminum oxide and the thickness of the prepared aluminum oxide thin film is 20nm.

[0084] S70, an ITO active layer 160 is formed on the gate dielectric layer 150. The ITO active layer 160 is formed on the gate dielectric layer 150 in S60 by radio frequency magnetron sputtering. The reaction conditions in this embodiment are as follows: sputtering pressure 0.4 Pa, volume ratio of Ar to O2 45:5, sputtering power 60 W, sputtering time 1000 s, and the thickness of the prepared ITO film is about 6 nm. Afterwards, it is annealed at 200 °C for 30 minutes under air conditions to improve the interface characteristics.

[0085] S80: A source electrode layer 170 is formed on the left side above the ITO active layer 160, and a drain electrode layer 180 is formed on the right side above the ITO active layer 160. In this embodiment, 100nm of metallic molybdenum is sputtered onto the surface of the ITO active layer 160 in S70. Through spin coating, photolithography, drying, exposure, and development, a patterned photoresist is obtained on the ITO surface. After etching the molybdenum metal, a lift-off process is performed to obtain the source and drain electrodes of the device. In this embodiment, the lengths of the source electrode layer 170 and the drain electrode layer 180 are 30μm, and the channel length between the source electrode layer 170 and the drain electrode layer 180 is 38μm. In other embodiments, other materials known in the art can also be used as the source / drain materials. Thus, the ferroelectric high-voltage ITO thin-film transistor has been fabricated.

[0086] Example 2

[0087] Similar to Embodiment 1, except that the length of the bottom gate electrode 120 in this embodiment is 18 μm, denoted as L. BG =18μm.

[0088] Example 3

[0089] Similar to Embodiment 1, except that the length of the bottom gate electrode 120 in this embodiment is 14 μm, denoted as L. BG =14μm.

[0090] Example 4

[0091] Similar to Embodiment 1, except that the length of the bottom gate electrode 120 in this embodiment is 10 μm, denoted as L. BG =10μm.

[0092] Example 5

[0093] Similar to Embodiment 1, except that the length of the bottom gate electrode 120 in this embodiment is 8 μm, denoted as L. BG =8μm.

[0094] Comparative Example 1

[0095] Similar to Example 1, the difference is that this comparative example does not have a bottom gate electrode and a ferroelectric thin film layer, but only a conventional TFT high voltage device. The structural schematic diagram is shown in Figure 3, which includes a conventional TFT high voltage device substrate 210, a conventional TFT high voltage device gate electrode layer 220, a conventional TFT high voltage device gate dielectric layer 230, a conventional TFT high voltage device ITO active layer 240, a conventional TFT high voltage device source electrode layer 250, and a conventional TFT high voltage device drain electrode layer 252. The labels in the figure are to distinguish them from the devices in the examples. The parameters of the same structure in this comparative example are consistent with those in the examples.

[0096] Comparative Example 2

[0097] Similar to Example 1, except that a bottom gate electrode 120 is not added. The polarization of the ferroelectric thin film is mainly controlled by the gate electrode layer 140. The ferroelectric thin film layer 130 is in direct contact with the substrate 110. The polarization retention phenomenon will be affected by various defects, reducing the ferroelectricity of the HZO layer.

[0098] Comparative Example 3

[0099] Similar to Embodiment 1, the difference lies in the overlap between the bottom gate electrode 120 and the drain electrode layer 180. Testing revealed that gate oxide breakdown is prone to occur at the drain end of the device.

[0100] Application examples

[0101] Performance tests were conducted on the devices prepared in Examples 1-5 and Comparative Example 1: First, a pulse voltage (pulse amplitude ±10V, pulse width 20ms) was applied to the bottom gate electrode in Examples 1-5, while the drain electrode (drain electrode layer 180) was grounded, so that the HfZrO ferroelectric thin film layer reached a polarized state under the action of the electric field; after the pulse ended, the remaining polarized charge could be retained in the ferroelectric thin film layer; subsequently, the bottom gate electrode was kept in a floating state, the source electrode (source electrode layer 170) in the examples and comparative examples was grounded, a fixed small voltage was applied to the gate electrode (gate electrode layer 140), and a scanning voltage was applied to the drain electrode (drain electrode layer 180) to obtain the output current curve of the device (drain voltage 0V scanned to 6V, step size 0.1V. Small voltages were applied to the gate electrode at 0V, 0.2V, 0.4V, 0.6V, 0.8V, 1V). The output characteristics of the devices were compared, as shown in Figure 4. The output current of the devices in the examples was higher than that of the comparative example; and the output current of the device increased significantly with the increase of the length of the bottom gate electrode. Therefore, different output characteristics can be obtained by designing bottom gate electrodes of different lengths, thereby achieving control over the device's on-resistance. Figure 5 shows the output current of the device after applying different pulse voltages to the bottom gate electrode. The effects exhibited by different embodiments are consistent. Taking Embodiment 2 as an example, the device output current is larger after applying a positive pulse voltage to the bottom gate electrode, and smaller after applying a negative pulse voltage, corresponding to different conduction states of the device. When testing the breakdown characteristics of the device, other electrodes were kept grounded, and a scanning voltage was applied to the drain electrode. The results are shown in Figure 6. Comparing devices with different bottom gate electrode lengths, the device breakdown voltage can reach approximately 140V, while the breakdown voltage of conventional high-voltage TFT devices is approximately 160V. The breakdown characteristics of the device in this embodiment are not significantly different from the withstand voltage characteristics of the comparative conventional high-voltage TFT devices. In summary, the embodiments of this invention realize a high-voltage ITO thin-film transistor with good withstand voltage characteristics and adjustable on-resistance.

Claims

1. A ferroelectric high-voltage ITO thin-film transistor, characterized in that, The ferroelectric high-voltage ITO thin-film transistor includes a substrate (110), a bottom gate electrode (120), a ferroelectric thin film layer (130), a gate electrode layer (140), a gate dielectric layer (150), an ITO active layer (160), a source electrode layer (170), and a drain electrode layer (180). The bottom gate electrode (120) is located in the middle of the upper surface of the substrate (110). The length of the bottom gate electrode (120) is based on the design range. The longer the bottom gate length, the stronger the current output capability of the corresponding device and the smaller the on-resistance. The ferroelectric thin film layer (130) covers the bottom gate electrode (120) and the substrate (110); The gate electrode layer (140) is disposed on the upper surface of the ferroelectric thin film layer (130), and there is an overlap area between the gate electrode layer (140) and the bottom gate electrode (120) in the horizontal direction; The gate dielectric layer (150) covers the gate electrode layer (140) and the ferroelectric thin film layer (130); The ITO active layer (160) is disposed on the upper surface of the gate dielectric layer (150); The source electrode layer (170) is disposed on the left side of the upper surface of the ITO active layer (160), and the drain electrode layer (180) is disposed on the right side of the upper surface of the ITO active layer (160). Furthermore, in the horizontal direction, there is an overlap region between the source electrode layer (170) and the gate electrode layer (140), and there is a non-overlap region between the drain electrode layer (180) and the gate electrode layer (140). A carrier drift region is formed in the ITO active layer (160), and in the horizontal direction, there is also a non-overlap region between the drain electrode layer (180) and the bottom gate electrode (120).

2. The ferroelectric high-voltage ITO thin-film transistor according to claim 1, characterized in that, The length range of the bottom gate electrode (120) is as follows: the left end extends to be flush with the gate electrode layer (140) and the right end extends to maintain a non-overlapping region with a length of at least 2 μm with the drain electrode layer (180).

3. The ferroelectric high-voltage ITO thin-film transistor according to claim 1, characterized in that, In the horizontal direction, the distance between the source electrode layer (170) and the drain electrode layer (180) is 18-60 μm, and the length of the non-overlapping region between the drain electrode layer (180) and the gate electrode layer (140) is 8-50 μm.

4. The ferroelectric high-voltage ITO thin-film transistor according to claim 1, characterized in that, In the horizontal direction, the length of the overlapping region between the bottom gate electrode (120) and the gate electrode layer (140) is 5-15 μm, and the length of the non-overlapping region between the bottom gate electrode (120) and the drain electrode layer (180) is 4-20 μm.

5. A ferroelectric high-voltage ITO thin-film transistor according to claim 1, characterized in that, The ferroelectric thin film layer (130) is made of HfZrO material with a thickness of 10-20 nm; the ITO active layer (160) is made of ITO material with a thickness of 4-10 nm.

6. A ferroelectric high-voltage ITO thin-film transistor according to claim 1, characterized in that, The bottom gate electrode (120) is made of molybdenum metal with a thickness of 50-120 nm; the gate electrode layer (140) is made of molybdenum metal with a thickness of 50-120 nm; the gate dielectric layer (150) is made of aluminum oxide with a thickness of 10-30 nm; and the source electrode layer (170) and drain electrode layer (180) are made of molybdenum with a thickness of 50-120 nm.

7. A method for fabricating a ferroelectric high-voltage ITO thin-film transistor according to claim 1, characterized in that, The steps are as follows: Step 1: Obtain the substrate (110); Step 2: Form a bottom gate electrode (120) on the substrate (110); Step 3: Form a ferroelectric thin film layer (130) on the bottom gate electrode (120) and the substrate (110); Step 4: Form a gate electrode layer (140) on the ferroelectric thin film layer (130); Step 5: Perform thermal annealing on the ferroelectric thin film layer (130); Step 6: Form a gate dielectric layer (150) on the gate electrode layer (140) and the ferroelectric thin film layer (130); Step 7: Form an ITO active layer (160) on the gate dielectric layer (150); Step 8: A source electrode layer (170) is formed on the left side above the ITO active layer (160), and a drain electrode layer (180) is formed on the right side above the ITO active layer (160).

8. The method for fabricating a ferroelectric high-voltage ITO thin-film transistor according to claim 7, characterized in that, When forming the bottom gate electrode (120), gate electrode layer (140), ITO active layer (160), source electrode layer (170) and drain electrode layer (180), magnetron sputtering process is used.

9. The method for fabricating a ferroelectric high-voltage ITO thin-film transistor according to claim 7, characterized in that, The ferroelectric thin film layer (130) and the gate dielectric layer (150) are formed using the ALD process.

10. The method for fabricating a ferroelectric high-voltage ITO thin-film transistor according to claim 7, characterized in that, The temperature for hot annealing in step five is 400-600℃.

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