Storage management method and apparatus, memory, device, storage medium, and product

Abstract

The present disclosure relates to the technical field of storage, and in particular, provides a storage management method and apparatus, a memory, an electronic device, a computer-readable storage medium, and a computer program product. In the present disclosure, when data of a first space block in a storage space needs to be modified, instead of performing whole-page erasure at an original space block address, a second space block is reallocated in an unallocated space, and modified data is written into the second space block; meanwhile, in a mapping table entry area, a second entry corresponding to the second space block is newly added, and an entry state of a first entry corresponding to the first space block is adjusted to invalid. The technical solution provided by the present disclosure can, to a certain extent, prolong the service life of a memory and a chip, and is simple, convenient, and efficient.

Description

Storage management methods and apparatus, memory, devices, storage media and products

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Chinese Patent Application No. 202510469693.7, filed on April 15, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of storage technology, and in particular to a storage management method and apparatus, memory, electronic device, computer-readable storage medium and computer program product. Background Technology

[0004] In related technologies, the data stored in the chip may need to be modified. Modifying a single piece of data may require erasing the entire page, which accelerates chip wear. For ease of understanding, let's take a smart card as an example. Smart cards, as a carrier for authentication and payment, are widely used in many industry scenarios. A smart card internally contains a small microcontroller unit (MCU) chip and runs a chip operating system (COS). Multiple applications can run on top of this operating system, each designed for a specific application scenario to implement the authentication and payment functions for that scenario.

[0005] Specifically, data on the card is typically stored in small amounts in the card's non-volatile flash memory (NORFLASH). In related technologies, modifying data stored at a specific address in the NORFLASH requires erasing the entire page containing that address before writing a new full page of data. This storage management mechanism necessitates frequent physical page erasures, which accelerates chip wear and reduces the smart card's lifespan. Furthermore, this full-page erasure management mechanism is too time-consuming and inefficient when dealing with small-sized data modifications. Summary of the Invention

[0006] This disclosure is made in view of the above-mentioned problems. This disclosure provides a storage management method and apparatus, a memory, an electronic device, a computer-readable storage medium, and a computer program product.

[0007] According to one aspect of this disclosure, a storage management method is provided, comprising:

[0008] When it is necessary to modify the data in the first space block, allocate a second space block in the unallocated space and write the modified data.

[0009] In the mapping table area, add a second entry corresponding to the second space block;

[0010] Adjust the entry status of the first entry corresponding to the first space block to invalid.

[0011] According to another aspect of this disclosure, a storage management apparatus is provided, comprising:

[0012] The first management unit is used to allocate a second space block in the unallocated space and write the modified data when it is necessary to modify the data in the first space block;

[0013] The second management unit is used to add a second entry corresponding to the second space block in the mapping table entry area;

[0014] The second management unit is further configured to adjust the entry status of the first entry corresponding to the first space block to invalid.

[0015] According to another aspect of this disclosure, a memory is provided, comprising:

[0016] Storage space, which provides: a mapping table entry area, unallocated space, and allocated space;

[0017] A storage management device for implementing the method described in any of the above embodiments.

[0018] According to another aspect of this disclosure, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the method described in any of the above embodiments.

[0019] According to another aspect of this disclosure, a computer-readable storage medium is provided that stores a computer program or instructions thereon, which, when executed by a processor, implement the methods described in any of the above embodiments.

[0020] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the methods described in any of the above embodiments. Attached Figure Description

[0021] The above and other objects, features, and advantages of this disclosure will become more apparent from the more detailed description of the embodiments thereof in conjunction with the accompanying drawings. The drawings are provided to offer a further understanding of the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0022] Figure 1 is a schematic flowchart of a storage management method provided in an embodiment of this disclosure.

[0023] Figure 2 is a schematic diagram of the structure of a storage space provided in an embodiment of this disclosure.

[0024] Figure 3 is a schematic diagram of a mapping table entry in an embodiment of the present invention.

[0025] Figure 4 is a structural comparison diagram of the related technologies and the mapping entries provided in this disclosure.

[0026] Figure 5 is a schematic diagram of the structure of a first linked list provided in an embodiment of this disclosure.

[0027] Figure 6 is a schematic diagram of another implementation scheme of the storage management method provided in the embodiments of this disclosure.

[0028] Figure 7 is a schematic diagram of the structure of a mapping space provided in an embodiment of this disclosure.

[0029] Figure 8 is a schematic diagram of a defragmentation implementation scheme provided by an embodiment of this disclosure.

[0030] Figure 9 is a schematic diagram of a fragmentation scheme provided in an embodiment of this disclosure.

[0031] Figure 10 is a schematic diagram of the update method of the mapping table entry area during the defragmentation process in an embodiment of this disclosure.

[0032] Figure 11 is a schematic diagram of another fragmentation scheme provided by an embodiment of this disclosure.

[0033] Figure 12 is a structural block diagram of a storage management device provided in an embodiment of this disclosure.

[0034] Figure 13 is a structural block diagram of a memory provided in an embodiment of this disclosure.

[0035] Figure 14 is a hardware block diagram of an electronic device provided in an embodiment of this disclosure.

[0036] Figure 15 is a schematic diagram of a computer-readable storage medium provided in an embodiment of this disclosure. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this disclosure more apparent, exemplary embodiments according to this disclosure will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments of this disclosure. It should be understood that this disclosure is not limited to the exemplary embodiments described herein.

[0038] This disclosure provides a storage management scheme that can be applied to the management of any stored data. Furthermore, this disclosure can be applied to any storage scenario involving non-volatile flash memory (NORFLASH) technology. In some embodiments, a storage scenario involving NORFLASH technology refers to any scenario where data is read and written using NORFLASH read / write methods, which may include, but is not limited to, the smart card storage scenario described in the background section.

[0039] Furthermore, NORFLASH storage can be applied to various application areas, such as wearable devices, artificial intelligence, connected vehicles, smart home appliances, smart terminals, routers, motherboards, base stations, etc. This disclosure does not impose any particular limitations on these applications, nor will it exhaustively list them all.

[0040] The characteristic of NORFLASH storage is that information is stored in the NORFLASH space in the form of small data (usually less than 100 bytes). When it is necessary to modify the stored data at a specific address in the NORFLASH space, the entire page at that address must be erased first, and then a new full page of data must be rewritten.

[0041] In practical scenarios, for ease of implementation, the memory processing system (such as the COS system of a smart card) typically encapsulates the read and write functions of NORFLASH into a specific NVM (Node Version Manager) management interface for developers of card applications to call. In this way, the NVM management interface can treat the available space (also referred to as storable space) in the NORFLASH storage space as heap space (NVM HEAP). The system side manages the data in the NORFLASH space through the NVM management interface, including storing data, modifying data, and deleting data.

[0042] To address the memory wear and efficiency issues associated with data storage using full-page erase in related technologies, this disclosure offers a novel design concept: when data modification is required, instead of performing a full-page erase and write-back, a new space block is allocated. Simultaneously, a mapping table entry is created for the newly allocated space block, and the original space block and its original mapping table entry are invalidated. Thus, the NORFLASH memory space contains only one modified, valid space block. Based on this, a series of operations involving full-page copying, modification, erasure, and write-back can be avoided. This not only improves data modification efficiency but also minimizes chip wear and tear, and to some extent extends the memory's lifespan compared to the full-page erase and write-back schemes in related technologies.

[0043] This disclosure provides a storage management method. Please refer to Figure 1, which is a flowchart illustrating a storage management method according to an embodiment of this disclosure. As shown in Figure 1, the method includes:

[0044] S102, when it is necessary to modify the data in the first space block, allocate the second space block in the unallocated space and write the modified data.

[0045] In this disclosure, the first space block can be any allocated space block in the storage space. This disclosure does not impose any particular restrictions on the data content and type stored in the first space block; it can be customized based on the actual scenario. For example, the first space block can be used to store any one or more types of data from one or more scenarios such as wearable devices, artificial intelligence, connected vehicles, smart home appliances, smart terminals, routers, motherboards, and base stations.

[0046] Furthermore, this disclosure does not impose any particular restrictions on the timing of modifying the data in the first space block. For example, it may be a data modification request initiated by an upper-layer application, a data modification instruction sent by a user, or a modification instruction on the data in the storage space initiated by other systems or devices.

[0047] Furthermore, regarding the storage space where the first space block resides, refer to Figure 2. This storage space can be stored on a chip or other form of hardware to implement non-volatile memory. The storage space includes a mapping table area and a storable area. The storable area can be divided into two regions based on whether it has been allocated: unallocated space and allocated space. Based on this, the first space block involved in this step can be any space block in the allocated space. Correspondingly, the second space block is a newly allocated space block in the unallocated space. After processing according to this scheme, the second space block also becomes part of the allocated space. In other words, as the amount of stored data increases, the allocated space in the storable area gradually increases, while the unallocated space gradually decreases. In practical scenarios, space blocks in the allocated space can be reclaimed. After reclamation, the space blocks are erased again, and data can be stored again. This will be explained in conjunction with the defragmentation section later.

[0048] Please refer to Figure 2, which is a schematic diagram of the structure of a storage space provided in an embodiment of this disclosure. As shown in Figure 2, the storage space in this disclosure can be a NORFLASH space, and the available space in the NORFLASH space is the heap space. The heap space consists of the following layers from low address to high address: mapping table entry area, unallocated space, and allocated space. Unallocated space refers to space where no data has been stored yet, while allocated space refers to space where data has already been stored. Together, they constitute the allocatable area.

[0049] As shown in Figure 2, the mapping table entry area maintains at least one mapping table entry, and the allocated space also maintains at least one space block. One mapping table entry corresponds to one space block. The mapping table entry is used to maintain relevant information about the space block, which will be detailed later. Furthermore, as shown in Figure 2, the mapping table entry area adds entries and maintains data from low address to high address (top to bottom in Figure 2), while the allocatable area adds allocated space blocks and maintains data from high address to low address (bottom to top in Figure 2). Thus, as the amount of stored data increases, the allocated space in the storable area gradually increases, while the unallocated space gradually decreases.

[0050] In one exemplary embodiment, the second space block can be partitioned at the high address of the unallocated space, and the modified data can be written into the second space block.

[0051] In practical implementation scenarios, a space of the same size as the first space block can be allocated starting from the high address of the unallocated space as the second space block. In other words, the second space block is the same size as the first space block; and / or, the low address of the unallocated space is adjacent to the mapping table entry area, and the high address of the unallocated space is adjacent to the allocated space.

[0052] Furthermore, in some implementations, if only a portion of the data in the first space block is modified, the second space block may also include the unmodified data; if all the data in the first space block is modified, the second space block may contain only the modified data.

[0053] Furthermore, as shown in Figure 2, the low address of the unallocated space is adjacent to the mapping table entry area, and the high address of the unallocated space is adjacent to the allocated space.

[0054] Therefore, by reallocating space blocks and writing data, the need for full-page erasure and write-back is eliminated. Furthermore, as mentioned earlier, in scenarios where storage space is only requested from the storage area to write data, full-page erasure is unnecessary; the allocation and writing process can be directly implemented through the NVM management interface.

[0055] Furthermore, as mentioned above, the mapping entries maintained in the mapping entry area correspond one-to-one with the space blocks in the allocated space. Therefore, in addition to allocating a new second space block, it is also necessary to establish a mapping entry corresponding to the second space block in the mapping entry area, which is referred to as the second entry in this scheme, as described in S104.

[0056] S104, In the mapping table entry area, add a second entry corresponding to the second space block.

[0057] In this disclosure, the mapping entry area is used to maintain the attribute information of allocated spatial blocks. In some implementations, the mapping entry area includes at least one mapping entry. That is, any mapping entry corresponds to a spatial block and is used to characterize the attribute information of that spatial block.

[0058] When performing this step, it is only necessary to assemble the relevant attribute information of the space block into a mapping table entry and write it to the mapping table entry area. Similar to allocating a new space block and writing data as described above, adding a new mapping table entry in the mapping table entry area does not require a full page erase and write-back operation of the mapping table entry area, which is highly efficient and causes almost no wear and tear on the chip.

[0059] In practical implementations, the correspondence between spatial blocks and mapping table entries is typically achieved through the index numbers of the spatial blocks. For example, the first spatial block shares the same index number as the first entry, and the second spatial block shares the same index number as the second entry. The strategy adopted in this disclosure is to replace the first spatial block with the second spatial block. Therefore, in this scenario, the first and second spatial blocks share the same index number; in other words, the index numbers of the first entry, the second entry, the first spatial block, and the second spatial block are all the same. Besides this, this disclosure can also use other methods or field information to correspond spatial blocks to mapping table entries, such as the same attribute information or the same distinguishing identifier, etc., to name a few.

[0060] S106, adjust the entry status of the first entry corresponding to the first space block to invalid.

[0061] In this disclosure, the first entry is the mapping table entry corresponding to the first spatial block in the mapping table entry area, used to characterize the attribute information of the first spatial block; the second entry mentioned above is the mapping table entry corresponding to the second spatial block in the mapping table entry area, used to characterize the attribute information of the second spatial block. It should be understood that in the embodiments of this disclosure, both the first entry and the second entry are mapping table entries in the mapping table entry area. In other words, the mapping table entries in the embodiments of this disclosure include: the first entry and the second entry.

[0062] In this disclosure, the status information of mapping table entries is used to indicate the status of corresponding spatial blocks. For example, for any mapping table entry, when the entry status is invalid (or: invalidated), the spatial block corresponding to the mapping table entry is in an invalid state, which can further be used to indicate that the data stored in the spatial block has also been invalidated. Similarly, when the entry status of the mapping table entry is released, it indicates that the spatial block corresponding to the mapping table entry is in a released state, and there is no data in the spatial block or the data in the spatial block has been released. Furthermore, when the entry status of the mapping table entry is valid, it indicates that the spatial block corresponding to the mapping table entry is also in a valid state, and the data stored in the spatial block is also valid data.

[0063] In order to indicate the status of mapping table entries, this disclosure adds a status field on top of the information content maintained by the mapping table entries in related technologies, so as to characterize the status information of the mapping table entries through the status field.

[0064] Based on this, in one exemplary embodiment, any of the mapping table entries includes at least a status field.

[0065] It should be understood that in real-world scenarios, mapping table entries can include more fields or carry more information. For example, a mapping table entry may also include at least one of the following: a validation field, an index field, a starting address field, a space block size field, etc., which will not be listed exhaustively but will be explained later.

[0066] The status field is used to characterize the entry status of the mapping table entry, and can also indicate the status of the space block corresponding to the mapping table entry. The status field can be modified by writing specific status bits to it using a write-back method; therefore, the status field can also be called a write-back status segment. For example, when creating a new mapping table entry, the write-back status segment can be empty or have only a small amount of data written, indicating that the mapping table entry is valid. When it is necessary to modify the entry status of the mapping table entry, (more) data can be written to this status field to represent different states in different data formats. That is, the entry status of the mapping table entry is modified using a write-back method.

[0067] In one exemplary embodiment, the entry status involved in this disclosure may include, but is not limited to, at least one of the following: valid, invalid, or released. In some embodiments, for any of the mapping table entries, at least one of the following conditions must be met:

[0068] When the status field is the third status bit (which may include, but is not limited to, the status field being empty, and therefore in some embodiments it may also be expressed as: when the status field is empty), the entry status of the mapping table entry is valid; when the status field is the first status bit, the entry status of the mapping table entry is invalid; when the status field is the second status bit, the entry status of the mapping table entry is released.

[0069] The first, second, and third status bits can be customized in actual scenarios. For example, when the status field is empty, it can be represented as all 0xFF, such as 0000 (assuming 4 characters), which indicates that the mapping table entry is valid. When the status field is the first status bit (represented as 0xAA), such as 1000, 0100, or 1100 (not exhaustive), it indicates that the mapping table entry is invalid. When the status field is the second status bit (represented as 0xBB), such as 1111, 0111, or 1110 (not exhaustive), it indicates that the mapping table entry is released.

[0070] Therefore, when adjusting the status of the first entry in this step, it is only necessary to write the information corresponding to the invalidation status into the status field of the first entry. For example, changing 0000 (i.e., the third status bit mentioned above) in the status field to 1000 (i.e., the first status bit mentioned above) will modify the status of the first entry.

[0071] Based on this, the storage space maintains the obsolete first space block and first entry, and the currently valid second space block and second entry. Thus, when data corresponding to the index number of a space block is needed later, the data in the second space block can be accessed directly based on the second entry, without accessing the original, unmodified data in the first space block. The first space block and first entry can be reclaimed during the subsequent defragmentation phase for reuse in storing data, as explained later.

[0072] In summary, in this disclosure, when it is necessary to modify the data of a first space block in the storage space, instead of performing a full page erase at the original space block address, a second space block is reallocated in the unallocated space, and the modified data is written into the second space block. Simultaneously, a second entry corresponding to the second space block is added to the mapping table entry area, and the entry status of the first entry corresponding to the first space block is adjusted to invalid. Thus, when the data is needed subsequently, since the first entry is invalid, the second space block can be directly determined based on the second entry, and the modified and updated data stored in the second space block can be used. Therefore, the technical solution provided by this disclosure does not require modifying data at the original address, thus eliminating the need for full page erase and write operations on the physical page, reducing chip wear caused by frequent data erasure, and improving the lifespan of smart cards and other memory devices. Furthermore, the operation of this solution is simple and easy to implement, effectively reducing the time spent on data modification and improving modification efficiency. Especially in scenarios involving small-sized data modifications, this solution is simple, efficient, and has minimal impact on the lifespan of chips and smart cards. In summary, the technical solution provided in this disclosure can improve the lifespan of memory and chips to a certain extent, and is simple and efficient.

[0073] Furthermore, as mentioned above, in this disclosure, mapping table entries may also include more or fewer fields. For example, in practical implementation scenarios, the index number or starting address of the space block can also be represented in other ways, such as by a single field. As another example, in one exemplary embodiment, any mapping table entry may also include at least one of the following: a verification field, an index field, a starting address field, a space block size field, etc., which can be added or removed based on the actual scenario.

[0074] The index field is used to represent the spatial block index number corresponding to the mapping table entry. This disclosure does not restrict the representation method of the spatial block index number; it can be customized according to the actual scenario. As mentioned above, in actual scenarios, the index numbers of the first entry, the second entry, the first spatial block, and the second spatial block are all the same.

[0075] The starting address field is used to characterize the starting address of the space block corresponding to the mapping table entry.

[0076] The space block size field is used to characterize the size of the space block corresponding to the mapping table entry. In practical scenarios, the size of each space block in the allocated space can be unlimited, or they can be the same size; when the size of each space block is the same, the space block size field can be omitted in the mapping table entry.

[0077] The verification field can be used to verify the data integrity of the mapped table entries. The verification field may include one or more. For example, in one possible scenario, the verification field may include at least one of the following: a table entry flag field, a checksum.

[0078] For ease of understanding, please refer to Figure 3, which is a schematic diagram of a mapping table entry in an embodiment of the present invention. In the embodiment shown in Figure 3, the mapping table entry is expanded from the original 8 bytes to 16 bytes. Compared to the three fields included in mapping table entries in related technologies (for example, related technologies generally only include three fields: index field, space block size field, and start address field), the mapping table entry provided in this disclosure, in addition to these three fields, may also include: an entry flag field (2 bytes, represented as 2B), a checksum (2B), and a status field (4B). The entry flag field and checksum are used to verify the integrity of the entry data; while the status field is used to mark the entry status.

[0079] It should be understood that the embodiment shown in Figure 3 is only exemplary. In actual scenarios, the fields contained in the mapping table entries, the order between fields, and the field size (bytes occupied) can all be customized based on the actual scenario.

[0080] Furthermore, based on the aforementioned solution provided in this disclosure, data in the storage space can be modified without erasing the entire page of the storage space.

[0081] Therefore, in this disclosure, the data maintained in the mapping entry area and the storable area are no longer arranged in index number order. Taking the mapping entry area as an example, please refer to Figure 4, which is a comparison diagram of the structure of mapping entry entries provided in related technologies and this disclosure.

[0082] As shown in Figure 4, in related technologies, the entries in the mapping table area of ​​the Flash space are sequentially sorted and assigned values ​​according to the allocation order of the space blocks. In other words, in the mapping table area, starting from the low address and moving towards the high address, the index numbers of each mapping table entry are sequentially sorted. Furthermore, in related technologies, when data needs to be modified, not only is a full page erase and write-back performed on the allocable space, but this erase and write-back does not change the index number of the space block. In other words, once the index number of each mapping table entry in the mapping table area is assigned, it will not change in subsequent applications. Thus, the NVM management interface can directly obtain the address of the corresponding entry by multiplying the index number by the size of each entry, thereby achieving fast retrieval of the index number. After finding the mapping table entry, fast retrieval of data in the space block can also be achieved.

[0083] However, as shown in Figure 4, in the storage management scheme provided by this disclosure, when a space block is modified or released, the entry status of the corresponding mapping table entries will also change, causing some mapping table entries to be marked as invalid or released. This also means that the index numbers of the mapping table entries maintained by this disclosure are no longer arranged in ascending order. For example, as shown in Figure 4, when space block 2 is invalidated, the original mapping table entry 2 (index number 2) is marked as invalid, and the mapping table entry corresponding to the newly allocated space block 2' is valid as mapping table entry 2' (index number 2). At this time, mapping table entry 2' is located below mapping table entry 4, and the index numbers are no longer arranged in ascending order.

[0084] Based on the situation shown in Figure 4, when the application requests access to or queries data based on the index number (denoted as the target index number), it needs to traverse the mapping table entry area to find the mapping table entry corresponding to the target index number, thereby determining the starting address of the target space block and accessing or querying the data of the target space block accordingly.

[0085] To further improve the efficiency of querying the mapping table entry corresponding to the target index number, this disclosure introduces a first linked list based on the aforementioned scheme. In this embodiment, the method may further include the following steps:

[0086] In random access memory (RAM), the first linked list is dynamically maintained. Dynamic maintenance includes at least one of creation and dynamic updating.

[0087] The first linked list, also known as the allocated mapping list, is used to sequentially maintain the allocated valid mapping entries. In other words, the first linked list only maintains valid mapping entries in the mapping entry area, and these valid entries are maintained sequentially. In practical scenarios, the valid mapping entries in the first linked list can be arranged in ascending or descending order based on their index numbers. Furthermore, in practical scenarios, the space block index numbers of the mapping entries are arranged in ascending order based on the allocation of space blocks. Therefore, the first linked list can be a singly linked list arranged in ascending order based on the index numbers of the mapping entries.

[0088] Based on this, the first linked list may include at least one linked list entry, and any one of the linked list entries corresponds to an allocated valid mapping table entry. That is, any one linked list entry is used to represent the attribute information of a corresponding mapping table entry.

[0089] In some embodiments, any of the linked list entries includes at least an index field and a pointer field. The index field indicates the index number in the mapping table entry, which is also the index number of the space block corresponding to the mapping table entry. The pointer field indicates the next entry in the linked list.

[0090] Similar to the mapping table entry area described above, linked list entries may have more or fewer fields. For example, any of the linked list entries may also include, but is not limited to, at least one of the following: a space block size field and a starting address field. The space block size field and starting address field are consistent with the contents of the mapping table entries and will not be elaborated upon here.

[0091] In summary, in the embodiments of this disclosure, the first linked list meets at least one of the following criteria:

[0092] The first linked list is a singly linked list arranged in ascending order based on the index number of the mapping table entries;

[0093] The first linked list includes at least one linked list entry, and any one of the linked list entries corresponds to an allocated valid mapping table entry;

[0094] Each of the linked list entries includes at least: an index field and a pointer field, wherein the pointer field is used to indicate the next entry of the linked list entry;

[0095] Each of the linked list entries further includes at least one of the following: a space block size field and a starting address field.

[0096] At this point, please refer to Figure 5, which is a schematic diagram of the structure of a first linked list provided in an embodiment of this disclosure. As shown in Figure 5, the storage management device can traverse all mapping table entries in the mapping table entry area of ​​the storage space, extract the valid data from them to form a linked list entry, and then chain these linked list entries with valid data together into a singly linked list through the NEXT pointer (i.e., the previous pointer field). Valid data refers to the information in valid mapping table entries (i.e., mapping table entries that have not been marked as invalid or released). This information can also be customized. In the embodiment shown in Figure 5, the valid information includes: the index number of the valid mapping table entry, the size of the space block, and the starting address of the space block. It should be understood that this is only an example; in actual scenarios, there may be more or less information, which will not be elaborated further. Based on these processes, as shown in Figure 5, a singly linked list sorted in ascending order of index number can be maintained on the RAM side.

[0097] Furthermore, in this disclosure, the first linked list is maintained on the RAM side rather than in the Flash storage space. This makes the maintenance and storage of the first linked list more flexible, without being limited by storage schemes such as full-page erase and write-back in the Flash storage space. Subsequently, it is also possible to quickly query the starting address of the space block corresponding to the target index number based on the first linked list stored on the RAM side. In this way, it is not necessary to traverse the mapping table entry area. In other words, the query time spent traversing the mapping table entry area is saved. Information such as the starting address and size of the space block corresponding to a target index number can be quickly and conveniently queried directly through the first linked list on the RAM side.

[0098] In this way, the first linked list enables fast retrieval of valid mapping table entries, so that when it is necessary to access the data of the target space block corresponding to a certain target index number, the relevant information of the target space block can be quickly retrieved.

[0099] In one exemplary embodiment, the storage management method may further include: when data of a target index number needs to be accessed, determining the starting address field corresponding to the target index number based on the first linked list; and accessing the data of the target space block corresponding to the target index number based on the starting address field. In this embodiment, it is unnecessary to traverse the mapping table area in the Flash storage space. The starting address of the target space block corresponding to the target index number can be quickly determined directly based on the more flexible and easily queryable first linked list. Thus, the information can be accessed directly from the allocated area based on the first linked list. Compared to the implementation scheme of traversing the mapping table area to determine the starting address of the target space block, the query method using the first linked list is more convenient and faster, effectively improving query efficiency, data access efficiency, and response efficiency to the application side, thereby improving the storage management effect.

[0100] Furthermore, it should be noted that, in order to ensure the accuracy of the first linked list, in actual implementation scenarios, regardless of any processing performed on the Flash storage space, or when operations other than simple queries, such as modification, invalidation, or release, are performed on the Flash storage space that have a real impact on the storage structure, in addition to updating the data in the mapping table entry area as shown in Figure 1, it is also necessary to update the data in the first linked list to ensure that the data in the first linked list is consistent with the valid data in the mapping table entry area, that is, to ensure that the first linked list can accurately represent the information of the space block corresponding to the index number.

[0101] In one exemplary embodiment, the storage management method may further include: when it is necessary to release the target space block corresponding to the target index number, adjusting the entry status of the mapping table entry corresponding to the target space block to release; and deleting the linked list entry corresponding to the target space block from the first linked list.

[0102] In another exemplary embodiment, the storage management method may further include: when it is necessary to invalidate the target space block corresponding to the target index number, adjusting the entry status of the mapping table entry corresponding to the target space block to invalid, as shown in S104 of Figure 1 above. In addition, it is also necessary to delete the linked list entry corresponding to the target space block from the first linked list. Further examples are omitted.

[0103] In a further possible embodiment, this disclosure may further dynamically maintain at least one of the following information in RAM: a maximum index number and an allocable space address. The maximum index number refers to the index number of a valid space block already allocated in the current Flash storage space, while the allocable space address can be the address of the byte preceding the lower address of the allocated space, i.e., the first byte address of the higher address of the unallocated space. Based on the maximum index number and the allocable space address, the RAM side can directly determine the starting address and index number of a newly allocated space block. For example, if the maximum index number maintained in RAM is 5 and the allocable space address is byte address A, then when the process shown in Figure 1 occurs or other scenarios requiring the allocation of a new space block occur, the storage management device can directly determine the starting address of the newly allocated space block as byte address A, and the index number of the newly allocated space block as 5+1, i.e., 6, based on these two data points. In this process, it is unnecessary to traverse the mapping table entry area in the Flash storage space, improving the maintenance efficiency of the first linked list.

[0104] In other words, in this embodiment, during the entire power-on cycle, the first linked list (i.e., the allocated mapping list), the maximum index number, and the allocatable space address on the RAM side are updated synchronously according to the allocation, modification, and release operations of space blocks, and the first linked list is always arranged in ascending order of index number to ensure the efficiency of adding, querying, and deleting subsequent mapping list entries.

[0105] In summary, this disclosure provides a storage management scheme that can improve the efficiency of data modification in Flash storage space and minimize the wear and tear on memory chips. For ease of understanding, this disclosure further provides a possible embodiment.

[0106] Please refer to Figure 6, which is a schematic diagram of another storage management method implementation scheme provided in this embodiment of the present disclosure. As shown in Figure 6, when the NVM management interface needs to allocate a new space block, it will allocate a new space block N from the high address of the unallocated space (this space block can be initialized with all zeros or kept in an unwritten state of all 0xFF). At the same time, a new mapping table entry K is added to the end of the mapping table entry area. This entry contains the index number I of the space block allocated this time, the starting address and size of the space block N, the magic number and checksum, and a write-after status field. This status field maintains an unwritten state of 0xFFFFFFFF, marking the mapping entry as a valid mapping entry.

[0107] Furthermore, in the first linked list (i.e., the mapping chain list) maintained on the RAM side, a new linked list entry L corresponding to the mapping list entry K is also added; in addition, the maximum index number and the allocatable space address are updated in RAM. Thus, in subsequent operations, the starting address of space block N can be found in the mapping chain list by the target index number, such as index number I, and the data content of space block N can be read.

[0108] Based on this, when the NVM management interface needs to write a new value to the space block corresponding to index number I, that is, when it needs to modify the data stored in space block N, it does not directly perform a full page erase on the physical page where space block N is located. Instead, it reallocates a space block N' of the same size from the unallocated space and directly writes the new value (i.e., modifies the data) into space block N'. At the same time, it writes the write-back status segment (i.e., the status field mentioned above) of the original mapping table entry K (i.e., the first entry mentioned above) pointing to space block N to 0xAAAAAAAA. This status field can be used to indicate that the mapping table entry K has been invalidated. In addition, the NVM management interface also adds a new mapping table entry K' to the end of the mapping table entry area. This entry points to space block N'. It should be understood that the mapping table entry K' is in a valid state, and its status field maintains an unwritten state of 0xFFFFFFFF, indicating that the mapping entry is a valid mapping entry.

[0109] Furthermore, the new mapping relationship between mapping table entry K' and space block N' is also updated in the mapping necklace table on the RAM side (i.e., the first linked list mentioned above). Additionally, the RAM side maintains a maximum index number and an allocable space address; in this case, the maximum index number does not need to be updated, only the allocable space address needs to be updated. Subsequently, the starting address of the queried space block N' can be retrieved in the mapping necklace table using index number I, and the data content of space block N' can be read.

[0110] Furthermore, if the NVM management interface needs to release the space block N' corresponding to index number I, it can write 0xBBBBBBBB to the write-back status segment of the mapping table entry K', indicating that the mapping entry has been released. This also indicates that the space block N' corresponding to index number I is also in a released state. Moreover, since the mapping chain table maintained on the RAM side only involves valid mapping table entries, when it is modified to a released state, the chain entry corresponding to mapping table entry K' can also be deleted from the mapping chain table maintained on the RAM side. Thus, in subsequent use, if the NVM management interface uses index number I as the target index number for querying, it will no longer be able to find the relevant information of the space block corresponding to index number I.

[0111] In the method described above, if a new value needs to be written to the space block corresponding to a certain index number, the already allocated space block is not erased in place and then written. Instead, a space block of the same size is directly allocated from the unallocated space (which is already in an erased state), and the new value is written directly. At the same time, the allocated mapping entries on the RAM and FLASH sides are modified to bind the index number to the newly allocated space block. Thus, this disclosure no longer performs a full-page erase and write-back of the storage space. Instead, it uses a rolling allocation and rolling write method to modify, discard, or release data in the storage space. On the one hand, this reduces chip wear caused by frequent data erasure, which is beneficial to extending the lifespan of smart cards and other memory devices. On the other hand, this solution is simple and easy to implement, effectively reducing the time spent on data modification and improving modification efficiency. Especially in scenarios involving small-sized data modifications, this solution is simple, efficient, and has minimal impact on the lifespan of chips and smart cards.

[0112] In this scheme, since both the mapping table area and the allocated space on the Flash side are modified using a rolling write method, they start from the low address and high address of the NVM HEAP area respectively, growing towards each other, and eventually colliding at a certain position in the middle of the NVM HEAP area. In extreme cases, even if only the space block is modified, the mapping table area and the allocated space will still grow towards each other, eventually colliding (i.e., the unallocated space is exhausted). At this time, refer to Figure 7, which is a schematic diagram of the structure of a mapping space provided by an embodiment of this disclosure. As shown in Figure 7, the mapping table area adds new mapping table entries from low address to high address, while the allocable space is released from high address to low address, rolling the allocation of new space blocks; with the continuous allocation and modification of space blocks, the two roll towards each other, causing the unallocated space to become smaller and smaller, and even colliding.

[0113] To avoid the aforementioned collisions, the storage management method provided in this disclosure further offers the following processing method: defragmenting the storage space; wherein the storage space includes at least one of the following: allocated space and the mapping table entry area. In this way, the space of invalidated and released storage space (space blocks and / or mapping table entries) can be completely released, transforming these spaces back into unallocated space, thus achieving sustainable storage use of the storage space. In practical scenarios, defragmentation can be performed separately on the allocated space and the mapping table entry area, or both can be defragmented together. The scope of defragmentation to be performed can be customized in different scenarios, and this disclosure does not impose any particular restrictions on this.

[0114] In this disclosure, defragmentation of storage space inevitably involves erasing and rewriting operations, which are time-consuming. Therefore, in practical scenarios, defragmentation should not be performed frequently. Thus, in practical scenarios, the timing, period, or conditions for triggering defragmentation operations can be customized. This disclosure does not impose any particular restrictions on the timing of defragmentation triggering; in practical scenarios, defragmentation can be performed periodically or periodically, or other trigger conditions can be customized, such as performing defragmentation before performing certain critical operations (which can be customized).

[0115] In one exemplary embodiment, defragmenting the storage space includes at least one of the following: defragmenting the storage space periodically; defragmenting the storage space periodically; and defragmenting the storage space before performing a target operation.

[0116] The periodicity of the periodic defragmentation can be customized; the target operation can also be customized, and in practical scenarios, it can be a custom, critical, or important operation. For example, the target operation can include, but is not limited to, any operation that requires the allocation of new space blocks, such as at least one of the following: modification operation, space block allocation request operation, etc. For example, the target operation can also be other possible operations, such as any operation other than a query operation, or at least one of a query operation, release operation, modification operation, or new space allocation operation, etc., without exhaustive list.

[0117] Furthermore, in another embodiment, defragmentation can be triggered directly when its triggering condition is met. Alternatively, after the triggering condition is met, further judgment can be made, and defragmentation will only be triggered when preset judgment conditions are met.

[0118] In one exemplary embodiment, defragmenting storage space may include the following steps: obtaining the size of the target space; and then, defragmenting the storage space when the size of the target space is less than or equal to a preset first threshold. In this embodiment, not only the aforementioned triggering condition needs to be met, but also a custom judgment condition of a smaller target space needs to be met. Defragmentation will only be performed when both conditions are met. However, if the size of the target space is greater than the first threshold, defragmentation is not required until the next triggering opportunity. The first threshold can be custom-designed; for example, it can be set to 1 physical page size (2048 bytes) or 1.5 physical page sizes (3072 bytes). It should be understood that in different triggering mechanism implementations, the ranges of the target space and the first threshold can be the same or different, and can be customized. For example, in one possible embodiment, the first threshold may include a second threshold and a third threshold, where the second threshold is the threshold corresponding to periodic defragmentation of the storage space; and the third threshold is the threshold corresponding to defragmentation of the storage space before the target operation. The values ​​of the second threshold and the third threshold can be the same or different. In practical scenarios, if these two fragmentation mechanisms are used in combination, the two thresholds can satisfy the condition that the second threshold is greater than the third threshold. This will be explained later with reference to Figure 8.

[0119] Furthermore, in the above embodiments, the target space can include two situations: the unallocated space, or the estimated allocatable space after the target operation is performed. In other words, the target space can be the current unallocated space. Alternatively, the target space can also be the unallocated space remaining after the target operation is performed. In this case, the target space is actually an estimated value, which is a value determined and estimated before the target operation is performed. In this situation, if a modification operation or a new space allocation operation is performed, resulting in a small or insufficient remaining unallocated space after the operation is completed to support the operation, then fragmentation can be performed in advance before the target operation is performed to ensure the smooth implementation of the target operation and the subsequent continued storage capacity.

[0120] For example, in a real-world scenario, defragmentation can be triggered periodically in 5-second intervals. If the current trigger point is within a cycle, the size of the target space can be further determined. If the target space is small, defragmentation can be triggered. In this embodiment, this can also be understood as periodically triggering conditional checks for defragmentation, or periodically checking whether defragmentation should be triggered. Furthermore, if the target space is determined to be small, it can be further determined whether other operations are currently being performed. If operations such as space allocation, modification, release, or reading are currently being performed, defragmentation can be paused until the operation is completed. Alternatively, in another possible scenario, defragmentation can still be triggered periodically in 5-second intervals. In this case, the target space size does not need to be considered; the defragmentation operation can be performed directly. Or, before performing defragmentation, it can be paused to wait for the current operation to finish, and then automatically performed after the current operation is completed. This example only uses periodic defragmentation; other triggering conditions can be handled based on this logic.

[0121] Furthermore, in practical implementations, the above triggering mechanisms can be used in combination. When different triggering mechanisms are used in combination, each mechanism can be used to determine whether defragmentation is needed. However, in practical scenarios, in order to ensure smooth external storage services, if the defragmentation requirement is met and other operations are currently in progress (e.g., defragmentation by other mechanisms is being performed, or any operation such as allocation, modification, release, or reading of space blocks is currently in progress), the defragmentation operation can be performed only after the other operations are completed.

[0122] For ease of understanding, taking the combination of periodic defragmentation and defragmentation before the target operation as an example, please refer to Figure 8. Figure 8 is a schematic diagram of a defragmentation implementation scheme provided by an embodiment of this disclosure.

[0123] As shown in Figure 8, defragmentation can be triggered and checked every 5 seconds. In a real-world scenario, the size of the target space can be calculated every 5 seconds. That is, the difference between the low address boundary of the allocated space and the high address boundary of the mapping table entry area is calculated and denoted as D1.

[0124] It further determines whether D1 is less than the preset second threshold (i.e. the first threshold corresponding to periodic defragmentation), denoted as Tp, which can be 1.5 physical pages in size. Thus, if D1 is less than Tp, it is determined that defragmentation needs to be performed and proceeds to the next step; otherwise, if D1 is greater than or equal to Tp, it means that defragmentation is not needed at present and continues to wait for the next round of periodic checks.

[0125] When D1 is less than Tp, it is also necessary to determine whether a space block-related operation (including allocation, modification, release, and reading) is currently in progress. If so, wait for the space block-related operation to complete before performing defragmentation to avoid conflicts between the space block-related operation and the defragmentation operation. If not, there is no related access operation or the access operation has been completed, and the defragmentation operation can be started directly. After defragmentation is completed, wait for the next round of periodic checks.

[0126] Furthermore, as shown in Figure 8, this disclosure can also perform a defragmentation trigger check before critical operations. For example, as shown in Figure 8, when it is necessary to allocate / modify space blocks, it is necessary to first determine whether a periodic check-triggered defragmentation is currently being performed. If so, it is necessary to wait for the defragmentation operation to complete to avoid conflicts between space block-related operations and the defragmentation operation.

[0127] If not, meaning there is no periodic defragmentation operation currently being performed, or the operation has already been completed, then the size of the target interval needs to be calculated. In this case, first calculate the difference D1 between the low address boundary of the allocated space and the high address boundary of the mapping table entry area. Then subtract the expected space size occupied by the operation from D1, i.e., the size of the space block to be allocated / modified and the size of a mapping table entry, to obtain D2. Then determine if D2 is less than a preset third threshold (i.e., the first threshold corresponding to defragmentation before the target operation), denoted as Tc, which can be set to the size of one physical page. Therefore, if D2 is greater than or equal to Tc, it means there is no need for defragmentation at this time, and critical operations such as space block allocation / modification can be performed directly; otherwise, if D2 is less than Tc, defragmentation is performed first, followed by space block allocation or modification operations.

[0128] In practical implementations, the second threshold can be greater than the third threshold. That is, the threshold for periodic checks triggering defragmentation (Tp) is greater than the threshold for checks before critical operations (Tc), i.e., Tp > Tc. This ensures that defragmentation triggered by periodic checks usually occurs before defragmentation triggered by checks before critical operations. This is because the former defragmentation operation can be performed during the intervals between block access operations, minimizing the blocking of block access operations and preventing the exhaustion of allocable space in advance, thus reducing the frequency of the latter defragmentation operation. On the other hand, defragmentation triggered by the latter (i.e., checks before critical operations) usually occurs when allocating / modifying large blocks, serving as a last resort to prevent the exhaustion of allocable space, but it will block the allocation / modification of blocks.

[0129] The following explains how to defragment the allocated space and the mapping table entry area separately. Furthermore, when both need to be defragmented together, the allocated space can be defragmented first, followed by the mapping table entry area, or vice versa, as described below. This will be explained in detail below.

[0130] In this disclosure, defragmentation can be achieved by erasing boundary reclaimed blocks and combining this with multiple rounds of iterative data movement. In some embodiments, at least one round of data movement can be performed until all reclaimed blocks are merged with the unallocated space. Each round of the data movement process includes: moving the reclaimed block furthest from the unallocated space in the allocated space to the front of adjacent valid data, in the direction facing the unallocated space.

[0131] A reclaimed block comprises one or more adjacent data blocks to be reclaimed; the data blocks to be reclaimed include: obsolete and / or released space blocks, and / or, mapping entries corresponding to the obsolete and / or released space blocks; the valid data includes: valid space blocks (i.e., space blocks in a valid state, also referred to as data blocks), and / or, mapping entries corresponding to the valid space blocks. This means that this iterative relocation scheme can be applied to the defragmentation of allocated space, and / or, also to the defragmentation of mapping entry areas.

[0132] As mentioned earlier, in Flash storage, from low address to high address, the memory locations are: mapping table entry area, unallocated space, and allocated space. Therefore, the defragmentation process for the mapping table entry area involves iteratively moving the mapping table entries to be reclaimed from low address to high address; while for the allocated space, it involves iteratively moving the blocks to be reclaimed from high address to low address. Ultimately, these reclaimed blocks are moved together with the unallocated space, thus defragmenting the reclaimed blocks.

[0133] Furthermore, it should be noted that during the aforementioned data iterative migration process, it is inevitable to encounter situations where two or more reclaimed blocks are adjacent. This adjacency may be due to accumulated space block operations or arise during the data migration process itself. For example, in the allocated space, from high address to low address, the sequence is: Reclaimed Block 1, Space Block 2, Reclaimed Block 3, Space Block 4… In one round of data migration during defragmentation, Reclaimed Block 1 will be moved towards the unallocated space. After the move, in the allocated space, from high address to low address, the sequence is: Space Block 2, Reclaimed Block 1, Reclaimed Block 3, Space Block 4… At this point, Reclaimed Block 1 and Reclaimed Block 3 are adjacent. When multiple reclaimed blocks are adjacent, they can be merged into a larger reclaimed block. That is, a reclaimed block can be one or more space blocks to be reclaimed. In subsequent data migration processes, this entire block can be moved to the front of the adjacent space block closest to the unallocated space in a single data migration. Continuing with the previous example, after the first round of data migration, reclaimed block 1 and reclaimed block 3 are adjacent. Therefore, in the next round of data migration, reclaimed block 1 and reclaimed block 3 can be merged into a large reclaimed block. This large reclaimed block can then be moved in front of space block 4 during the next round of data migration. Thus, the structure after the migration is: space block 2, space block 4, reclaimed block 1, reclaimed block 3, and so on. Iterative migration can continue afterward, which will not be elaborated upon here.

[0134] In addition, to further simplify the processing, this disclosure allows for virtual merging of multiple valid space blocks with adjacent physical addresses. It should be noted that virtual merging simply means treating them as a single space block during subsequent reorganization. After the merge, they are restored to their original, independent state and can be accessed as separate space blocks. This process does not actually change the actual storage structure of the space blocks. In other words, this disclosure does not perform an actual merging operation on the valid space blocks; instead, it treats them as a single unit for relocation—a virtual mimicry. Thus, during data migration, a single migration process can move a reclaimed block to the front of multiple adjacent space blocks.

[0135] In some implementation scenarios, the merging of reclaimed blocks can be achieved through a second linked list maintained on the RAM side. In one exemplary embodiment, the storage management method provided in this disclosure further includes:

[0136] Traverse the storage space and maintain the data to be reclaimed in the second linked list;

[0137] Based on the positional relationship between the data to be recycled, the data to be recycled in the second linked list is merged and organized to obtain the recycling blocks that are sequentially maintained in the second linked list.

[0138] In this disclosure, a second linked list (also called a recycling necklace list) is used to sequentially maintain data to be recycled (i.e., recycling items). In practical scenarios, the second linked list is maintained in RAM; therefore, it can also be called a RAM-side recycling necklace list. Furthermore, the second linked list can maintain the sequential order of the data to be recycled based on the ascending order of the starting addresses of the data to be recycled; that is, the second linked list is a singly linked list arranged in ascending order based on the starting addresses of the data to be recycled. In some embodiments, structurally, the second linked list includes at least one recycling block entry, and any one of the recycling block entries includes: a recycling block address and a recycling block size.

[0139] It should be understood that when the second linked list is used in the defragmentation process of allocated space, the second linked list is used to sequentially maintain the space blocks to be reclaimed (i.e., reclaimed blocks); when the second linked list is used in the defragmentation process of the mapping table entry area, the second linked list is used to sequentially maintain the mapping table entry entries.

[0140] Please refer to Figure 9, which is a schematic diagram of a fragmentation scheme provided by an embodiment of this disclosure. As shown in Figure 9, before performing the multi-round iterative relocation scheme as described above, the recycled blocks can be merged and organized using a second linked list to determine the space to be organized.

[0141] When defragmentation is initiated, reclaimed blocks and space blocks need to be merged first. In some embodiments, the NVM management interface can first traverse all obsolete or released mapping table entries in the mapping table entry area, treat the space blocks corresponding to these entries as reclaimed blocks, and store the address and size of the reclaimed blocks as reclaimed entries in the reclaimed chain table on the RAM side, i.e., multiple reclaimed block entries as shown in Figure 9; and the second chain table is sorted from high to low according to the starting address of each reclaimed block to facilitate subsequent merging, moving and defragmentation.

[0142] Furthermore, in the second linked list, multiple reclaimed blocks with adjacent physical addresses can be merged into a new, larger reclaimed block. For example, as shown in Figure 9, space blocks 2 and 3 with adjacent physical addresses can be merged into a new reclaimed block 1, and space blocks 8 and 9 with adjacent physical addresses can be merged into a new reclaimed block 2. Additionally, as shown in Figure 9, this disclosure can also perform virtual merging of each valid space block. After virtual merging, space blocks 4 and 5 in the allocated space are merged into a new space block 1, and reclaimed blocks are also merged into a new reclaimed block.

[0143] Thus, the boundary reclaimed blocks, namely the lowest and highest reclaimed blocks in the allocated space, are erased (in actual scenarios, these boundary reclaimed blocks may exist; if they do, they need to be erased; if they do not exist, this step can be omitted). Then, starting from the first reclaimed block at the high address and counting down to the low address, there will be n reclaimed blocks and n space blocks, thus determining the space to be reorganized. In this way, at least one round of data migration can begin in the space to be reorganized to achieve the defragmentation of the reclaimed blocks.

[0144] In some implementations, the data migration process refers to starting from the highest address block and moving one reclaimed block towards the unallocated space in each round (this can also be understood as moving one block away from the unallocated space) to eliminate reclaimed blocks in the adjacent high address direction. Furthermore, after each migration, the starting address of the new block is added to the displacement amount to obtain a new starting address. The corresponding mapping table entry for this block is then located in the mapping table area, and the starting address in that entry is updated to the new value. If the migrated block is a merged block created through virtual merging in the previous process, then the starting addresses of each of the original sub-blocks in the composite block are added to the displacement amount, and their corresponding entries in the mapping table area are updated. After n rounds of block migration operations, all reclaimed blocks are eliminated, and the entire cleanup operation is complete.

[0145] As shown in Figure 9, when fragmentation of allocated space is required, a multi-round iterative relocation method can be used. In the first round of data relocation, reclaimed block 1 is moved above space block 1. In the second round of data relocation, reclaimed block 1 and reclaimed block 2 are treated as a merged reclaimed block (or denoted as a new reclaimed block) 1, and this merged reclaimed block is moved above space block 2. This process continues, and through multiple rounds of merging and relocation of reclaimed blocks, the reclaiming of all reclaimed blocks is ultimately achieved. Furthermore, as shown in Figure 9, in each round of data relocation, the relevant mapping table entries in the mapping table area are updated.

[0146] Furthermore, as mentioned above, in this disclosure, after data migration of a space block, the starting address and other related information of the space block change. Therefore, when data migration of a space block is performed, it is also necessary to modify the mapping table entries of each space block.

[0147] In other words, when the reclaimed block includes invalid and / or released space blocks, that is, when defragmenting the allocated space, the starting address of each space block in the mapping table entry area also needs to be updated during any round of data migration.

[0148] Furthermore, during the defragmentation of allocated space, updating the mapping table entry area requires modifying some fields in the original mapping table entry. In this case, the rolling write scheme provided above is not applicable. Therefore, during the defragmentation process, when it is necessary to modify the relevant mapping table entry data simultaneously, a full-page erase and write-back method is required. In other words, during any round of data migration, the starting address of each space block in the mapping table entry area needs to be updated using a full-page erase and write-back method.

[0149] For example, Figure 10 is a schematic diagram of the update method of the mapping table entry area during defragmentation in an embodiment of this disclosure. As shown in Figure 10, the so-called whole-page erase and write-back method refers to copying the physical page containing the mapping table entry that needs to be modified to the cache space on the RAM side, that is, the RAM-side cache page shown in Figure 10, so that the data can be directly modified on the RAM-side cache page; while the physical page containing the mapping table entry stored in the original mapping table entry area is erased in its entirety; then, the data in the modified RAM-side cache page is written back to the erased physical page. In this way, the corresponding entry in the mapping table entry area can be modified in place.

[0150] It should be noted that the processing scheme shown in Figure 10 is only used to ensure consistency between the data stored in the mapping table entry area and the data stored in the allocated space. It does not itself defragment the entries that have been invalidated or released in the mapping table entry area. It can be regarded as an auxiliary process for defragmenting the allocated space. Based on this, in actual implementation scenarios, if the allocated space has already been defragmented according to the above scheme, the defragmentation of the mapping table entry area can still be performed again according to this scheme.

[0151] Based on this, by combining the schemes shown in Figure 9 and Figure 10, it is possible to organize the fragments of the allocated space and reclaim the space.

[0152] Furthermore, this disclosure provides an implementation method for defragmenting the mapping table entry area. Please refer to Figure 11, which is a schematic diagram of another defragmentation scheme provided by an embodiment of this disclosure. As shown in Figure 11, the defragmentation method for the mapping table entry area is similar to the defragmentation method for allocated space, both employing a strategy of merging first and then moving.

[0153] As shown in Figure 11, after the defragmentation of the mapping table entry area is initiated, reclaimed blocks and data blocks can be merged first (virtual merging). In some embodiments, the NVM management interface can first traverse all obsolete or released mapping table entry entries in the mapping table entry area. These mapping table entry entries to be reclaimed can be used as reclaimed blocks themselves, or merged and defragmented to form new reclaimed blocks. The address and size of the entry (i.e., the starting address and size of the space block) are stored as reclaimed items in the reclaimed chain table (i.e., the second linked list) on the RAM side, and sorted from low to high according to the starting address of each reclaimed item to facilitate subsequent merging and defragmentation.

[0154] Next, multiple entries to be reclaimed that are physically adjacent in the reclaimed chain table (i.e., reclaimed block entries in the second linked list) are merged into a new, larger reclaimed block, denoted as the new reclaimed block. Furthermore, for currently valid mapping table entries (that do not require reclaiming), a virtual merging method can be used to virtually merge multiple mapping table entries that are physically adjacent into a new, larger virtual data block. The concept of virtual merging is the same as before and will not be repeated.

[0155] After completing the aforementioned operations of merging reclaimed blocks and virtually merging data blocks, the new reclaimed blocks and new data blocks are generally interspersed. Thus, after erasing the boundary reclaimed block at the highest address (if any), starting from the first reclaimed block at the lower address and counting towards the higher address, there will be at least one reclaimed block and at least one data block, thereby determining the space to be reorganized. In this way, at least one round of data migration process can be started.

[0156] In some embodiments, the data migration process begins with the lowest address space block, moving one data block (or reclaimed block) at a time in each round to eliminate reclaimed blocks in the adjacent lower address direction, until all reclaimed blocks are moved to a location merged with unallocated space. This completes the defragmentation of the mapping table entry area.

[0157] In summary, this disclosure provides a Flash storage space allocation and management method based on rolling allocation and rolling write. On one hand, this disclosure extends the structure (or information type) of each mapping entry in the mapping table entry area by adding a write-after status segment (i.e., a status field) to each mapping entry to indicate its status: available, invalid, or released. Therefore, when the space block corresponding to a mapping entry needs to be modified, a new space block is reallocated to that space block through rolling allocation, and the original mapping entry corresponding to the space block is invalidated (for example, by writing a specific value to the write-after status segment of the mapping entry to indicate its invalidation status). Simultaneously, a new mapping entry with a changed space block start address is written to the end of the mapping table entry area, maintaining its write-after status segment in an unwritten state, indicating that the mapping entry is available. Thus, the implementation of the rolling allocation and rolling write scheme is guaranteed from the mapping table area. On the other hand, this disclosure adopts a rolling allocation and rolling write method to modify the data in the space block. That is, if the value of the space block needs to be modified, the space block will not be modified in place (i.e., it is not a full page erase and write-back method). Instead, a new space block is reallocated, the new value is written, and the starting address of the new space block is updated to the aforementioned new mapping entry. Since it is not necessary to modify the data at the original address, the operation of full page erase and write is eliminated, reducing the chip wear problem caused by frequent data erasure and helping to improve the service life of smart cards and other memories. Moreover, the operation of this solution is simple and easy to implement, which can effectively reduce the time consumption of data modification and improve the modification efficiency. Especially when facing small-size data modification scenarios, this solution is simple, efficient and has little impact on the service life of chips and smart cards.

[0158] In addition, to further improve the retrieval and allocation speed of space blocks, this disclosure also introduces a RAM-side mapping chain table (i.e., the first linked list), the maximum index number, and the allocatable space address. Through the data maintained by the first linked list, the relevant information of the space block corresponding to a certain index number can be quickly and effectively queried without traversing the mapping item table area.

[0159] Furthermore, to further improve the efficiency of defragmentation, this disclosure introduces a defragmentation mechanism, such as periodic defragmentation, defragmentation before critical operations, and a combined defragmentation triggering mechanism and judgment strategy. This ensures that defragmentation operations are performed as much as possible during the access intervals of space blocks, avoiding blocking normal user access. Simultaneously, a merging-then-moving method is used during defragmentation to reduce the number of chip erase operations.

[0160] The storage management method according to embodiments of the present disclosure has been described above with reference to the accompanying drawings.

[0161] This disclosure also provides a storage management device. Figure 12 is a structural block diagram of a storage management device provided in an embodiment of this disclosure. As shown in Figure 12, the storage management device 1200 includes:

[0162] The first management unit 1210 is used to allocate a second space block in the unallocated space and write the modified data when it is necessary to modify the data in the first space block;

[0163] The second management unit 1220 is used to add a second entry corresponding to the second space block in the mapping table entry area;

[0164] The second management unit 1220 is also used to adjust the entry status of the first entry corresponding to the first space block to invalid.

[0165] In one exemplary embodiment, the mapping entry area is used to maintain attribute information of allocated space blocks; the mapping entry area includes at least one mapping entry; the mapping entry includes: the first entry and the second entry;

[0166] Each of the mapping table entries includes at least a status field; wherein the status field is used to characterize the entry status of the mapping table entry.

[0167] In one exemplary embodiment, the entry status includes: valid, invalid, and released;

[0168] For any of the aforementioned mapping table entries, at least one of the following conditions must be met:

[0169] When the status field is empty, the status of the mapping table entry is valid;

[0170] When the status field is the first status bit, the status of the mapping table entry is invalid;

[0171] When the status field is the second status bit, the entry status of the mapping table entry is released.

[0172] In one exemplary embodiment, the index field is used to characterize the index number of the spatial block corresponding to the mapping table entry;

[0173] The index numbers of the first entry, the second entry, the first space block, and the second space block are all the same.

[0174] In one exemplary embodiment, any of the mapping table entries further includes at least one of the following: a verification field, an index field, a starting address field, and a space block size field;

[0175] The verification field is used to verify the data integrity of the mapping table entries;

[0176] The verification field includes at least one of the following: a table entry flag field and a checksum.

[0177] In one exemplary embodiment, the storage management device 1200 includes:

[0178] The third management unit (not shown in Figure 12) is used to dynamically maintain a first linked list in the random access memory (RAM), the first linked list being used to sequentially maintain the allocated valid mapping table entries.

[0179] Wherein, the first linked list is a singly linked list arranged in ascending order based on the index number of the mapping table entry; the first linked list meets at least one of the following conditions:

[0180] The first linked list is a singly linked list arranged in ascending order based on the index number of the mapping table entries;

[0181] The first linked list includes at least one linked list entry, and any one of the linked list entries corresponds to an allocated valid mapping table entry;

[0182] Each of the linked list entries includes at least: an index field and a pointer field, wherein the pointer field is used to indicate the next entry of the linked list entry;

[0183] Each of the linked list entries further includes at least one of the following: a space block size field and a starting address field.

[0184] In one exemplary embodiment, the third management unit is configured to:

[0185] When it is necessary to access data of the target index number, the starting address field corresponding to the target index number is determined based on the first linked list;

[0186] Based on the starting address field, access the data of the target space block corresponding to the target index number.

[0187] In one exemplary embodiment, the third management unit is configured to:

[0188] When it is necessary to release the target space block corresponding to the target index number, the entry status of the mapping table entry corresponding to the target space block is adjusted to release;

[0189] Delete the linked list entry corresponding to the target space block from the first linked list.

[0190] In one exemplary embodiment, the storage management device 1200 further includes a third management unit (not shown in FIG12); the third management unit is configured to:

[0191] In the RAM, at least one of the following information is dynamically maintained: maximum index number and allocable space address.

[0192] In one exemplary embodiment, the first management unit 1210 is used to:

[0193] At the high address of the unallocated space, the second space block is partitioned, and the modified data is written into the second space block;

[0194] Wherein, the second space block has the same size as the first space block; and / or, the low address of the unallocated space is adjacent to the mapping table entry area, and the high address of the unallocated space is adjacent to the allocated space.

[0195] In one exemplary embodiment, the storage management device 1200 further includes a fourth management unit (not shown in FIG12); the fourth management unit is configured to:

[0196] Defragment the storage space;

[0197] The storage space includes at least one of the following: allocated space and the mapping table entry area.

[0198] In one exemplary embodiment, the fourth management unit is configured to be at least one of the following:

[0199] Regularly defragment the storage space;

[0200] Periodically defragment the storage space;

[0201] Before performing the target operation, the storage space is defragmented.

[0202] In one exemplary embodiment, the fourth management unit is configured to:

[0203] Obtain the size of the target space; wherein the target space includes: the unallocated space, or the estimated allocatable space after performing the target operation;

[0204] When the size of the target space is less than or equal to a preset first threshold, the storage space is defragmented.

[0205] In one exemplary embodiment, the first threshold includes: a second threshold and a third threshold;

[0206] Wherein, the second threshold is greater than the third threshold;

[0207] The second threshold is the threshold corresponding to periodic defragmentation of the storage space;

[0208] The third threshold is the threshold corresponding to defragmenting the storage space before the target operation.

[0209] In one exemplary embodiment, the fourth management unit is configured to:

[0210] Erase boundary reclaim blocks;

[0211] Perform at least one round of data migration until all reclaimed blocks are merged with unallocated space;

[0212] Any one of the data migration processes mentioned above includes:

[0213] In the direction facing the unallocated space, the reclaimed block that is farthest from the unallocated space in the allocated space is moved in front of the adjacent valid data;

[0214] Wherein, one of the reclaimed blocks includes one or more adjacent data to be reclaimed; wherein, the data to be reclaimed includes: obsolete and / or released space blocks, and / or, mapping table entries corresponding to the obsolete and / or released space blocks;

[0215] The valid data includes: valid space blocks, and / or, mapping table entries corresponding to the valid space blocks.

[0216] In one exemplary embodiment, the fourth management unit is configured to:

[0217] When the reclaimed block includes invalidated and / or released space blocks, during any round of data migration, the starting address of each space block in the mapping table entry area is updated by a full-page erase and write-back method.

[0218] In one exemplary embodiment, the fourth management unit is further configured to:

[0219] Traverse the storage space and maintain the data to be reclaimed in the second linked list;

[0220] Based on the positional relationship between the data to be recycled, the data to be recycled in the second linked list is merged and sorted to obtain the recycling blocks that are sequentially maintained in the second linked list;

[0221] The second linked list is maintained in RAM;

[0222] The second linked list is a singly linked list arranged in ascending order based on the starting address of the data to be recycled;

[0223] The second linked list includes at least one reclaimed block entry, and each of the reclaimed block entries includes: reclaimed block address and reclaimed block size.

[0224] This disclosure also provides a memory. Figure 13 is a structural block diagram of a memory provided in an embodiment of this disclosure. As shown in Figure 13, the memory 1300 includes:

[0225] Storage space 1310, the storage space is used to provide: a mapping table entry area, unallocated space, and allocated space;

[0226] Storage management device 1320 is used in the storage management method described in any of the preceding embodiments.

[0227] When the storage management solution provided in this disclosure is applied to the field of smart cards, the storage management device in any of the above embodiments can be a COS system, and the storage space can be the storage space of the smart card. Referring to the preceding text, further details are omitted.

[0228] Figure 14 is a hardware block diagram of an electronic device provided in an embodiment of this disclosure. The electronic device 1400 according to an embodiment of this disclosure includes at least a memory, a processor, and a computer program stored in the memory. The processor executes the computer program to implement the memory management method described in any of the above embodiments.

[0229] The electronic device 1400 shown in Figure 14 includes a central processing unit (CPU) 1401, a graphics processing unit (GPU) 1402, and a memory 1403. These units are interconnected via a bus 1404. The CPU 1401 and / or GPU 1402 can function as the aforementioned processors, and the memory 1403 can function as the aforementioned memory for storing computer-readable instructions. Furthermore, the electronic device 1400 may also include a communication unit 1405, a storage unit 1406, an output unit 1407, an input unit 1408, and an external device 1409, all of which are also connected to the bus 1404.

[0230] Figure 15 is a schematic diagram of a computer-readable storage medium provided in an embodiment of this disclosure. The computer-readable storage medium according to an embodiment of this disclosure stores a computer program / instruction (including but not limited to computer-readable instructions). As shown in Figure 15, the computer-readable storage medium 1500 stores a computer-readable instruction 1501. When executed by a processor, this computer program / instruction implements the storage management method described in any of the preceding embodiments of this disclosure. The computer-readable storage medium includes, for example, volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, optical disk, magnetic disk, etc.

[0231] This disclosure further provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the storage management method described in any of the preceding embodiments of this disclosure.

[0232] The basic principles of this disclosure have been described above in conjunction with embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing them for implementation.

[0233] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0234] Additionally, as used herein, the “or” used in a list of items beginning with “at least one” indicates a separate list, such that a list of, for example, “at least one of A, B, or C” means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word “exemplary” does not imply that the described example is preferred or better than other examples.

[0235] It should also be noted that in the systems and methods of this disclosure, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions to this disclosure.

[0236] Various changes, substitutions, and modifications can be made to the technology described herein without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of this disclosure is not limited to the processes, machines, manufactures, events, means, methods, and actions described above. Currently existing or later-developed processes, machines, manufactures, events, means, methods, or actions that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein can be utilized. Therefore, the appended claims include such processes, machines, manufactures, events, means, methods, or actions within their scope.

[0237] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0238] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A storage management method, comprising: When it is necessary to modify the data in the first space block, allocate a second space block in the unallocated space and write the modified data. In the mapping table area, add a second entry corresponding to the second space block; Adjust the entry status of the first entry corresponding to the first space block to invalid.

2. The method according to claim 1, wherein, The mapping table area is used to maintain the attribute information of the allocated space blocks; The mapping table area includes at least one mapping table entry; The mapping table entries include: the first entry and the second entry; Each of the aforementioned mapping table entries includes at least: a status field; The status field is used to characterize the entry status of the mapping table entry.

3. The method of claim 2, wherein, The entry status includes: valid, invalid, and released; For any of the aforementioned mapping table entries, at least one of the following conditions must be met: When the status field is empty, the status of the mapping table entry is valid; When the status field is the first status bit, the status of the mapping table entry is invalid; When the status field is the second status bit, the entry status of the mapping table entry is released.

4. The method according to claim 2, wherein, The index field is used to represent the index number of the spatial block corresponding to the mapping table entry; The index numbers of the first entry, the second entry, the first space block, and the second space block are all the same.

5. The method according to claim 2, wherein, Any of the aforementioned mapping table entries also includes at least one of the following: a verification field, an index field, a starting address field, and a space block size field; The verification field is used to verify the data integrity of the mapping table entries; The verification field includes at least one of the following: a table entry flag field and a checksum.

6. The method according to any one of claims 1-5, wherein, The method further includes: In random access memory (RAM), a first linked list is dynamically maintained, which is used to sequentially maintain allocated and valid mapping table entries; the first linked list meets at least one of the following conditions: The first linked list is a singly linked list arranged in ascending order based on the index number of the mapping table entries; The first linked list includes at least one linked list entry, and any one of the linked list entries corresponds to an allocated valid mapping table entry; Each of the linked list entries includes at least: an index field and a pointer field, wherein the pointer field is used to indicate the next entry of the linked list entry; Each of the linked list entries further includes at least one of the following: a space block size field and a starting address field.

7. The method according to claim 6, wherein, The method further includes: When it is necessary to access data of the target index number, the starting address field corresponding to the target index number is determined based on the first linked list; Based on the starting address field, access the data of the target space block corresponding to the target index number.

8. The method according to claim 6 or 7, wherein, The method further includes: When it is necessary to release the target space block corresponding to the target index number, the entry status of the mapping table entry corresponding to the target space block is adjusted to release; Delete the linked list entry corresponding to the target space block from the first linked list.

9. The method according to any one of claims 6-8, wherein, The method further includes: In the RAM, at least one of the following information is dynamically maintained: maximum index number and allocable space address.

10. The method according to any one of claims 1-8, wherein, The step of allocating a second space block in the unallocated space and writing modified data includes: At the high address of the unallocated space, the second space block is partitioned, and the modified data is written into the second space block; Wherein, the second space block has the same size as the first space block; and / or, the low address of the unallocated space is adjacent to the mapping table entry area, and the high address of the unallocated space is adjacent to the allocated space.

11. The method according to any one of claims 1-8, wherein, The method further includes: Defragment the storage space; The storage space includes at least one of the following: allocated space and the mapping table area.

12. The method according to claim 11, wherein, The defragmentation of storage space includes at least one of the following: Regularly defragment the storage space; Periodically defragment the storage space; Before performing the target operation, the storage space is defragmented.

13. The method according to claim 11 or 12, wherein, The defragmentation of storage space includes: Obtain the size of the target space; wherein the target space includes: the unallocated space, or the estimated allocatable space after performing the target operation; When the size of the target space is less than or equal to a preset first threshold, the storage space is defragmented.

14. The method according to claim 13, wherein, The first threshold includes: a second threshold and a third threshold; Wherein, the second threshold is greater than the third threshold; The second threshold is the threshold corresponding to periodic defragmentation of the storage space; The third threshold is the threshold corresponding to defragmenting the storage space before the target operation.

15. The method according to any one of claims 11-14, wherein, The defragmentation of storage space includes at least one of the following: Erase boundary reclaim blocks; Perform at least one round of data migration until all reclaimed blocks are merged with unallocated space; Any one of the data migration processes mentioned above includes: In the direction facing the unallocated space, the reclaimed block that is farthest from the unallocated space in the allocated space is moved in front of the adjacent valid data; Wherein, one of the reclaimed blocks includes one or more adjacent data to be reclaimed; wherein, the data to be reclaimed includes: obsolete and / or released space blocks, and / or, mapping table entries corresponding to the obsolete and / or released space blocks; The valid data includes: valid space blocks, and / or, mapping table entries corresponding to the valid space blocks.

16. The method according to claim 15, wherein, When the reclaimed block includes: obsolete and / or released space blocks, the method further includes, during any round of data migration: The starting address of each space block in the mapping table entry area is updated by using a full-page erase and write-back method.

17. The method according to claim 15 or 16, wherein, The method further includes: Traverse the storage space and maintain the data to be reclaimed in the second linked list; Based on the positional relationship between the data to be recycled, the data to be recycled in the second linked list is merged and sorted to obtain the recycling blocks that are sequentially maintained in the second linked list; The second linked list is maintained in RAM; The second linked list is a singly linked list arranged in ascending order based on the starting address of the data to be recycled; The second linked list includes at least one reclaimed block entry, and each of the reclaimed block entries includes: reclaimed block address and reclaimed block size.

18. A storage management device, comprising: The first management unit is used to allocate a second space block in the unallocated space and write the modified data when it is necessary to modify the data in the first space block; The second management unit is used to add a second entry corresponding to the second space block in the mapping table entry area; The second management unit is further configured to adjust the entry status of the first entry corresponding to the first space block to invalid.

19. A memory comprising: Storage space, which provides: a mapping table entry area, unallocated space, and allocated space; A storage management device for implementing the method according to any one of claims 1-17.

20. An electronic device comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the method according to any one of claims 1-17.

21. A computer-readable storage medium having a computer program or instructions stored thereon, characterized in that, When the computer program or instructions are executed by a processor, they implement the method described in any one of claims 1-17.

22. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method described in any one of claims 1-17.

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